3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/pm_runtime.h>
22 #include <drm/exynos_drm.h>
23 #include <plat/regs-fb-v4.h>
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_fbdev.h"
27 #include "exynos_drm_crtc.h"
30 * FIMD is stand for Fully Interactive Mobile Display and
31 * as a display controller, it transfers contents drawn on memory
32 * to a LCD Panel through Display Interfaces such as RGB or
36 /* position control register for hardware window 0, 2 ~ 4.*/
37 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
38 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
39 /* size control register for hardware window 0. */
40 #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
41 /* alpha control register for hardware window 1 ~ 4. */
42 #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
43 /* size control register for hardware window 1 ~ 4. */
44 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
46 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
47 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
48 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
50 /* color key control register for hardware window 1 ~ 4. */
51 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
52 /* color key value register for hardware window 1 ~ 4. */
53 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
55 /* FIMD has totally five hardware windows. */
58 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
60 struct fimd_win_data {
61 unsigned int offset_x;
62 unsigned int offset_y;
63 unsigned int ovl_width;
64 unsigned int ovl_height;
65 unsigned int fb_width;
66 unsigned int fb_height;
70 unsigned int buf_offsize;
71 unsigned int line_size; /* bytes */
76 struct exynos_drm_subdrv subdrv;
78 struct drm_crtc *crtc;
81 struct resource *regs_res;
83 struct fimd_win_data win_data[WINDOWS_NR];
85 unsigned int default_win;
86 unsigned long irq_flags;
92 struct fb_videomode *timing;
95 static bool fimd_display_is_connected(struct device *dev)
97 DRM_DEBUG_KMS("%s\n", __FILE__);
104 static void *fimd_get_timing(struct device *dev)
106 struct fimd_context *ctx = get_fimd_context(dev);
108 DRM_DEBUG_KMS("%s\n", __FILE__);
113 static int fimd_check_timing(struct device *dev, void *timing)
115 DRM_DEBUG_KMS("%s\n", __FILE__);
122 static int fimd_display_power_on(struct device *dev, int mode)
124 DRM_DEBUG_KMS("%s\n", __FILE__);
131 static struct exynos_drm_display_ops fimd_display_ops = {
132 .type = EXYNOS_DISPLAY_TYPE_LCD,
133 .is_connected = fimd_display_is_connected,
134 .get_timing = fimd_get_timing,
135 .check_timing = fimd_check_timing,
136 .power_on = fimd_display_power_on,
139 static void fimd_dpms(struct device *subdrv_dev, int mode)
141 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
143 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
145 mutex_lock(&ctx->lock);
148 case DRM_MODE_DPMS_ON:
150 * enable fimd hardware only if suspended status.
152 * P.S. fimd_dpms function would be called at booting time so
153 * clk_enable could be called double time.
156 pm_runtime_get_sync(subdrv_dev);
158 case DRM_MODE_DPMS_STANDBY:
159 case DRM_MODE_DPMS_SUSPEND:
160 case DRM_MODE_DPMS_OFF:
162 pm_runtime_put_sync(subdrv_dev);
165 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
169 mutex_unlock(&ctx->lock);
172 static void fimd_apply(struct device *subdrv_dev)
174 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
175 struct exynos_drm_manager *mgr = &ctx->subdrv.manager;
176 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
177 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
178 struct fimd_win_data *win_data;
181 DRM_DEBUG_KMS("%s\n", __FILE__);
183 for (i = 0; i < WINDOWS_NR; i++) {
184 win_data = &ctx->win_data[i];
185 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
186 ovl_ops->commit(subdrv_dev, i);
189 if (mgr_ops && mgr_ops->commit)
190 mgr_ops->commit(subdrv_dev);
193 static void fimd_commit(struct device *dev)
195 struct fimd_context *ctx = get_fimd_context(dev);
196 struct fb_videomode *timing = ctx->timing;
202 DRM_DEBUG_KMS("%s\n", __FILE__);
204 /* setup polarity values from machine code. */
205 writel(ctx->vidcon1, ctx->regs + VIDCON1);
207 /* setup vertical timing values. */
208 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
209 VIDTCON0_VFPD(timing->lower_margin - 1) |
210 VIDTCON0_VSPW(timing->vsync_len - 1);
211 writel(val, ctx->regs + VIDTCON0);
213 /* setup horizontal timing values. */
214 val = VIDTCON1_HBPD(timing->left_margin - 1) |
215 VIDTCON1_HFPD(timing->right_margin - 1) |
216 VIDTCON1_HSPW(timing->hsync_len - 1);
217 writel(val, ctx->regs + VIDTCON1);
219 /* setup horizontal and vertical display size. */
220 val = VIDTCON2_LINEVAL(timing->yres - 1) |
221 VIDTCON2_HOZVAL(timing->xres - 1);
222 writel(val, ctx->regs + VIDTCON2);
224 /* setup clock source, clock divider, enable dma. */
226 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
229 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
231 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
234 * fields of register with prefix '_F' would be updated
235 * at vsync(same as dma start)
237 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
238 writel(val, ctx->regs + VIDCON0);
241 static int fimd_enable_vblank(struct device *dev)
243 struct fimd_context *ctx = get_fimd_context(dev);
246 DRM_DEBUG_KMS("%s\n", __FILE__);
251 if (!test_and_set_bit(0, &ctx->irq_flags)) {
252 val = readl(ctx->regs + VIDINTCON0);
254 val |= VIDINTCON0_INT_ENABLE;
255 val |= VIDINTCON0_INT_FRAME;
257 val &= ~VIDINTCON0_FRAMESEL0_MASK;
258 val |= VIDINTCON0_FRAMESEL0_VSYNC;
259 val &= ~VIDINTCON0_FRAMESEL1_MASK;
260 val |= VIDINTCON0_FRAMESEL1_NONE;
262 writel(val, ctx->regs + VIDINTCON0);
268 static void fimd_disable_vblank(struct device *dev)
270 struct fimd_context *ctx = get_fimd_context(dev);
273 DRM_DEBUG_KMS("%s\n", __FILE__);
278 if (test_and_clear_bit(0, &ctx->irq_flags)) {
279 val = readl(ctx->regs + VIDINTCON0);
281 val &= ~VIDINTCON0_INT_FRAME;
282 val &= ~VIDINTCON0_INT_ENABLE;
284 writel(val, ctx->regs + VIDINTCON0);
288 static struct exynos_drm_manager_ops fimd_manager_ops = {
291 .commit = fimd_commit,
292 .enable_vblank = fimd_enable_vblank,
293 .disable_vblank = fimd_disable_vblank,
296 static void fimd_win_mode_set(struct device *dev,
297 struct exynos_drm_overlay *overlay)
299 struct fimd_context *ctx = get_fimd_context(dev);
300 struct fimd_win_data *win_data;
302 unsigned long offset;
304 DRM_DEBUG_KMS("%s\n", __FILE__);
307 dev_err(dev, "overlay is NULL\n");
312 if (win == DEFAULT_ZPOS)
313 win = ctx->default_win;
315 if (win < 0 || win > WINDOWS_NR)
318 offset = overlay->fb_x * (overlay->bpp >> 3);
319 offset += overlay->fb_y * overlay->pitch;
321 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
323 win_data = &ctx->win_data[win];
325 win_data->offset_x = overlay->crtc_x;
326 win_data->offset_y = overlay->crtc_y;
327 win_data->ovl_width = overlay->crtc_width;
328 win_data->ovl_height = overlay->crtc_height;
329 win_data->fb_width = overlay->fb_width;
330 win_data->fb_height = overlay->fb_height;
331 win_data->dma_addr = overlay->dma_addr[0] + offset;
332 win_data->vaddr = overlay->vaddr[0] + offset;
333 win_data->bpp = overlay->bpp;
334 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
336 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
338 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
339 win_data->offset_x, win_data->offset_y);
340 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
341 win_data->ovl_width, win_data->ovl_height);
342 DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
343 (unsigned long)win_data->dma_addr,
344 (unsigned long)win_data->vaddr);
345 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
346 overlay->fb_width, overlay->crtc_width);
349 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
351 struct fimd_context *ctx = get_fimd_context(dev);
352 struct fimd_win_data *win_data = &ctx->win_data[win];
355 DRM_DEBUG_KMS("%s\n", __FILE__);
359 switch (win_data->bpp) {
361 val |= WINCON0_BPPMODE_1BPP;
362 val |= WINCONx_BITSWP;
363 val |= WINCONx_BURSTLEN_4WORD;
366 val |= WINCON0_BPPMODE_2BPP;
367 val |= WINCONx_BITSWP;
368 val |= WINCONx_BURSTLEN_8WORD;
371 val |= WINCON0_BPPMODE_4BPP;
372 val |= WINCONx_BITSWP;
373 val |= WINCONx_BURSTLEN_8WORD;
376 val |= WINCON0_BPPMODE_8BPP_PALETTE;
377 val |= WINCONx_BURSTLEN_8WORD;
378 val |= WINCONx_BYTSWP;
381 val |= WINCON0_BPPMODE_16BPP_565;
382 val |= WINCONx_HAWSWP;
383 val |= WINCONx_BURSTLEN_16WORD;
386 val |= WINCON0_BPPMODE_24BPP_888;
388 val |= WINCONx_BURSTLEN_16WORD;
391 val |= WINCON1_BPPMODE_28BPP_A4888
392 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
394 val |= WINCONx_BURSTLEN_16WORD;
397 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
399 val |= WINCON0_BPPMODE_24BPP_888;
401 val |= WINCONx_BURSTLEN_16WORD;
405 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
407 writel(val, ctx->regs + WINCON(win));
410 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
412 struct fimd_context *ctx = get_fimd_context(dev);
413 unsigned int keycon0 = 0, keycon1 = 0;
415 DRM_DEBUG_KMS("%s\n", __FILE__);
417 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
418 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
420 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
422 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
423 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
426 static void fimd_win_commit(struct device *dev, int zpos)
428 struct fimd_context *ctx = get_fimd_context(dev);
429 struct fimd_win_data *win_data;
431 unsigned long val, alpha, size;
433 DRM_DEBUG_KMS("%s\n", __FILE__);
438 if (win == DEFAULT_ZPOS)
439 win = ctx->default_win;
441 if (win < 0 || win > WINDOWS_NR)
444 win_data = &ctx->win_data[win];
447 * SHADOWCON register is used for enabling timing.
449 * for example, once only width value of a register is set,
450 * if the dma is started then fimd hardware could malfunction so
451 * with protect window setting, the register fields with prefix '_F'
452 * wouldn't be updated at vsync also but updated once unprotect window
456 /* protect windows */
457 val = readl(ctx->regs + SHADOWCON);
458 val |= SHADOWCON_WINx_PROTECT(win);
459 writel(val, ctx->regs + SHADOWCON);
461 /* buffer start address */
462 val = (unsigned long)win_data->dma_addr;
463 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
465 /* buffer end address */
466 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
467 val = (unsigned long)(win_data->dma_addr + size);
468 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
470 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
471 (unsigned long)win_data->dma_addr, val, size);
472 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
473 win_data->ovl_width, win_data->ovl_height);
476 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
477 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
478 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
481 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
482 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
483 writel(val, ctx->regs + VIDOSD_A(win));
485 val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
486 win_data->ovl_width - 1) |
487 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
488 win_data->ovl_height - 1);
489 writel(val, ctx->regs + VIDOSD_B(win));
491 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
492 win_data->offset_x, win_data->offset_y,
493 win_data->offset_x + win_data->ovl_width - 1,
494 win_data->offset_y + win_data->ovl_height - 1);
496 /* hardware window 0 doesn't support alpha channel. */
499 alpha = VIDISD14C_ALPHA1_R(0xf) |
500 VIDISD14C_ALPHA1_G(0xf) |
501 VIDISD14C_ALPHA1_B(0xf);
503 writel(alpha, ctx->regs + VIDOSD_C(win));
507 if (win != 3 && win != 4) {
508 u32 offset = VIDOSD_D(win);
510 offset = VIDOSD_C_SIZE_W0;
511 val = win_data->ovl_width * win_data->ovl_height;
512 writel(val, ctx->regs + offset);
514 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
517 fimd_win_set_pixfmt(dev, win);
519 /* hardware window 0 doesn't support color key. */
521 fimd_win_set_colkey(dev, win);
524 val = readl(ctx->regs + WINCON(win));
525 val |= WINCONx_ENWIN;
526 writel(val, ctx->regs + WINCON(win));
528 /* Enable DMA channel and unprotect windows */
529 val = readl(ctx->regs + SHADOWCON);
530 val |= SHADOWCON_CHx_ENABLE(win);
531 val &= ~SHADOWCON_WINx_PROTECT(win);
532 writel(val, ctx->regs + SHADOWCON);
534 win_data->enabled = true;
537 static void fimd_win_disable(struct device *dev, int zpos)
539 struct fimd_context *ctx = get_fimd_context(dev);
540 struct fimd_win_data *win_data;
544 DRM_DEBUG_KMS("%s\n", __FILE__);
546 if (win == DEFAULT_ZPOS)
547 win = ctx->default_win;
549 if (win < 0 || win > WINDOWS_NR)
552 win_data = &ctx->win_data[win];
554 /* protect windows */
555 val = readl(ctx->regs + SHADOWCON);
556 val |= SHADOWCON_WINx_PROTECT(win);
557 writel(val, ctx->regs + SHADOWCON);
560 val = readl(ctx->regs + WINCON(win));
561 val &= ~WINCONx_ENWIN;
562 writel(val, ctx->regs + WINCON(win));
564 /* unprotect windows */
565 val = readl(ctx->regs + SHADOWCON);
566 val &= ~SHADOWCON_CHx_ENABLE(win);
567 val &= ~SHADOWCON_WINx_PROTECT(win);
568 writel(val, ctx->regs + SHADOWCON);
570 win_data->enabled = false;
573 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
574 .mode_set = fimd_win_mode_set,
575 .commit = fimd_win_commit,
576 .disable = fimd_win_disable,
579 static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
581 struct exynos_drm_private *dev_priv = drm_dev->dev_private;
582 struct drm_pending_vblank_event *e, *t;
585 bool is_checked = false;
587 spin_lock_irqsave(&drm_dev->event_lock, flags);
589 list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
591 /* if event's pipe isn't same as crtc then ignore it. */
597 do_gettimeofday(&now);
598 e->event.sequence = 0;
599 e->event.tv_sec = now.tv_sec;
600 e->event.tv_usec = now.tv_usec;
602 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
603 wake_up_interruptible(&e->base.file_priv->event_wait);
608 * call drm_vblank_put only in case that drm_vblank_get was
611 if (atomic_read(&drm_dev->vblank_refcount[crtc]) > 0)
612 drm_vblank_put(drm_dev, crtc);
615 * don't off vblank if vblank_disable_allowed is 1,
616 * because vblank would be off by timer handler.
618 if (!drm_dev->vblank_disable_allowed)
619 drm_vblank_off(drm_dev, crtc);
622 spin_unlock_irqrestore(&drm_dev->event_lock, flags);
625 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
627 struct fimd_context *ctx = (struct fimd_context *)dev_id;
628 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
629 struct drm_device *drm_dev = subdrv->drm_dev;
630 struct exynos_drm_manager *manager = &subdrv->manager;
633 val = readl(ctx->regs + VIDINTCON1);
635 if (val & VIDINTCON1_INT_FRAME)
636 /* VSYNC interrupt */
637 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
639 /* check the crtc is detached already from encoder */
640 if (manager->pipe < 0)
643 drm_handle_vblank(drm_dev, manager->pipe);
644 fimd_finish_pageflip(drm_dev, manager->pipe);
650 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
652 DRM_DEBUG_KMS("%s\n", __FILE__);
655 * enable drm irq mode.
656 * - with irq_enabled = 1, we can use the vblank feature.
658 * P.S. note that we wouldn't use drm irq handler but
659 * just specific driver own one instead because
660 * drm framework supports only one irq handler.
662 drm_dev->irq_enabled = 1;
665 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
666 * by drm timer once a current process gives up ownership of
667 * vblank event.(after drm_vblank_put function is called)
669 drm_dev->vblank_disable_allowed = 1;
674 static void fimd_subdrv_remove(struct drm_device *drm_dev)
676 DRM_DEBUG_KMS("%s\n", __FILE__);
681 static int fimd_calc_clkdiv(struct fimd_context *ctx,
682 struct fb_videomode *timing)
684 unsigned long clk = clk_get_rate(ctx->lcd_clk);
687 u32 best_framerate = 0;
690 DRM_DEBUG_KMS("%s\n", __FILE__);
692 retrace = timing->left_margin + timing->hsync_len +
693 timing->right_margin + timing->xres;
694 retrace *= timing->upper_margin + timing->vsync_len +
695 timing->lower_margin + timing->yres;
697 /* default framerate is 60Hz */
698 if (!timing->refresh)
699 timing->refresh = 60;
703 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
706 /* get best framerate */
707 framerate = clk / clkdiv;
708 tmp = timing->refresh - framerate;
710 best_framerate = framerate;
714 best_framerate = framerate;
715 else if (tmp < (best_framerate - framerate))
716 best_framerate = framerate;
724 static void fimd_clear_win(struct fimd_context *ctx, int win)
728 DRM_DEBUG_KMS("%s\n", __FILE__);
730 writel(0, ctx->regs + WINCON(win));
731 writel(0, ctx->regs + VIDOSD_A(win));
732 writel(0, ctx->regs + VIDOSD_B(win));
733 writel(0, ctx->regs + VIDOSD_C(win));
735 if (win == 1 || win == 2)
736 writel(0, ctx->regs + VIDOSD_D(win));
738 val = readl(ctx->regs + SHADOWCON);
739 val &= ~SHADOWCON_WINx_PROTECT(win);
740 writel(val, ctx->regs + SHADOWCON);
743 static int fimd_power_on(struct fimd_context *ctx, bool enable)
745 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
746 struct device *dev = subdrv->manager.dev;
748 DRM_DEBUG_KMS("%s\n", __FILE__);
750 if (enable != false && enable != true)
756 ret = clk_enable(ctx->bus_clk);
760 ret = clk_enable(ctx->lcd_clk);
762 clk_disable(ctx->bus_clk);
766 ctx->suspended = false;
768 /* if vblank was enabled status, enable it again. */
769 if (test_and_clear_bit(0, &ctx->irq_flags))
770 fimd_enable_vblank(dev);
774 clk_disable(ctx->lcd_clk);
775 clk_disable(ctx->bus_clk);
777 ctx->suspended = true;
783 static int __devinit fimd_probe(struct platform_device *pdev)
785 struct device *dev = &pdev->dev;
786 struct fimd_context *ctx;
787 struct exynos_drm_subdrv *subdrv;
788 struct exynos_drm_fimd_pdata *pdata;
789 struct fb_videomode *timing;
790 struct resource *res;
794 DRM_DEBUG_KMS("%s\n", __FILE__);
796 pdata = pdev->dev.platform_data;
798 dev_err(dev, "no platform data specified\n");
802 timing = &pdata->timing;
804 dev_err(dev, "timing is null.\n");
808 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
812 ctx->bus_clk = clk_get(dev, "fimd");
813 if (IS_ERR(ctx->bus_clk)) {
814 dev_err(dev, "failed to get bus clock\n");
815 ret = PTR_ERR(ctx->bus_clk);
819 clk_enable(ctx->bus_clk);
821 ctx->lcd_clk = clk_get(dev, "sclk_fimd");
822 if (IS_ERR(ctx->lcd_clk)) {
823 dev_err(dev, "failed to get lcd clock\n");
824 ret = PTR_ERR(ctx->lcd_clk);
828 clk_enable(ctx->lcd_clk);
830 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832 dev_err(dev, "failed to find registers\n");
837 ctx->regs_res = request_mem_region(res->start, resource_size(res),
839 if (!ctx->regs_res) {
840 dev_err(dev, "failed to claim register region\n");
845 ctx->regs = ioremap(res->start, resource_size(res));
847 dev_err(dev, "failed to map registers\n");
849 goto err_req_region_io;
852 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
854 dev_err(dev, "irq request failed.\n");
855 goto err_req_region_irq;
858 ctx->irq = res->start;
860 ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
862 dev_err(dev, "irq request failed.\n");
866 ctx->clkdiv = fimd_calc_clkdiv(ctx, timing);
867 ctx->vidcon0 = pdata->vidcon0;
868 ctx->vidcon1 = pdata->vidcon1;
869 ctx->default_win = pdata->default_win;
870 ctx->timing = timing;
872 timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
874 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
875 timing->pixclock, ctx->clkdiv);
877 subdrv = &ctx->subdrv;
879 subdrv->probe = fimd_subdrv_probe;
880 subdrv->remove = fimd_subdrv_remove;
881 subdrv->manager.pipe = -1;
882 subdrv->manager.ops = &fimd_manager_ops;
883 subdrv->manager.overlay_ops = &fimd_overlay_ops;
884 subdrv->manager.display_ops = &fimd_display_ops;
885 subdrv->manager.dev = dev;
887 mutex_init(&ctx->lock);
889 platform_set_drvdata(pdev, ctx);
891 pm_runtime_set_active(dev);
892 pm_runtime_enable(dev);
893 pm_runtime_get_sync(dev);
895 for (win = 0; win < WINDOWS_NR; win++)
896 fimd_clear_win(ctx, win);
898 exynos_drm_subdrv_register(subdrv);
907 release_resource(ctx->regs_res);
908 kfree(ctx->regs_res);
911 clk_disable(ctx->lcd_clk);
912 clk_put(ctx->lcd_clk);
915 clk_disable(ctx->bus_clk);
916 clk_put(ctx->bus_clk);
923 static int __devexit fimd_remove(struct platform_device *pdev)
925 struct device *dev = &pdev->dev;
926 struct fimd_context *ctx = platform_get_drvdata(pdev);
928 DRM_DEBUG_KMS("%s\n", __FILE__);
930 exynos_drm_subdrv_unregister(&ctx->subdrv);
935 clk_disable(ctx->lcd_clk);
936 clk_disable(ctx->bus_clk);
938 pm_runtime_set_suspended(dev);
939 pm_runtime_put_sync(dev);
942 pm_runtime_disable(dev);
944 clk_put(ctx->lcd_clk);
945 clk_put(ctx->bus_clk);
948 release_resource(ctx->regs_res);
949 kfree(ctx->regs_res);
950 free_irq(ctx->irq, ctx);
957 #ifdef CONFIG_PM_SLEEP
958 static int fimd_suspend(struct device *dev)
960 struct fimd_context *ctx = get_fimd_context(dev);
962 if (pm_runtime_suspended(dev))
966 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
967 * called here, an error would be returned by that interface
968 * because the usage_count of pm runtime is more than 1.
970 return fimd_power_on(ctx, false);
973 static int fimd_resume(struct device *dev)
975 struct fimd_context *ctx = get_fimd_context(dev);
978 * if entered to sleep when lcd panel was on, the usage_count
979 * of pm runtime would still be 1 so in this case, fimd driver
980 * should be on directly not drawing on pm runtime interface.
982 if (!pm_runtime_suspended(dev))
983 return fimd_power_on(ctx, true);
989 #ifdef CONFIG_PM_RUNTIME
990 static int fimd_runtime_suspend(struct device *dev)
992 struct fimd_context *ctx = get_fimd_context(dev);
994 DRM_DEBUG_KMS("%s\n", __FILE__);
996 return fimd_power_on(ctx, false);
999 static int fimd_runtime_resume(struct device *dev)
1001 struct fimd_context *ctx = get_fimd_context(dev);
1003 DRM_DEBUG_KMS("%s\n", __FILE__);
1005 return fimd_power_on(ctx, true);
1009 static const struct dev_pm_ops fimd_pm_ops = {
1010 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1011 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1014 static struct platform_driver fimd_driver = {
1015 .probe = fimd_probe,
1016 .remove = __devexit_p(fimd_remove),
1018 .name = "exynos4-fb",
1019 .owner = THIS_MODULE,
1024 static int __init fimd_init(void)
1026 return platform_driver_register(&fimd_driver);
1029 static void __exit fimd_exit(void)
1031 platform_driver_unregister(&fimd_driver);
1034 module_init(fimd_init);
1035 module_exit(fimd_exit);
1037 MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
1038 MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
1039 MODULE_DESCRIPTION("Samsung DRM FIMD Driver");
1040 MODULE_LICENSE("GPL");