drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc_helper.h"
  34 #include "drm_fb_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include <linux/pci.h>
  40 #include <linux/vgaarb.h>
  41 #include <linux/acpi.h>
  42 #include <linux/pnp.h>
  43 #include <linux/vga_switcheroo.h>
  44 #include <linux/slab.h>
  45 #include <acpi/video.h>
  46 #include <asm/pat.h>
  47
  48 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  49
  50 #define BEGIN_LP_RING(n) \
  51         intel_ring_begin(LP_RING(dev_priv), (n))
  52
  53 #define OUT_RING(x) \
  54         intel_ring_emit(LP_RING(dev_priv), x)
  55
  56 #define ADVANCE_LP_RING() \
  57         intel_ring_advance(LP_RING(dev_priv))
  58
  59 /**
  60  * Lock test for when it's just for synchronization of ring access.
  61  *
  62  * In that case, we don't need to do it when GEM is initialized as nobody else
  63  * has access to the ring.
  64  */
  65 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  66         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  67                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  68 } while (0)
  69
  70 static inline u32
  71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  72 {
  73         if (I915_NEED_GFX_HWS(dev_priv->dev))
  74                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  75         else
  76                 return intel_read_status_page(LP_RING(dev_priv), reg);
  77 }
  78
  79 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  80 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  81 #define I915_BREADCRUMB_INDEX           0x21
  82
  83 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  84 {
  85         drm_i915_private_t *dev_priv = dev->dev_private;
  86         struct drm_i915_master_private *master_priv;
  87
  88         if (dev->primary->master) {
  89                 master_priv = dev->primary->master->driver_priv;
  90                 if (master_priv->sarea_priv)
  91                         master_priv->sarea_priv->last_dispatch =
  92                                 READ_BREADCRUMB(dev_priv);
  93         }
  94 }
  95
  96 static void i915_write_hws_pga(struct drm_device *dev)
  97 {
  98         drm_i915_private_t *dev_priv = dev->dev_private;
  99         u32 addr;
 100
 101         addr = dev_priv->status_page_dmah->busaddr;
 102         if (INTEL_INFO(dev)->gen >= 4)
 103                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 104         I915_WRITE(HWS_PGA, addr);
 105 }
 106
 107 /**
 108  * Sets up the hardware status page for devices that need a physical address
 109  * in the register.
 110  */
 111 static int i915_init_phys_hws(struct drm_device *dev)
 112 {
 113         drm_i915_private_t *dev_priv = dev->dev_private;
 114
 115         /* Program Hardware Status Page */
 116         dev_priv->status_page_dmah =
 117                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
 118
 119         if (!dev_priv->status_page_dmah) {
 120                 DRM_ERROR("Can not allocate hardware status page\n");
 121                 return -ENOMEM;
 122         }
 123
 124         memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
 125                   0, PAGE_SIZE);
 126
 127         i915_write_hws_pga(dev);
 128
 129         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 130         return 0;
 131 }
 132
 133 /**
 134  * Frees the hardware status page, whether it's a physical address or a virtual
 135  * address set up by the X Server.
 136  */
 137 static void i915_free_hws(struct drm_device *dev)
 138 {
 139         drm_i915_private_t *dev_priv = dev->dev_private;
 140         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 141
 142         if (dev_priv->status_page_dmah) {
 143                 drm_pci_free(dev, dev_priv->status_page_dmah);
 144                 dev_priv->status_page_dmah = NULL;
 145         }
 146
 147         if (ring->status_page.gfx_addr) {
 148                 ring->status_page.gfx_addr = 0;
 149                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 150         }
 151
 152         /* Need to rewrite hardware status page */
 153         I915_WRITE(HWS_PGA, 0x1ffff000);
 154 }
 155
 156 void i915_kernel_lost_context(struct drm_device * dev)
 157 {
 158         drm_i915_private_t *dev_priv = dev->dev_private;
 159         struct drm_i915_master_private *master_priv;
 160         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 161
 162         /*
 163          * We should never lose context on the ring with modesetting
 164          * as we don't expose it to userspace
 165          */
 166         if (drm_core_check_feature(dev, DRIVER_MODESET))
 167                 return;
 168
 169         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 170         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 171         ring->space = ring->head - (ring->tail + 8);
 172         if (ring->space < 0)
 173                 ring->space += ring->size;
 174
 175         if (!dev->primary->master)
 176                 return;
 177
 178         master_priv = dev->primary->master->driver_priv;
 179         if (ring->head == ring->tail && master_priv->sarea_priv)
 180                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 181 }
 182
 183 static int i915_dma_cleanup(struct drm_device * dev)
 184 {
 185         drm_i915_private_t *dev_priv = dev->dev_private;
 186         int i;
 187
 188         /* Make sure interrupts are disabled here because the uninstall ioctl
 189          * may not have been called from userspace and after dev_private
 190          * is freed, it's too late.
 191          */
 192         if (dev->irq_enabled)
 193                 drm_irq_uninstall(dev);
 194
 195         mutex_lock(&dev->struct_mutex);
 196         for (i = 0; i < I915_NUM_RINGS; i++)
 197                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 198         mutex_unlock(&dev->struct_mutex);
 199
 200         /* Clear the HWS virtual address at teardown */
 201         if (I915_NEED_GFX_HWS(dev))
 202                 i915_free_hws(dev);
 203
 204         return 0;
 205 }
 206
 207 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 208 {
 209         drm_i915_private_t *dev_priv = dev->dev_private;
 210         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 211         int ret;
 212
 213         master_priv->sarea = drm_getsarea(dev);
 214         if (master_priv->sarea) {
 215                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 216                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 217         } else {
 218                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 219         }
 220
 221         if (init->ring_size != 0) {
 222                 if (LP_RING(dev_priv)->obj != NULL) {
 223                         i915_dma_cleanup(dev);
 224                         DRM_ERROR("Client tried to initialize ringbuffer in "
 225                                   "GEM mode\n");
 226                         return -EINVAL;
 227                 }
 228
 229                 ret = intel_render_ring_init_dri(dev,
 230                                                  init->ring_start,
 231                                                  init->ring_size);
 232                 if (ret) {
 233                         i915_dma_cleanup(dev);
 234                         return ret;
 235                 }
 236         }
 237
 238         dev_priv->dri1.cpp = init->cpp;
 239         dev_priv->dri1.back_offset = init->back_offset;
 240         dev_priv->dri1.front_offset = init->front_offset;
 241         dev_priv->dri1.current_page = 0;
 242         if (master_priv->sarea_priv)
 243                 master_priv->sarea_priv->pf_current_page = 0;
 244
 245         /* Allow hardware batchbuffers unless told otherwise.
 246          */
 247         dev_priv->dri1.allow_batchbuffer = 1;
 248
 249         return 0;
 250 }
 251
 252 static int i915_dma_resume(struct drm_device * dev)
 253 {
 254         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 255         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 256
 257         DRM_DEBUG_DRIVER("%s\n", __func__);
 258
 259         if (ring->virtual_start == NULL) {
 260                 DRM_ERROR("can not ioremap virtual address for"
 261                           " ring buffer\n");
 262                 return -ENOMEM;
 263         }
 264
 265         /* Program Hardware Status Page */
 266         if (!ring->status_page.page_addr) {
 267                 DRM_ERROR("Can not find hardware status page\n");
 268                 return -EINVAL;
 269         }
 270         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 271                                 ring->status_page.page_addr);
 272         if (ring->status_page.gfx_addr != 0)
 273                 intel_ring_setup_status_page(ring);
 274         else
 275                 i915_write_hws_pga(dev);
 276
 277         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 278
 279         return 0;
 280 }
 281
 282 static int i915_dma_init(struct drm_device *dev, void *data,
 283                          struct drm_file *file_priv)
 284 {
 285         drm_i915_init_t *init = data;
 286         int retcode = 0;
 287
 288         if (drm_core_check_feature(dev, DRIVER_MODESET))
 289                 return -ENODEV;
 290
 291         switch (init->func) {
 292         case I915_INIT_DMA:
 293                 retcode = i915_initialize(dev, init);
 294                 break;
 295         case I915_CLEANUP_DMA:
 296                 retcode = i915_dma_cleanup(dev);
 297                 break;
 298         case I915_RESUME_DMA:
 299                 retcode = i915_dma_resume(dev);
 300                 break;
 301         default:
 302                 retcode = -EINVAL;
 303                 break;
 304         }
 305
 306         return retcode;
 307 }
 308
 309 /* Implement basically the same security restrictions as hardware does
 310  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 311  *
 312  * Most of the calculations below involve calculating the size of a
 313  * particular instruction.  It's important to get the size right as
 314  * that tells us where the next instruction to check is.  Any illegal
 315  * instruction detected will be given a size of zero, which is a
 316  * signal to abort the rest of the buffer.
 317  */
 318 static int validate_cmd(int cmd)
 319 {
 320         switch (((cmd >> 29) & 0x7)) {
 321         case 0x0:
 322                 switch ((cmd >> 23) & 0x3f) {
 323                 case 0x0:
 324                         return 1;       /* MI_NOOP */
 325                 case 0x4:
 326                         return 1;       /* MI_FLUSH */
 327                 default:
 328                         return 0;       /* disallow everything else */
 329                 }
 330                 break;
 331         case 0x1:
 332                 return 0;       /* reserved */
 333         case 0x2:
 334                 return (cmd & 0xff) + 2;        /* 2d commands */
 335         case 0x3:
 336                 if (((cmd >> 24) & 0x1f) <= 0x18)
 337                         return 1;
 338
 339                 switch ((cmd >> 24) & 0x1f) {
 340                 case 0x1c:
 341                         return 1;
 342                 case 0x1d:
 343                         switch ((cmd >> 16) & 0xff) {
 344                         case 0x3:
 345                                 return (cmd & 0x1f) + 2;
 346                         case 0x4:
 347                                 return (cmd & 0xf) + 2;
 348                         default:
 349                                 return (cmd & 0xffff) + 2;
 350                         }
 351                 case 0x1e:
 352                         if (cmd & (1 << 23))
 353                                 return (cmd & 0xffff) + 1;
 354                         else
 355                                 return 1;
 356                 case 0x1f:
 357                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 358                                 return (cmd & 0x1ffff) + 2;
 359                         else if (cmd & (1 << 17))       /* indirect random */
 360                                 if ((cmd & 0xffff) == 0)
 361                                         return 0;       /* unknown length, too hard */
 362                                 else
 363                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 364                         else
 365                                 return 2;       /* indirect sequential */
 366                 default:
 367                         return 0;
 368                 }
 369         default:
 370                 return 0;
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 377 {
 378         drm_i915_private_t *dev_priv = dev->dev_private;
 379         int i, ret;
 380
 381         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 382                 return -EINVAL;
 383
 384         for (i = 0; i < dwords;) {
 385                 int sz = validate_cmd(buffer[i]);
 386                 if (sz == 0 || i + sz > dwords)
 387                         return -EINVAL;
 388                 i += sz;
 389         }
 390
 391         ret = BEGIN_LP_RING((dwords+1)&~1);
 392         if (ret)
 393                 return ret;
 394
 395         for (i = 0; i < dwords; i++)
 396                 OUT_RING(buffer[i]);
 397         if (dwords & 1)
 398                 OUT_RING(0);
 399
 400         ADVANCE_LP_RING();
 401
 402         return 0;
 403 }
 404
 405 int
 406 i915_emit_box(struct drm_device *dev,
 407               struct drm_clip_rect *box,
 408               int DR1, int DR4)
 409 {
 410         struct drm_i915_private *dev_priv = dev->dev_private;
 411         int ret;
 412
 413         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 414             box->y2 <= 0 || box->x2 <= 0) {
 415                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 416                           box->x1, box->y1, box->x2, box->y2);
 417                 return -EINVAL;
 418         }
 419
 420         if (INTEL_INFO(dev)->gen >= 4) {
 421                 ret = BEGIN_LP_RING(4);
 422                 if (ret)
 423                         return ret;
 424
 425                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 426                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 427                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 428                 OUT_RING(DR4);
 429         } else {
 430                 ret = BEGIN_LP_RING(6);
 431                 if (ret)
 432                         return ret;
 433
 434                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 435                 OUT_RING(DR1);
 436                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 437                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 438                 OUT_RING(DR4);
 439                 OUT_RING(0);
 440         }
 441         ADVANCE_LP_RING();
 442
 443         return 0;
 444 }
 445
 446 /* XXX: Emitting the counter should really be moved to part of the IRQ
 447  * emit. For now, do it in both places:
 448  */
 449
 450 static void i915_emit_breadcrumb(struct drm_device *dev)
 451 {
 452         drm_i915_private_t *dev_priv = dev->dev_private;
 453         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 454
 455         dev_priv->counter++;
 456         if (dev_priv->counter > 0x7FFFFFFFUL)
 457                 dev_priv->counter = 0;
 458         if (master_priv->sarea_priv)
 459                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 460
 461         if (BEGIN_LP_RING(4) == 0) {
 462                 OUT_RING(MI_STORE_DWORD_INDEX);
 463                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 464                 OUT_RING(dev_priv->counter);
 465                 OUT_RING(0);
 466                 ADVANCE_LP_RING();
 467         }
 468 }
 469
 470 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 471                                    drm_i915_cmdbuffer_t *cmd,
 472                                    struct drm_clip_rect *cliprects,
 473                                    void *cmdbuf)
 474 {
 475         int nbox = cmd->num_cliprects;
 476         int i = 0, count, ret;
 477
 478         if (cmd->sz & 0x3) {
 479                 DRM_ERROR("alignment");
 480                 return -EINVAL;
 481         }
 482
 483         i915_kernel_lost_context(dev);
 484
 485         count = nbox ? nbox : 1;
 486
 487         for (i = 0; i < count; i++) {
 488                 if (i < nbox) {
 489                         ret = i915_emit_box(dev, &cliprects[i],
 490                                             cmd->DR1, cmd->DR4);
 491                         if (ret)
 492                                 return ret;
 493                 }
 494
 495                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 496                 if (ret)
 497                         return ret;
 498         }
 499
 500         i915_emit_breadcrumb(dev);
 501         return 0;
 502 }
 503
 504 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 505                                      drm_i915_batchbuffer_t * batch,
 506                                      struct drm_clip_rect *cliprects)
 507 {
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         int nbox = batch->num_cliprects;
 510         int i, count, ret;
 511
 512         if ((batch->start | batch->used) & 0x7) {
 513                 DRM_ERROR("alignment");
 514                 return -EINVAL;
 515         }
 516
 517         i915_kernel_lost_context(dev);
 518
 519         count = nbox ? nbox : 1;
 520         for (i = 0; i < count; i++) {
 521                 if (i < nbox) {
 522                         ret = i915_emit_box(dev, &cliprects[i],
 523                                             batch->DR1, batch->DR4);
 524                         if (ret)
 525                                 return ret;
 526                 }
 527
 528                 if (!IS_I830(dev) && !IS_845G(dev)) {
 529                         ret = BEGIN_LP_RING(2);
 530                         if (ret)
 531                                 return ret;
 532
 533                         if (INTEL_INFO(dev)->gen >= 4) {
 534                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 535                                 OUT_RING(batch->start);
 536                         } else {
 537                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 538                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 539                         }
 540                 } else {
 541                         ret = BEGIN_LP_RING(4);
 542                         if (ret)
 543                                 return ret;
 544
 545                         OUT_RING(MI_BATCH_BUFFER);
 546                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 547                         OUT_RING(batch->start + batch->used - 4);
 548                         OUT_RING(0);
 549                 }
 550                 ADVANCE_LP_RING();
 551         }
 552
 553
 554         if (IS_G4X(dev) || IS_GEN5(dev)) {
 555                 if (BEGIN_LP_RING(2) == 0) {
 556                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 557                         OUT_RING(MI_NOOP);
 558                         ADVANCE_LP_RING();
 559                 }
 560         }
 561
 562         i915_emit_breadcrumb(dev);
 563         return 0;
 564 }
 565
 566 static int i915_dispatch_flip(struct drm_device * dev)
 567 {
 568         drm_i915_private_t *dev_priv = dev->dev_private;
 569         struct drm_i915_master_private *master_priv =
 570                 dev->primary->master->driver_priv;
 571         int ret;
 572
 573         if (!master_priv->sarea_priv)
 574                 return -EINVAL;
 575
 576         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 577                           __func__,
 578                          dev_priv->dri1.current_page,
 579                          master_priv->sarea_priv->pf_current_page);
 580
 581         i915_kernel_lost_context(dev);
 582
 583         ret = BEGIN_LP_RING(10);
 584         if (ret)
 585                 return ret;
 586
 587         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 588         OUT_RING(0);
 589
 590         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 591         OUT_RING(0);
 592         if (dev_priv->dri1.current_page == 0) {
 593                 OUT_RING(dev_priv->dri1.back_offset);
 594                 dev_priv->dri1.current_page = 1;
 595         } else {
 596                 OUT_RING(dev_priv->dri1.front_offset);
 597                 dev_priv->dri1.current_page = 0;
 598         }
 599         OUT_RING(0);
 600
 601         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 602         OUT_RING(0);
 603
 604         ADVANCE_LP_RING();
 605
 606         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 607
 608         if (BEGIN_LP_RING(4) == 0) {
 609                 OUT_RING(MI_STORE_DWORD_INDEX);
 610                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 611                 OUT_RING(dev_priv->counter);
 612                 OUT_RING(0);
 613                 ADVANCE_LP_RING();
 614         }
 615
 616         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 617         return 0;
 618 }
 619
 620 static int i915_quiescent(struct drm_device *dev)
 621 {
 622         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 623
 624         i915_kernel_lost_context(dev);
 625         return intel_wait_ring_idle(ring);
 626 }
 627
 628 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 629                             struct drm_file *file_priv)
 630 {
 631         int ret;
 632
 633         if (drm_core_check_feature(dev, DRIVER_MODESET))
 634                 return -ENODEV;
 635
 636         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 637
 638         mutex_lock(&dev->struct_mutex);
 639         ret = i915_quiescent(dev);
 640         mutex_unlock(&dev->struct_mutex);
 641
 642         return ret;
 643 }
 644
 645 static int i915_batchbuffer(struct drm_device *dev, void *data,
 646                             struct drm_file *file_priv)
 647 {
 648         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 649         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 650         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 651             master_priv->sarea_priv;
 652         drm_i915_batchbuffer_t *batch = data;
 653         int ret;
 654         struct drm_clip_rect *cliprects = NULL;
 655
 656         if (drm_core_check_feature(dev, DRIVER_MODESET))
 657                 return -ENODEV;
 658
 659         if (!dev_priv->dri1.allow_batchbuffer) {
 660                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 661                 return -EINVAL;
 662         }
 663
 664         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 665                         batch->start, batch->used, batch->num_cliprects);
 666
 667         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 668
 669         if (batch->num_cliprects < 0)
 670                 return -EINVAL;
 671
 672         if (batch->num_cliprects) {
 673                 cliprects = kcalloc(batch->num_cliprects,
 674                                     sizeof(struct drm_clip_rect),
 675                                     GFP_KERNEL);
 676                 if (cliprects == NULL)
 677                         return -ENOMEM;
 678
 679                 ret = copy_from_user(cliprects, batch->cliprects,
 680                                      batch->num_cliprects *
 681                                      sizeof(struct drm_clip_rect));
 682                 if (ret != 0) {
 683                         ret = -EFAULT;
 684                         goto fail_free;
 685                 }
 686         }
 687
 688         mutex_lock(&dev->struct_mutex);
 689         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 690         mutex_unlock(&dev->struct_mutex);
 691
 692         if (sarea_priv)
 693                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 694
 695 fail_free:
 696         kfree(cliprects);
 697
 698         return ret;
 699 }
 700
 701 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 702                           struct drm_file *file_priv)
 703 {
 704         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 705         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 706         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 707             master_priv->sarea_priv;
 708         drm_i915_cmdbuffer_t *cmdbuf = data;
 709         struct drm_clip_rect *cliprects = NULL;
 710         void *batch_data;
 711         int ret;
 712
 713         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 714                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 715
 716         if (drm_core_check_feature(dev, DRIVER_MODESET))
 717                 return -ENODEV;
 718
 719         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 720
 721         if (cmdbuf->num_cliprects < 0)
 722                 return -EINVAL;
 723
 724         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 725         if (batch_data == NULL)
 726                 return -ENOMEM;
 727
 728         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 729         if (ret != 0) {
 730                 ret = -EFAULT;
 731                 goto fail_batch_free;
 732         }
 733
 734         if (cmdbuf->num_cliprects) {
 735                 cliprects = kcalloc(cmdbuf->num_cliprects,
 736                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 737                 if (cliprects == NULL) {
 738                         ret = -ENOMEM;
 739                         goto fail_batch_free;
 740                 }
 741
 742                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 743                                      cmdbuf->num_cliprects *
 744                                      sizeof(struct drm_clip_rect));
 745                 if (ret != 0) {
 746                         ret = -EFAULT;
 747                         goto fail_clip_free;
 748                 }
 749         }
 750
 751         mutex_lock(&dev->struct_mutex);
 752         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 753         mutex_unlock(&dev->struct_mutex);
 754         if (ret) {
 755                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 756                 goto fail_clip_free;
 757         }
 758
 759         if (sarea_priv)
 760                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 761
 762 fail_clip_free:
 763         kfree(cliprects);
 764 fail_batch_free:
 765         kfree(batch_data);
 766
 767         return ret;
 768 }
 769
 770 static int i915_emit_irq(struct drm_device * dev)
 771 {
 772         drm_i915_private_t *dev_priv = dev->dev_private;
 773         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 774
 775         i915_kernel_lost_context(dev);
 776
 777         DRM_DEBUG_DRIVER("\n");
 778
 779         dev_priv->counter++;
 780         if (dev_priv->counter > 0x7FFFFFFFUL)
 781                 dev_priv->counter = 1;
 782         if (master_priv->sarea_priv)
 783                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 784
 785         if (BEGIN_LP_RING(4) == 0) {
 786                 OUT_RING(MI_STORE_DWORD_INDEX);
 787                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 788                 OUT_RING(dev_priv->counter);
 789                 OUT_RING(MI_USER_INTERRUPT);
 790                 ADVANCE_LP_RING();
 791         }
 792
 793         return dev_priv->counter;
 794 }
 795
 796 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 797 {
 798         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 799         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 800         int ret = 0;
 801         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 802
 803         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 804                   READ_BREADCRUMB(dev_priv));
 805
 806         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 807                 if (master_priv->sarea_priv)
 808                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 809                 return 0;
 810         }
 811
 812         if (master_priv->sarea_priv)
 813                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 814
 815         if (ring->irq_get(ring)) {
 816                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 817                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 818                 ring->irq_put(ring);
 819         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 820                 ret = -EBUSY;
 821
 822         if (ret == -EBUSY) {
 823                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 824                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 825         }
 826
 827         return ret;
 828 }
 829
 830 /* Needs the lock as it touches the ring.
 831  */
 832 static int i915_irq_emit(struct drm_device *dev, void *data,
 833                          struct drm_file *file_priv)
 834 {
 835         drm_i915_private_t *dev_priv = dev->dev_private;
 836         drm_i915_irq_emit_t *emit = data;
 837         int result;
 838
 839         if (drm_core_check_feature(dev, DRIVER_MODESET))
 840                 return -ENODEV;
 841
 842         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 843                 DRM_ERROR("called with no initialization\n");
 844                 return -EINVAL;
 845         }
 846
 847         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 848
 849         mutex_lock(&dev->struct_mutex);
 850         result = i915_emit_irq(dev);
 851         mutex_unlock(&dev->struct_mutex);
 852
 853         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 854                 DRM_ERROR("copy_to_user\n");
 855                 return -EFAULT;
 856         }
 857
 858         return 0;
 859 }
 860
 861 /* Doesn't need the hardware lock.
 862  */
 863 static int i915_irq_wait(struct drm_device *dev, void *data,
 864                          struct drm_file *file_priv)
 865 {
 866         drm_i915_private_t *dev_priv = dev->dev_private;
 867         drm_i915_irq_wait_t *irqwait = data;
 868
 869         if (drm_core_check_feature(dev, DRIVER_MODESET))
 870                 return -ENODEV;
 871
 872         if (!dev_priv) {
 873                 DRM_ERROR("called with no initialization\n");
 874                 return -EINVAL;
 875         }
 876
 877         return i915_wait_irq(dev, irqwait->irq_seq);
 878 }
 879
 880 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 881                          struct drm_file *file_priv)
 882 {
 883         drm_i915_private_t *dev_priv = dev->dev_private;
 884         drm_i915_vblank_pipe_t *pipe = data;
 885
 886         if (drm_core_check_feature(dev, DRIVER_MODESET))
 887                 return -ENODEV;
 888
 889         if (!dev_priv) {
 890                 DRM_ERROR("called with no initialization\n");
 891                 return -EINVAL;
 892         }
 893
 894         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 895
 896         return 0;
 897 }
 898
 899 /**
 900  * Schedule buffer swap at given vertical blank.
 901  */
 902 static int i915_vblank_swap(struct drm_device *dev, void *data,
 903                      struct drm_file *file_priv)
 904 {
 905         /* The delayed swap mechanism was fundamentally racy, and has been
 906          * removed.  The model was that the client requested a delayed flip/swap
 907          * from the kernel, then waited for vblank before continuing to perform
 908          * rendering.  The problem was that the kernel might wake the client
 909          * up before it dispatched the vblank swap (since the lock has to be
 910          * held while touching the ringbuffer), in which case the client would
 911          * clear and start the next frame before the swap occurred, and
 912          * flicker would occur in addition to likely missing the vblank.
 913          *
 914          * In the absence of this ioctl, userland falls back to a correct path
 915          * of waiting for a vblank, then dispatching the swap on its own.
 916          * Context switching to userland and back is plenty fast enough for
 917          * meeting the requirements of vblank swapping.
 918          */
 919         return -EINVAL;
 920 }
 921
 922 static int i915_flip_bufs(struct drm_device *dev, void *data,
 923                           struct drm_file *file_priv)
 924 {
 925         int ret;
 926
 927         if (drm_core_check_feature(dev, DRIVER_MODESET))
 928                 return -ENODEV;
 929
 930         DRM_DEBUG_DRIVER("%s\n", __func__);
 931
 932         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 933
 934         mutex_lock(&dev->struct_mutex);
 935         ret = i915_dispatch_flip(dev);
 936         mutex_unlock(&dev->struct_mutex);
 937
 938         return ret;
 939 }
 940
 941 static int i915_getparam(struct drm_device *dev, void *data,
 942                          struct drm_file *file_priv)
 943 {
 944         drm_i915_private_t *dev_priv = dev->dev_private;
 945         drm_i915_getparam_t *param = data;
 946         int value;
 947
 948         if (!dev_priv) {
 949                 DRM_ERROR("called with no initialization\n");
 950                 return -EINVAL;
 951         }
 952
 953         switch (param->param) {
 954         case I915_PARAM_IRQ_ACTIVE:
 955                 value = dev->pdev->irq ? 1 : 0;
 956                 break;
 957         case I915_PARAM_ALLOW_BATCHBUFFER:
 958                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 959                 break;
 960         case I915_PARAM_LAST_DISPATCH:
 961                 value = READ_BREADCRUMB(dev_priv);
 962                 break;
 963         case I915_PARAM_CHIPSET_ID:
 964                 value = dev->pci_device;
 965                 break;
 966         case I915_PARAM_HAS_GEM:
 967                 value = 1;
 968                 break;
 969         case I915_PARAM_NUM_FENCES_AVAIL:
 970                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 971                 break;
 972         case I915_PARAM_HAS_OVERLAY:
 973                 value = dev_priv->overlay ? 1 : 0;
 974                 break;
 975         case I915_PARAM_HAS_PAGEFLIPPING:
 976                 value = 1;
 977                 break;
 978         case I915_PARAM_HAS_EXECBUF2:
 979                 /* depends on GEM */
 980                 value = 1;
 981                 break;
 982         case I915_PARAM_HAS_BSD:
 983                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 984                 break;
 985         case I915_PARAM_HAS_BLT:
 986                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 987                 break;
 988         case I915_PARAM_HAS_RELAXED_FENCING:
 989                 value = 1;
 990                 break;
 991         case I915_PARAM_HAS_COHERENT_RINGS:
 992                 value = 1;
 993                 break;
 994         case I915_PARAM_HAS_EXEC_CONSTANTS:
 995                 value = INTEL_INFO(dev)->gen >= 4;
 996                 break;
 997         case I915_PARAM_HAS_RELAXED_DELTA:
 998                 value = 1;
 999                 break;
1000         case I915_PARAM_HAS_GEN7_SOL_RESET:
1001                 value = 1;
1002                 break;
1003         case I915_PARAM_HAS_LLC:
1004                 value = HAS_LLC(dev);
1005                 break;
1006         case I915_PARAM_HAS_ALIASING_PPGTT:
1007                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1008                 break;
1009         case I915_PARAM_HAS_WAIT_TIMEOUT:
1010                 value = 1;
1011                 break;
1012         case I915_PARAM_HAS_SEMAPHORES:
1013                 value = i915_semaphore_is_enabled(dev);
1014                 break;
1015         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1016                 value = 1;
1017                 break;
1018         case I915_PARAM_HAS_SECURE_BATCHES:
1019                 value = capable(CAP_SYS_ADMIN);
1020                 break;
1021         default:
1022                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1023                                  param->param);
1024                 return -EINVAL;
1025         }
1026
1027         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1028                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1029                 return -EFAULT;
1030         }
1031
1032         return 0;
1033 }
1034
1035 static int i915_setparam(struct drm_device *dev, void *data,
1036                          struct drm_file *file_priv)
1037 {
1038         drm_i915_private_t *dev_priv = dev->dev_private;
1039         drm_i915_setparam_t *param = data;
1040
1041         if (!dev_priv) {
1042                 DRM_ERROR("called with no initialization\n");
1043                 return -EINVAL;
1044         }
1045
1046         switch (param->param) {
1047         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1048                 break;
1049         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1050                 break;
1051         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1052                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1053                 break;
1054         case I915_SETPARAM_NUM_USED_FENCES:
1055                 if (param->value > dev_priv->num_fence_regs ||
1056                     param->value < 0)
1057                         return -EINVAL;
1058                 /* Userspace can use first N regs */
1059                 dev_priv->fence_reg_start = param->value;
1060                 break;
1061         default:
1062                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1063                                         param->param);
1064                 return -EINVAL;
1065         }
1066
1067         return 0;
1068 }
1069
1070 static int i915_set_status_page(struct drm_device *dev, void *data,
1071                                 struct drm_file *file_priv)
1072 {
1073         drm_i915_private_t *dev_priv = dev->dev_private;
1074         drm_i915_hws_addr_t *hws = data;
1075         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1076
1077         if (drm_core_check_feature(dev, DRIVER_MODESET))
1078                 return -ENODEV;
1079
1080         if (!I915_NEED_GFX_HWS(dev))
1081                 return -EINVAL;
1082
1083         if (!dev_priv) {
1084                 DRM_ERROR("called with no initialization\n");
1085                 return -EINVAL;
1086         }
1087
1088         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1089                 WARN(1, "tried to set status page when mode setting active\n");
1090                 return 0;
1091         }
1092
1093         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1094
1095         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1096
1097         dev_priv->dri1.gfx_hws_cpu_addr =
1098                 ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
1099         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1100                 i915_dma_cleanup(dev);
1101                 ring->status_page.gfx_addr = 0;
1102                 DRM_ERROR("can not ioremap virtual address for"
1103                                 " G33 hw status page\n");
1104                 return -ENOMEM;
1105         }
1106
1107         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1108         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1109
1110         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1111                          ring->status_page.gfx_addr);
1112         DRM_DEBUG_DRIVER("load hws at %p\n",
1113                          ring->status_page.page_addr);
1114         return 0;
1115 }
1116
1117 static int i915_get_bridge_dev(struct drm_device *dev)
1118 {
1119         struct drm_i915_private *dev_priv = dev->dev_private;
1120
1121         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1122         if (!dev_priv->bridge_dev) {
1123                 DRM_ERROR("bridge device not found\n");
1124                 return -1;
1125         }
1126         return 0;
1127 }
1128
1129 #define MCHBAR_I915 0x44
1130 #define MCHBAR_I965 0x48
1131 #define MCHBAR_SIZE (4*4096)
1132
1133 #define DEVEN_REG 0x54
1134 #define   DEVEN_MCHBAR_EN (1 << 28)
1135
1136 /* Allocate space for the MCH regs if needed, return nonzero on error */
1137 static int
1138 intel_alloc_mchbar_resource(struct drm_device *dev)
1139 {
1140         drm_i915_private_t *dev_priv = dev->dev_private;
1141         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1142         u32 temp_lo, temp_hi = 0;
1143         u64 mchbar_addr;
1144         int ret;
1145
1146         if (INTEL_INFO(dev)->gen >= 4)
1147                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1148         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1149         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1150
1151         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1152 #ifdef CONFIG_PNP
1153         if (mchbar_addr &&
1154             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1155                 return 0;
1156 #endif
1157
1158         /* Get some space for it */
1159         dev_priv->mch_res.name = "i915 MCHBAR";
1160         dev_priv->mch_res.flags = IORESOURCE_MEM;
1161         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1162                                      &dev_priv->mch_res,
1163                                      MCHBAR_SIZE, MCHBAR_SIZE,
1164                                      PCIBIOS_MIN_MEM,
1165                                      0, pcibios_align_resource,
1166                                      dev_priv->bridge_dev);
1167         if (ret) {
1168                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1169                 dev_priv->mch_res.start = 0;
1170                 return ret;
1171         }
1172
1173         if (INTEL_INFO(dev)->gen >= 4)
1174                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1175                                        upper_32_bits(dev_priv->mch_res.start));
1176
1177         pci_write_config_dword(dev_priv->bridge_dev, reg,
1178                                lower_32_bits(dev_priv->mch_res.start));
1179         return 0;
1180 }
1181
1182 /* Setup MCHBAR if possible, return true if we should disable it again */
1183 static void
1184 intel_setup_mchbar(struct drm_device *dev)
1185 {
1186         drm_i915_private_t *dev_priv = dev->dev_private;
1187         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1188         u32 temp;
1189         bool enabled;
1190
1191         dev_priv->mchbar_need_disable = false;
1192
1193         if (IS_I915G(dev) || IS_I915GM(dev)) {
1194                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1195                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1196         } else {
1197                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1198                 enabled = temp & 1;
1199         }
1200
1201         /* If it's already enabled, don't have to do anything */
1202         if (enabled)
1203                 return;
1204
1205         if (intel_alloc_mchbar_resource(dev))
1206                 return;
1207
1208         dev_priv->mchbar_need_disable = true;
1209
1210         /* Space is allocated or reserved, so enable it. */
1211         if (IS_I915G(dev) || IS_I915GM(dev)) {
1212                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1213                                        temp | DEVEN_MCHBAR_EN);
1214         } else {
1215                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1216                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1217         }
1218 }
1219
1220 static void
1221 intel_teardown_mchbar(struct drm_device *dev)
1222 {
1223         drm_i915_private_t *dev_priv = dev->dev_private;
1224         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1225         u32 temp;
1226
1227         if (dev_priv->mchbar_need_disable) {
1228                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1229                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1230                         temp &= ~DEVEN_MCHBAR_EN;
1231                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1232                 } else {
1233                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1234                         temp &= ~1;
1235                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1236                 }
1237         }
1238
1239         if (dev_priv->mch_res.start)
1240                 release_resource(&dev_priv->mch_res);
1241 }
1242
1243 /* true = enable decode, false = disable decoder */
1244 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1245 {
1246         struct drm_device *dev = cookie;
1247
1248         intel_modeset_vga_set_state(dev, state);
1249         if (state)
1250                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1251                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1252         else
1253                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1254 }
1255
1256 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1257 {
1258         struct drm_device *dev = pci_get_drvdata(pdev);
1259         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1260         if (state == VGA_SWITCHEROO_ON) {
1261                 pr_info("switched on\n");
1262                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1263                 /* i915 resume handler doesn't set to D0 */
1264                 pci_set_power_state(dev->pdev, PCI_D0);
1265                 i915_resume(dev);
1266                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1267         } else {
1268                 pr_err("switched off\n");
1269                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1270                 i915_suspend(dev, pmm);
1271                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1272         }
1273 }
1274
1275 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1276 {
1277         struct drm_device *dev = pci_get_drvdata(pdev);
1278         bool can_switch;
1279
1280         spin_lock(&dev->count_lock);
1281         can_switch = (dev->open_count == 0);
1282         spin_unlock(&dev->count_lock);
1283         return can_switch;
1284 }
1285
1286 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1287         .set_gpu_state = i915_switcheroo_set_state,
1288         .reprobe = NULL,
1289         .can_switch = i915_switcheroo_can_switch,
1290 };
1291
1292 static int i915_load_modeset_init(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295         int ret;
1296
1297         ret = intel_parse_bios(dev);
1298         if (ret)
1299                 DRM_INFO("failed to find VBIOS tables\n");
1300
1301         /* If we have > 1 VGA cards, then we need to arbitrate access
1302          * to the common VGA resources.
1303          *
1304          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1305          * then we do not take part in VGA arbitration and the
1306          * vga_client_register() fails with -ENODEV.
1307          */
1308         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1309         if (ret && ret != -ENODEV)
1310                 goto out;
1311
1312         intel_register_dsm_handler();
1313
1314         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1315         if (ret)
1316                 goto cleanup_vga_client;
1317
1318         /* Initialise stolen first so that we may reserve preallocated
1319          * objects for the BIOS to KMS transition.
1320          */
1321         ret = i915_gem_init_stolen(dev);
1322         if (ret)
1323                 goto cleanup_vga_switcheroo;
1324
1325         intel_modeset_init(dev);
1326
1327         ret = i915_gem_init(dev);
1328         if (ret)
1329                 goto cleanup_gem_stolen;
1330
1331         intel_modeset_gem_init(dev);
1332
1333         ret = drm_irq_install(dev);
1334         if (ret)
1335                 goto cleanup_gem;
1336
1337         /* Always safe in the mode setting case. */
1338         /* FIXME: do pre/post-mode set stuff in core KMS code */
1339         dev->vblank_disable_allowed = 1;
1340
1341         ret = intel_fbdev_init(dev);
1342         if (ret)
1343                 goto cleanup_irq;
1344
1345         drm_kms_helper_poll_init(dev);
1346
1347         /* We're off and running w/KMS */
1348         dev_priv->mm.suspended = 0;
1349
1350         return 0;
1351
1352 cleanup_irq:
1353         drm_irq_uninstall(dev);
1354 cleanup_gem:
1355         mutex_lock(&dev->struct_mutex);
1356         i915_gem_cleanup_ringbuffer(dev);
1357         mutex_unlock(&dev->struct_mutex);
1358         i915_gem_cleanup_aliasing_ppgtt(dev);
1359 cleanup_gem_stolen:
1360         i915_gem_cleanup_stolen(dev);
1361 cleanup_vga_switcheroo:
1362         vga_switcheroo_unregister_client(dev->pdev);
1363 cleanup_vga_client:
1364         vga_client_register(dev->pdev, NULL, NULL, NULL);
1365 out:
1366         return ret;
1367 }
1368
1369 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1370 {
1371         struct drm_i915_master_private *master_priv;
1372
1373         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1374         if (!master_priv)
1375                 return -ENOMEM;
1376
1377         master->driver_priv = master_priv;
1378         return 0;
1379 }
1380
1381 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1382 {
1383         struct drm_i915_master_private *master_priv = master->driver_priv;
1384
1385         if (!master_priv)
1386                 return;
1387
1388         kfree(master_priv);
1389
1390         master->driver_priv = NULL;
1391 }
1392
1393 static void
1394 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1395                 unsigned long size)
1396 {
1397         dev_priv->mm.gtt_mtrr = -1;
1398
1399 #if defined(CONFIG_X86_PAT)
1400         if (cpu_has_pat)
1401                 return;
1402 #endif
1403
1404         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1405          * one would think, because the kernel disables PAT on first
1406          * generation Core chips because WC PAT gets overridden by a UC
1407          * MTRR if present.  Even if a UC MTRR isn't present.
1408          */
1409         dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1410         if (dev_priv->mm.gtt_mtrr < 0) {
1411                 DRM_INFO("MTRR allocation failed.  Graphics "
1412                          "performance may suffer.\n");
1413         }
1414 }
1415
1416 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1417 {
1418         struct apertures_struct *ap;
1419         struct pci_dev *pdev = dev_priv->dev->pdev;
1420         bool primary;
1421
1422         ap = alloc_apertures(1);
1423         if (!ap)
1424                 return;
1425
1426         ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1427         ap->ranges[0].size =
1428                 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1429         primary =
1430                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1431
1432         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1433
1434         kfree(ap);
1435 }
1436
1437 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1438 {
1439         const struct intel_device_info *info = dev_priv->info;
1440
1441 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
1442 #define DEV_INFO_SEP ,
1443         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1444                          "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1445                          info->gen,
1446                          dev_priv->dev->pdev->device,
1447                          DEV_INFO_FLAGS);
1448 #undef DEV_INFO_FLAG
1449 #undef DEV_INFO_SEP
1450 }
1451
1452 /**
1453  * i915_driver_load - setup chip and create an initial config
1454  * @dev: DRM device
1455  * @flags: startup flags
1456  *
1457  * The driver load routine has to do several things:
1458  *   - drive output discovery via intel_modeset_init()
1459  *   - initialize the memory manager
1460  *   - allocate initial config memory
1461  *   - setup the DRM framebuffer with the allocated memory
1462  */
1463 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1464 {
1465         struct drm_i915_private *dev_priv;
1466         struct intel_device_info *info;
1467         int ret = 0, mmio_bar, mmio_size;
1468         uint32_t aperture_size;
1469
1470         info = (struct intel_device_info *) flags;
1471
1472         /* Refuse to load on gen6+ without kms enabled. */
1473         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1474                 return -ENODEV;
1475
1476         /* i915 has 4 more counters */
1477         dev->counters += 4;
1478         dev->types[6] = _DRM_STAT_IRQ;
1479         dev->types[7] = _DRM_STAT_PRIMARY;
1480         dev->types[8] = _DRM_STAT_SECONDARY;
1481         dev->types[9] = _DRM_STAT_DMA;
1482
1483         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1484         if (dev_priv == NULL)
1485                 return -ENOMEM;
1486
1487         dev->dev_private = (void *)dev_priv;
1488         dev_priv->dev = dev;
1489         dev_priv->info = info;
1490
1491         i915_dump_device_info(dev_priv);
1492
1493         if (i915_get_bridge_dev(dev)) {
1494                 ret = -EIO;
1495                 goto free_priv;
1496         }
1497
1498         ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
1499         if (!ret) {
1500                 DRM_ERROR("failed to set up gmch\n");
1501                 ret = -EIO;
1502                 goto put_bridge;
1503         }
1504
1505         dev_priv->mm.gtt = intel_gtt_get();
1506         if (!dev_priv->mm.gtt) {
1507                 DRM_ERROR("Failed to initialize GTT\n");
1508                 ret = -ENODEV;
1509                 goto put_gmch;
1510         }
1511
1512         i915_kick_out_firmware_fb(dev_priv);
1513
1514         pci_set_master(dev->pdev);
1515
1516         /* overlay on gen2 is broken and can't address above 1G */
1517         if (IS_GEN2(dev))
1518                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1519
1520         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1521          * using 32bit addressing, overwriting memory if HWS is located
1522          * above 4GB.
1523          *
1524          * The documentation also mentions an issue with undefined
1525          * behaviour if any general state is accessed within a page above 4GB,
1526          * which also needs to be handled carefully.
1527          */
1528         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1529                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1530
1531         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1532         /* Before gen4, the registers and the GTT are behind different BARs.
1533          * However, from gen4 onwards, the registers and the GTT are shared
1534          * in the same BAR, so we want to restrict this ioremap from
1535          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1536          * the register BAR remains the same size for all the earlier
1537          * generations up to Ironlake.
1538          */
1539         if (info->gen < 5)
1540                 mmio_size = 512*1024;
1541         else
1542                 mmio_size = 2*1024*1024;
1543
1544         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1545         if (!dev_priv->regs) {
1546                 DRM_ERROR("failed to map registers\n");
1547                 ret = -EIO;
1548                 goto put_gmch;
1549         }
1550
1551         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1552         dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1553
1554         dev_priv->mm.gtt_mapping =
1555                 io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1556                                      aperture_size);
1557         if (dev_priv->mm.gtt_mapping == NULL) {
1558                 ret = -EIO;
1559                 goto out_rmmap;
1560         }
1561
1562         i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1563                         aperture_size);
1564
1565         /* The i915 workqueue is primarily used for batched retirement of
1566          * requests (and thus managing bo) once the task has been completed
1567          * by the GPU. i915_gem_retire_requests() is called directly when we
1568          * need high-priority retirement, such as waiting for an explicit
1569          * bo.
1570          *
1571          * It is also used for periodic low-priority events, such as
1572          * idle-timers and recording error state.
1573          *
1574          * All tasks on the workqueue are expected to acquire the dev mutex
1575          * so there is no point in running more than one instance of the
1576          * workqueue at any time.  Use an ordered one.
1577          */
1578         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1579         if (dev_priv->wq == NULL) {
1580                 DRM_ERROR("Failed to create our workqueue.\n");
1581                 ret = -ENOMEM;
1582                 goto out_mtrrfree;
1583         }
1584
1585         /* This must be called before any calls to HAS_PCH_* */
1586         intel_detect_pch(dev);
1587
1588         intel_irq_init(dev);
1589         intel_gt_init(dev);
1590
1591         /* Try to make sure MCHBAR is enabled before poking at it */
1592         intel_setup_mchbar(dev);
1593         intel_setup_gmbus(dev);
1594         intel_opregion_setup(dev);
1595
1596         /* Make sure the bios did its job and set up vital registers */
1597         intel_setup_bios(dev);
1598
1599         i915_gem_load(dev);
1600
1601         /* Init HWS */
1602         if (!I915_NEED_GFX_HWS(dev)) {
1603                 ret = i915_init_phys_hws(dev);
1604                 if (ret)
1605                         goto out_gem_unload;
1606         }
1607
1608         /* On the 945G/GM, the chipset reports the MSI capability on the
1609          * integrated graphics even though the support isn't actually there
1610          * according to the published specs.  It doesn't appear to function
1611          * correctly in testing on 945G.
1612          * This may be a side effect of MSI having been made available for PEG
1613          * and the registers being closely associated.
1614          *
1615          * According to chipset errata, on the 965GM, MSI interrupts may
1616          * be lost or delayed, but we use them anyways to avoid
1617          * stuck interrupts on some machines.
1618          */
1619         if (!IS_I945G(dev) && !IS_I945GM(dev))
1620                 pci_enable_msi(dev->pdev);
1621
1622         spin_lock_init(&dev_priv->irq_lock);
1623         spin_lock_init(&dev_priv->error_lock);
1624         spin_lock_init(&dev_priv->rps.lock);
1625         spin_lock_init(&dev_priv->dpio_lock);
1626
1627         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1628                 dev_priv->num_pipe = 3;
1629         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1630                 dev_priv->num_pipe = 2;
1631         else
1632                 dev_priv->num_pipe = 1;
1633
1634         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1635         if (ret)
1636                 goto out_gem_unload;
1637
1638         /* Start out suspended */
1639         dev_priv->mm.suspended = 1;
1640
1641         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1642                 ret = i915_load_modeset_init(dev);
1643                 if (ret < 0) {
1644                         DRM_ERROR("failed to init modeset\n");
1645                         goto out_gem_unload;
1646                 }
1647         }
1648
1649         i915_setup_sysfs(dev);
1650
1651         /* Must be done after probing outputs */
1652         intel_opregion_init(dev);
1653         acpi_video_register();
1654
1655         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1656                     (unsigned long) dev);
1657
1658         if (IS_GEN5(dev))
1659                 intel_gpu_ips_init(dev_priv);
1660
1661         return 0;
1662
1663 out_gem_unload:
1664         if (dev_priv->mm.inactive_shrinker.shrink)
1665                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1666
1667         if (dev->pdev->msi_enabled)
1668                 pci_disable_msi(dev->pdev);
1669
1670         intel_teardown_gmbus(dev);
1671         intel_teardown_mchbar(dev);
1672         destroy_workqueue(dev_priv->wq);
1673 out_mtrrfree:
1674         if (dev_priv->mm.gtt_mtrr >= 0) {
1675                 mtrr_del(dev_priv->mm.gtt_mtrr,
1676                          dev_priv->mm.gtt_base_addr,
1677                          aperture_size);
1678                 dev_priv->mm.gtt_mtrr = -1;
1679         }
1680         io_mapping_free(dev_priv->mm.gtt_mapping);
1681 out_rmmap:
1682         pci_iounmap(dev->pdev, dev_priv->regs);
1683 put_gmch:
1684         intel_gmch_remove();
1685 put_bridge:
1686         pci_dev_put(dev_priv->bridge_dev);
1687 free_priv:
1688         kfree(dev_priv);
1689         return ret;
1690 }
1691
1692 int i915_driver_unload(struct drm_device *dev)
1693 {
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         int ret;
1696
1697         intel_gpu_ips_teardown();
1698
1699         i915_teardown_sysfs(dev);
1700
1701         if (dev_priv->mm.inactive_shrinker.shrink)
1702                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1703
1704         mutex_lock(&dev->struct_mutex);
1705         ret = i915_gpu_idle(dev);
1706         if (ret)
1707                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1708         i915_gem_retire_requests(dev);
1709         mutex_unlock(&dev->struct_mutex);
1710
1711         /* Cancel the retire work handler, which should be idle now. */
1712         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1713
1714         io_mapping_free(dev_priv->mm.gtt_mapping);
1715         if (dev_priv->mm.gtt_mtrr >= 0) {
1716                 mtrr_del(dev_priv->mm.gtt_mtrr,
1717                          dev_priv->mm.gtt_base_addr,
1718                          dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1719                 dev_priv->mm.gtt_mtrr = -1;
1720         }
1721
1722         acpi_video_unregister();
1723
1724         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1725                 intel_fbdev_fini(dev);
1726                 intel_modeset_cleanup(dev);
1727
1728                 /*
1729                  * free the memory space allocated for the child device
1730                  * config parsed from VBT
1731                  */
1732                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1733                         kfree(dev_priv->child_dev);
1734                         dev_priv->child_dev = NULL;
1735                         dev_priv->child_dev_num = 0;
1736                 }
1737
1738                 vga_switcheroo_unregister_client(dev->pdev);
1739                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1740         }
1741
1742         /* Free error state after interrupts are fully disabled. */
1743         del_timer_sync(&dev_priv->hangcheck_timer);
1744         cancel_work_sync(&dev_priv->error_work);
1745         i915_destroy_error_state(dev);
1746
1747         if (dev->pdev->msi_enabled)
1748                 pci_disable_msi(dev->pdev);
1749
1750         intel_opregion_fini(dev);
1751
1752         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1753                 /* Flush any outstanding unpin_work. */
1754                 flush_workqueue(dev_priv->wq);
1755
1756                 mutex_lock(&dev->struct_mutex);
1757                 i915_gem_free_all_phys_object(dev);
1758                 i915_gem_cleanup_ringbuffer(dev);
1759                 i915_gem_context_fini(dev);
1760                 mutex_unlock(&dev->struct_mutex);
1761                 i915_gem_cleanup_aliasing_ppgtt(dev);
1762                 i915_gem_cleanup_stolen(dev);
1763                 drm_mm_takedown(&dev_priv->mm.stolen);
1764
1765                 intel_cleanup_overlay(dev);
1766
1767                 if (!I915_NEED_GFX_HWS(dev))
1768                         i915_free_hws(dev);
1769         }
1770
1771         if (dev_priv->regs != NULL)
1772                 pci_iounmap(dev->pdev, dev_priv->regs);
1773
1774         intel_teardown_gmbus(dev);
1775         intel_teardown_mchbar(dev);
1776
1777         destroy_workqueue(dev_priv->wq);
1778
1779         pci_dev_put(dev_priv->bridge_dev);
1780         kfree(dev->dev_private);
1781
1782         return 0;
1783 }
1784
1785 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1786 {
1787         struct drm_i915_file_private *file_priv;
1788
1789         DRM_DEBUG_DRIVER("\n");
1790         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1791         if (!file_priv)
1792                 return -ENOMEM;
1793
1794         file->driver_priv = file_priv;
1795
1796         spin_lock_init(&file_priv->mm.lock);
1797         INIT_LIST_HEAD(&file_priv->mm.request_list);
1798
1799         idr_init(&file_priv->context_idr);
1800
1801         return 0;
1802 }
1803
1804 /**
1805  * i915_driver_lastclose - clean up after all DRM clients have exited
1806  * @dev: DRM device
1807  *
1808  * Take care of cleaning up after all DRM clients have exited.  In the
1809  * mode setting case, we want to restore the kernel's initial mode (just
1810  * in case the last client left us in a bad state).
1811  *
1812  * Additionally, in the non-mode setting case, we'll tear down the GTT
1813  * and DMA structures, since the kernel won't be using them, and clea
1814  * up any GEM state.
1815  */
1816 void i915_driver_lastclose(struct drm_device * dev)
1817 {
1818         drm_i915_private_t *dev_priv = dev->dev_private;
1819
1820         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1821          * goes right around and calls lastclose. Check for this and don't clean
1822          * up anything. */
1823         if (!dev_priv)
1824                 return;
1825
1826         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1827                 intel_fb_restore_mode(dev);
1828                 vga_switcheroo_process_delayed_switch();
1829                 return;
1830         }
1831
1832         i915_gem_lastclose(dev);
1833
1834         i915_dma_cleanup(dev);
1835 }
1836
1837 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1838 {
1839         i915_gem_context_close(dev, file_priv);
1840         i915_gem_release(dev, file_priv);
1841 }
1842
1843 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1844 {
1845         struct drm_i915_file_private *file_priv = file->driver_priv;
1846
1847         kfree(file_priv);
1848 }
1849
1850 struct drm_ioctl_desc i915_ioctls[] = {
1851         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1852         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1853         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1854         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1855         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1856         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1857         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1858         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1859         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1860         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1861         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1862         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1863         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1864         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1865         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1866         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1867         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1868         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1869         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1870         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1871         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1872         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1873         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1874         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHEING, i915_gem_set_cacheing_ioctl, DRM_UNLOCKED),
1875         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHEING, i915_gem_get_cacheing_ioctl, DRM_UNLOCKED),
1876         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1877         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1878         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1879         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1880         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1881         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1882         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1883         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1884         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1885         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1886         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1887         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1888         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1889         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1890         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1891         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1892         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1893         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1894         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1895         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1896         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1897         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1898         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1899 };
1900
1901 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1902
1903 /*
1904  * This is really ugly: Because old userspace abused the linux agp interface to
1905  * manage the gtt, we need to claim that all intel devices are agp.  For
1906  * otherwise the drm core refuses to initialize the agp support code.
1907  */
1908 int i915_driver_device_is_agp(struct drm_device * dev)
1909 {
1910         return 1;
1911 }