1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/console.h>
41 #include <linux/vgaarb.h>
42 #include <linux/acpi.h>
43 #include <linux/pnp.h>
44 #include <linux/vga_switcheroo.h>
45 #include <linux/slab.h>
46 #include <acpi/video.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/oom.h>
51 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
53 #define BEGIN_LP_RING(n) \
54 intel_ring_begin(LP_RING(dev_priv), (n))
57 intel_ring_emit(LP_RING(dev_priv), x)
59 #define ADVANCE_LP_RING() \
60 __intel_ring_advance(LP_RING(dev_priv))
63 * Lock test for when it's just for synchronization of ring access.
65 * In that case, we don't need to do it when GEM is initialized as nobody else
66 * has access to the ring.
68 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
69 if (LP_RING(dev->dev_private)->buffer->obj == NULL) \
70 LOCK_TEST_WITH_RETURN(dev, file); \
74 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
76 if (I915_NEED_GFX_HWS(dev_priv->dev))
77 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
79 return intel_read_status_page(LP_RING(dev_priv), reg);
82 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
83 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
84 #define I915_BREADCRUMB_INDEX 0x21
86 void i915_update_dri1_breadcrumb(struct drm_device *dev)
88 struct drm_i915_private *dev_priv = dev->dev_private;
89 struct drm_i915_master_private *master_priv;
92 * The dri breadcrumb update races against the drm master disappearing.
93 * Instead of trying to fix this (this is by far not the only ums issue)
94 * just don't do the update in kms mode.
96 if (drm_core_check_feature(dev, DRIVER_MODESET))
99 if (dev->primary->master) {
100 master_priv = dev->primary->master->driver_priv;
101 if (master_priv->sarea_priv)
102 master_priv->sarea_priv->last_dispatch =
103 READ_BREADCRUMB(dev_priv);
107 static void i915_write_hws_pga(struct drm_device *dev)
109 struct drm_i915_private *dev_priv = dev->dev_private;
112 addr = dev_priv->status_page_dmah->busaddr;
113 if (INTEL_INFO(dev)->gen >= 4)
114 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
115 I915_WRITE(HWS_PGA, addr);
119 * Frees the hardware status page, whether it's a physical address or a virtual
120 * address set up by the X Server.
122 static void i915_free_hws(struct drm_device *dev)
124 struct drm_i915_private *dev_priv = dev->dev_private;
125 struct intel_engine_cs *ring = LP_RING(dev_priv);
127 if (dev_priv->status_page_dmah) {
128 drm_pci_free(dev, dev_priv->status_page_dmah);
129 dev_priv->status_page_dmah = NULL;
132 if (ring->status_page.gfx_addr) {
133 ring->status_page.gfx_addr = 0;
134 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
137 /* Need to rewrite hardware status page */
138 I915_WRITE(HWS_PGA, 0x1ffff000);
141 void i915_kernel_lost_context(struct drm_device * dev)
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 struct drm_i915_master_private *master_priv;
145 struct intel_engine_cs *ring = LP_RING(dev_priv);
146 struct intel_ringbuffer *ringbuf = ring->buffer;
149 * We should never lose context on the ring with modesetting
150 * as we don't expose it to userspace
152 if (drm_core_check_feature(dev, DRIVER_MODESET))
155 ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
156 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
157 ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
158 if (ringbuf->space < 0)
159 ringbuf->space += ringbuf->size;
161 if (!dev->primary->master)
164 master_priv = dev->primary->master->driver_priv;
165 if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
166 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
169 static int i915_dma_cleanup(struct drm_device * dev)
171 struct drm_i915_private *dev_priv = dev->dev_private;
174 /* Make sure interrupts are disabled here because the uninstall ioctl
175 * may not have been called from userspace and after dev_private
176 * is freed, it's too late.
178 if (dev->irq_enabled)
179 drm_irq_uninstall(dev);
181 mutex_lock(&dev->struct_mutex);
182 for (i = 0; i < I915_NUM_RINGS; i++)
183 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
184 mutex_unlock(&dev->struct_mutex);
186 /* Clear the HWS virtual address at teardown */
187 if (I915_NEED_GFX_HWS(dev))
193 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
199 master_priv->sarea = drm_getsarea(dev);
200 if (master_priv->sarea) {
201 master_priv->sarea_priv = (drm_i915_sarea_t *)
202 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
204 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
207 if (init->ring_size != 0) {
208 if (LP_RING(dev_priv)->buffer->obj != NULL) {
209 i915_dma_cleanup(dev);
210 DRM_ERROR("Client tried to initialize ringbuffer in "
215 ret = intel_render_ring_init_dri(dev,
219 i915_dma_cleanup(dev);
224 dev_priv->dri1.cpp = init->cpp;
225 dev_priv->dri1.back_offset = init->back_offset;
226 dev_priv->dri1.front_offset = init->front_offset;
227 dev_priv->dri1.current_page = 0;
228 if (master_priv->sarea_priv)
229 master_priv->sarea_priv->pf_current_page = 0;
231 /* Allow hardware batchbuffers unless told otherwise.
233 dev_priv->dri1.allow_batchbuffer = 1;
238 static int i915_dma_resume(struct drm_device * dev)
240 struct drm_i915_private *dev_priv = dev->dev_private;
241 struct intel_engine_cs *ring = LP_RING(dev_priv);
243 DRM_DEBUG_DRIVER("%s\n", __func__);
245 if (ring->buffer->virtual_start == NULL) {
246 DRM_ERROR("can not ioremap virtual address for"
251 /* Program Hardware Status Page */
252 if (!ring->status_page.page_addr) {
253 DRM_ERROR("Can not find hardware status page\n");
256 DRM_DEBUG_DRIVER("hw status page @ %p\n",
257 ring->status_page.page_addr);
258 if (ring->status_page.gfx_addr != 0)
259 intel_ring_setup_status_page(ring);
261 i915_write_hws_pga(dev);
263 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
268 static int i915_dma_init(struct drm_device *dev, void *data,
269 struct drm_file *file_priv)
271 drm_i915_init_t *init = data;
274 if (drm_core_check_feature(dev, DRIVER_MODESET))
277 switch (init->func) {
279 retcode = i915_initialize(dev, init);
281 case I915_CLEANUP_DMA:
282 retcode = i915_dma_cleanup(dev);
284 case I915_RESUME_DMA:
285 retcode = i915_dma_resume(dev);
295 /* Implement basically the same security restrictions as hardware does
296 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
298 * Most of the calculations below involve calculating the size of a
299 * particular instruction. It's important to get the size right as
300 * that tells us where the next instruction to check is. Any illegal
301 * instruction detected will be given a size of zero, which is a
302 * signal to abort the rest of the buffer.
304 static int validate_cmd(int cmd)
306 switch (((cmd >> 29) & 0x7)) {
308 switch ((cmd >> 23) & 0x3f) {
310 return 1; /* MI_NOOP */
312 return 1; /* MI_FLUSH */
314 return 0; /* disallow everything else */
318 return 0; /* reserved */
320 return (cmd & 0xff) + 2; /* 2d commands */
322 if (((cmd >> 24) & 0x1f) <= 0x18)
325 switch ((cmd >> 24) & 0x1f) {
329 switch ((cmd >> 16) & 0xff) {
331 return (cmd & 0x1f) + 2;
333 return (cmd & 0xf) + 2;
335 return (cmd & 0xffff) + 2;
339 return (cmd & 0xffff) + 1;
343 if ((cmd & (1 << 23)) == 0) /* inline vertices */
344 return (cmd & 0x1ffff) + 2;
345 else if (cmd & (1 << 17)) /* indirect random */
346 if ((cmd & 0xffff) == 0)
347 return 0; /* unknown length, too hard */
349 return (((cmd & 0xffff) + 1) / 2) + 1;
351 return 2; /* indirect sequential */
362 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
364 struct drm_i915_private *dev_priv = dev->dev_private;
367 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
370 for (i = 0; i < dwords;) {
371 int sz = validate_cmd(buffer[i]);
372 if (sz == 0 || i + sz > dwords)
377 ret = BEGIN_LP_RING((dwords+1)&~1);
381 for (i = 0; i < dwords; i++)
392 i915_emit_box(struct drm_device *dev,
393 struct drm_clip_rect *box,
396 struct drm_i915_private *dev_priv = dev->dev_private;
399 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
400 box->y2 <= 0 || box->x2 <= 0) {
401 DRM_ERROR("Bad box %d,%d..%d,%d\n",
402 box->x1, box->y1, box->x2, box->y2);
406 if (INTEL_INFO(dev)->gen >= 4) {
407 ret = BEGIN_LP_RING(4);
411 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
412 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
413 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
416 ret = BEGIN_LP_RING(6);
420 OUT_RING(GFX_OP_DRAWRECT_INFO);
422 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
423 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
432 /* XXX: Emitting the counter should really be moved to part of the IRQ
433 * emit. For now, do it in both places:
436 static void i915_emit_breadcrumb(struct drm_device *dev)
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
441 dev_priv->dri1.counter++;
442 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
443 dev_priv->dri1.counter = 0;
444 if (master_priv->sarea_priv)
445 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
447 if (BEGIN_LP_RING(4) == 0) {
448 OUT_RING(MI_STORE_DWORD_INDEX);
449 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
450 OUT_RING(dev_priv->dri1.counter);
456 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
457 drm_i915_cmdbuffer_t *cmd,
458 struct drm_clip_rect *cliprects,
461 int nbox = cmd->num_cliprects;
462 int i = 0, count, ret;
465 DRM_ERROR("alignment");
469 i915_kernel_lost_context(dev);
471 count = nbox ? nbox : 1;
473 for (i = 0; i < count; i++) {
475 ret = i915_emit_box(dev, &cliprects[i],
481 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
486 i915_emit_breadcrumb(dev);
490 static int i915_dispatch_batchbuffer(struct drm_device * dev,
491 drm_i915_batchbuffer_t * batch,
492 struct drm_clip_rect *cliprects)
494 struct drm_i915_private *dev_priv = dev->dev_private;
495 int nbox = batch->num_cliprects;
498 if ((batch->start | batch->used) & 0x7) {
499 DRM_ERROR("alignment");
503 i915_kernel_lost_context(dev);
505 count = nbox ? nbox : 1;
506 for (i = 0; i < count; i++) {
508 ret = i915_emit_box(dev, &cliprects[i],
509 batch->DR1, batch->DR4);
514 if (!IS_I830(dev) && !IS_845G(dev)) {
515 ret = BEGIN_LP_RING(2);
519 if (INTEL_INFO(dev)->gen >= 4) {
520 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
521 OUT_RING(batch->start);
523 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
524 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
527 ret = BEGIN_LP_RING(4);
531 OUT_RING(MI_BATCH_BUFFER);
532 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
533 OUT_RING(batch->start + batch->used - 4);
540 if (IS_G4X(dev) || IS_GEN5(dev)) {
541 if (BEGIN_LP_RING(2) == 0) {
542 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
548 i915_emit_breadcrumb(dev);
552 static int i915_dispatch_flip(struct drm_device * dev)
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct drm_i915_master_private *master_priv =
556 dev->primary->master->driver_priv;
559 if (!master_priv->sarea_priv)
562 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
564 dev_priv->dri1.current_page,
565 master_priv->sarea_priv->pf_current_page);
567 i915_kernel_lost_context(dev);
569 ret = BEGIN_LP_RING(10);
573 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
576 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
578 if (dev_priv->dri1.current_page == 0) {
579 OUT_RING(dev_priv->dri1.back_offset);
580 dev_priv->dri1.current_page = 1;
582 OUT_RING(dev_priv->dri1.front_offset);
583 dev_priv->dri1.current_page = 0;
587 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
592 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
594 if (BEGIN_LP_RING(4) == 0) {
595 OUT_RING(MI_STORE_DWORD_INDEX);
596 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
597 OUT_RING(dev_priv->dri1.counter);
602 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
606 static int i915_quiescent(struct drm_device *dev)
608 i915_kernel_lost_context(dev);
609 return intel_ring_idle(LP_RING(dev->dev_private));
612 static int i915_flush_ioctl(struct drm_device *dev, void *data,
613 struct drm_file *file_priv)
617 if (drm_core_check_feature(dev, DRIVER_MODESET))
620 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
622 mutex_lock(&dev->struct_mutex);
623 ret = i915_quiescent(dev);
624 mutex_unlock(&dev->struct_mutex);
629 static int i915_batchbuffer(struct drm_device *dev, void *data,
630 struct drm_file *file_priv)
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 struct drm_i915_master_private *master_priv;
634 drm_i915_sarea_t *sarea_priv;
635 drm_i915_batchbuffer_t *batch = data;
637 struct drm_clip_rect *cliprects = NULL;
639 if (drm_core_check_feature(dev, DRIVER_MODESET))
642 master_priv = dev->primary->master->driver_priv;
643 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
645 if (!dev_priv->dri1.allow_batchbuffer) {
646 DRM_ERROR("Batchbuffer ioctl disabled\n");
650 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
651 batch->start, batch->used, batch->num_cliprects);
653 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
655 if (batch->num_cliprects < 0)
658 if (batch->num_cliprects) {
659 cliprects = kcalloc(batch->num_cliprects,
662 if (cliprects == NULL)
665 ret = copy_from_user(cliprects, batch->cliprects,
666 batch->num_cliprects *
667 sizeof(struct drm_clip_rect));
674 mutex_lock(&dev->struct_mutex);
675 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
676 mutex_unlock(&dev->struct_mutex);
679 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
687 static int i915_cmdbuffer(struct drm_device *dev, void *data,
688 struct drm_file *file_priv)
690 struct drm_i915_private *dev_priv = dev->dev_private;
691 struct drm_i915_master_private *master_priv;
692 drm_i915_sarea_t *sarea_priv;
693 drm_i915_cmdbuffer_t *cmdbuf = data;
694 struct drm_clip_rect *cliprects = NULL;
698 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
699 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
701 if (drm_core_check_feature(dev, DRIVER_MODESET))
704 master_priv = dev->primary->master->driver_priv;
705 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
707 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
709 if (cmdbuf->num_cliprects < 0)
712 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
713 if (batch_data == NULL)
716 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
719 goto fail_batch_free;
722 if (cmdbuf->num_cliprects) {
723 cliprects = kcalloc(cmdbuf->num_cliprects,
724 sizeof(*cliprects), GFP_KERNEL);
725 if (cliprects == NULL) {
727 goto fail_batch_free;
730 ret = copy_from_user(cliprects, cmdbuf->cliprects,
731 cmdbuf->num_cliprects *
732 sizeof(struct drm_clip_rect));
739 mutex_lock(&dev->struct_mutex);
740 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
741 mutex_unlock(&dev->struct_mutex);
743 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
748 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
758 static int i915_emit_irq(struct drm_device * dev)
760 struct drm_i915_private *dev_priv = dev->dev_private;
761 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
763 i915_kernel_lost_context(dev);
765 DRM_DEBUG_DRIVER("\n");
767 dev_priv->dri1.counter++;
768 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
769 dev_priv->dri1.counter = 1;
770 if (master_priv->sarea_priv)
771 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
773 if (BEGIN_LP_RING(4) == 0) {
774 OUT_RING(MI_STORE_DWORD_INDEX);
775 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
776 OUT_RING(dev_priv->dri1.counter);
777 OUT_RING(MI_USER_INTERRUPT);
781 return dev_priv->dri1.counter;
784 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
786 struct drm_i915_private *dev_priv = dev->dev_private;
787 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
789 struct intel_engine_cs *ring = LP_RING(dev_priv);
791 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
792 READ_BREADCRUMB(dev_priv));
794 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
795 if (master_priv->sarea_priv)
796 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
800 if (master_priv->sarea_priv)
801 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
803 if (ring->irq_get(ring)) {
804 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
805 READ_BREADCRUMB(dev_priv) >= irq_nr);
807 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
811 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
812 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
818 /* Needs the lock as it touches the ring.
820 static int i915_irq_emit(struct drm_device *dev, void *data,
821 struct drm_file *file_priv)
823 struct drm_i915_private *dev_priv = dev->dev_private;
824 drm_i915_irq_emit_t *emit = data;
827 if (drm_core_check_feature(dev, DRIVER_MODESET))
830 if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
831 DRM_ERROR("called with no initialization\n");
835 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
837 mutex_lock(&dev->struct_mutex);
838 result = i915_emit_irq(dev);
839 mutex_unlock(&dev->struct_mutex);
841 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
842 DRM_ERROR("copy_to_user\n");
849 /* Doesn't need the hardware lock.
851 static int i915_irq_wait(struct drm_device *dev, void *data,
852 struct drm_file *file_priv)
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 drm_i915_irq_wait_t *irqwait = data;
857 if (drm_core_check_feature(dev, DRIVER_MODESET))
861 DRM_ERROR("called with no initialization\n");
865 return i915_wait_irq(dev, irqwait->irq_seq);
868 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
869 struct drm_file *file_priv)
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 drm_i915_vblank_pipe_t *pipe = data;
874 if (drm_core_check_feature(dev, DRIVER_MODESET))
878 DRM_ERROR("called with no initialization\n");
882 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
888 * Schedule buffer swap at given vertical blank.
890 static int i915_vblank_swap(struct drm_device *dev, void *data,
891 struct drm_file *file_priv)
893 /* The delayed swap mechanism was fundamentally racy, and has been
894 * removed. The model was that the client requested a delayed flip/swap
895 * from the kernel, then waited for vblank before continuing to perform
896 * rendering. The problem was that the kernel might wake the client
897 * up before it dispatched the vblank swap (since the lock has to be
898 * held while touching the ringbuffer), in which case the client would
899 * clear and start the next frame before the swap occurred, and
900 * flicker would occur in addition to likely missing the vblank.
902 * In the absence of this ioctl, userland falls back to a correct path
903 * of waiting for a vblank, then dispatching the swap on its own.
904 * Context switching to userland and back is plenty fast enough for
905 * meeting the requirements of vblank swapping.
910 static int i915_flip_bufs(struct drm_device *dev, void *data,
911 struct drm_file *file_priv)
915 if (drm_core_check_feature(dev, DRIVER_MODESET))
918 DRM_DEBUG_DRIVER("%s\n", __func__);
920 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
922 mutex_lock(&dev->struct_mutex);
923 ret = i915_dispatch_flip(dev);
924 mutex_unlock(&dev->struct_mutex);
929 static int i915_getparam(struct drm_device *dev, void *data,
930 struct drm_file *file_priv)
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 drm_i915_getparam_t *param = data;
937 DRM_ERROR("called with no initialization\n");
941 switch (param->param) {
942 case I915_PARAM_IRQ_ACTIVE:
943 value = dev->pdev->irq ? 1 : 0;
945 case I915_PARAM_ALLOW_BATCHBUFFER:
946 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
948 case I915_PARAM_LAST_DISPATCH:
949 value = READ_BREADCRUMB(dev_priv);
951 case I915_PARAM_CHIPSET_ID:
952 value = dev->pdev->device;
954 case I915_PARAM_HAS_GEM:
957 case I915_PARAM_NUM_FENCES_AVAIL:
958 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
960 case I915_PARAM_HAS_OVERLAY:
961 value = dev_priv->overlay ? 1 : 0;
963 case I915_PARAM_HAS_PAGEFLIPPING:
966 case I915_PARAM_HAS_EXECBUF2:
970 case I915_PARAM_HAS_BSD:
971 value = intel_ring_initialized(&dev_priv->ring[VCS]);
973 case I915_PARAM_HAS_BLT:
974 value = intel_ring_initialized(&dev_priv->ring[BCS]);
976 case I915_PARAM_HAS_VEBOX:
977 value = intel_ring_initialized(&dev_priv->ring[VECS]);
979 case I915_PARAM_HAS_RELAXED_FENCING:
982 case I915_PARAM_HAS_COHERENT_RINGS:
985 case I915_PARAM_HAS_EXEC_CONSTANTS:
986 value = INTEL_INFO(dev)->gen >= 4;
988 case I915_PARAM_HAS_RELAXED_DELTA:
991 case I915_PARAM_HAS_GEN7_SOL_RESET:
994 case I915_PARAM_HAS_LLC:
995 value = HAS_LLC(dev);
997 case I915_PARAM_HAS_WT:
1000 case I915_PARAM_HAS_ALIASING_PPGTT:
1001 value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev);
1003 case I915_PARAM_HAS_WAIT_TIMEOUT:
1006 case I915_PARAM_HAS_SEMAPHORES:
1007 value = i915_semaphore_is_enabled(dev);
1009 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1012 case I915_PARAM_HAS_SECURE_BATCHES:
1013 value = capable(CAP_SYS_ADMIN);
1015 case I915_PARAM_HAS_PINNED_BATCHES:
1018 case I915_PARAM_HAS_EXEC_NO_RELOC:
1021 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1024 case I915_PARAM_CMD_PARSER_VERSION:
1025 value = i915_cmd_parser_get_version();
1028 DRM_DEBUG("Unknown parameter %d\n", param->param);
1032 if (copy_to_user(param->value, &value, sizeof(int))) {
1033 DRM_ERROR("copy_to_user failed\n");
1040 static int i915_setparam(struct drm_device *dev, void *data,
1041 struct drm_file *file_priv)
1043 struct drm_i915_private *dev_priv = dev->dev_private;
1044 drm_i915_setparam_t *param = data;
1047 DRM_ERROR("called with no initialization\n");
1051 switch (param->param) {
1052 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1054 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1056 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1057 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1059 case I915_SETPARAM_NUM_USED_FENCES:
1060 if (param->value > dev_priv->num_fence_regs ||
1063 /* Userspace can use first N regs */
1064 dev_priv->fence_reg_start = param->value;
1067 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1075 static int i915_set_status_page(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv)
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 drm_i915_hws_addr_t *hws = data;
1080 struct intel_engine_cs *ring;
1082 if (drm_core_check_feature(dev, DRIVER_MODESET))
1085 if (!I915_NEED_GFX_HWS(dev))
1089 DRM_ERROR("called with no initialization\n");
1093 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1094 WARN(1, "tried to set status page when mode setting active\n");
1098 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1100 ring = LP_RING(dev_priv);
1101 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1103 dev_priv->dri1.gfx_hws_cpu_addr =
1104 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1105 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1106 i915_dma_cleanup(dev);
1107 ring->status_page.gfx_addr = 0;
1108 DRM_ERROR("can not ioremap virtual address for"
1109 " G33 hw status page\n");
1113 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1114 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1116 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1117 ring->status_page.gfx_addr);
1118 DRM_DEBUG_DRIVER("load hws at %p\n",
1119 ring->status_page.page_addr);
1123 static int i915_get_bridge_dev(struct drm_device *dev)
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1127 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1128 if (!dev_priv->bridge_dev) {
1129 DRM_ERROR("bridge device not found\n");
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48
1137 #define MCHBAR_SIZE (4*4096)
1139 #define DEVEN_REG 0x54
1140 #define DEVEN_MCHBAR_EN (1 << 28)
1142 /* Allocate space for the MCH regs if needed, return nonzero on error */
1144 intel_alloc_mchbar_resource(struct drm_device *dev)
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1148 u32 temp_lo, temp_hi = 0;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1157 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1160 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1164 /* Get some space for it */
1165 dev_priv->mch_res.name = "i915 MCHBAR";
1166 dev_priv->mch_res.flags = IORESOURCE_MEM;
1167 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1169 MCHBAR_SIZE, MCHBAR_SIZE,
1171 0, pcibios_align_resource,
1172 dev_priv->bridge_dev);
1174 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1175 dev_priv->mch_res.start = 0;
1179 if (INTEL_INFO(dev)->gen >= 4)
1180 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1181 upper_32_bits(dev_priv->mch_res.start));
1183 pci_write_config_dword(dev_priv->bridge_dev, reg,
1184 lower_32_bits(dev_priv->mch_res.start));
1188 /* Setup MCHBAR if possible, return true if we should disable it again */
1190 intel_setup_mchbar(struct drm_device *dev)
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1197 if (IS_VALLEYVIEW(dev))
1200 dev_priv->mchbar_need_disable = false;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1210 /* If it's already enabled, don't have to do anything */
1214 if (intel_alloc_mchbar_resource(dev))
1217 dev_priv->mchbar_need_disable = true;
1219 /* Space is allocated or reserved, so enable it. */
1220 if (IS_I915G(dev) || IS_I915GM(dev)) {
1221 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1222 temp | DEVEN_MCHBAR_EN);
1224 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1225 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1230 intel_teardown_mchbar(struct drm_device *dev)
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1236 if (dev_priv->mchbar_need_disable) {
1237 if (IS_I915G(dev) || IS_I915GM(dev)) {
1238 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1239 temp &= ~DEVEN_MCHBAR_EN;
1240 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1242 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1244 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1248 if (dev_priv->mch_res.start)
1249 release_resource(&dev_priv->mch_res);
1252 /* true = enable decode, false = disable decoder */
1253 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1255 struct drm_device *dev = cookie;
1257 intel_modeset_vga_set_state(dev, state);
1259 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1260 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1262 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1265 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1267 struct drm_device *dev = pci_get_drvdata(pdev);
1268 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1269 if (state == VGA_SWITCHEROO_ON) {
1270 pr_info("switched on\n");
1271 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1272 /* i915 resume handler doesn't set to D0 */
1273 pci_set_power_state(dev->pdev, PCI_D0);
1275 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1277 pr_err("switched off\n");
1278 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1279 i915_suspend(dev, pmm);
1280 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1284 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1286 struct drm_device *dev = pci_get_drvdata(pdev);
1289 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1290 * locking inversion with the driver load path. And the access here is
1291 * completely racy anyway. So don't bother with locking for now.
1293 return dev->open_count == 0;
1296 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1297 .set_gpu_state = i915_switcheroo_set_state,
1299 .can_switch = i915_switcheroo_can_switch,
1302 static int i915_load_modeset_init(struct drm_device *dev)
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1307 ret = intel_parse_bios(dev);
1309 DRM_INFO("failed to find VBIOS tables\n");
1311 /* If we have > 1 VGA cards, then we need to arbitrate access
1312 * to the common VGA resources.
1314 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1315 * then we do not take part in VGA arbitration and the
1316 * vga_client_register() fails with -ENODEV.
1318 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1319 if (ret && ret != -ENODEV)
1322 intel_register_dsm_handler();
1324 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1326 goto cleanup_vga_client;
1328 /* Initialise stolen first so that we may reserve preallocated
1329 * objects for the BIOS to KMS transition.
1331 ret = i915_gem_init_stolen(dev);
1333 goto cleanup_vga_switcheroo;
1335 intel_power_domains_init_hw(dev_priv);
1337 ret = drm_irq_install(dev, dev->pdev->irq);
1339 goto cleanup_gem_stolen;
1341 /* Important: The output setup functions called by modeset_init need
1342 * working irqs for e.g. gmbus and dp aux transfers. */
1343 intel_modeset_init(dev);
1345 ret = i915_gem_init(dev);
1349 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1351 intel_modeset_gem_init(dev);
1353 /* Always safe in the mode setting case. */
1354 /* FIXME: do pre/post-mode set stuff in core KMS code */
1355 dev->vblank_disable_allowed = true;
1356 if (INTEL_INFO(dev)->num_pipes == 0)
1359 ret = intel_fbdev_init(dev);
1363 /* Only enable hotplug handling once the fbdev is fully set up. */
1364 intel_hpd_init(dev);
1367 * Some ports require correctly set-up hpd registers for detection to
1368 * work properly (leading to ghost connected connector status), e.g. VGA
1369 * on gm45. Hence we can only set up the initial fbdev config after hpd
1370 * irqs are fully enabled. Now we should scan for the initial config
1371 * only once hotplug handling is enabled, but due to screwed-up locking
1372 * around kms/fbdev init we can't protect the fdbev initial config
1373 * scanning against hotplug events. Hence do this first and ignore the
1374 * tiny window where we will loose hotplug notifactions.
1376 intel_fbdev_initial_config(dev);
1378 /* Only enable hotplug handling once the fbdev is fully set up. */
1379 dev_priv->enable_hotplug_processing = true;
1381 drm_kms_helper_poll_init(dev);
1386 mutex_lock(&dev->struct_mutex);
1387 i915_gem_cleanup_ringbuffer(dev);
1388 i915_gem_context_fini(dev);
1389 mutex_unlock(&dev->struct_mutex);
1390 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1392 drm_irq_uninstall(dev);
1394 i915_gem_cleanup_stolen(dev);
1395 cleanup_vga_switcheroo:
1396 vga_switcheroo_unregister_client(dev->pdev);
1398 vga_client_register(dev->pdev, NULL, NULL, NULL);
1403 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1405 struct drm_i915_master_private *master_priv;
1407 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1411 master->driver_priv = master_priv;
1415 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1417 struct drm_i915_master_private *master_priv = master->driver_priv;
1424 master->driver_priv = NULL;
1427 #if IS_ENABLED(CONFIG_FB)
1428 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1430 struct apertures_struct *ap;
1431 struct pci_dev *pdev = dev_priv->dev->pdev;
1434 ap = alloc_apertures(1);
1438 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1439 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1442 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1444 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1449 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1454 #if !defined(CONFIG_VGA_CONSOLE)
1455 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1459 #elif !defined(CONFIG_DUMMY_CONSOLE)
1460 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1465 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1469 DRM_INFO("Replacing VGA console driver\n");
1472 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1474 ret = do_unregister_con_driver(&vga_con);
1476 /* Ignore "already unregistered". */
1486 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1488 const struct intel_device_info *info = &dev_priv->info;
1490 #define PRINT_S(name) "%s"
1492 #define PRINT_FLAG(name) info->name ? #name "," : ""
1494 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1495 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1497 dev_priv->dev->pdev->device,
1498 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1506 * Determine various intel_device_info fields at runtime.
1508 * Use it when either:
1509 * - it's judged too laborious to fill n static structures with the limit
1510 * when a simple if statement does the job,
1511 * - run-time checks (eg read fuse/strap registers) are needed.
1513 * This function needs to be called:
1514 * - after the MMIO has been setup as we are reading registers,
1515 * - after the PCH has been detected,
1516 * - before the first usage of the fields it can tweak.
1518 static void intel_device_info_runtime_init(struct drm_device *dev)
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 struct intel_device_info *info;
1524 info = (struct intel_device_info *)&dev_priv->info;
1526 if (IS_VALLEYVIEW(dev))
1528 info->num_sprites[pipe] = 2;
1531 info->num_sprites[pipe] = 1;
1533 if (i915.disable_display) {
1534 DRM_INFO("Display disabled (module parameter)\n");
1535 info->num_pipes = 0;
1536 } else if (info->num_pipes > 0 &&
1537 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1538 !IS_VALLEYVIEW(dev)) {
1539 u32 fuse_strap = I915_READ(FUSE_STRAP);
1540 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1543 * SFUSE_STRAP is supposed to have a bit signalling the display
1544 * is fused off. Unfortunately it seems that, at least in
1545 * certain cases, fused off display means that PCH display
1546 * reads don't land anywhere. In that case, we read 0s.
1548 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1549 * should be set when taking over after the firmware.
1551 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1552 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1553 (dev_priv->pch_type == PCH_CPT &&
1554 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1555 DRM_INFO("Display fused off, disabling\n");
1556 info->num_pipes = 0;
1562 * i915_driver_load - setup chip and create an initial config
1564 * @flags: startup flags
1566 * The driver load routine has to do several things:
1567 * - drive output discovery via intel_modeset_init()
1568 * - initialize the memory manager
1569 * - allocate initial config memory
1570 * - setup the DRM framebuffer with the allocated memory
1572 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1574 struct drm_i915_private *dev_priv;
1575 struct intel_device_info *info, *device_info;
1576 int ret = 0, mmio_bar, mmio_size;
1577 uint32_t aperture_size;
1579 info = (struct intel_device_info *) flags;
1581 /* Refuse to load on gen6+ without kms enabled. */
1582 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1583 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1584 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1588 /* UMS needs agp support. */
1589 if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
1592 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1593 if (dev_priv == NULL)
1596 dev->dev_private = (void *)dev_priv;
1597 dev_priv->dev = dev;
1599 /* copy initial configuration to dev_priv->info */
1600 device_info = (struct intel_device_info *)&dev_priv->info;
1601 *device_info = *info;
1603 spin_lock_init(&dev_priv->irq_lock);
1604 spin_lock_init(&dev_priv->gpu_error.lock);
1605 spin_lock_init(&dev_priv->backlight_lock);
1606 spin_lock_init(&dev_priv->uncore.lock);
1607 spin_lock_init(&dev_priv->mm.object_stat_lock);
1608 mutex_init(&dev_priv->dpio_lock);
1609 mutex_init(&dev_priv->modeset_restore_lock);
1611 intel_pm_setup(dev);
1613 intel_display_crc_init(dev);
1615 i915_dump_device_info(dev_priv);
1617 /* Not all pre-production machines fall into this category, only the
1618 * very first ones. Almost everything should work, except for maybe
1619 * suspend/resume. And we don't implement workarounds that affect only
1620 * pre-production machines. */
1621 if (IS_HSW_EARLY_SDV(dev))
1622 DRM_INFO("This is an early pre-production Haswell machine. "
1623 "It may not be fully functional.\n");
1625 if (i915_get_bridge_dev(dev)) {
1630 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1631 /* Before gen4, the registers and the GTT are behind different BARs.
1632 * However, from gen4 onwards, the registers and the GTT are shared
1633 * in the same BAR, so we want to restrict this ioremap from
1634 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1635 * the register BAR remains the same size for all the earlier
1636 * generations up to Ironlake.
1639 mmio_size = 512*1024;
1641 mmio_size = 2*1024*1024;
1643 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1644 if (!dev_priv->regs) {
1645 DRM_ERROR("failed to map registers\n");
1650 /* This must be called before any calls to HAS_PCH_* */
1651 intel_detect_pch(dev);
1653 intel_uncore_init(dev);
1655 ret = i915_gem_gtt_init(dev);
1659 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1660 ret = i915_kick_out_vgacon(dev_priv);
1662 DRM_ERROR("failed to remove conflicting VGA console\n");
1666 i915_kick_out_firmware_fb(dev_priv);
1669 pci_set_master(dev->pdev);
1671 /* overlay on gen2 is broken and can't address above 1G */
1673 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1675 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1676 * using 32bit addressing, overwriting memory if HWS is located
1679 * The documentation also mentions an issue with undefined
1680 * behaviour if any general state is accessed within a page above 4GB,
1681 * which also needs to be handled carefully.
1683 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1684 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1686 aperture_size = dev_priv->gtt.mappable_end;
1688 dev_priv->gtt.mappable =
1689 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1691 if (dev_priv->gtt.mappable == NULL) {
1696 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1699 /* The i915 workqueue is primarily used for batched retirement of
1700 * requests (and thus managing bo) once the task has been completed
1701 * by the GPU. i915_gem_retire_requests() is called directly when we
1702 * need high-priority retirement, such as waiting for an explicit
1705 * It is also used for periodic low-priority events, such as
1706 * idle-timers and recording error state.
1708 * All tasks on the workqueue are expected to acquire the dev mutex
1709 * so there is no point in running more than one instance of the
1710 * workqueue at any time. Use an ordered one.
1712 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1713 if (dev_priv->wq == NULL) {
1714 DRM_ERROR("Failed to create our workqueue.\n");
1719 intel_irq_init(dev);
1720 intel_uncore_sanitize(dev);
1722 /* Try to make sure MCHBAR is enabled before poking at it */
1723 intel_setup_mchbar(dev);
1724 intel_setup_gmbus(dev);
1725 intel_opregion_setup(dev);
1727 intel_setup_bios(dev);
1731 /* On the 945G/GM, the chipset reports the MSI capability on the
1732 * integrated graphics even though the support isn't actually there
1733 * according to the published specs. It doesn't appear to function
1734 * correctly in testing on 945G.
1735 * This may be a side effect of MSI having been made available for PEG
1736 * and the registers being closely associated.
1738 * According to chipset errata, on the 965GM, MSI interrupts may
1739 * be lost or delayed, but we use them anyways to avoid
1740 * stuck interrupts on some machines.
1742 if (!IS_I945G(dev) && !IS_I945GM(dev))
1743 pci_enable_msi(dev->pdev);
1745 intel_device_info_runtime_init(dev);
1747 if (INTEL_INFO(dev)->num_pipes) {
1748 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1750 goto out_gem_unload;
1753 intel_power_domains_init(dev_priv);
1755 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1756 ret = i915_load_modeset_init(dev);
1758 DRM_ERROR("failed to init modeset\n");
1759 goto out_power_well;
1762 /* Start out suspended in ums mode. */
1763 dev_priv->ums.mm_suspended = 1;
1766 i915_setup_sysfs(dev);
1768 if (INTEL_INFO(dev)->num_pipes) {
1769 /* Must be done after probing outputs */
1770 intel_opregion_init(dev);
1771 acpi_video_register();
1775 intel_gpu_ips_init(dev_priv);
1777 intel_init_runtime_pm(dev_priv);
1782 intel_power_domains_remove(dev_priv);
1783 drm_vblank_cleanup(dev);
1785 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1786 unregister_shrinker(&dev_priv->mm.shrinker);
1788 if (dev->pdev->msi_enabled)
1789 pci_disable_msi(dev->pdev);
1791 intel_teardown_gmbus(dev);
1792 intel_teardown_mchbar(dev);
1793 pm_qos_remove_request(&dev_priv->pm_qos);
1794 destroy_workqueue(dev_priv->wq);
1796 arch_phys_wc_del(dev_priv->gtt.mtrr);
1797 io_mapping_free(dev_priv->gtt.mappable);
1799 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1801 intel_uncore_fini(dev);
1802 pci_iounmap(dev->pdev, dev_priv->regs);
1804 pci_dev_put(dev_priv->bridge_dev);
1807 kmem_cache_destroy(dev_priv->slab);
1812 int i915_driver_unload(struct drm_device *dev)
1814 struct drm_i915_private *dev_priv = dev->dev_private;
1817 ret = i915_gem_suspend(dev);
1819 DRM_ERROR("failed to idle hardware: %d\n", ret);
1823 intel_fini_runtime_pm(dev_priv);
1825 intel_gpu_ips_teardown();
1827 /* The i915.ko module is still not prepared to be loaded when
1828 * the power well is not enabled, so just enable it in case
1829 * we're going to unload/reload. */
1830 intel_display_set_init_power(dev_priv, true);
1831 intel_power_domains_remove(dev_priv);
1833 i915_teardown_sysfs(dev);
1835 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1836 unregister_shrinker(&dev_priv->mm.shrinker);
1838 io_mapping_free(dev_priv->gtt.mappable);
1839 arch_phys_wc_del(dev_priv->gtt.mtrr);
1841 acpi_video_unregister();
1843 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1844 intel_fbdev_fini(dev);
1845 intel_modeset_cleanup(dev);
1846 cancel_work_sync(&dev_priv->console_resume_work);
1849 * free the memory space allocated for the child device
1850 * config parsed from VBT
1852 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1853 kfree(dev_priv->vbt.child_dev);
1854 dev_priv->vbt.child_dev = NULL;
1855 dev_priv->vbt.child_dev_num = 0;
1858 vga_switcheroo_unregister_client(dev->pdev);
1859 vga_client_register(dev->pdev, NULL, NULL, NULL);
1862 /* Free error state after interrupts are fully disabled. */
1863 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1864 cancel_work_sync(&dev_priv->gpu_error.work);
1865 i915_destroy_error_state(dev);
1867 if (dev->pdev->msi_enabled)
1868 pci_disable_msi(dev->pdev);
1870 intel_opregion_fini(dev);
1872 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1873 /* Flush any outstanding unpin_work. */
1874 flush_workqueue(dev_priv->wq);
1876 mutex_lock(&dev->struct_mutex);
1877 i915_gem_cleanup_ringbuffer(dev);
1878 i915_gem_context_fini(dev);
1879 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1880 mutex_unlock(&dev->struct_mutex);
1881 i915_gem_cleanup_stolen(dev);
1883 if (!I915_NEED_GFX_HWS(dev))
1887 WARN_ON(!list_empty(&dev_priv->vm_list));
1889 drm_vblank_cleanup(dev);
1891 intel_teardown_gmbus(dev);
1892 intel_teardown_mchbar(dev);
1894 destroy_workqueue(dev_priv->wq);
1895 pm_qos_remove_request(&dev_priv->pm_qos);
1897 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1899 intel_uncore_fini(dev);
1900 if (dev_priv->regs != NULL)
1901 pci_iounmap(dev->pdev, dev_priv->regs);
1904 kmem_cache_destroy(dev_priv->slab);
1906 pci_dev_put(dev_priv->bridge_dev);
1912 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1916 ret = i915_gem_open(dev, file);
1924 * i915_driver_lastclose - clean up after all DRM clients have exited
1927 * Take care of cleaning up after all DRM clients have exited. In the
1928 * mode setting case, we want to restore the kernel's initial mode (just
1929 * in case the last client left us in a bad state).
1931 * Additionally, in the non-mode setting case, we'll tear down the GTT
1932 * and DMA structures, since the kernel won't be using them, and clea
1935 void i915_driver_lastclose(struct drm_device * dev)
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1939 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1940 * goes right around and calls lastclose. Check for this and don't clean
1945 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1946 intel_fbdev_restore_mode(dev);
1947 vga_switcheroo_process_delayed_switch();
1951 i915_gem_lastclose(dev);
1953 i915_dma_cleanup(dev);
1956 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1958 mutex_lock(&dev->struct_mutex);
1959 i915_gem_context_close(dev, file_priv);
1960 i915_gem_release(dev, file_priv);
1961 mutex_unlock(&dev->struct_mutex);
1964 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1966 struct drm_i915_file_private *file_priv = file->driver_priv;
1968 if (file_priv && file_priv->bsd_ring)
1969 file_priv->bsd_ring = NULL;
1973 const struct drm_ioctl_desc i915_ioctls[] = {
1974 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1975 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1976 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1977 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1978 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1979 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1980 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1981 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1982 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1983 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1984 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1985 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1986 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1987 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1988 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1989 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1990 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1991 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1992 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1993 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1994 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1995 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1996 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1997 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1998 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1999 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2000 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2001 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2002 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2003 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2004 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2005 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2006 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2007 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2008 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2009 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2010 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2011 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2012 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2013 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2014 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2015 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2016 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2017 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2018 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2019 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2020 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2021 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2022 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2023 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2026 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2029 * This is really ugly: Because old userspace abused the linux agp interface to
2030 * manage the gtt, we need to claim that all intel devices are agp. For
2031 * otherwise the drm core refuses to initialize the agp support code.
2033 int i915_driver_device_is_agp(struct drm_device * dev)