2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 struct change_domains {
40 uint32_t invalidate_domains;
41 uint32_t flush_domains;
45 static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv);
46 static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv);
48 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
50 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
51 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
52 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
54 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
57 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
58 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
60 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
62 bool map_and_fenceable);
63 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
64 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
65 struct drm_i915_gem_pwrite *args,
66 struct drm_file *file_priv);
67 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
69 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
89 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
90 struct drm_i915_gem_object *obj)
92 dev_priv->mm.gtt_count++;
93 dev_priv->mm.gtt_memory += obj->gtt_space->size;
94 if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) {
95 dev_priv->mm.mappable_gtt_used +=
96 min_t(size_t, obj->gtt_space->size,
97 dev_priv->mm.gtt_mappable_end - obj->gtt_offset);
101 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
102 struct drm_i915_gem_object *obj)
104 dev_priv->mm.gtt_count--;
105 dev_priv->mm.gtt_memory -= obj->gtt_space->size;
106 if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) {
107 dev_priv->mm.mappable_gtt_used -=
108 min_t(size_t, obj->gtt_space->size,
109 dev_priv->mm.gtt_mappable_end - obj->gtt_offset);
114 * Update the mappable working set counters. Call _only_ when there is a change
115 * in one of (pin|fault)_mappable and update *_mappable _before_ calling.
116 * @mappable: new state the changed mappable flag (either pin_ or fault_).
119 i915_gem_info_update_mappable(struct drm_i915_private *dev_priv,
120 struct drm_i915_gem_object *obj,
124 if (obj->pin_mappable && obj->fault_mappable)
125 /* Combined state was already mappable. */
127 dev_priv->mm.gtt_mappable_count++;
128 dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size;
130 if (obj->pin_mappable || obj->fault_mappable)
131 /* Combined state still mappable. */
133 dev_priv->mm.gtt_mappable_count--;
134 dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size;
138 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
139 struct drm_i915_gem_object *obj,
142 dev_priv->mm.pin_count++;
143 dev_priv->mm.pin_memory += obj->gtt_space->size;
145 obj->pin_mappable = true;
146 i915_gem_info_update_mappable(dev_priv, obj, true);
150 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
151 struct drm_i915_gem_object *obj)
153 dev_priv->mm.pin_count--;
154 dev_priv->mm.pin_memory -= obj->gtt_space->size;
155 if (obj->pin_mappable) {
156 obj->pin_mappable = false;
157 i915_gem_info_update_mappable(dev_priv, obj, false);
162 i915_gem_check_is_wedged(struct drm_device *dev)
164 struct drm_i915_private *dev_priv = dev->dev_private;
165 struct completion *x = &dev_priv->error_completion;
169 if (!atomic_read(&dev_priv->mm.wedged))
172 ret = wait_for_completion_interruptible(x);
176 /* Success, we reset the GPU! */
177 if (!atomic_read(&dev_priv->mm.wedged))
180 /* GPU is hung, bump the completion count to account for
181 * the token we just consumed so that we never hit zero and
182 * end up waiting upon a subsequent completion event that
185 spin_lock_irqsave(&x->wait.lock, flags);
187 spin_unlock_irqrestore(&x->wait.lock, flags);
191 static int i915_mutex_lock_interruptible(struct drm_device *dev)
193 struct drm_i915_private *dev_priv = dev->dev_private;
196 ret = i915_gem_check_is_wedged(dev);
200 ret = mutex_lock_interruptible(&dev->struct_mutex);
204 if (atomic_read(&dev_priv->mm.wedged)) {
205 mutex_unlock(&dev->struct_mutex);
209 WARN_ON(i915_verify_lists(dev));
214 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
216 return obj_priv->gtt_space &&
218 obj_priv->pin_count == 0;
221 int i915_gem_do_init(struct drm_device *dev,
223 unsigned long mappable_end,
226 drm_i915_private_t *dev_priv = dev->dev_private;
229 (start & (PAGE_SIZE - 1)) != 0 ||
230 (end & (PAGE_SIZE - 1)) != 0) {
234 drm_mm_init(&dev_priv->mm.gtt_space, start,
237 dev_priv->mm.gtt_total = end - start;
238 dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
239 dev_priv->mm.gtt_mappable_end = mappable_end;
245 i915_gem_init_ioctl(struct drm_device *dev, void *data,
246 struct drm_file *file_priv)
248 struct drm_i915_gem_init *args = data;
251 mutex_lock(&dev->struct_mutex);
252 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
253 mutex_unlock(&dev->struct_mutex);
259 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
260 struct drm_file *file_priv)
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_i915_gem_get_aperture *args = data;
265 if (!(dev->driver->driver_features & DRIVER_GEM))
268 mutex_lock(&dev->struct_mutex);
269 args->aper_size = dev_priv->mm.gtt_total;
270 args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
271 mutex_unlock(&dev->struct_mutex);
278 * Creates a new mm object and returns a handle to it.
281 i915_gem_create_ioctl(struct drm_device *dev, void *data,
282 struct drm_file *file_priv)
284 struct drm_i915_gem_create *args = data;
285 struct drm_gem_object *obj;
289 args->size = roundup(args->size, PAGE_SIZE);
291 /* Allocate the new object */
292 obj = i915_gem_alloc_object(dev, args->size);
296 ret = drm_gem_handle_create(file_priv, obj, &handle);
298 drm_gem_object_release(obj);
299 i915_gem_info_remove_obj(dev->dev_private, obj->size);
304 /* drop reference from allocate - handle holds it now */
305 drm_gem_object_unreference(obj);
306 trace_i915_gem_object_create(obj);
308 args->handle = handle;
312 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
314 drm_i915_private_t *dev_priv = obj->dev->dev_private;
315 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
317 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
318 obj_priv->tiling_mode != I915_TILING_NONE;
322 slow_shmem_copy(struct page *dst_page,
324 struct page *src_page,
328 char *dst_vaddr, *src_vaddr;
330 dst_vaddr = kmap(dst_page);
331 src_vaddr = kmap(src_page);
333 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
340 slow_shmem_bit17_copy(struct page *gpu_page,
342 struct page *cpu_page,
347 char *gpu_vaddr, *cpu_vaddr;
349 /* Use the unswizzled path if this page isn't affected. */
350 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
352 return slow_shmem_copy(cpu_page, cpu_offset,
353 gpu_page, gpu_offset, length);
355 return slow_shmem_copy(gpu_page, gpu_offset,
356 cpu_page, cpu_offset, length);
359 gpu_vaddr = kmap(gpu_page);
360 cpu_vaddr = kmap(cpu_page);
362 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
363 * XORing with the other bits (A9 for Y, A9 and A10 for X)
366 int cacheline_end = ALIGN(gpu_offset + 1, 64);
367 int this_length = min(cacheline_end - gpu_offset, length);
368 int swizzled_gpu_offset = gpu_offset ^ 64;
371 memcpy(cpu_vaddr + cpu_offset,
372 gpu_vaddr + swizzled_gpu_offset,
375 memcpy(gpu_vaddr + swizzled_gpu_offset,
376 cpu_vaddr + cpu_offset,
379 cpu_offset += this_length;
380 gpu_offset += this_length;
381 length -= this_length;
389 * This is the fast shmem pread path, which attempts to copy_from_user directly
390 * from the backing pages of the object to the user's address space. On a
391 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
394 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
395 struct drm_i915_gem_pread *args,
396 struct drm_file *file_priv)
398 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
399 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
402 char __user *user_data;
403 int page_offset, page_length;
405 user_data = (char __user *) (uintptr_t) args->data_ptr;
408 obj_priv = to_intel_bo(obj);
409 offset = args->offset;
416 /* Operation in this page
418 * page_offset = offset within page
419 * page_length = bytes to copy for this page
421 page_offset = offset & (PAGE_SIZE-1);
422 page_length = remain;
423 if ((page_offset + remain) > PAGE_SIZE)
424 page_length = PAGE_SIZE - page_offset;
426 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
427 GFP_HIGHUSER | __GFP_RECLAIMABLE);
429 return PTR_ERR(page);
431 vaddr = kmap_atomic(page);
432 ret = __copy_to_user_inatomic(user_data,
435 kunmap_atomic(vaddr);
437 mark_page_accessed(page);
438 page_cache_release(page);
442 remain -= page_length;
443 user_data += page_length;
444 offset += page_length;
451 * This is the fallback shmem pread path, which allocates temporary storage
452 * in kernel space to copy_to_user into outside of the struct_mutex, so we
453 * can copy out of the object's backing pages while holding the struct mutex
454 * and not take page faults.
457 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
458 struct drm_i915_gem_pread *args,
459 struct drm_file *file_priv)
461 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
462 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
463 struct mm_struct *mm = current->mm;
464 struct page **user_pages;
466 loff_t offset, pinned_pages, i;
467 loff_t first_data_page, last_data_page, num_pages;
468 int shmem_page_offset;
469 int data_page_index, data_page_offset;
472 uint64_t data_ptr = args->data_ptr;
473 int do_bit17_swizzling;
477 /* Pin the user pages containing the data. We can't fault while
478 * holding the struct mutex, yet we want to hold it while
479 * dereferencing the user data.
481 first_data_page = data_ptr / PAGE_SIZE;
482 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
483 num_pages = last_data_page - first_data_page + 1;
485 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
486 if (user_pages == NULL)
489 mutex_unlock(&dev->struct_mutex);
490 down_read(&mm->mmap_sem);
491 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
492 num_pages, 1, 0, user_pages, NULL);
493 up_read(&mm->mmap_sem);
494 mutex_lock(&dev->struct_mutex);
495 if (pinned_pages < num_pages) {
500 ret = i915_gem_object_set_cpu_read_domain_range(obj,
506 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
508 obj_priv = to_intel_bo(obj);
509 offset = args->offset;
514 /* Operation in this page
516 * shmem_page_offset = offset within page in shmem file
517 * data_page_index = page number in get_user_pages return
518 * data_page_offset = offset with data_page_index page.
519 * page_length = bytes to copy for this page
521 shmem_page_offset = offset & ~PAGE_MASK;
522 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
523 data_page_offset = data_ptr & ~PAGE_MASK;
525 page_length = remain;
526 if ((shmem_page_offset + page_length) > PAGE_SIZE)
527 page_length = PAGE_SIZE - shmem_page_offset;
528 if ((data_page_offset + page_length) > PAGE_SIZE)
529 page_length = PAGE_SIZE - data_page_offset;
531 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
532 GFP_HIGHUSER | __GFP_RECLAIMABLE);
534 return PTR_ERR(page);
536 if (do_bit17_swizzling) {
537 slow_shmem_bit17_copy(page,
539 user_pages[data_page_index],
544 slow_shmem_copy(user_pages[data_page_index],
551 mark_page_accessed(page);
552 page_cache_release(page);
554 remain -= page_length;
555 data_ptr += page_length;
556 offset += page_length;
560 for (i = 0; i < pinned_pages; i++) {
561 SetPageDirty(user_pages[i]);
562 mark_page_accessed(user_pages[i]);
563 page_cache_release(user_pages[i]);
565 drm_free_large(user_pages);
571 * Reads data from the object referenced by handle.
573 * On error, the contents of *data are undefined.
576 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
577 struct drm_file *file_priv)
579 struct drm_i915_gem_pread *args = data;
580 struct drm_gem_object *obj;
581 struct drm_i915_gem_object *obj_priv;
584 ret = i915_mutex_lock_interruptible(dev);
588 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
593 obj_priv = to_intel_bo(obj);
595 /* Bounds check source. */
596 if (args->offset > obj->size || args->size > obj->size - args->offset) {
604 if (!access_ok(VERIFY_WRITE,
605 (char __user *)(uintptr_t)args->data_ptr,
611 ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
618 ret = i915_gem_object_set_cpu_read_domain_range(obj,
625 if (!i915_gem_object_needs_bit17_swizzle(obj))
626 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
628 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
631 drm_gem_object_unreference(obj);
633 mutex_unlock(&dev->struct_mutex);
637 /* This is the fast write path which cannot handle
638 * page faults in the source data
642 fast_user_write(struct io_mapping *mapping,
643 loff_t page_base, int page_offset,
644 char __user *user_data,
648 unsigned long unwritten;
650 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
651 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
653 io_mapping_unmap_atomic(vaddr_atomic);
657 /* Here's the write path which can sleep for
662 slow_kernel_write(struct io_mapping *mapping,
663 loff_t gtt_base, int gtt_offset,
664 struct page *user_page, int user_offset,
667 char __iomem *dst_vaddr;
670 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
671 src_vaddr = kmap(user_page);
673 memcpy_toio(dst_vaddr + gtt_offset,
674 src_vaddr + user_offset,
678 io_mapping_unmap(dst_vaddr);
682 * This is the fast pwrite path, where we copy the data directly from the
683 * user into the GTT, uncached.
686 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
687 struct drm_i915_gem_pwrite *args,
688 struct drm_file *file_priv)
690 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
691 drm_i915_private_t *dev_priv = dev->dev_private;
693 loff_t offset, page_base;
694 char __user *user_data;
695 int page_offset, page_length;
697 user_data = (char __user *) (uintptr_t) args->data_ptr;
700 obj_priv = to_intel_bo(obj);
701 offset = obj_priv->gtt_offset + args->offset;
704 /* Operation in this page
706 * page_base = page offset within aperture
707 * page_offset = offset within page
708 * page_length = bytes to copy for this page
710 page_base = (offset & ~(PAGE_SIZE-1));
711 page_offset = offset & (PAGE_SIZE-1);
712 page_length = remain;
713 if ((page_offset + remain) > PAGE_SIZE)
714 page_length = PAGE_SIZE - page_offset;
716 /* If we get a fault while copying data, then (presumably) our
717 * source page isn't available. Return the error and we'll
718 * retry in the slow path.
720 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
721 page_offset, user_data, page_length))
725 remain -= page_length;
726 user_data += page_length;
727 offset += page_length;
734 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
735 * the memory and maps it using kmap_atomic for copying.
737 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
738 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
741 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
742 struct drm_i915_gem_pwrite *args,
743 struct drm_file *file_priv)
745 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
746 drm_i915_private_t *dev_priv = dev->dev_private;
748 loff_t gtt_page_base, offset;
749 loff_t first_data_page, last_data_page, num_pages;
750 loff_t pinned_pages, i;
751 struct page **user_pages;
752 struct mm_struct *mm = current->mm;
753 int gtt_page_offset, data_page_offset, data_page_index, page_length;
755 uint64_t data_ptr = args->data_ptr;
759 /* Pin the user pages containing the data. We can't fault while
760 * holding the struct mutex, and all of the pwrite implementations
761 * want to hold it while dereferencing the user data.
763 first_data_page = data_ptr / PAGE_SIZE;
764 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
765 num_pages = last_data_page - first_data_page + 1;
767 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
768 if (user_pages == NULL)
771 mutex_unlock(&dev->struct_mutex);
772 down_read(&mm->mmap_sem);
773 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
774 num_pages, 0, 0, user_pages, NULL);
775 up_read(&mm->mmap_sem);
776 mutex_lock(&dev->struct_mutex);
777 if (pinned_pages < num_pages) {
779 goto out_unpin_pages;
782 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
784 goto out_unpin_pages;
786 obj_priv = to_intel_bo(obj);
787 offset = obj_priv->gtt_offset + args->offset;
790 /* Operation in this page
792 * gtt_page_base = page offset within aperture
793 * gtt_page_offset = offset within page in aperture
794 * data_page_index = page number in get_user_pages return
795 * data_page_offset = offset with data_page_index page.
796 * page_length = bytes to copy for this page
798 gtt_page_base = offset & PAGE_MASK;
799 gtt_page_offset = offset & ~PAGE_MASK;
800 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
801 data_page_offset = data_ptr & ~PAGE_MASK;
803 page_length = remain;
804 if ((gtt_page_offset + page_length) > PAGE_SIZE)
805 page_length = PAGE_SIZE - gtt_page_offset;
806 if ((data_page_offset + page_length) > PAGE_SIZE)
807 page_length = PAGE_SIZE - data_page_offset;
809 slow_kernel_write(dev_priv->mm.gtt_mapping,
810 gtt_page_base, gtt_page_offset,
811 user_pages[data_page_index],
815 remain -= page_length;
816 offset += page_length;
817 data_ptr += page_length;
821 for (i = 0; i < pinned_pages; i++)
822 page_cache_release(user_pages[i]);
823 drm_free_large(user_pages);
829 * This is the fast shmem pwrite path, which attempts to directly
830 * copy_from_user into the kmapped pages backing the object.
833 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
834 struct drm_i915_gem_pwrite *args,
835 struct drm_file *file_priv)
837 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
838 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
841 char __user *user_data;
842 int page_offset, page_length;
844 user_data = (char __user *) (uintptr_t) args->data_ptr;
847 obj_priv = to_intel_bo(obj);
848 offset = args->offset;
856 /* Operation in this page
858 * page_offset = offset within page
859 * page_length = bytes to copy for this page
861 page_offset = offset & (PAGE_SIZE-1);
862 page_length = remain;
863 if ((page_offset + remain) > PAGE_SIZE)
864 page_length = PAGE_SIZE - page_offset;
866 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
867 GFP_HIGHUSER | __GFP_RECLAIMABLE);
869 return PTR_ERR(page);
871 vaddr = kmap_atomic(page, KM_USER0);
872 ret = __copy_from_user_inatomic(vaddr + page_offset,
875 kunmap_atomic(vaddr, KM_USER0);
877 set_page_dirty(page);
878 mark_page_accessed(page);
879 page_cache_release(page);
881 /* If we get a fault while copying data, then (presumably) our
882 * source page isn't available. Return the error and we'll
883 * retry in the slow path.
888 remain -= page_length;
889 user_data += page_length;
890 offset += page_length;
897 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
898 * the memory and maps it using kmap_atomic for copying.
900 * This avoids taking mmap_sem for faulting on the user's address while the
901 * struct_mutex is held.
904 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
905 struct drm_i915_gem_pwrite *args,
906 struct drm_file *file_priv)
908 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
909 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
910 struct mm_struct *mm = current->mm;
911 struct page **user_pages;
913 loff_t offset, pinned_pages, i;
914 loff_t first_data_page, last_data_page, num_pages;
915 int shmem_page_offset;
916 int data_page_index, data_page_offset;
919 uint64_t data_ptr = args->data_ptr;
920 int do_bit17_swizzling;
924 /* Pin the user pages containing the data. We can't fault while
925 * holding the struct mutex, and all of the pwrite implementations
926 * want to hold it while dereferencing the user data.
928 first_data_page = data_ptr / PAGE_SIZE;
929 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
930 num_pages = last_data_page - first_data_page + 1;
932 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
933 if (user_pages == NULL)
936 mutex_unlock(&dev->struct_mutex);
937 down_read(&mm->mmap_sem);
938 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
939 num_pages, 0, 0, user_pages, NULL);
940 up_read(&mm->mmap_sem);
941 mutex_lock(&dev->struct_mutex);
942 if (pinned_pages < num_pages) {
947 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
951 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
953 obj_priv = to_intel_bo(obj);
954 offset = args->offset;
960 /* Operation in this page
962 * shmem_page_offset = offset within page in shmem file
963 * data_page_index = page number in get_user_pages return
964 * data_page_offset = offset with data_page_index page.
965 * page_length = bytes to copy for this page
967 shmem_page_offset = offset & ~PAGE_MASK;
968 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
969 data_page_offset = data_ptr & ~PAGE_MASK;
971 page_length = remain;
972 if ((shmem_page_offset + page_length) > PAGE_SIZE)
973 page_length = PAGE_SIZE - shmem_page_offset;
974 if ((data_page_offset + page_length) > PAGE_SIZE)
975 page_length = PAGE_SIZE - data_page_offset;
977 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
978 GFP_HIGHUSER | __GFP_RECLAIMABLE);
984 if (do_bit17_swizzling) {
985 slow_shmem_bit17_copy(page,
987 user_pages[data_page_index],
992 slow_shmem_copy(page,
994 user_pages[data_page_index],
999 set_page_dirty(page);
1000 mark_page_accessed(page);
1001 page_cache_release(page);
1003 remain -= page_length;
1004 data_ptr += page_length;
1005 offset += page_length;
1009 for (i = 0; i < pinned_pages; i++)
1010 page_cache_release(user_pages[i]);
1011 drm_free_large(user_pages);
1017 * Writes data to the object referenced by handle.
1019 * On error, the contents of the buffer that were to be modified are undefined.
1022 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1023 struct drm_file *file)
1025 struct drm_i915_gem_pwrite *args = data;
1026 struct drm_gem_object *obj;
1027 struct drm_i915_gem_object *obj_priv;
1030 ret = i915_mutex_lock_interruptible(dev);
1034 obj = drm_gem_object_lookup(dev, file, args->handle);
1039 obj_priv = to_intel_bo(obj);
1042 /* Bounds check destination. */
1043 if (args->offset > obj->size || args->size > obj->size - args->offset) {
1048 if (args->size == 0)
1051 if (!access_ok(VERIFY_READ,
1052 (char __user *)(uintptr_t)args->data_ptr,
1058 ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
1065 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1066 * it would end up going through the fenced access, and we'll get
1067 * different detiling behavior between reading and writing.
1068 * pread/pwrite currently are reading and writing from the CPU
1069 * perspective, requiring manual detiling by the client.
1071 if (obj_priv->phys_obj)
1072 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1073 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1074 obj_priv->gtt_space &&
1075 obj->write_domain != I915_GEM_DOMAIN_CPU) {
1076 ret = i915_gem_object_pin(obj, 0, true);
1080 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1084 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1086 ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1089 i915_gem_object_unpin(obj);
1091 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1096 if (!i915_gem_object_needs_bit17_swizzle(obj))
1097 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1099 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1103 drm_gem_object_unreference(obj);
1105 mutex_unlock(&dev->struct_mutex);
1110 * Called when user space prepares to use an object with the CPU, either
1111 * through the mmap ioctl's mapping or a GTT mapping.
1114 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv)
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 struct drm_i915_gem_set_domain *args = data;
1119 struct drm_gem_object *obj;
1120 struct drm_i915_gem_object *obj_priv;
1121 uint32_t read_domains = args->read_domains;
1122 uint32_t write_domain = args->write_domain;
1125 if (!(dev->driver->driver_features & DRIVER_GEM))
1128 /* Only handle setting domains to types used by the CPU. */
1129 if (write_domain & I915_GEM_GPU_DOMAINS)
1132 if (read_domains & I915_GEM_GPU_DOMAINS)
1135 /* Having something in the write domain implies it's in the read
1136 * domain, and only that read domain. Enforce that in the request.
1138 if (write_domain != 0 && read_domains != write_domain)
1141 ret = i915_mutex_lock_interruptible(dev);
1145 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1150 obj_priv = to_intel_bo(obj);
1152 intel_mark_busy(dev, obj);
1154 if (read_domains & I915_GEM_DOMAIN_GTT) {
1155 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1157 /* Update the LRU on the fence for the CPU access that's
1160 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1161 struct drm_i915_fence_reg *reg =
1162 &dev_priv->fence_regs[obj_priv->fence_reg];
1163 list_move_tail(®->lru_list,
1164 &dev_priv->mm.fence_list);
1167 /* Silently promote "you're not bound, there was nothing to do"
1168 * to success, since the client was just asking us to
1169 * make sure everything was done.
1174 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1177 /* Maintain LRU order of "inactive" objects */
1178 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1179 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1181 drm_gem_object_unreference(obj);
1183 mutex_unlock(&dev->struct_mutex);
1188 * Called when user space has done writes to this buffer
1191 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1192 struct drm_file *file_priv)
1194 struct drm_i915_gem_sw_finish *args = data;
1195 struct drm_gem_object *obj;
1198 if (!(dev->driver->driver_features & DRIVER_GEM))
1201 ret = i915_mutex_lock_interruptible(dev);
1205 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1211 /* Pinned buffers may be scanout, so flush the cache */
1212 if (to_intel_bo(obj)->pin_count)
1213 i915_gem_object_flush_cpu_write_domain(obj);
1215 drm_gem_object_unreference(obj);
1217 mutex_unlock(&dev->struct_mutex);
1222 * Maps the contents of an object, returning the address it is mapped
1225 * While the mapping holds a reference on the contents of the object, it doesn't
1226 * imply a ref on the object itself.
1229 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1230 struct drm_file *file_priv)
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 struct drm_i915_gem_mmap *args = data;
1234 struct drm_gem_object *obj;
1238 if (!(dev->driver->driver_features & DRIVER_GEM))
1241 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1245 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1246 drm_gem_object_unreference_unlocked(obj);
1250 offset = args->offset;
1252 down_write(¤t->mm->mmap_sem);
1253 addr = do_mmap(obj->filp, 0, args->size,
1254 PROT_READ | PROT_WRITE, MAP_SHARED,
1256 up_write(¤t->mm->mmap_sem);
1257 drm_gem_object_unreference_unlocked(obj);
1258 if (IS_ERR((void *)addr))
1261 args->addr_ptr = (uint64_t) addr;
1267 * i915_gem_fault - fault a page into the GTT
1268 * vma: VMA in question
1271 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1272 * from userspace. The fault handler takes care of binding the object to
1273 * the GTT (if needed), allocating and programming a fence register (again,
1274 * only if needed based on whether the old reg is still valid or the object
1275 * is tiled) and inserting a new PTE into the faulting process.
1277 * Note that the faulting process may involve evicting existing objects
1278 * from the GTT and/or fence registers to make room. So performance may
1279 * suffer if the GTT working set is large or there are few fence registers
1282 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1284 struct drm_gem_object *obj = vma->vm_private_data;
1285 struct drm_device *dev = obj->dev;
1286 drm_i915_private_t *dev_priv = dev->dev_private;
1287 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1288 pgoff_t page_offset;
1291 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1293 /* We don't use vmf->pgoff since that has the fake offset */
1294 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1297 /* Now bind it into the GTT if needed */
1298 mutex_lock(&dev->struct_mutex);
1299 BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable);
1301 if (obj_priv->gtt_space) {
1302 if (!obj_priv->map_and_fenceable) {
1303 ret = i915_gem_object_unbind(obj);
1309 if (!obj_priv->gtt_space) {
1310 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1315 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1319 if (!obj_priv->fault_mappable) {
1320 obj_priv->fault_mappable = true;
1321 i915_gem_info_update_mappable(dev_priv, obj_priv, true);
1324 /* Need a new fence register? */
1325 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1326 ret = i915_gem_object_get_fence_reg(obj, true);
1331 if (i915_gem_object_is_inactive(obj_priv))
1332 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1334 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1337 /* Finally, remap it using the new GTT offset */
1338 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1340 mutex_unlock(&dev->struct_mutex);
1347 return VM_FAULT_NOPAGE;
1349 return VM_FAULT_OOM;
1351 return VM_FAULT_SIGBUS;
1356 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1357 * @obj: obj in question
1359 * GEM memory mapping works by handing back to userspace a fake mmap offset
1360 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1361 * up the object based on the offset and sets up the various memory mapping
1364 * This routine allocates and attaches a fake offset for @obj.
1367 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1369 struct drm_device *dev = obj->dev;
1370 struct drm_gem_mm *mm = dev->mm_private;
1371 struct drm_map_list *list;
1372 struct drm_local_map *map;
1375 /* Set the object up for mmap'ing */
1376 list = &obj->map_list;
1377 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1382 map->type = _DRM_GEM;
1383 map->size = obj->size;
1386 /* Get a DRM GEM mmap offset allocated... */
1387 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1388 obj->size / PAGE_SIZE, 0, 0);
1389 if (!list->file_offset_node) {
1390 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1395 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1396 obj->size / PAGE_SIZE, 0);
1397 if (!list->file_offset_node) {
1402 list->hash.key = list->file_offset_node->start;
1403 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1405 DRM_ERROR("failed to add to map hash\n");
1412 drm_mm_put_block(list->file_offset_node);
1421 * i915_gem_release_mmap - remove physical page mappings
1422 * @obj: obj in question
1424 * Preserve the reservation of the mmapping with the DRM core code, but
1425 * relinquish ownership of the pages back to the system.
1427 * It is vital that we remove the page mapping if we have mapped a tiled
1428 * object through the GTT and then lose the fence register due to
1429 * resource pressure. Similarly if the object has been moved out of the
1430 * aperture, than pages mapped into userspace must be revoked. Removing the
1431 * mapping will then trigger a page fault on the next user access, allowing
1432 * fixup by i915_gem_fault().
1435 i915_gem_release_mmap(struct drm_gem_object *obj)
1437 struct drm_device *dev = obj->dev;
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1441 if (unlikely(obj->map_list.map && dev->dev_mapping))
1442 unmap_mapping_range(dev->dev_mapping,
1443 (loff_t)obj->map_list.hash.key<<PAGE_SHIFT,
1446 if (obj_priv->fault_mappable) {
1447 obj_priv->fault_mappable = false;
1448 i915_gem_info_update_mappable(dev_priv, obj_priv, false);
1453 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1455 struct drm_device *dev = obj->dev;
1456 struct drm_gem_mm *mm = dev->mm_private;
1457 struct drm_map_list *list = &obj->map_list;
1459 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1460 drm_mm_put_block(list->file_offset_node);
1466 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1467 * @obj: object to check
1469 * Return the required GTT alignment for an object, taking into account
1470 * potential fence register mapping.
1473 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv)
1475 struct drm_device *dev = obj_priv->base.dev;
1478 * Minimum alignment is 4k (GTT page size), but might be greater
1479 * if a fence register is needed for the object.
1481 if (INTEL_INFO(dev)->gen >= 4 ||
1482 obj_priv->tiling_mode == I915_TILING_NONE)
1486 * Previous chips need to be aligned to the size of the smallest
1487 * fence register that can contain the object.
1489 return i915_gem_get_gtt_size(obj_priv);
1493 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1495 * @obj: object to check
1497 * Return the required GTT alignment for an object, only taking into account
1498 * unfenced tiled surface requirements.
1501 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj_priv)
1503 struct drm_device *dev = obj_priv->base.dev;
1507 * Minimum alignment is 4k (GTT page size) for sane hw.
1509 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1510 obj_priv->tiling_mode == I915_TILING_NONE)
1514 * Older chips need unfenced tiled buffers to be aligned to the left
1515 * edge of an even tile row (where tile rows are counted as if the bo is
1516 * placed in a fenced gtt region).
1519 (obj_priv->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1524 return tile_height * obj_priv->stride * 2;
1528 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv)
1530 struct drm_device *dev = obj_priv->base.dev;
1534 * Minimum alignment is 4k (GTT page size), but might be greater
1535 * if a fence register is needed for the object.
1537 if (INTEL_INFO(dev)->gen >= 4)
1538 return obj_priv->base.size;
1541 * Previous chips need to be aligned to the size of the smallest
1542 * fence register that can contain the object.
1544 if (INTEL_INFO(dev)->gen == 3)
1549 while (size < obj_priv->base.size)
1556 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1558 * @data: GTT mapping ioctl data
1559 * @file_priv: GEM object info
1561 * Simply returns the fake offset to userspace so it can mmap it.
1562 * The mmap call will end up in drm_gem_mmap(), which will set things
1563 * up so we can get faults in the handler above.
1565 * The fault handler will take care of binding the object into the GTT
1566 * (since it may have been evicted to make room for something), allocating
1567 * a fence register, and mapping the appropriate aperture address into
1571 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1572 struct drm_file *file_priv)
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 struct drm_i915_gem_mmap_gtt *args = data;
1576 struct drm_gem_object *obj;
1577 struct drm_i915_gem_object *obj_priv;
1580 if (!(dev->driver->driver_features & DRIVER_GEM))
1583 ret = i915_mutex_lock_interruptible(dev);
1587 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1592 obj_priv = to_intel_bo(obj);
1594 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1599 if (obj_priv->madv != I915_MADV_WILLNEED) {
1600 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1605 if (!obj->map_list.map) {
1606 ret = i915_gem_create_mmap_offset(obj);
1611 args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
1614 drm_gem_object_unreference(obj);
1616 mutex_unlock(&dev->struct_mutex);
1621 i915_gem_object_get_pages_gtt(struct drm_gem_object *obj,
1624 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1626 struct address_space *mapping;
1627 struct inode *inode;
1630 /* Get the list of pages out of our struct file. They'll be pinned
1631 * at this point until we release them.
1633 page_count = obj->size / PAGE_SIZE;
1634 BUG_ON(obj_priv->pages != NULL);
1635 obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1636 if (obj_priv->pages == NULL)
1639 inode = obj->filp->f_path.dentry->d_inode;
1640 mapping = inode->i_mapping;
1641 for (i = 0; i < page_count; i++) {
1642 page = read_cache_page_gfp(mapping, i,
1650 obj_priv->pages[i] = page;
1653 if (obj_priv->tiling_mode != I915_TILING_NONE)
1654 i915_gem_object_do_bit_17_swizzle(obj);
1660 page_cache_release(obj_priv->pages[i]);
1662 drm_free_large(obj_priv->pages);
1663 obj_priv->pages = NULL;
1664 return PTR_ERR(page);
1668 i915_gem_object_put_pages_gtt(struct drm_gem_object *obj)
1670 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1671 int page_count = obj->size / PAGE_SIZE;
1674 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1676 if (obj_priv->tiling_mode != I915_TILING_NONE)
1677 i915_gem_object_save_bit_17_swizzle(obj);
1679 if (obj_priv->madv == I915_MADV_DONTNEED)
1680 obj_priv->dirty = 0;
1682 for (i = 0; i < page_count; i++) {
1683 if (obj_priv->dirty)
1684 set_page_dirty(obj_priv->pages[i]);
1686 if (obj_priv->madv == I915_MADV_WILLNEED)
1687 mark_page_accessed(obj_priv->pages[i]);
1689 page_cache_release(obj_priv->pages[i]);
1691 obj_priv->dirty = 0;
1693 drm_free_large(obj_priv->pages);
1694 obj_priv->pages = NULL;
1698 i915_gem_next_request_seqno(struct drm_device *dev,
1699 struct intel_ring_buffer *ring)
1701 drm_i915_private_t *dev_priv = dev->dev_private;
1702 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1706 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1707 struct intel_ring_buffer *ring)
1709 struct drm_device *dev = obj->dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1712 uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1714 BUG_ON(ring == NULL);
1715 obj_priv->ring = ring;
1717 /* Add a reference if we're newly entering the active list. */
1718 if (!obj_priv->active) {
1719 drm_gem_object_reference(obj);
1720 obj_priv->active = 1;
1723 /* Move from whatever list we were on to the tail of execution. */
1724 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list);
1725 list_move_tail(&obj_priv->ring_list, &ring->active_list);
1726 obj_priv->last_rendering_seqno = seqno;
1730 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1732 struct drm_device *dev = obj->dev;
1733 drm_i915_private_t *dev_priv = dev->dev_private;
1734 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1736 BUG_ON(!obj_priv->active);
1737 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list);
1738 list_del_init(&obj_priv->ring_list);
1739 obj_priv->last_rendering_seqno = 0;
1742 /* Immediately discard the backing storage */
1744 i915_gem_object_truncate(struct drm_gem_object *obj)
1746 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1747 struct inode *inode;
1749 /* Our goal here is to return as much of the memory as
1750 * is possible back to the system as we are called from OOM.
1751 * To do this we must instruct the shmfs to drop all of its
1752 * backing pages, *now*. Here we mirror the actions taken
1753 * when by shmem_delete_inode() to release the backing store.
1755 inode = obj->filp->f_path.dentry->d_inode;
1756 truncate_inode_pages(inode->i_mapping, 0);
1757 if (inode->i_op->truncate_range)
1758 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1760 obj_priv->madv = __I915_MADV_PURGED;
1764 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1766 return obj_priv->madv == I915_MADV_DONTNEED;
1770 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1772 struct drm_device *dev = obj->dev;
1773 drm_i915_private_t *dev_priv = dev->dev_private;
1774 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1776 if (obj_priv->pin_count != 0)
1777 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list);
1779 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1780 list_del_init(&obj_priv->ring_list);
1782 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1784 obj_priv->last_rendering_seqno = 0;
1785 obj_priv->ring = NULL;
1786 if (obj_priv->active) {
1787 obj_priv->active = 0;
1788 drm_gem_object_unreference(obj);
1790 WARN_ON(i915_verify_lists(dev));
1794 i915_gem_process_flushing_list(struct drm_device *dev,
1795 uint32_t flush_domains,
1796 struct intel_ring_buffer *ring)
1798 drm_i915_private_t *dev_priv = dev->dev_private;
1799 struct drm_i915_gem_object *obj_priv, *next;
1801 list_for_each_entry_safe(obj_priv, next,
1802 &ring->gpu_write_list,
1804 struct drm_gem_object *obj = &obj_priv->base;
1806 if (obj->write_domain & flush_domains) {
1807 uint32_t old_write_domain = obj->write_domain;
1809 obj->write_domain = 0;
1810 list_del_init(&obj_priv->gpu_write_list);
1811 i915_gem_object_move_to_active(obj, ring);
1813 /* update the fence lru list */
1814 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1815 struct drm_i915_fence_reg *reg =
1816 &dev_priv->fence_regs[obj_priv->fence_reg];
1817 list_move_tail(®->lru_list,
1818 &dev_priv->mm.fence_list);
1821 trace_i915_gem_object_change_domain(obj,
1829 i915_add_request(struct drm_device *dev,
1830 struct drm_file *file,
1831 struct drm_i915_gem_request *request,
1832 struct intel_ring_buffer *ring)
1834 drm_i915_private_t *dev_priv = dev->dev_private;
1835 struct drm_i915_file_private *file_priv = NULL;
1840 BUG_ON(request == NULL);
1843 file_priv = file->driver_priv;
1845 ret = ring->add_request(ring, &seqno);
1849 ring->outstanding_lazy_request = false;
1851 request->seqno = seqno;
1852 request->ring = ring;
1853 request->emitted_jiffies = jiffies;
1854 was_empty = list_empty(&ring->request_list);
1855 list_add_tail(&request->list, &ring->request_list);
1858 spin_lock(&file_priv->mm.lock);
1859 request->file_priv = file_priv;
1860 list_add_tail(&request->client_list,
1861 &file_priv->mm.request_list);
1862 spin_unlock(&file_priv->mm.lock);
1865 if (!dev_priv->mm.suspended) {
1866 mod_timer(&dev_priv->hangcheck_timer,
1867 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1869 queue_delayed_work(dev_priv->wq,
1870 &dev_priv->mm.retire_work, HZ);
1876 * Command execution barrier
1878 * Ensures that all commands in the ring are finished
1879 * before signalling the CPU
1882 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1884 uint32_t flush_domains = 0;
1886 /* The sampler always gets flushed on i965 (sigh) */
1887 if (INTEL_INFO(dev)->gen >= 4)
1888 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1890 ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains);
1894 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1896 struct drm_i915_file_private *file_priv = request->file_priv;
1901 spin_lock(&file_priv->mm.lock);
1902 list_del(&request->client_list);
1903 request->file_priv = NULL;
1904 spin_unlock(&file_priv->mm.lock);
1907 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1908 struct intel_ring_buffer *ring)
1910 while (!list_empty(&ring->request_list)) {
1911 struct drm_i915_gem_request *request;
1913 request = list_first_entry(&ring->request_list,
1914 struct drm_i915_gem_request,
1917 list_del(&request->list);
1918 i915_gem_request_remove_from_client(request);
1922 while (!list_empty(&ring->active_list)) {
1923 struct drm_i915_gem_object *obj_priv;
1925 obj_priv = list_first_entry(&ring->active_list,
1926 struct drm_i915_gem_object,
1929 obj_priv->base.write_domain = 0;
1930 list_del_init(&obj_priv->gpu_write_list);
1931 i915_gem_object_move_to_inactive(&obj_priv->base);
1935 void i915_gem_reset(struct drm_device *dev)
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 struct drm_i915_gem_object *obj_priv;
1941 i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1942 i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1943 i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring);
1945 /* Remove anything from the flushing lists. The GPU cache is likely
1946 * to be lost on reset along with the data, so simply move the
1947 * lost bo to the inactive list.
1949 while (!list_empty(&dev_priv->mm.flushing_list)) {
1950 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1951 struct drm_i915_gem_object,
1954 obj_priv->base.write_domain = 0;
1955 list_del_init(&obj_priv->gpu_write_list);
1956 i915_gem_object_move_to_inactive(&obj_priv->base);
1959 /* Move everything out of the GPU domains to ensure we do any
1960 * necessary invalidation upon reuse.
1962 list_for_each_entry(obj_priv,
1963 &dev_priv->mm.inactive_list,
1966 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1969 /* The fence registers are invalidated so clear them out */
1970 for (i = 0; i < 16; i++) {
1971 struct drm_i915_fence_reg *reg;
1973 reg = &dev_priv->fence_regs[i];
1977 i915_gem_clear_fence_reg(reg->obj);
1982 * This function clears the request list as sequence numbers are passed.
1985 i915_gem_retire_requests_ring(struct drm_device *dev,
1986 struct intel_ring_buffer *ring)
1988 drm_i915_private_t *dev_priv = dev->dev_private;
1991 if (!ring->status_page.page_addr ||
1992 list_empty(&ring->request_list))
1995 WARN_ON(i915_verify_lists(dev));
1997 seqno = ring->get_seqno(ring);
1998 while (!list_empty(&ring->request_list)) {
1999 struct drm_i915_gem_request *request;
2001 request = list_first_entry(&ring->request_list,
2002 struct drm_i915_gem_request,
2005 if (!i915_seqno_passed(seqno, request->seqno))
2008 trace_i915_gem_request_retire(dev, request->seqno);
2010 list_del(&request->list);
2011 i915_gem_request_remove_from_client(request);
2015 /* Move any buffers on the active list that are no longer referenced
2016 * by the ringbuffer to the flushing/inactive lists as appropriate.
2018 while (!list_empty(&ring->active_list)) {
2019 struct drm_gem_object *obj;
2020 struct drm_i915_gem_object *obj_priv;
2022 obj_priv = list_first_entry(&ring->active_list,
2023 struct drm_i915_gem_object,
2026 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
2029 obj = &obj_priv->base;
2030 if (obj->write_domain != 0)
2031 i915_gem_object_move_to_flushing(obj);
2033 i915_gem_object_move_to_inactive(obj);
2036 if (unlikely (dev_priv->trace_irq_seqno &&
2037 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
2038 ring->user_irq_put(ring);
2039 dev_priv->trace_irq_seqno = 0;
2042 WARN_ON(i915_verify_lists(dev));
2046 i915_gem_retire_requests(struct drm_device *dev)
2048 drm_i915_private_t *dev_priv = dev->dev_private;
2050 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2051 struct drm_i915_gem_object *obj_priv, *tmp;
2053 /* We must be careful that during unbind() we do not
2054 * accidentally infinitely recurse into retire requests.
2056 * retire -> free -> unbind -> wait -> retire_ring
2058 list_for_each_entry_safe(obj_priv, tmp,
2059 &dev_priv->mm.deferred_free_list,
2061 i915_gem_free_object_tail(&obj_priv->base);
2064 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
2065 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
2066 i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring);
2070 i915_gem_retire_work_handler(struct work_struct *work)
2072 drm_i915_private_t *dev_priv;
2073 struct drm_device *dev;
2075 dev_priv = container_of(work, drm_i915_private_t,
2076 mm.retire_work.work);
2077 dev = dev_priv->dev;
2079 /* Come back later if the device is busy... */
2080 if (!mutex_trylock(&dev->struct_mutex)) {
2081 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2085 i915_gem_retire_requests(dev);
2087 if (!dev_priv->mm.suspended &&
2088 (!list_empty(&dev_priv->render_ring.request_list) ||
2089 !list_empty(&dev_priv->bsd_ring.request_list) ||
2090 !list_empty(&dev_priv->blt_ring.request_list)))
2091 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2092 mutex_unlock(&dev->struct_mutex);
2096 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
2097 bool interruptible, struct intel_ring_buffer *ring)
2099 drm_i915_private_t *dev_priv = dev->dev_private;
2105 if (atomic_read(&dev_priv->mm.wedged))
2108 if (seqno == ring->outstanding_lazy_request) {
2109 struct drm_i915_gem_request *request;
2111 request = kzalloc(sizeof(*request), GFP_KERNEL);
2112 if (request == NULL)
2115 ret = i915_add_request(dev, NULL, request, ring);
2121 seqno = request->seqno;
2124 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2125 if (HAS_PCH_SPLIT(dev))
2126 ier = I915_READ(DEIER) | I915_READ(GTIER);
2128 ier = I915_READ(IER);
2130 DRM_ERROR("something (likely vbetool) disabled "
2131 "interrupts, re-enabling\n");
2132 i915_driver_irq_preinstall(dev);
2133 i915_driver_irq_postinstall(dev);
2136 trace_i915_gem_request_wait_begin(dev, seqno);
2138 ring->waiting_seqno = seqno;
2139 ring->user_irq_get(ring);
2141 ret = wait_event_interruptible(ring->irq_queue,
2142 i915_seqno_passed(ring->get_seqno(ring), seqno)
2143 || atomic_read(&dev_priv->mm.wedged));
2145 wait_event(ring->irq_queue,
2146 i915_seqno_passed(ring->get_seqno(ring), seqno)
2147 || atomic_read(&dev_priv->mm.wedged));
2149 ring->user_irq_put(ring);
2150 ring->waiting_seqno = 0;
2152 trace_i915_gem_request_wait_end(dev, seqno);
2154 if (atomic_read(&dev_priv->mm.wedged))
2157 if (ret && ret != -ERESTARTSYS)
2158 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2159 __func__, ret, seqno, ring->get_seqno(ring),
2160 dev_priv->next_seqno);
2162 /* Directly dispatch request retiring. While we have the work queue
2163 * to handle this, the waiter on a request often wants an associated
2164 * buffer to have made it to the inactive list, and we would need
2165 * a separate wait queue to handle that.
2168 i915_gem_retire_requests_ring(dev, ring);
2174 * Waits for a sequence number to be signaled, and cleans up the
2175 * request and object lists appropriately for that event.
2178 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2179 struct intel_ring_buffer *ring)
2181 return i915_do_wait_request(dev, seqno, 1, ring);
2185 i915_gem_flush_ring(struct drm_device *dev,
2186 struct drm_file *file_priv,
2187 struct intel_ring_buffer *ring,
2188 uint32_t invalidate_domains,
2189 uint32_t flush_domains)
2191 ring->flush(ring, invalidate_domains, flush_domains);
2192 i915_gem_process_flushing_list(dev, flush_domains, ring);
2196 i915_gem_flush(struct drm_device *dev,
2197 struct drm_file *file_priv,
2198 uint32_t invalidate_domains,
2199 uint32_t flush_domains,
2200 uint32_t flush_rings)
2202 drm_i915_private_t *dev_priv = dev->dev_private;
2204 if (flush_domains & I915_GEM_DOMAIN_CPU)
2205 drm_agp_chipset_flush(dev);
2207 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2208 if (flush_rings & RING_RENDER)
2209 i915_gem_flush_ring(dev, file_priv,
2210 &dev_priv->render_ring,
2211 invalidate_domains, flush_domains);
2212 if (flush_rings & RING_BSD)
2213 i915_gem_flush_ring(dev, file_priv,
2214 &dev_priv->bsd_ring,
2215 invalidate_domains, flush_domains);
2216 if (flush_rings & RING_BLT)
2217 i915_gem_flush_ring(dev, file_priv,
2218 &dev_priv->blt_ring,
2219 invalidate_domains, flush_domains);
2224 * Ensures that all rendering to the object has completed and the object is
2225 * safe to unbind from the GTT or access from the CPU.
2228 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2231 struct drm_device *dev = obj->dev;
2232 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2235 /* This function only exists to support waiting for existing rendering,
2236 * not for emitting required flushes.
2238 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2240 /* If there is rendering queued on the buffer being evicted, wait for
2243 if (obj_priv->active) {
2244 ret = i915_do_wait_request(dev,
2245 obj_priv->last_rendering_seqno,
2256 * Unbinds an object from the GTT aperture.
2259 i915_gem_object_unbind(struct drm_gem_object *obj)
2261 struct drm_device *dev = obj->dev;
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2266 if (obj_priv->gtt_space == NULL)
2269 if (obj_priv->pin_count != 0) {
2270 DRM_ERROR("Attempting to unbind pinned buffer\n");
2274 /* blow away mappings if mapped through GTT */
2275 i915_gem_release_mmap(obj);
2277 /* Move the object to the CPU domain to ensure that
2278 * any possible CPU writes while it's not in the GTT
2279 * are flushed when we go to remap it. This will
2280 * also ensure that all pending GPU writes are finished
2283 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2284 if (ret == -ERESTARTSYS)
2286 /* Continue on if we fail due to EIO, the GPU is hung so we
2287 * should be safe and we need to cleanup or else we might
2288 * cause memory corruption through use-after-free.
2291 i915_gem_clflush_object(obj);
2292 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2295 /* release the fence reg _after_ flushing */
2296 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2297 i915_gem_clear_fence_reg(obj);
2299 drm_unbind_agp(obj_priv->agp_mem);
2300 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2302 i915_gem_object_put_pages_gtt(obj);
2304 i915_gem_info_remove_gtt(dev_priv, obj_priv);
2305 list_del_init(&obj_priv->mm_list);
2306 /* Avoid an unnecessary call to unbind on rebind. */
2307 obj_priv->map_and_fenceable = true;
2309 drm_mm_put_block(obj_priv->gtt_space);
2310 obj_priv->gtt_space = NULL;
2311 obj_priv->gtt_offset = 0;
2313 if (i915_gem_object_is_purgeable(obj_priv))
2314 i915_gem_object_truncate(obj);
2316 trace_i915_gem_object_unbind(obj);
2321 static int i915_ring_idle(struct drm_device *dev,
2322 struct intel_ring_buffer *ring)
2324 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2327 i915_gem_flush_ring(dev, NULL, ring,
2328 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2329 return i915_wait_request(dev,
2330 i915_gem_next_request_seqno(dev, ring),
2335 i915_gpu_idle(struct drm_device *dev)
2337 drm_i915_private_t *dev_priv = dev->dev_private;
2341 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2342 list_empty(&dev_priv->mm.active_list));
2346 /* Flush everything onto the inactive list. */
2347 ret = i915_ring_idle(dev, &dev_priv->render_ring);
2351 ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2355 ret = i915_ring_idle(dev, &dev_priv->blt_ring);
2362 static void sandybridge_write_fence_reg(struct drm_gem_object *obj)
2364 struct drm_device *dev = obj->dev;
2365 drm_i915_private_t *dev_priv = dev->dev_private;
2366 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2367 u32 size = i915_gem_get_gtt_size(obj_priv);
2368 int regnum = obj_priv->fence_reg;
2371 val = (uint64_t)((obj_priv->gtt_offset + size - 4096) &
2373 val |= obj_priv->gtt_offset & 0xfffff000;
2374 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2375 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2377 if (obj_priv->tiling_mode == I915_TILING_Y)
2378 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2379 val |= I965_FENCE_REG_VALID;
2381 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2384 static void i965_write_fence_reg(struct drm_gem_object *obj)
2386 struct drm_device *dev = obj->dev;
2387 drm_i915_private_t *dev_priv = dev->dev_private;
2388 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2389 u32 size = i915_gem_get_gtt_size(obj_priv);
2390 int regnum = obj_priv->fence_reg;
2393 val = (uint64_t)((obj_priv->gtt_offset + size - 4096) &
2395 val |= obj_priv->gtt_offset & 0xfffff000;
2396 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2397 if (obj_priv->tiling_mode == I915_TILING_Y)
2398 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2399 val |= I965_FENCE_REG_VALID;
2401 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2404 static void i915_write_fence_reg(struct drm_gem_object *obj)
2406 struct drm_device *dev = obj->dev;
2407 drm_i915_private_t *dev_priv = dev->dev_private;
2408 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2409 u32 size = i915_gem_get_gtt_size(obj_priv);
2410 uint32_t fence_reg, val, pitch_val;
2413 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2414 (obj_priv->gtt_offset & (size - 1))) {
2415 WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n",
2416 __func__, obj_priv->gtt_offset, obj_priv->map_and_fenceable, size,
2417 obj_priv->gtt_space->start, obj_priv->gtt_space->size);
2421 if (obj_priv->tiling_mode == I915_TILING_Y &&
2422 HAS_128_BYTE_Y_TILING(dev))
2427 /* Note: pitch better be a power of two tile widths */
2428 pitch_val = obj_priv->stride / tile_width;
2429 pitch_val = ffs(pitch_val) - 1;
2431 if (obj_priv->tiling_mode == I915_TILING_Y &&
2432 HAS_128_BYTE_Y_TILING(dev))
2433 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2435 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2437 val = obj_priv->gtt_offset;
2438 if (obj_priv->tiling_mode == I915_TILING_Y)
2439 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2440 val |= I915_FENCE_SIZE_BITS(size);
2441 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2442 val |= I830_FENCE_REG_VALID;
2444 fence_reg = obj_priv->fence_reg;
2446 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2448 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2449 I915_WRITE(fence_reg, val);
2452 static void i830_write_fence_reg(struct drm_gem_object *obj)
2454 struct drm_device *dev = obj->dev;
2455 drm_i915_private_t *dev_priv = dev->dev_private;
2456 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2457 u32 size = i915_gem_get_gtt_size(obj_priv);
2458 int regnum = obj_priv->fence_reg;
2461 uint32_t fence_size_bits;
2463 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2464 (obj_priv->gtt_offset & (obj->size - 1))) {
2465 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2466 __func__, obj_priv->gtt_offset);
2470 pitch_val = obj_priv->stride / 128;
2471 pitch_val = ffs(pitch_val) - 1;
2472 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2474 val = obj_priv->gtt_offset;
2475 if (obj_priv->tiling_mode == I915_TILING_Y)
2476 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2477 fence_size_bits = I830_FENCE_SIZE_BITS(size);
2478 WARN_ON(fence_size_bits & ~0x00000f00);
2479 val |= fence_size_bits;
2480 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2481 val |= I830_FENCE_REG_VALID;
2483 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2486 static int i915_find_fence_reg(struct drm_device *dev,
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490 struct drm_i915_fence_reg *reg;
2491 struct drm_i915_gem_object *obj_priv = NULL;
2494 /* First try to find a free reg */
2496 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2497 reg = &dev_priv->fence_regs[i];
2501 obj_priv = to_intel_bo(reg->obj);
2502 if (!obj_priv->pin_count)
2509 /* None available, try to steal one or wait for a user to finish */
2510 avail = I915_FENCE_REG_NONE;
2511 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2513 obj_priv = to_intel_bo(reg->obj);
2514 if (obj_priv->pin_count)
2518 avail = obj_priv->fence_reg;
2522 BUG_ON(avail == I915_FENCE_REG_NONE);
2524 /* We only have a reference on obj from the active list. put_fence_reg
2525 * might drop that one, causing a use-after-free in it. So hold a
2526 * private reference to obj like the other callers of put_fence_reg
2527 * (set_tiling ioctl) do. */
2528 drm_gem_object_reference(&obj_priv->base);
2529 ret = i915_gem_object_put_fence_reg(&obj_priv->base, interruptible);
2530 drm_gem_object_unreference(&obj_priv->base);
2538 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2539 * @obj: object to map through a fence reg
2541 * When mapping objects through the GTT, userspace wants to be able to write
2542 * to them without having to worry about swizzling if the object is tiled.
2544 * This function walks the fence regs looking for a free one for @obj,
2545 * stealing one if it can't find any.
2547 * It then sets up the reg based on the object's properties: address, pitch
2548 * and tiling format.
2551 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2554 struct drm_device *dev = obj->dev;
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2557 struct drm_i915_fence_reg *reg = NULL;
2560 /* Just update our place in the LRU if our fence is getting used. */
2561 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2562 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2563 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2567 switch (obj_priv->tiling_mode) {
2568 case I915_TILING_NONE:
2569 WARN(1, "allocating a fence for non-tiled object?\n");
2572 if (!obj_priv->stride)
2574 WARN((obj_priv->stride & (512 - 1)),
2575 "object 0x%08x is X tiled but has non-512B pitch\n",
2576 obj_priv->gtt_offset);
2579 if (!obj_priv->stride)
2581 WARN((obj_priv->stride & (128 - 1)),
2582 "object 0x%08x is Y tiled but has non-128B pitch\n",
2583 obj_priv->gtt_offset);
2587 ret = i915_find_fence_reg(dev, interruptible);
2591 obj_priv->fence_reg = ret;
2592 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2593 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2597 switch (INTEL_INFO(dev)->gen) {
2599 sandybridge_write_fence_reg(obj);
2603 i965_write_fence_reg(obj);
2606 i915_write_fence_reg(obj);
2609 i830_write_fence_reg(obj);
2613 trace_i915_gem_object_get_fence(obj,
2614 obj_priv->fence_reg,
2615 obj_priv->tiling_mode);
2621 * i915_gem_clear_fence_reg - clear out fence register info
2622 * @obj: object to clear
2624 * Zeroes out the fence register itself and clears out the associated
2625 * data structures in dev_priv and obj_priv.
2628 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2630 struct drm_device *dev = obj->dev;
2631 drm_i915_private_t *dev_priv = dev->dev_private;
2632 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2633 struct drm_i915_fence_reg *reg =
2634 &dev_priv->fence_regs[obj_priv->fence_reg];
2637 switch (INTEL_INFO(dev)->gen) {
2639 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2640 (obj_priv->fence_reg * 8), 0);
2644 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2647 if (obj_priv->fence_reg >= 8)
2648 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2651 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2653 I915_WRITE(fence_reg, 0);
2658 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2659 list_del_init(®->lru_list);
2663 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2664 * to the buffer to finish, and then resets the fence register.
2665 * @obj: tiled object holding a fence register.
2666 * @bool: whether the wait upon the fence is interruptible
2668 * Zeroes out the fence register itself and clears out the associated
2669 * data structures in dev_priv and obj_priv.
2672 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2675 struct drm_device *dev = obj->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2678 struct drm_i915_fence_reg *reg;
2680 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2683 /* If we've changed tiling, GTT-mappings of the object
2684 * need to re-fault to ensure that the correct fence register
2685 * setup is in place.
2687 i915_gem_release_mmap(obj);
2689 /* On the i915, GPU access to tiled buffers is via a fence,
2690 * therefore we must wait for any outstanding access to complete
2691 * before clearing the fence.
2693 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2697 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2701 ret = i915_gem_object_wait_rendering(obj, interruptible);
2708 i915_gem_object_flush_gtt_write_domain(obj);
2709 i915_gem_clear_fence_reg(obj);
2715 * Finds free space in the GTT aperture and binds the object there.
2718 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
2720 bool map_and_fenceable)
2722 struct drm_device *dev = obj->dev;
2723 drm_i915_private_t *dev_priv = dev->dev_private;
2724 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2725 struct drm_mm_node *free_space;
2726 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2727 u32 size, fence_size, fence_alignment, unfenced_alignment;
2728 bool mappable, fenceable;
2731 if (obj_priv->madv != I915_MADV_WILLNEED) {
2732 DRM_ERROR("Attempting to bind a purgeable object\n");
2736 fence_size = i915_gem_get_gtt_size(obj_priv);
2737 fence_alignment = i915_gem_get_gtt_alignment(obj_priv);
2738 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj_priv);
2741 alignment = map_and_fenceable ? fence_alignment :
2743 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2744 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2748 size = map_and_fenceable ? fence_size : obj->size;
2750 /* If the object is bigger than the entire aperture, reject it early
2751 * before evicting everything in a vain attempt to find space.
2754 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2755 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2760 if (map_and_fenceable)
2762 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2764 dev_priv->mm.gtt_mappable_end,
2767 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2768 size, alignment, 0);
2770 if (free_space != NULL) {
2771 if (map_and_fenceable)
2772 obj_priv->gtt_space =
2773 drm_mm_get_block_range_generic(free_space,
2775 dev_priv->mm.gtt_mappable_end,
2778 obj_priv->gtt_space =
2779 drm_mm_get_block(free_space, size, alignment);
2781 if (obj_priv->gtt_space == NULL) {
2782 /* If the gtt is empty and we're still having trouble
2783 * fitting our object in, we're out of memory.
2785 ret = i915_gem_evict_something(dev, size, alignment,
2793 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2795 drm_mm_put_block(obj_priv->gtt_space);
2796 obj_priv->gtt_space = NULL;
2798 if (ret == -ENOMEM) {
2799 /* first try to clear up some space from the GTT */
2800 ret = i915_gem_evict_something(dev, size,
2804 /* now try to shrink everyone else */
2819 /* Create an AGP memory structure pointing at our pages, and bind it
2822 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2824 obj->size >> PAGE_SHIFT,
2825 obj_priv->gtt_space->start,
2826 obj_priv->agp_type);
2827 if (obj_priv->agp_mem == NULL) {
2828 i915_gem_object_put_pages_gtt(obj);
2829 drm_mm_put_block(obj_priv->gtt_space);
2830 obj_priv->gtt_space = NULL;
2832 ret = i915_gem_evict_something(dev, size,
2833 alignment, map_and_fenceable);
2840 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2842 /* keep track of bounds object by adding it to the inactive list */
2843 list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
2844 i915_gem_info_add_gtt(dev_priv, obj_priv);
2846 /* Assert that the object is not currently in any GPU domain. As it
2847 * wasn't in the GTT, there shouldn't be any way it could have been in
2850 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2851 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2853 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, map_and_fenceable);
2856 obj_priv->gtt_space->size == fence_size &&
2857 (obj_priv->gtt_space->start & (fence_alignment -1)) == 0;
2860 obj_priv->gtt_offset + obj->size <= dev_priv->mm.gtt_mappable_end;
2862 obj_priv->map_and_fenceable = mappable && fenceable;
2868 i915_gem_clflush_object(struct drm_gem_object *obj)
2870 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2872 /* If we don't have a page list set up, then we're not pinned
2873 * to GPU, and we can ignore the cache flush because it'll happen
2874 * again at bind time.
2876 if (obj_priv->pages == NULL)
2879 trace_i915_gem_object_clflush(obj);
2881 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2884 /** Flushes any GPU write domain for the object if it's dirty. */
2886 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2889 struct drm_device *dev = obj->dev;
2891 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2894 /* Queue the GPU write cache flushing we need. */
2895 i915_gem_flush_ring(dev, NULL,
2896 to_intel_bo(obj)->ring,
2897 0, obj->write_domain);
2898 BUG_ON(obj->write_domain);
2903 return i915_gem_object_wait_rendering(obj, true);
2906 /** Flushes the GTT write domain for the object if it's dirty. */
2908 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2910 uint32_t old_write_domain;
2912 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2915 /* No actual flushing is required for the GTT write domain. Writes
2916 * to it immediately go to main memory as far as we know, so there's
2917 * no chipset flush. It also doesn't land in render cache.
2919 i915_gem_release_mmap(obj);
2921 old_write_domain = obj->write_domain;
2922 obj->write_domain = 0;
2924 trace_i915_gem_object_change_domain(obj,
2929 /** Flushes the CPU write domain for the object if it's dirty. */
2931 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2933 struct drm_device *dev = obj->dev;
2934 uint32_t old_write_domain;
2936 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2939 i915_gem_clflush_object(obj);
2940 drm_agp_chipset_flush(dev);
2941 old_write_domain = obj->write_domain;
2942 obj->write_domain = 0;
2944 trace_i915_gem_object_change_domain(obj,
2950 * Moves a single object to the GTT read, and possibly write domain.
2952 * This function returns when the move is complete, including waiting on
2956 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2958 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2959 uint32_t old_write_domain, old_read_domains;
2962 /* Not valid to be called on unbound objects. */
2963 if (obj_priv->gtt_space == NULL)
2966 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2970 i915_gem_object_flush_cpu_write_domain(obj);
2973 ret = i915_gem_object_wait_rendering(obj, true);
2978 old_write_domain = obj->write_domain;
2979 old_read_domains = obj->read_domains;
2981 /* It should now be out of any other write domains, and we can update
2982 * the domain values for our changes.
2984 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2985 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2987 obj->read_domains = I915_GEM_DOMAIN_GTT;
2988 obj->write_domain = I915_GEM_DOMAIN_GTT;
2989 obj_priv->dirty = 1;
2992 trace_i915_gem_object_change_domain(obj,
3000 * Prepare buffer for display plane. Use uninterruptible for possible flush
3001 * wait, as in modesetting process we're not supposed to be interrupted.
3004 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
3007 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3008 uint32_t old_read_domains;
3011 /* Not valid to be called on unbound objects. */
3012 if (obj_priv->gtt_space == NULL)
3015 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
3019 /* Currently, we are always called from an non-interruptible context. */
3021 ret = i915_gem_object_wait_rendering(obj, false);
3026 i915_gem_object_flush_cpu_write_domain(obj);
3028 old_read_domains = obj->read_domains;
3029 obj->read_domains |= I915_GEM_DOMAIN_GTT;
3031 trace_i915_gem_object_change_domain(obj,
3039 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
3045 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
3046 i915_gem_flush_ring(obj->base.dev, NULL, obj->ring,
3047 0, obj->base.write_domain);
3049 return i915_gem_object_wait_rendering(&obj->base, interruptible);
3053 * Moves a single object to the CPU read, and possibly write domain.
3055 * This function returns when the move is complete, including waiting on
3059 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
3061 uint32_t old_write_domain, old_read_domains;
3064 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3068 i915_gem_object_flush_gtt_write_domain(obj);
3070 /* If we have a partially-valid cache of the object in the CPU,
3071 * finish invalidating it and free the per-page flags.
3073 i915_gem_object_set_to_full_cpu_read_domain(obj);
3076 ret = i915_gem_object_wait_rendering(obj, true);
3081 old_write_domain = obj->write_domain;
3082 old_read_domains = obj->read_domains;
3084 /* Flush the CPU cache if it's still invalid. */
3085 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3086 i915_gem_clflush_object(obj);
3088 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3091 /* It should now be out of any other write domains, and we can update
3092 * the domain values for our changes.
3094 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3096 /* If we're writing through the CPU, then the GPU read domains will
3097 * need to be invalidated at next use.
3100 obj->read_domains = I915_GEM_DOMAIN_CPU;
3101 obj->write_domain = I915_GEM_DOMAIN_CPU;
3104 trace_i915_gem_object_change_domain(obj,
3112 * Set the next domain for the specified object. This
3113 * may not actually perform the necessary flushing/invaliding though,
3114 * as that may want to be batched with other set_domain operations
3116 * This is (we hope) the only really tricky part of gem. The goal
3117 * is fairly simple -- track which caches hold bits of the object
3118 * and make sure they remain coherent. A few concrete examples may
3119 * help to explain how it works. For shorthand, we use the notation
3120 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3121 * a pair of read and write domain masks.
3123 * Case 1: the batch buffer
3129 * 5. Unmapped from GTT
3132 * Let's take these a step at a time
3135 * Pages allocated from the kernel may still have
3136 * cache contents, so we set them to (CPU, CPU) always.
3137 * 2. Written by CPU (using pwrite)
3138 * The pwrite function calls set_domain (CPU, CPU) and
3139 * this function does nothing (as nothing changes)
3141 * This function asserts that the object is not
3142 * currently in any GPU-based read or write domains
3144 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3145 * As write_domain is zero, this function adds in the
3146 * current read domains (CPU+COMMAND, 0).
3147 * flush_domains is set to CPU.
3148 * invalidate_domains is set to COMMAND
3149 * clflush is run to get data out of the CPU caches
3150 * then i915_dev_set_domain calls i915_gem_flush to
3151 * emit an MI_FLUSH and drm_agp_chipset_flush
3152 * 5. Unmapped from GTT
3153 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3154 * flush_domains and invalidate_domains end up both zero
3155 * so no flushing/invalidating happens
3159 * Case 2: The shared render buffer
3163 * 3. Read/written by GPU
3164 * 4. set_domain to (CPU,CPU)
3165 * 5. Read/written by CPU
3166 * 6. Read/written by GPU
3169 * Same as last example, (CPU, CPU)
3171 * Nothing changes (assertions find that it is not in the GPU)
3172 * 3. Read/written by GPU
3173 * execbuffer calls set_domain (RENDER, RENDER)
3174 * flush_domains gets CPU
3175 * invalidate_domains gets GPU
3177 * MI_FLUSH and drm_agp_chipset_flush
3178 * 4. set_domain (CPU, CPU)
3179 * flush_domains gets GPU
3180 * invalidate_domains gets CPU
3181 * wait_rendering (obj) to make sure all drawing is complete.
3182 * This will include an MI_FLUSH to get the data from GPU
3184 * clflush (obj) to invalidate the CPU cache
3185 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3186 * 5. Read/written by CPU
3187 * cache lines are loaded and dirtied
3188 * 6. Read written by GPU
3189 * Same as last GPU access
3191 * Case 3: The constant buffer
3196 * 4. Updated (written) by CPU again
3205 * flush_domains = CPU
3206 * invalidate_domains = RENDER
3209 * drm_agp_chipset_flush
3210 * 4. Updated (written) by CPU again
3212 * flush_domains = 0 (no previous write domain)
3213 * invalidate_domains = 0 (no new read domains)
3216 * flush_domains = CPU
3217 * invalidate_domains = RENDER
3220 * drm_agp_chipset_flush
3223 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
3224 struct intel_ring_buffer *ring,
3225 struct change_domains *cd)
3227 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3228 uint32_t invalidate_domains = 0;
3229 uint32_t flush_domains = 0;
3232 * If the object isn't moving to a new write domain,
3233 * let the object stay in multiple read domains
3235 if (obj->pending_write_domain == 0)
3236 obj->pending_read_domains |= obj->read_domains;
3239 * Flush the current write domain if
3240 * the new read domains don't match. Invalidate
3241 * any read domains which differ from the old
3244 if (obj->write_domain &&
3245 (obj->write_domain != obj->pending_read_domains ||
3246 obj_priv->ring != ring)) {
3247 flush_domains |= obj->write_domain;
3248 invalidate_domains |=
3249 obj->pending_read_domains & ~obj->write_domain;
3252 * Invalidate any read caches which may have
3253 * stale data. That is, any new read domains.
3255 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3256 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3257 i915_gem_clflush_object(obj);
3259 /* blow away mappings if mapped through GTT */
3260 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT)
3261 i915_gem_release_mmap(obj);
3263 /* The actual obj->write_domain will be updated with
3264 * pending_write_domain after we emit the accumulated flush for all
3265 * of our domain changes in execbuffers (which clears objects'
3266 * write_domains). So if we have a current write domain that we
3267 * aren't changing, set pending_write_domain to that.
3269 if (flush_domains == 0 && obj->pending_write_domain == 0)
3270 obj->pending_write_domain = obj->write_domain;
3272 cd->invalidate_domains |= invalidate_domains;
3273 cd->flush_domains |= flush_domains;
3274 if (flush_domains & I915_GEM_GPU_DOMAINS)
3275 cd->flush_rings |= obj_priv->ring->id;
3276 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
3277 cd->flush_rings |= ring->id;
3281 * Moves the object from a partially CPU read to a full one.
3283 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3284 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3287 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3289 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3291 if (!obj_priv->page_cpu_valid)
3294 /* If we're partially in the CPU read domain, finish moving it in.
3296 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3299 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3300 if (obj_priv->page_cpu_valid[i])
3302 drm_clflush_pages(obj_priv->pages + i, 1);
3306 /* Free the page_cpu_valid mappings which are now stale, whether
3307 * or not we've got I915_GEM_DOMAIN_CPU.
3309 kfree(obj_priv->page_cpu_valid);
3310 obj_priv->page_cpu_valid = NULL;
3314 * Set the CPU read domain on a range of the object.
3316 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3317 * not entirely valid. The page_cpu_valid member of the object flags which
3318 * pages have been flushed, and will be respected by
3319 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3320 * of the whole object.
3322 * This function returns when the move is complete, including waiting on
3326 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3327 uint64_t offset, uint64_t size)
3329 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3330 uint32_t old_read_domains;
3333 if (offset == 0 && size == obj->size)
3334 return i915_gem_object_set_to_cpu_domain(obj, 0);
3336 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3339 i915_gem_object_flush_gtt_write_domain(obj);
3341 /* If we're already fully in the CPU read domain, we're done. */
3342 if (obj_priv->page_cpu_valid == NULL &&
3343 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3346 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3347 * newly adding I915_GEM_DOMAIN_CPU
3349 if (obj_priv->page_cpu_valid == NULL) {
3350 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3352 if (obj_priv->page_cpu_valid == NULL)
3354 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3355 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3357 /* Flush the cache on any pages that are still invalid from the CPU's
3360 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3362 if (obj_priv->page_cpu_valid[i])
3365 drm_clflush_pages(obj_priv->pages + i, 1);
3367 obj_priv->page_cpu_valid[i] = 1;
3370 /* It should now be out of any other write domains, and we can update
3371 * the domain values for our changes.
3373 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3375 old_read_domains = obj->read_domains;
3376 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3378 trace_i915_gem_object_change_domain(obj,
3386 * Pin an object to the GTT and evaluate the relocations landing in it.
3389 i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj,
3390 struct drm_file *file_priv,
3391 struct drm_i915_gem_exec_object2 *entry)
3393 struct drm_device *dev = obj->base.dev;
3394 drm_i915_private_t *dev_priv = dev->dev_private;
3395 struct drm_i915_gem_relocation_entry __user *user_relocs;
3396 struct drm_gem_object *target_obj = NULL;
3397 uint32_t target_handle = 0;
3400 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3401 for (i = 0; i < entry->relocation_count; i++) {
3402 struct drm_i915_gem_relocation_entry reloc;
3403 uint32_t target_offset;
3405 if (__copy_from_user_inatomic(&reloc,
3412 if (reloc.target_handle != target_handle) {
3413 drm_gem_object_unreference(target_obj);
3415 target_obj = drm_gem_object_lookup(dev, file_priv,
3416 reloc.target_handle);
3417 if (target_obj == NULL) {
3422 target_handle = reloc.target_handle;
3424 target_offset = to_intel_bo(target_obj)->gtt_offset;
3427 DRM_INFO("%s: obj %p offset %08x target %d "
3428 "read %08x write %08x gtt %08x "
3429 "presumed %08x delta %08x\n",
3433 (int) reloc.target_handle,
3434 (int) reloc.read_domains,
3435 (int) reloc.write_domain,
3436 (int) target_offset,
3437 (int) reloc.presumed_offset,
3441 /* The target buffer should have appeared before us in the
3442 * exec_object list, so it should have a GTT space bound by now.
3444 if (target_offset == 0) {
3445 DRM_ERROR("No GTT space found for object %d\n",
3446 reloc.target_handle);
3451 /* Validate that the target is in a valid r/w GPU domain */
3452 if (reloc.write_domain & (reloc.write_domain - 1)) {
3453 DRM_ERROR("reloc with multiple write domains: "
3454 "obj %p target %d offset %d "
3455 "read %08x write %08x",
3456 obj, reloc.target_handle,
3459 reloc.write_domain);
3463 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
3464 reloc.read_domains & I915_GEM_DOMAIN_CPU) {
3465 DRM_ERROR("reloc with read/write CPU domains: "
3466 "obj %p target %d offset %d "
3467 "read %08x write %08x",
3468 obj, reloc.target_handle,
3471 reloc.write_domain);
3475 if (reloc.write_domain && target_obj->pending_write_domain &&
3476 reloc.write_domain != target_obj->pending_write_domain) {
3477 DRM_ERROR("Write domain conflict: "
3478 "obj %p target %d offset %d "
3479 "new %08x old %08x\n",
3480 obj, reloc.target_handle,
3483 target_obj->pending_write_domain);
3488 target_obj->pending_read_domains |= reloc.read_domains;
3489 target_obj->pending_write_domain |= reloc.write_domain;
3491 /* If the relocation already has the right value in it, no
3492 * more work needs to be done.
3494 if (target_offset == reloc.presumed_offset)
3497 /* Check that the relocation address is valid... */
3498 if (reloc.offset > obj->base.size - 4) {
3499 DRM_ERROR("Relocation beyond object bounds: "
3500 "obj %p target %d offset %d size %d.\n",
3501 obj, reloc.target_handle,
3502 (int) reloc.offset, (int) obj->base.size);
3506 if (reloc.offset & 3) {
3507 DRM_ERROR("Relocation not 4-byte aligned: "
3508 "obj %p target %d offset %d.\n",
3509 obj, reloc.target_handle,
3510 (int) reloc.offset);
3515 /* and points to somewhere within the target object. */
3516 if (reloc.delta >= target_obj->size) {
3517 DRM_ERROR("Relocation beyond target object bounds: "
3518 "obj %p target %d delta %d size %d.\n",
3519 obj, reloc.target_handle,
3520 (int) reloc.delta, (int) target_obj->size);
3525 reloc.delta += target_offset;
3526 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3527 uint32_t page_offset = reloc.offset & ~PAGE_MASK;
3530 vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]);
3531 *(uint32_t *)(vaddr + page_offset) = reloc.delta;
3532 kunmap_atomic(vaddr);
3534 uint32_t __iomem *reloc_entry;
3535 void __iomem *reloc_page;
3537 ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
3541 /* Map the page containing the relocation we're going to perform. */
3542 reloc.offset += obj->gtt_offset;
3543 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3544 reloc.offset & PAGE_MASK);
3545 reloc_entry = (uint32_t __iomem *)
3546 (reloc_page + (reloc.offset & ~PAGE_MASK));
3547 iowrite32(reloc.delta, reloc_entry);
3548 io_mapping_unmap_atomic(reloc_page);
3551 /* and update the user's relocation entry */
3552 reloc.presumed_offset = target_offset;
3553 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
3554 &reloc.presumed_offset,
3555 sizeof(reloc.presumed_offset))) {
3561 drm_gem_object_unreference(target_obj);
3566 i915_gem_execbuffer_pin(struct drm_device *dev,
3567 struct drm_file *file,
3568 struct drm_gem_object **object_list,
3569 struct drm_i915_gem_exec_object2 *exec_list,
3572 struct drm_i915_private *dev_priv = dev->dev_private;
3575 /* attempt to pin all of the buffers into the GTT */
3579 for (i = 0; i < count; i++) {
3580 struct drm_i915_gem_exec_object2 *entry = &exec_list[i];
3581 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3583 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3584 obj->tiling_mode != I915_TILING_NONE;
3586 /* g33/pnv can't fence buffers in the unmappable part */
3587 bool need_mappable =
3588 entry->relocation_count ? true : need_fence;
3590 /* Check fence reg constraints and rebind if necessary */
3591 if (need_mappable && !obj->map_and_fenceable) {
3592 ret = i915_gem_object_unbind(&obj->base);
3597 ret = i915_gem_object_pin(&obj->base,
3604 * Pre-965 chips need a fence register set up in order
3605 * to properly handle blits to/from tiled surfaces.
3608 ret = i915_gem_object_get_fence_reg(&obj->base, true);
3610 i915_gem_object_unpin(&obj->base);
3614 dev_priv->fence_regs[obj->fence_reg].gpu = true;
3617 entry->offset = obj->gtt_offset;
3621 i915_gem_object_unpin(object_list[i]);
3623 if (ret != -ENOSPC || retry > 1)
3626 /* First attempt, just clear anything that is purgeable.
3627 * Second attempt, clear the entire GTT.
3629 ret = i915_gem_evict_everything(dev, retry == 0);
3638 i915_gem_execbuffer_move_to_gpu(struct drm_device *dev,
3639 struct drm_file *file,
3640 struct intel_ring_buffer *ring,
3641 struct drm_gem_object **objects,
3644 struct change_domains cd;
3647 cd.invalidate_domains = 0;
3648 cd.flush_domains = 0;
3650 for (i = 0; i < count; i++)
3651 i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd);
3653 if (cd.invalidate_domains | cd.flush_domains) {
3655 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3657 cd.invalidate_domains,
3660 i915_gem_flush(dev, file,
3661 cd.invalidate_domains,
3666 for (i = 0; i < count; i++) {
3667 struct drm_i915_gem_object *obj = to_intel_bo(objects[i]);
3668 /* XXX replace with semaphores */
3669 if (obj->ring && ring != obj->ring) {
3670 ret = i915_gem_object_wait_rendering(&obj->base, true);
3679 /* Throttle our rendering by waiting until the ring has completed our requests
3680 * emitted over 20 msec ago.
3682 * Note that if we were to use the current jiffies each time around the loop,
3683 * we wouldn't escape the function with any frames outstanding if the time to
3684 * render a frame was over 20ms.
3686 * This should get us reasonable parallelism between CPU and GPU but also
3687 * relatively low latency when blocking on a particular request to finish.
3690 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 struct drm_i915_file_private *file_priv = file->driver_priv;
3694 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3695 struct drm_i915_gem_request *request;
3696 struct intel_ring_buffer *ring = NULL;
3700 spin_lock(&file_priv->mm.lock);
3701 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3702 if (time_after_eq(request->emitted_jiffies, recent_enough))
3705 ring = request->ring;
3706 seqno = request->seqno;
3708 spin_unlock(&file_priv->mm.lock);
3714 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3715 /* And wait for the seqno passing without holding any locks and
3716 * causing extra latency for others. This is safe as the irq
3717 * generation is designed to be run atomically and so is
3720 ring->user_irq_get(ring);
3721 ret = wait_event_interruptible(ring->irq_queue,
3722 i915_seqno_passed(ring->get_seqno(ring), seqno)
3723 || atomic_read(&dev_priv->mm.wedged));
3724 ring->user_irq_put(ring);
3726 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3731 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3737 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec,
3738 uint64_t exec_offset)
3740 uint32_t exec_start, exec_len;
3742 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3743 exec_len = (uint32_t) exec->batch_len;
3745 if ((exec_start | exec_len) & 0x7)
3755 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3760 for (i = 0; i < count; i++) {
3761 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3762 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry);
3764 if (!access_ok(VERIFY_READ, ptr, length))
3767 /* we may also need to update the presumed offsets */
3768 if (!access_ok(VERIFY_WRITE, ptr, length))
3771 if (fault_in_pages_readable(ptr, length))
3779 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3780 struct drm_file *file,
3781 struct drm_i915_gem_execbuffer2 *args,
3782 struct drm_i915_gem_exec_object2 *exec_list)
3784 drm_i915_private_t *dev_priv = dev->dev_private;
3785 struct drm_gem_object **object_list = NULL;
3786 struct drm_gem_object *batch_obj;
3787 struct drm_clip_rect *cliprects = NULL;
3788 struct drm_i915_gem_request *request = NULL;
3790 uint64_t exec_offset;
3792 struct intel_ring_buffer *ring = NULL;
3794 ret = i915_gem_check_is_wedged(dev);
3798 ret = validate_exec_list(exec_list, args->buffer_count);
3803 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3804 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3806 switch (args->flags & I915_EXEC_RING_MASK) {
3807 case I915_EXEC_DEFAULT:
3808 case I915_EXEC_RENDER:
3809 ring = &dev_priv->render_ring;
3812 if (!HAS_BSD(dev)) {
3813 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3816 ring = &dev_priv->bsd_ring;
3819 if (!HAS_BLT(dev)) {
3820 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3823 ring = &dev_priv->blt_ring;
3826 DRM_ERROR("execbuf with unknown ring: %d\n",
3827 (int)(args->flags & I915_EXEC_RING_MASK));
3831 if (args->buffer_count < 1) {
3832 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3835 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3836 if (object_list == NULL) {
3837 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3838 args->buffer_count);
3843 if (args->num_cliprects != 0) {
3844 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3846 if (cliprects == NULL) {
3851 ret = copy_from_user(cliprects,
3852 (struct drm_clip_rect __user *)
3853 (uintptr_t) args->cliprects_ptr,
3854 sizeof(*cliprects) * args->num_cliprects);
3856 DRM_ERROR("copy %d cliprects failed: %d\n",
3857 args->num_cliprects, ret);
3863 request = kzalloc(sizeof(*request), GFP_KERNEL);
3864 if (request == NULL) {
3869 ret = i915_mutex_lock_interruptible(dev);
3873 if (dev_priv->mm.suspended) {
3874 mutex_unlock(&dev->struct_mutex);
3879 /* Look up object handles */
3880 for (i = 0; i < args->buffer_count; i++) {
3881 struct drm_i915_gem_object *obj_priv;
3883 object_list[i] = drm_gem_object_lookup(dev, file,
3884 exec_list[i].handle);
3885 if (object_list[i] == NULL) {
3886 DRM_ERROR("Invalid object handle %d at index %d\n",
3887 exec_list[i].handle, i);
3888 /* prevent error path from reading uninitialized data */
3889 args->buffer_count = i + 1;
3894 obj_priv = to_intel_bo(object_list[i]);
3895 if (obj_priv->in_execbuffer) {
3896 DRM_ERROR("Object %p appears more than once in object list\n",
3898 /* prevent error path from reading uninitialized data */
3899 args->buffer_count = i + 1;
3903 obj_priv->in_execbuffer = true;
3906 /* Move the objects en-masse into the GTT, evicting if necessary. */
3907 ret = i915_gem_execbuffer_pin(dev, file,
3908 object_list, exec_list,
3909 args->buffer_count);
3913 /* The objects are in their final locations, apply the relocations. */
3914 for (i = 0; i < args->buffer_count; i++) {
3915 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3916 obj->base.pending_read_domains = 0;
3917 obj->base.pending_write_domain = 0;
3918 ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]);
3923 /* Set the pending read domains for the batch buffer to COMMAND */
3924 batch_obj = object_list[args->buffer_count-1];
3925 if (batch_obj->pending_write_domain) {
3926 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3930 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3932 /* Sanity check the batch buffer */
3933 exec_offset = to_intel_bo(batch_obj)->gtt_offset;
3934 ret = i915_gem_check_execbuffer(args, exec_offset);
3936 DRM_ERROR("execbuf with invalid offset/length\n");
3940 ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring,
3941 object_list, args->buffer_count);
3946 for (i = 0; i < args->buffer_count; i++) {
3947 i915_gem_object_check_coherency(object_list[i],
3948 exec_list[i].handle);
3953 i915_gem_dump_object(batch_obj,
3959 /* Check for any pending flips. As we only maintain a flip queue depth
3960 * of 1, we can simply insert a WAIT for the next display flip prior
3961 * to executing the batch and avoid stalling the CPU.
3964 for (i = 0; i < args->buffer_count; i++) {
3965 if (object_list[i]->write_domain)
3966 flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip);
3969 int plane, flip_mask;
3971 for (plane = 0; flips >> plane; plane++) {
3972 if (((flips >> plane) & 1) == 0)
3976 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
3978 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
3980 ret = intel_ring_begin(ring, 2);
3984 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
3985 intel_ring_emit(ring, MI_NOOP);
3986 intel_ring_advance(ring);
3990 /* Exec the batchbuffer */
3991 ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset);
3993 DRM_ERROR("dispatch failed %d\n", ret);
3997 for (i = 0; i < args->buffer_count; i++) {
3998 struct drm_gem_object *obj = object_list[i];
4000 obj->read_domains = obj->pending_read_domains;
4001 obj->write_domain = obj->pending_write_domain;
4003 i915_gem_object_move_to_active(obj, ring);
4004 if (obj->write_domain) {
4005 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4006 obj_priv->dirty = 1;
4007 list_move_tail(&obj_priv->gpu_write_list,
4008 &ring->gpu_write_list);
4009 intel_mark_busy(dev, obj);
4012 trace_i915_gem_object_change_domain(obj,
4018 * Ensure that the commands in the batch buffer are
4019 * finished before the interrupt fires
4021 i915_retire_commands(dev, ring);
4023 if (i915_add_request(dev, file, request, ring))
4024 i915_gem_next_request_seqno(dev, ring);
4029 for (i = 0; i < args->buffer_count; i++) {
4030 if (object_list[i] == NULL)
4033 to_intel_bo(object_list[i])->in_execbuffer = false;
4034 drm_gem_object_unreference(object_list[i]);
4037 mutex_unlock(&dev->struct_mutex);
4040 drm_free_large(object_list);
4048 * Legacy execbuffer just creates an exec2 list from the original exec object
4049 * list array and passes it to the real function.
4052 i915_gem_execbuffer(struct drm_device *dev, void *data,
4053 struct drm_file *file_priv)
4055 struct drm_i915_gem_execbuffer *args = data;
4056 struct drm_i915_gem_execbuffer2 exec2;
4057 struct drm_i915_gem_exec_object *exec_list = NULL;
4058 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4062 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4063 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4066 if (args->buffer_count < 1) {
4067 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4071 /* Copy in the exec list from userland */
4072 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4073 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4074 if (exec_list == NULL || exec2_list == NULL) {
4075 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4076 args->buffer_count);
4077 drm_free_large(exec_list);
4078 drm_free_large(exec2_list);
4081 ret = copy_from_user(exec_list,
4082 (struct drm_i915_relocation_entry __user *)
4083 (uintptr_t) args->buffers_ptr,
4084 sizeof(*exec_list) * args->buffer_count);
4086 DRM_ERROR("copy %d exec entries failed %d\n",
4087 args->buffer_count, ret);
4088 drm_free_large(exec_list);
4089 drm_free_large(exec2_list);
4093 for (i = 0; i < args->buffer_count; i++) {
4094 exec2_list[i].handle = exec_list[i].handle;
4095 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4096 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4097 exec2_list[i].alignment = exec_list[i].alignment;
4098 exec2_list[i].offset = exec_list[i].offset;
4099 if (INTEL_INFO(dev)->gen < 4)
4100 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4102 exec2_list[i].flags = 0;
4105 exec2.buffers_ptr = args->buffers_ptr;
4106 exec2.buffer_count = args->buffer_count;
4107 exec2.batch_start_offset = args->batch_start_offset;
4108 exec2.batch_len = args->batch_len;
4109 exec2.DR1 = args->DR1;
4110 exec2.DR4 = args->DR4;
4111 exec2.num_cliprects = args->num_cliprects;
4112 exec2.cliprects_ptr = args->cliprects_ptr;
4113 exec2.flags = I915_EXEC_RENDER;
4115 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4117 /* Copy the new buffer offsets back to the user's exec list. */
4118 for (i = 0; i < args->buffer_count; i++)
4119 exec_list[i].offset = exec2_list[i].offset;
4120 /* ... and back out to userspace */
4121 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4122 (uintptr_t) args->buffers_ptr,
4124 sizeof(*exec_list) * args->buffer_count);
4127 DRM_ERROR("failed to copy %d exec entries "
4128 "back to user (%d)\n",
4129 args->buffer_count, ret);
4133 drm_free_large(exec_list);
4134 drm_free_large(exec2_list);
4139 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4140 struct drm_file *file_priv)
4142 struct drm_i915_gem_execbuffer2 *args = data;
4143 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4147 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4148 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4151 if (args->buffer_count < 1) {
4152 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4156 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4157 if (exec2_list == NULL) {
4158 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4159 args->buffer_count);
4162 ret = copy_from_user(exec2_list,
4163 (struct drm_i915_relocation_entry __user *)
4164 (uintptr_t) args->buffers_ptr,
4165 sizeof(*exec2_list) * args->buffer_count);
4167 DRM_ERROR("copy %d exec entries failed %d\n",
4168 args->buffer_count, ret);
4169 drm_free_large(exec2_list);
4173 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4175 /* Copy the new buffer offsets back to the user's exec list. */
4176 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4177 (uintptr_t) args->buffers_ptr,
4179 sizeof(*exec2_list) * args->buffer_count);
4182 DRM_ERROR("failed to copy %d exec entries "
4183 "back to user (%d)\n",
4184 args->buffer_count, ret);
4188 drm_free_large(exec2_list);
4193 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment,
4194 bool map_and_fenceable)
4196 struct drm_device *dev = obj->dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4201 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4202 BUG_ON(map_and_fenceable && !map_and_fenceable);
4203 WARN_ON(i915_verify_lists(dev));
4205 if (obj_priv->gtt_space != NULL) {
4206 if ((alignment && obj_priv->gtt_offset & (alignment - 1)) ||
4207 (map_and_fenceable && !obj_priv->map_and_fenceable)) {
4208 WARN(obj_priv->pin_count,
4209 "bo is already pinned with incorrect alignment:"
4210 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
4211 " obj->map_and_fenceable=%d\n",
4212 obj_priv->gtt_offset, alignment,
4214 obj_priv->map_and_fenceable);
4215 ret = i915_gem_object_unbind(obj);
4221 if (obj_priv->gtt_space == NULL) {
4222 ret = i915_gem_object_bind_to_gtt(obj, alignment,
4228 if (obj_priv->pin_count++ == 0) {
4229 i915_gem_info_add_pin(dev_priv, obj_priv, map_and_fenceable);
4230 if (!obj_priv->active)
4231 list_move_tail(&obj_priv->mm_list,
4232 &dev_priv->mm.pinned_list);
4234 BUG_ON(!obj_priv->pin_mappable && map_and_fenceable);
4236 WARN_ON(i915_verify_lists(dev));
4241 i915_gem_object_unpin(struct drm_gem_object *obj)
4243 struct drm_device *dev = obj->dev;
4244 drm_i915_private_t *dev_priv = dev->dev_private;
4245 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4247 WARN_ON(i915_verify_lists(dev));
4248 BUG_ON(obj_priv->pin_count == 0);
4249 BUG_ON(obj_priv->gtt_space == NULL);
4251 if (--obj_priv->pin_count == 0) {
4252 if (!obj_priv->active)
4253 list_move_tail(&obj_priv->mm_list,
4254 &dev_priv->mm.inactive_list);
4255 i915_gem_info_remove_pin(dev_priv, obj_priv);
4257 WARN_ON(i915_verify_lists(dev));
4261 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4262 struct drm_file *file_priv)
4264 struct drm_i915_gem_pin *args = data;
4265 struct drm_gem_object *obj;
4266 struct drm_i915_gem_object *obj_priv;
4269 ret = i915_mutex_lock_interruptible(dev);
4273 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4278 obj_priv = to_intel_bo(obj);
4280 if (obj_priv->madv != I915_MADV_WILLNEED) {
4281 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4286 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4287 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4293 obj_priv->user_pin_count++;
4294 obj_priv->pin_filp = file_priv;
4295 if (obj_priv->user_pin_count == 1) {
4296 ret = i915_gem_object_pin(obj, args->alignment, true);
4301 /* XXX - flush the CPU caches for pinned objects
4302 * as the X server doesn't manage domains yet
4304 i915_gem_object_flush_cpu_write_domain(obj);
4305 args->offset = obj_priv->gtt_offset;
4307 drm_gem_object_unreference(obj);
4309 mutex_unlock(&dev->struct_mutex);
4314 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4315 struct drm_file *file_priv)
4317 struct drm_i915_gem_pin *args = data;
4318 struct drm_gem_object *obj;
4319 struct drm_i915_gem_object *obj_priv;
4322 ret = i915_mutex_lock_interruptible(dev);
4326 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4331 obj_priv = to_intel_bo(obj);
4333 if (obj_priv->pin_filp != file_priv) {
4334 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4339 obj_priv->user_pin_count--;
4340 if (obj_priv->user_pin_count == 0) {
4341 obj_priv->pin_filp = NULL;
4342 i915_gem_object_unpin(obj);
4346 drm_gem_object_unreference(obj);
4348 mutex_unlock(&dev->struct_mutex);
4353 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4354 struct drm_file *file_priv)
4356 struct drm_i915_gem_busy *args = data;
4357 struct drm_gem_object *obj;
4358 struct drm_i915_gem_object *obj_priv;
4361 ret = i915_mutex_lock_interruptible(dev);
4365 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4370 obj_priv = to_intel_bo(obj);
4372 /* Count all active objects as busy, even if they are currently not used
4373 * by the gpu. Users of this interface expect objects to eventually
4374 * become non-busy without any further actions, therefore emit any
4375 * necessary flushes here.
4377 args->busy = obj_priv->active;
4379 /* Unconditionally flush objects, even when the gpu still uses this
4380 * object. Userspace calling this function indicates that it wants to
4381 * use this buffer rather sooner than later, so issuing the required
4382 * flush earlier is beneficial.
4384 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4385 i915_gem_flush_ring(dev, file_priv,
4387 0, obj->write_domain);
4389 /* Update the active list for the hardware's current position.
4390 * Otherwise this only updates on a delayed timer or when irqs
4391 * are actually unmasked, and our working set ends up being
4392 * larger than required.
4394 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4396 args->busy = obj_priv->active;
4399 drm_gem_object_unreference(obj);
4401 mutex_unlock(&dev->struct_mutex);
4406 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4407 struct drm_file *file_priv)
4409 return i915_gem_ring_throttle(dev, file_priv);
4413 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4414 struct drm_file *file_priv)
4416 struct drm_i915_gem_madvise *args = data;
4417 struct drm_gem_object *obj;
4418 struct drm_i915_gem_object *obj_priv;
4421 switch (args->madv) {
4422 case I915_MADV_DONTNEED:
4423 case I915_MADV_WILLNEED:
4429 ret = i915_mutex_lock_interruptible(dev);
4433 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4438 obj_priv = to_intel_bo(obj);
4440 if (obj_priv->pin_count) {
4445 if (obj_priv->madv != __I915_MADV_PURGED)
4446 obj_priv->madv = args->madv;
4448 /* if the object is no longer bound, discard its backing storage */
4449 if (i915_gem_object_is_purgeable(obj_priv) &&
4450 obj_priv->gtt_space == NULL)
4451 i915_gem_object_truncate(obj);
4453 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4456 drm_gem_object_unreference(obj);
4458 mutex_unlock(&dev->struct_mutex);
4462 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4465 struct drm_i915_private *dev_priv = dev->dev_private;
4466 struct drm_i915_gem_object *obj;
4468 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4472 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4477 i915_gem_info_add_obj(dev_priv, size);
4479 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4480 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4482 obj->agp_type = AGP_USER_MEMORY;
4483 obj->base.driver_private = NULL;
4484 obj->fence_reg = I915_FENCE_REG_NONE;
4485 INIT_LIST_HEAD(&obj->mm_list);
4486 INIT_LIST_HEAD(&obj->ring_list);
4487 INIT_LIST_HEAD(&obj->gpu_write_list);
4488 obj->madv = I915_MADV_WILLNEED;
4489 /* Avoid an unnecessary call to unbind on the first bind. */
4490 obj->map_and_fenceable = true;
4495 int i915_gem_init_object(struct drm_gem_object *obj)
4502 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4504 struct drm_device *dev = obj->dev;
4505 drm_i915_private_t *dev_priv = dev->dev_private;
4506 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4509 ret = i915_gem_object_unbind(obj);
4510 if (ret == -ERESTARTSYS) {
4511 list_move(&obj_priv->mm_list,
4512 &dev_priv->mm.deferred_free_list);
4516 if (obj->map_list.map)
4517 i915_gem_free_mmap_offset(obj);
4519 drm_gem_object_release(obj);
4520 i915_gem_info_remove_obj(dev_priv, obj->size);
4522 kfree(obj_priv->page_cpu_valid);
4523 kfree(obj_priv->bit_17);
4527 void i915_gem_free_object(struct drm_gem_object *obj)
4529 struct drm_device *dev = obj->dev;
4530 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4532 trace_i915_gem_object_destroy(obj);
4534 while (obj_priv->pin_count > 0)
4535 i915_gem_object_unpin(obj);
4537 if (obj_priv->phys_obj)
4538 i915_gem_detach_phys_object(dev, obj);
4540 i915_gem_free_object_tail(obj);
4544 i915_gem_idle(struct drm_device *dev)
4546 drm_i915_private_t *dev_priv = dev->dev_private;
4549 mutex_lock(&dev->struct_mutex);
4551 if (dev_priv->mm.suspended) {
4552 mutex_unlock(&dev->struct_mutex);
4556 ret = i915_gpu_idle(dev);
4558 mutex_unlock(&dev->struct_mutex);
4562 /* Under UMS, be paranoid and evict. */
4563 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4564 ret = i915_gem_evict_inactive(dev, false);
4566 mutex_unlock(&dev->struct_mutex);
4571 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4572 * We need to replace this with a semaphore, or something.
4573 * And not confound mm.suspended!
4575 dev_priv->mm.suspended = 1;
4576 del_timer_sync(&dev_priv->hangcheck_timer);
4578 i915_kernel_lost_context(dev);
4579 i915_gem_cleanup_ringbuffer(dev);
4581 mutex_unlock(&dev->struct_mutex);
4583 /* Cancel the retire work handler, which should be idle now. */
4584 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4590 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4591 * over cache flushing.
4594 i915_gem_init_pipe_control(struct drm_device *dev)
4596 drm_i915_private_t *dev_priv = dev->dev_private;
4597 struct drm_gem_object *obj;
4598 struct drm_i915_gem_object *obj_priv;
4601 obj = i915_gem_alloc_object(dev, 4096);
4603 DRM_ERROR("Failed to allocate seqno page\n");
4607 obj_priv = to_intel_bo(obj);
4608 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4610 ret = i915_gem_object_pin(obj, 4096, true);
4614 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4615 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4616 if (dev_priv->seqno_page == NULL)
4619 dev_priv->seqno_obj = obj;
4620 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4625 i915_gem_object_unpin(obj);
4627 drm_gem_object_unreference(obj);
4634 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4636 drm_i915_private_t *dev_priv = dev->dev_private;
4637 struct drm_gem_object *obj;
4638 struct drm_i915_gem_object *obj_priv;
4640 obj = dev_priv->seqno_obj;
4641 obj_priv = to_intel_bo(obj);
4642 kunmap(obj_priv->pages[0]);
4643 i915_gem_object_unpin(obj);
4644 drm_gem_object_unreference(obj);
4645 dev_priv->seqno_obj = NULL;
4647 dev_priv->seqno_page = NULL;
4651 i915_gem_init_ringbuffer(struct drm_device *dev)
4653 drm_i915_private_t *dev_priv = dev->dev_private;
4656 if (HAS_PIPE_CONTROL(dev)) {
4657 ret = i915_gem_init_pipe_control(dev);
4662 ret = intel_init_render_ring_buffer(dev);
4664 goto cleanup_pipe_control;
4667 ret = intel_init_bsd_ring_buffer(dev);
4669 goto cleanup_render_ring;
4673 ret = intel_init_blt_ring_buffer(dev);
4675 goto cleanup_bsd_ring;
4678 dev_priv->next_seqno = 1;
4683 intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4684 cleanup_render_ring:
4685 intel_cleanup_ring_buffer(&dev_priv->render_ring);
4686 cleanup_pipe_control:
4687 if (HAS_PIPE_CONTROL(dev))
4688 i915_gem_cleanup_pipe_control(dev);
4693 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4695 drm_i915_private_t *dev_priv = dev->dev_private;
4697 intel_cleanup_ring_buffer(&dev_priv->render_ring);
4698 intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4699 intel_cleanup_ring_buffer(&dev_priv->blt_ring);
4700 if (HAS_PIPE_CONTROL(dev))
4701 i915_gem_cleanup_pipe_control(dev);
4705 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4706 struct drm_file *file_priv)
4708 drm_i915_private_t *dev_priv = dev->dev_private;
4711 if (drm_core_check_feature(dev, DRIVER_MODESET))
4714 if (atomic_read(&dev_priv->mm.wedged)) {
4715 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4716 atomic_set(&dev_priv->mm.wedged, 0);
4719 mutex_lock(&dev->struct_mutex);
4720 dev_priv->mm.suspended = 0;
4722 ret = i915_gem_init_ringbuffer(dev);
4724 mutex_unlock(&dev->struct_mutex);
4728 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4729 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4730 BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list));
4731 BUG_ON(!list_empty(&dev_priv->blt_ring.active_list));
4732 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4733 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4734 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4735 BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list));
4736 BUG_ON(!list_empty(&dev_priv->blt_ring.request_list));
4737 mutex_unlock(&dev->struct_mutex);
4739 ret = drm_irq_install(dev);
4741 goto cleanup_ringbuffer;
4746 mutex_lock(&dev->struct_mutex);
4747 i915_gem_cleanup_ringbuffer(dev);
4748 dev_priv->mm.suspended = 1;
4749 mutex_unlock(&dev->struct_mutex);
4755 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4756 struct drm_file *file_priv)
4758 if (drm_core_check_feature(dev, DRIVER_MODESET))
4761 drm_irq_uninstall(dev);
4762 return i915_gem_idle(dev);
4766 i915_gem_lastclose(struct drm_device *dev)
4770 if (drm_core_check_feature(dev, DRIVER_MODESET))
4773 ret = i915_gem_idle(dev);
4775 DRM_ERROR("failed to idle hardware: %d\n", ret);
4779 init_ring_lists(struct intel_ring_buffer *ring)
4781 INIT_LIST_HEAD(&ring->active_list);
4782 INIT_LIST_HEAD(&ring->request_list);
4783 INIT_LIST_HEAD(&ring->gpu_write_list);
4787 i915_gem_load(struct drm_device *dev)
4790 drm_i915_private_t *dev_priv = dev->dev_private;
4792 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4793 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4794 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4795 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
4796 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4797 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4798 init_ring_lists(&dev_priv->render_ring);
4799 init_ring_lists(&dev_priv->bsd_ring);
4800 init_ring_lists(&dev_priv->blt_ring);
4801 for (i = 0; i < 16; i++)
4802 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4803 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4804 i915_gem_retire_work_handler);
4805 init_completion(&dev_priv->error_completion);
4807 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4809 u32 tmp = I915_READ(MI_ARB_STATE);
4810 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4811 /* arb state is a masked write, so set bit + bit in mask */
4812 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4813 I915_WRITE(MI_ARB_STATE, tmp);
4817 /* Old X drivers will take 0-2 for front, back, depth buffers */
4818 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4819 dev_priv->fence_reg_start = 3;
4821 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4822 dev_priv->num_fence_regs = 16;
4824 dev_priv->num_fence_regs = 8;
4826 /* Initialize fence registers to zero */
4827 switch (INTEL_INFO(dev)->gen) {
4829 for (i = 0; i < 16; i++)
4830 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4834 for (i = 0; i < 16; i++)
4835 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4838 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4839 for (i = 0; i < 8; i++)
4840 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4842 for (i = 0; i < 8; i++)
4843 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4846 i915_gem_detect_bit_6_swizzle(dev);
4847 init_waitqueue_head(&dev_priv->pending_flip_queue);
4849 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4850 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4851 register_shrinker(&dev_priv->mm.inactive_shrinker);
4855 * Create a physically contiguous memory object for this object
4856 * e.g. for cursor + overlay regs
4858 static int i915_gem_init_phys_object(struct drm_device *dev,
4859 int id, int size, int align)
4861 drm_i915_private_t *dev_priv = dev->dev_private;
4862 struct drm_i915_gem_phys_object *phys_obj;
4865 if (dev_priv->mm.phys_objs[id - 1] || !size)
4868 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4874 phys_obj->handle = drm_pci_alloc(dev, size, align);
4875 if (!phys_obj->handle) {
4880 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4883 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4891 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4893 drm_i915_private_t *dev_priv = dev->dev_private;
4894 struct drm_i915_gem_phys_object *phys_obj;
4896 if (!dev_priv->mm.phys_objs[id - 1])
4899 phys_obj = dev_priv->mm.phys_objs[id - 1];
4900 if (phys_obj->cur_obj) {
4901 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4905 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4907 drm_pci_free(dev, phys_obj->handle);
4909 dev_priv->mm.phys_objs[id - 1] = NULL;
4912 void i915_gem_free_all_phys_object(struct drm_device *dev)
4916 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4917 i915_gem_free_phys_object(dev, i);
4920 void i915_gem_detach_phys_object(struct drm_device *dev,
4921 struct drm_gem_object *obj)
4923 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
4924 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4929 if (!obj_priv->phys_obj)
4931 vaddr = obj_priv->phys_obj->handle->vaddr;
4933 page_count = obj->size / PAGE_SIZE;
4935 for (i = 0; i < page_count; i++) {
4936 struct page *page = read_cache_page_gfp(mapping, i,
4937 GFP_HIGHUSER | __GFP_RECLAIMABLE);
4938 if (!IS_ERR(page)) {
4939 char *dst = kmap_atomic(page);
4940 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4943 drm_clflush_pages(&page, 1);
4945 set_page_dirty(page);
4946 mark_page_accessed(page);
4947 page_cache_release(page);
4950 drm_agp_chipset_flush(dev);
4952 obj_priv->phys_obj->cur_obj = NULL;
4953 obj_priv->phys_obj = NULL;
4957 i915_gem_attach_phys_object(struct drm_device *dev,
4958 struct drm_gem_object *obj,
4962 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
4963 drm_i915_private_t *dev_priv = dev->dev_private;
4964 struct drm_i915_gem_object *obj_priv;
4969 if (id > I915_MAX_PHYS_OBJECT)
4972 obj_priv = to_intel_bo(obj);
4974 if (obj_priv->phys_obj) {
4975 if (obj_priv->phys_obj->id == id)
4977 i915_gem_detach_phys_object(dev, obj);
4980 /* create a new object */
4981 if (!dev_priv->mm.phys_objs[id - 1]) {
4982 ret = i915_gem_init_phys_object(dev, id,
4985 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4990 /* bind to the object */
4991 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4992 obj_priv->phys_obj->cur_obj = obj;
4994 page_count = obj->size / PAGE_SIZE;
4996 for (i = 0; i < page_count; i++) {
5000 page = read_cache_page_gfp(mapping, i,
5001 GFP_HIGHUSER | __GFP_RECLAIMABLE);
5003 return PTR_ERR(page);
5005 src = kmap_atomic(page);
5006 dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5007 memcpy(dst, src, PAGE_SIZE);
5010 mark_page_accessed(page);
5011 page_cache_release(page);
5018 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5019 struct drm_i915_gem_pwrite *args,
5020 struct drm_file *file_priv)
5022 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5023 void *vaddr = obj_priv->phys_obj->handle->vaddr + args->offset;
5024 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
5026 DRM_DEBUG_DRIVER("vaddr %p, %lld\n", vaddr, args->size);
5028 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
5029 unsigned long unwritten;
5031 /* The physical object once assigned is fixed for the lifetime
5032 * of the obj, so we can safely drop the lock and continue
5035 mutex_unlock(&dev->struct_mutex);
5036 unwritten = copy_from_user(vaddr, user_data, args->size);
5037 mutex_lock(&dev->struct_mutex);
5042 drm_agp_chipset_flush(dev);
5046 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5048 struct drm_i915_file_private *file_priv = file->driver_priv;
5050 /* Clean up our request list when the client is going away, so that
5051 * later retire_requests won't dereference our soon-to-be-gone
5054 spin_lock(&file_priv->mm.lock);
5055 while (!list_empty(&file_priv->mm.request_list)) {
5056 struct drm_i915_gem_request *request;
5058 request = list_first_entry(&file_priv->mm.request_list,
5059 struct drm_i915_gem_request,
5061 list_del(&request->client_list);
5062 request->file_priv = NULL;
5064 spin_unlock(&file_priv->mm.lock);
5068 i915_gpu_is_active(struct drm_device *dev)
5070 drm_i915_private_t *dev_priv = dev->dev_private;
5073 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
5074 list_empty(&dev_priv->mm.active_list);
5076 return !lists_empty;
5080 i915_gem_inactive_shrink(struct shrinker *shrinker,
5084 struct drm_i915_private *dev_priv =
5085 container_of(shrinker,
5086 struct drm_i915_private,
5087 mm.inactive_shrinker);
5088 struct drm_device *dev = dev_priv->dev;
5089 struct drm_i915_gem_object *obj, *next;
5092 if (!mutex_trylock(&dev->struct_mutex))
5095 /* "fast-path" to count number of available objects */
5096 if (nr_to_scan == 0) {
5098 list_for_each_entry(obj,
5099 &dev_priv->mm.inactive_list,
5102 mutex_unlock(&dev->struct_mutex);
5103 return cnt / 100 * sysctl_vfs_cache_pressure;
5107 /* first scan for clean buffers */
5108 i915_gem_retire_requests(dev);
5110 list_for_each_entry_safe(obj, next,
5111 &dev_priv->mm.inactive_list,
5113 if (i915_gem_object_is_purgeable(obj)) {
5114 i915_gem_object_unbind(&obj->base);
5115 if (--nr_to_scan == 0)
5120 /* second pass, evict/count anything still on the inactive list */
5122 list_for_each_entry_safe(obj, next,
5123 &dev_priv->mm.inactive_list,
5126 i915_gem_object_unbind(&obj->base);
5132 if (nr_to_scan && i915_gpu_is_active(dev)) {
5134 * We are desperate for pages, so as a last resort, wait
5135 * for the GPU to finish and discard whatever we can.
5136 * This has a dramatic impact to reduce the number of
5137 * OOM-killer events whilst running the GPU aggressively.
5139 if (i915_gpu_idle(dev) == 0)
5142 mutex_unlock(&dev->struct_mutex);
5143 return cnt / 100 * sysctl_vfs_cache_pressure;