2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int
42 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
43 struct i915_address_space *vm,
45 bool map_and_fenceable,
47 static int i915_gem_phys_pwrite(struct drm_device *dev,
48 struct drm_i915_gem_object *obj,
49 struct drm_i915_gem_pwrite *args,
50 struct drm_file *file);
52 static void i915_gem_write_fence(struct drm_device *dev, int reg,
53 struct drm_i915_gem_object *obj);
54 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
55 struct drm_i915_fence_reg *fence,
58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
61 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
62 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
64 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
67 i915_gem_release_mmap(obj);
69 /* As we do not have an associated fence register, we will force
70 * a tiling change if we ever need to acquire one.
72 obj->fence_dirty = false;
73 obj->fence_reg = I915_FENCE_REG_NONE;
76 /* some bookkeeping */
77 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
80 spin_lock(&dev_priv->mm.object_stat_lock);
81 dev_priv->mm.object_count++;
82 dev_priv->mm.object_memory += size;
83 spin_unlock(&dev_priv->mm.object_stat_lock);
86 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
89 spin_lock(&dev_priv->mm.object_stat_lock);
90 dev_priv->mm.object_count--;
91 dev_priv->mm.object_memory -= size;
92 spin_unlock(&dev_priv->mm.object_stat_lock);
96 i915_gem_wait_for_error(struct i915_gpu_error *error)
100 #define EXIT_COND (!i915_reset_in_progress(error) || \
101 i915_terminally_wedged(error))
106 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
107 * userspace. If it takes that long something really bad is going on and
108 * we should simply try to bail out and fail as gracefully as possible.
110 ret = wait_event_interruptible_timeout(error->reset_queue,
114 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
116 } else if (ret < 0) {
124 int i915_mutex_lock_interruptible(struct drm_device *dev)
126 struct drm_i915_private *dev_priv = dev->dev_private;
129 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
133 ret = mutex_lock_interruptible(&dev->struct_mutex);
137 WARN_ON(i915_verify_lists(dev));
142 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
144 return i915_gem_obj_bound_any(obj) && !obj->active;
148 i915_gem_init_ioctl(struct drm_device *dev, void *data,
149 struct drm_file *file)
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 struct drm_i915_gem_init *args = data;
154 if (drm_core_check_feature(dev, DRIVER_MODESET))
157 if (args->gtt_start >= args->gtt_end ||
158 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev)->gen >= 5)
165 mutex_lock(&dev->struct_mutex);
166 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
168 dev_priv->gtt.mappable_end = args->gtt_end;
169 mutex_unlock(&dev->struct_mutex);
175 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
176 struct drm_file *file)
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 struct drm_i915_gem_get_aperture *args = data;
180 struct drm_i915_gem_object *obj;
184 mutex_lock(&dev->struct_mutex);
185 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
187 pinned += i915_gem_obj_ggtt_size(obj);
188 mutex_unlock(&dev->struct_mutex);
190 args->aper_size = dev_priv->gtt.base.total;
191 args->aper_available_size = args->aper_size - pinned;
196 void *i915_gem_object_alloc(struct drm_device *dev)
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
202 void i915_gem_object_free(struct drm_i915_gem_object *obj)
204 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
205 kmem_cache_free(dev_priv->slab, obj);
209 i915_gem_create(struct drm_file *file,
210 struct drm_device *dev,
214 struct drm_i915_gem_object *obj;
218 size = roundup(size, PAGE_SIZE);
222 /* Allocate the new object */
223 obj = i915_gem_alloc_object(dev, size);
227 ret = drm_gem_handle_create(file, &obj->base, &handle);
228 /* drop reference from allocate - handle holds it now */
229 drm_gem_object_unreference_unlocked(&obj->base);
238 i915_gem_dumb_create(struct drm_file *file,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args)
242 /* have to work out size/pitch and return them */
243 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
244 args->size = args->pitch * args->height;
245 return i915_gem_create(file, dev,
246 args->size, &args->handle);
249 int i915_gem_dumb_destroy(struct drm_file *file,
250 struct drm_device *dev,
253 return drm_gem_handle_delete(file, handle);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
261 struct drm_file *file)
263 struct drm_i915_gem_create *args = data;
265 return i915_gem_create(file, dev,
266 args->size, &args->handle);
270 __copy_to_user_swizzled(char __user *cpu_vaddr,
271 const char *gpu_vaddr, int gpu_offset,
274 int ret, cpu_offset = 0;
277 int cacheline_end = ALIGN(gpu_offset + 1, 64);
278 int this_length = min(cacheline_end - gpu_offset, length);
279 int swizzled_gpu_offset = gpu_offset ^ 64;
281 ret = __copy_to_user(cpu_vaddr + cpu_offset,
282 gpu_vaddr + swizzled_gpu_offset,
287 cpu_offset += this_length;
288 gpu_offset += this_length;
289 length -= this_length;
296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
297 const char __user *cpu_vaddr,
300 int ret, cpu_offset = 0;
303 int cacheline_end = ALIGN(gpu_offset + 1, 64);
304 int this_length = min(cacheline_end - gpu_offset, length);
305 int swizzled_gpu_offset = gpu_offset ^ 64;
307 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
308 cpu_vaddr + cpu_offset,
313 cpu_offset += this_length;
314 gpu_offset += this_length;
315 length -= this_length;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
326 char __user *user_data,
327 bool page_do_bit17_swizzling, bool needs_clflush)
332 if (unlikely(page_do_bit17_swizzling))
335 vaddr = kmap_atomic(page);
337 drm_clflush_virt_range(vaddr + shmem_page_offset,
339 ret = __copy_to_user_inatomic(user_data,
340 vaddr + shmem_page_offset,
342 kunmap_atomic(vaddr);
344 return ret ? -EFAULT : 0;
348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
351 if (unlikely(swizzled)) {
352 unsigned long start = (unsigned long) addr;
353 unsigned long end = (unsigned long) addr + length;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start = round_down(start, 128);
360 end = round_up(end, 128);
362 drm_clflush_virt_range((void *)start, end - start);
364 drm_clflush_virt_range(addr, length);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
373 char __user *user_data,
374 bool page_do_bit17_swizzling, bool needs_clflush)
381 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383 page_do_bit17_swizzling);
385 if (page_do_bit17_swizzling)
386 ret = __copy_to_user_swizzled(user_data,
387 vaddr, shmem_page_offset,
390 ret = __copy_to_user(user_data,
391 vaddr + shmem_page_offset,
395 return ret ? - EFAULT : 0;
399 i915_gem_shmem_pread(struct drm_device *dev,
400 struct drm_i915_gem_object *obj,
401 struct drm_i915_gem_pread *args,
402 struct drm_file *file)
404 char __user *user_data;
407 int shmem_page_offset, page_length, ret = 0;
408 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410 int needs_clflush = 0;
411 struct sg_page_iter sg_iter;
413 user_data = to_user_ptr(args->data_ptr);
416 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj->cache_level == I915_CACHE_NONE)
425 if (i915_gem_obj_bound_any(obj)) {
426 ret = i915_gem_object_set_to_gtt_domain(obj, false);
432 ret = i915_gem_object_get_pages(obj);
436 i915_gem_object_pin_pages(obj);
438 offset = args->offset;
440 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
441 offset >> PAGE_SHIFT) {
442 struct page *page = sg_page_iter_page(&sg_iter);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset = offset_in_page(offset);
453 page_length = remain;
454 if ((shmem_page_offset + page_length) > PAGE_SIZE)
455 page_length = PAGE_SIZE - shmem_page_offset;
457 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
458 (page_to_phys(page) & (1 << 17)) != 0;
460 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
461 user_data, page_do_bit17_swizzling,
466 mutex_unlock(&dev->struct_mutex);
468 if (likely(!i915_prefault_disable) && !prefaulted) {
469 ret = fault_in_multipages_writeable(user_data, remain);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
479 user_data, page_do_bit17_swizzling,
482 mutex_lock(&dev->struct_mutex);
485 mark_page_accessed(page);
490 remain -= page_length;
491 user_data += page_length;
492 offset += page_length;
496 i915_gem_object_unpin_pages(obj);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
508 struct drm_file *file)
510 struct drm_i915_gem_pread *args = data;
511 struct drm_i915_gem_object *obj;
517 if (!access_ok(VERIFY_WRITE,
518 to_user_ptr(args->data_ptr),
522 ret = i915_mutex_lock_interruptible(dev);
526 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
527 if (&obj->base == NULL) {
532 /* Bounds check source. */
533 if (args->offset > obj->base.size ||
534 args->size > obj->base.size - args->offset) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj->base.filp) {
547 trace_i915_gem_object_pread(obj, args->offset, args->size);
549 ret = i915_gem_shmem_pread(dev, obj, args, file);
552 drm_gem_object_unreference(&obj->base);
554 mutex_unlock(&dev->struct_mutex);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping *mapping,
564 loff_t page_base, int page_offset,
565 char __user *user_data,
568 void __iomem *vaddr_atomic;
570 unsigned long unwritten;
572 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr = (void __force*)vaddr_atomic + page_offset;
575 unwritten = __copy_from_user_inatomic_nocache(vaddr,
577 io_mapping_unmap_atomic(vaddr_atomic);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
587 struct drm_i915_gem_object *obj,
588 struct drm_i915_gem_pwrite *args,
589 struct drm_file *file)
591 drm_i915_private_t *dev_priv = dev->dev_private;
593 loff_t offset, page_base;
594 char __user *user_data;
595 int page_offset, page_length, ret;
597 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
601 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 ret = i915_gem_object_put_fence(obj);
609 user_data = to_user_ptr(args->data_ptr);
612 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base = offset & PAGE_MASK;
622 page_offset = offset_in_page(offset);
623 page_length = remain;
624 if ((page_offset + remain) > PAGE_SIZE)
625 page_length = PAGE_SIZE - page_offset;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv->gtt.mappable, page_base,
632 page_offset, user_data, page_length)) {
637 remain -= page_length;
638 user_data += page_length;
639 offset += page_length;
643 i915_gem_object_unpin(obj);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
654 char __user *user_data,
655 bool page_do_bit17_swizzling,
656 bool needs_clflush_before,
657 bool needs_clflush_after)
662 if (unlikely(page_do_bit17_swizzling))
665 vaddr = kmap_atomic(page);
666 if (needs_clflush_before)
667 drm_clflush_virt_range(vaddr + shmem_page_offset,
669 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
672 if (needs_clflush_after)
673 drm_clflush_virt_range(vaddr + shmem_page_offset,
675 kunmap_atomic(vaddr);
677 return ret ? -EFAULT : 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
684 char __user *user_data,
685 bool page_do_bit17_swizzling,
686 bool needs_clflush_before,
687 bool needs_clflush_after)
693 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
694 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
696 page_do_bit17_swizzling);
697 if (page_do_bit17_swizzling)
698 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 ret = __copy_from_user(vaddr + shmem_page_offset,
705 if (needs_clflush_after)
706 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708 page_do_bit17_swizzling);
711 return ret ? -EFAULT : 0;
715 i915_gem_shmem_pwrite(struct drm_device *dev,
716 struct drm_i915_gem_object *obj,
717 struct drm_i915_gem_pwrite *args,
718 struct drm_file *file)
722 char __user *user_data;
723 int shmem_page_offset, page_length, ret = 0;
724 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
725 int hit_slowpath = 0;
726 int needs_clflush_after = 0;
727 int needs_clflush_before = 0;
728 struct sg_page_iter sg_iter;
730 user_data = to_user_ptr(args->data_ptr);
733 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
735 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj->cache_level == I915_CACHE_NONE)
741 needs_clflush_after = 1;
742 if (i915_gem_obj_bound_any(obj)) {
743 ret = i915_gem_object_set_to_gtt_domain(obj, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
751 && obj->cache_level == I915_CACHE_NONE)
752 needs_clflush_before = 1;
754 ret = i915_gem_object_get_pages(obj);
758 i915_gem_object_pin_pages(obj);
760 offset = args->offset;
763 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
764 offset >> PAGE_SHIFT) {
765 struct page *page = sg_page_iter_page(&sg_iter);
766 int partial_cacheline_write;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset = offset_in_page(offset);
778 page_length = remain;
779 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780 page_length = PAGE_SIZE - shmem_page_offset;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write = needs_clflush_before &&
786 ((shmem_page_offset | page_length)
787 & (boot_cpu_data.x86_clflush_size - 1));
789 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
790 (page_to_phys(page) & (1 << 17)) != 0;
792 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
793 user_data, page_do_bit17_swizzling,
794 partial_cacheline_write,
795 needs_clflush_after);
800 mutex_unlock(&dev->struct_mutex);
801 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
802 user_data, page_do_bit17_swizzling,
803 partial_cacheline_write,
804 needs_clflush_after);
806 mutex_lock(&dev->struct_mutex);
809 set_page_dirty(page);
810 mark_page_accessed(page);
815 remain -= page_length;
816 user_data += page_length;
817 offset += page_length;
821 i915_gem_object_unpin_pages(obj);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after &&
830 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
831 i915_gem_clflush_object(obj);
832 i915_gem_chipset_flush(dev);
836 if (needs_clflush_after)
837 i915_gem_chipset_flush(dev);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file)
851 struct drm_i915_gem_pwrite *args = data;
852 struct drm_i915_gem_object *obj;
858 if (!access_ok(VERIFY_READ,
859 to_user_ptr(args->data_ptr),
863 if (likely(!i915_prefault_disable)) {
864 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
870 ret = i915_mutex_lock_interruptible(dev);
874 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
875 if (&obj->base == NULL) {
880 /* Bounds check destination. */
881 if (args->offset > obj->base.size ||
882 args->size > obj->base.size - args->offset) {
887 /* prime objects have no backing filp to GEM pread/pwrite
890 if (!obj->base.filp) {
895 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
898 /* We can only do the GTT pwrite on untiled buffers, as otherwise
899 * it would end up going through the fenced access, and we'll get
900 * different detiling behavior between reading and writing.
901 * pread/pwrite currently are reading and writing from the CPU
902 * perspective, requiring manual detiling by the client.
905 ret = i915_gem_phys_pwrite(dev, obj, args, file);
909 if (obj->cache_level == I915_CACHE_NONE &&
910 obj->tiling_mode == I915_TILING_NONE &&
911 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
912 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
913 /* Note that the gtt paths might fail with non-page-backed user
914 * pointers (e.g. gtt mappings when moving data between
915 * textures). Fallback to the shmem path in that case. */
918 if (ret == -EFAULT || ret == -ENOSPC)
919 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
922 drm_gem_object_unreference(&obj->base);
924 mutex_unlock(&dev->struct_mutex);
929 i915_gem_check_wedge(struct i915_gpu_error *error,
932 if (i915_reset_in_progress(error)) {
933 /* Non-interruptible callers can't handle -EAGAIN, hence return
934 * -EIO unconditionally for these. */
938 /* Recovery complete, but the reset failed ... */
939 if (i915_terminally_wedged(error))
949 * Compare seqno against outstanding lazy request. Emit a request if they are
953 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
957 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
960 if (seqno == ring->outstanding_lazy_request)
961 ret = i915_add_request(ring, NULL);
967 * __wait_seqno - wait until execution of seqno has finished
968 * @ring: the ring expected to report seqno
970 * @reset_counter: reset sequence associated with the given seqno
971 * @interruptible: do an interruptible wait (normally yes)
972 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
974 * Note: It is of utmost importance that the passed in seqno and reset_counter
975 * values have been read by the caller in an smp safe manner. Where read-side
976 * locks are involved, it is sufficient to read the reset_counter before
977 * unlocking the lock that protects the seqno. For lockless tricks, the
978 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
981 * Returns 0 if the seqno was found within the alloted time. Else returns the
982 * errno with remaining time filled in timeout argument.
984 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
985 unsigned reset_counter,
986 bool interruptible, struct timespec *timeout)
988 drm_i915_private_t *dev_priv = ring->dev->dev_private;
989 struct timespec before, now, wait_time={1,0};
990 unsigned long timeout_jiffies;
992 bool wait_forever = true;
995 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
998 trace_i915_gem_request_wait_begin(ring, seqno);
1000 if (timeout != NULL) {
1001 wait_time = *timeout;
1002 wait_forever = false;
1005 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1007 if (WARN_ON(!ring->irq_get(ring)))
1010 /* Record current time in case interrupted by signal, or wedged * */
1011 getrawmonotonic(&before);
1014 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1015 i915_reset_in_progress(&dev_priv->gpu_error) || \
1016 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1019 end = wait_event_interruptible_timeout(ring->irq_queue,
1023 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1026 /* We need to check whether any gpu reset happened in between
1027 * the caller grabbing the seqno and now ... */
1028 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1031 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1033 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1036 } while (end == 0 && wait_forever);
1038 getrawmonotonic(&now);
1040 ring->irq_put(ring);
1041 trace_i915_gem_request_wait_end(ring, seqno);
1045 struct timespec sleep_time = timespec_sub(now, before);
1046 *timeout = timespec_sub(*timeout, sleep_time);
1047 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1048 set_normalized_timespec(timeout, 0, 0);
1053 case -EAGAIN: /* Wedged */
1054 case -ERESTARTSYS: /* Signal */
1056 case 0: /* Timeout */
1058 default: /* Completed */
1059 WARN_ON(end < 0); /* We're not aware of other errors */
1065 * Waits for a sequence number to be signaled, and cleans up the
1066 * request and object lists appropriately for that event.
1069 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1071 struct drm_device *dev = ring->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 bool interruptible = dev_priv->mm.interruptible;
1076 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1079 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1083 ret = i915_gem_check_olr(ring, seqno);
1087 return __wait_seqno(ring, seqno,
1088 atomic_read(&dev_priv->gpu_error.reset_counter),
1089 interruptible, NULL);
1093 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1094 struct intel_ring_buffer *ring)
1096 i915_gem_retire_requests_ring(ring);
1098 /* Manually manage the write flush as we may have not yet
1099 * retired the buffer.
1101 * Note that the last_write_seqno is always the earlier of
1102 * the two (read/write) seqno, so if we haved successfully waited,
1103 * we know we have passed the last write.
1105 obj->last_write_seqno = 0;
1106 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1112 * Ensures that all rendering to the object has completed and the object is
1113 * safe to unbind from the GTT or access from the CPU.
1115 static __must_check int
1116 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1119 struct intel_ring_buffer *ring = obj->ring;
1123 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1127 ret = i915_wait_seqno(ring, seqno);
1131 return i915_gem_object_wait_rendering__tail(obj, ring);
1134 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1135 * as the object state may change during this call.
1137 static __must_check int
1138 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1141 struct drm_device *dev = obj->base.dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 struct intel_ring_buffer *ring = obj->ring;
1144 unsigned reset_counter;
1148 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1149 BUG_ON(!dev_priv->mm.interruptible);
1151 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1155 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1159 ret = i915_gem_check_olr(ring, seqno);
1163 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1164 mutex_unlock(&dev->struct_mutex);
1165 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1166 mutex_lock(&dev->struct_mutex);
1170 return i915_gem_object_wait_rendering__tail(obj, ring);
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file)
1181 struct drm_i915_gem_set_domain *args = data;
1182 struct drm_i915_gem_object *obj;
1183 uint32_t read_domains = args->read_domains;
1184 uint32_t write_domain = args->write_domain;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain & I915_GEM_GPU_DOMAINS)
1191 if (read_domains & I915_GEM_GPU_DOMAINS)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain != 0 && read_domains != write_domain)
1200 ret = i915_mutex_lock_interruptible(dev);
1204 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1205 if (&obj->base == NULL) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218 if (read_domains & I915_GEM_DOMAIN_GTT) {
1219 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232 drm_gem_object_unreference(&obj->base);
1234 mutex_unlock(&dev->struct_mutex);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1243 struct drm_file *file)
1245 struct drm_i915_gem_sw_finish *args = data;
1246 struct drm_i915_gem_object *obj;
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj);
1263 drm_gem_object_unreference(&obj->base);
1265 mutex_unlock(&dev->struct_mutex);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1278 struct drm_file *file)
1280 struct drm_i915_gem_mmap *args = data;
1281 struct drm_gem_object *obj;
1284 obj = drm_gem_object_lookup(dev, file, args->handle);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj);
1296 addr = vm_mmap(obj->filp, 0, args->size,
1297 PROT_READ | PROT_WRITE, MAP_SHARED,
1299 drm_gem_object_unreference_unlocked(obj);
1300 if (IS_ERR((void *)addr))
1303 args->addr_ptr = (uint64_t) addr;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1326 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1327 struct drm_device *dev = obj->base.dev;
1328 drm_i915_private_t *dev_priv = dev->dev_private;
1329 pgoff_t page_offset;
1332 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1338 ret = i915_mutex_lock_interruptible(dev);
1342 trace_i915_gem_object_fault(obj, page_offset, true, write);
1344 /* Access to snoopable pages through the GTT is incoherent. */
1345 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1350 /* Now bind it into the GTT if needed */
1351 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1355 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1359 ret = i915_gem_object_get_fence(obj);
1363 obj->fault_mappable = true;
1365 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1369 /* Finally, remap it using the new GTT offset */
1370 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1372 i915_gem_object_unpin(obj);
1374 mutex_unlock(&dev->struct_mutex);
1378 /* If this -EIO is due to a gpu hang, give the reset code a
1379 * chance to clean up the mess. Otherwise return the proper
1381 if (i915_terminally_wedged(&dev_priv->gpu_error))
1382 return VM_FAULT_SIGBUS;
1384 /* Give the error handler a chance to run and move the
1385 * objects off the GPU active list. Next time we service the
1386 * fault, we should be able to transition the page into the
1387 * GTT without touching the GPU (and so avoid further
1388 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1389 * with coherency, just lost writes.
1397 * EBUSY is ok: this just means that another thread
1398 * already did the job.
1400 return VM_FAULT_NOPAGE;
1402 return VM_FAULT_OOM;
1404 return VM_FAULT_SIGBUS;
1406 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1407 return VM_FAULT_SIGBUS;
1412 * i915_gem_release_mmap - remove physical page mappings
1413 * @obj: obj in question
1415 * Preserve the reservation of the mmapping with the DRM core code, but
1416 * relinquish ownership of the pages back to the system.
1418 * It is vital that we remove the page mapping if we have mapped a tiled
1419 * object through the GTT and then lose the fence register due to
1420 * resource pressure. Similarly if the object has been moved out of the
1421 * aperture, than pages mapped into userspace must be revoked. Removing the
1422 * mapping will then trigger a page fault on the next user access, allowing
1423 * fixup by i915_gem_fault().
1426 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1428 if (!obj->fault_mappable)
1431 if (obj->base.dev->dev_mapping)
1432 unmap_mapping_range(obj->base.dev->dev_mapping,
1433 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1436 obj->fault_mappable = false;
1440 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1444 if (INTEL_INFO(dev)->gen >= 4 ||
1445 tiling_mode == I915_TILING_NONE)
1448 /* Previous chips need a power-of-two fence region when tiling */
1449 if (INTEL_INFO(dev)->gen == 3)
1450 gtt_size = 1024*1024;
1452 gtt_size = 512*1024;
1454 while (gtt_size < size)
1461 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1462 * @obj: object to check
1464 * Return the required GTT alignment for an object, taking into account
1465 * potential fence register mapping.
1468 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1469 int tiling_mode, bool fenced)
1472 * Minimum alignment is 4k (GTT page size), but might be greater
1473 * if a fence register is needed for the object.
1475 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1476 tiling_mode == I915_TILING_NONE)
1480 * Previous chips need to be aligned to the size of the smallest
1481 * fence register that can contain the object.
1483 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1486 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1488 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1491 if (obj->base.map_list.map)
1494 dev_priv->mm.shrinker_no_lock_stealing = true;
1496 ret = drm_gem_create_mmap_offset(&obj->base);
1500 /* Badly fragmented mmap space? The only way we can recover
1501 * space is by destroying unwanted objects. We can't randomly release
1502 * mmap_offsets as userspace expects them to be persistent for the
1503 * lifetime of the objects. The closest we can is to release the
1504 * offsets on purgeable objects by truncating it and marking it purged,
1505 * which prevents userspace from ever using that object again.
1507 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1508 ret = drm_gem_create_mmap_offset(&obj->base);
1512 i915_gem_shrink_all(dev_priv);
1513 ret = drm_gem_create_mmap_offset(&obj->base);
1515 dev_priv->mm.shrinker_no_lock_stealing = false;
1520 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1522 if (!obj->base.map_list.map)
1525 drm_gem_free_mmap_offset(&obj->base);
1529 i915_gem_mmap_gtt(struct drm_file *file,
1530 struct drm_device *dev,
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 struct drm_i915_gem_object *obj;
1538 ret = i915_mutex_lock_interruptible(dev);
1542 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1543 if (&obj->base == NULL) {
1548 if (obj->base.size > dev_priv->gtt.mappable_end) {
1553 if (obj->madv != I915_MADV_WILLNEED) {
1554 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1559 ret = i915_gem_object_create_mmap_offset(obj);
1563 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1566 drm_gem_object_unreference(&obj->base);
1568 mutex_unlock(&dev->struct_mutex);
1573 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1575 * @data: GTT mapping ioctl data
1576 * @file: GEM object info
1578 * Simply returns the fake offset to userspace so it can mmap it.
1579 * The mmap call will end up in drm_gem_mmap(), which will set things
1580 * up so we can get faults in the handler above.
1582 * The fault handler will take care of binding the object into the GTT
1583 * (since it may have been evicted to make room for something), allocating
1584 * a fence register, and mapping the appropriate aperture address into
1588 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1589 struct drm_file *file)
1591 struct drm_i915_gem_mmap_gtt *args = data;
1593 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1596 /* Immediately discard the backing storage */
1598 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1600 struct inode *inode;
1602 i915_gem_object_free_mmap_offset(obj);
1604 if (obj->base.filp == NULL)
1607 /* Our goal here is to return as much of the memory as
1608 * is possible back to the system as we are called from OOM.
1609 * To do this we must instruct the shmfs to drop all of its
1610 * backing pages, *now*.
1612 inode = file_inode(obj->base.filp);
1613 shmem_truncate_range(inode, 0, (loff_t)-1);
1615 obj->madv = __I915_MADV_PURGED;
1619 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1621 return obj->madv == I915_MADV_DONTNEED;
1625 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1627 struct sg_page_iter sg_iter;
1630 BUG_ON(obj->madv == __I915_MADV_PURGED);
1632 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1634 /* In the event of a disaster, abandon all caches and
1635 * hope for the best.
1637 WARN_ON(ret != -EIO);
1638 i915_gem_clflush_object(obj);
1639 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1642 if (i915_gem_object_needs_bit17_swizzle(obj))
1643 i915_gem_object_save_bit_17_swizzle(obj);
1645 if (obj->madv == I915_MADV_DONTNEED)
1648 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1649 struct page *page = sg_page_iter_page(&sg_iter);
1652 set_page_dirty(page);
1654 if (obj->madv == I915_MADV_WILLNEED)
1655 mark_page_accessed(page);
1657 page_cache_release(page);
1661 sg_free_table(obj->pages);
1666 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1668 const struct drm_i915_gem_object_ops *ops = obj->ops;
1670 if (obj->pages == NULL)
1673 if (obj->pages_pin_count)
1676 BUG_ON(i915_gem_obj_bound_any(obj));
1678 /* ->put_pages might need to allocate memory for the bit17 swizzle
1679 * array, hence protect them from being reaped by removing them from gtt
1681 list_del(&obj->global_list);
1683 ops->put_pages(obj);
1686 if (i915_gem_object_is_purgeable(obj))
1687 i915_gem_object_truncate(obj);
1693 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1694 bool purgeable_only)
1696 struct drm_i915_gem_object *obj, *next;
1699 list_for_each_entry_safe(obj, next,
1700 &dev_priv->mm.unbound_list,
1702 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1703 i915_gem_object_put_pages(obj) == 0) {
1704 count += obj->base.size >> PAGE_SHIFT;
1705 if (count >= target)
1710 list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
1712 struct i915_vma *vma, *v;
1714 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1717 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1718 if (i915_vma_unbind(vma))
1721 if (!i915_gem_object_put_pages(obj)) {
1722 count += obj->base.size >> PAGE_SHIFT;
1723 if (count >= target)
1732 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1734 return __i915_gem_shrink(dev_priv, target, true);
1738 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1740 struct drm_i915_gem_object *obj, *next;
1742 i915_gem_evict_everything(dev_priv->dev);
1744 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1746 i915_gem_object_put_pages(obj);
1750 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1752 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1754 struct address_space *mapping;
1755 struct sg_table *st;
1756 struct scatterlist *sg;
1757 struct sg_page_iter sg_iter;
1759 unsigned long last_pfn = 0; /* suppress gcc warning */
1762 /* Assert that the object is not currently in any GPU domain. As it
1763 * wasn't in the GTT, there shouldn't be any way it could have been in
1766 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1767 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1769 st = kmalloc(sizeof(*st), GFP_KERNEL);
1773 page_count = obj->base.size / PAGE_SIZE;
1774 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1780 /* Get the list of pages out of our struct file. They'll be pinned
1781 * at this point until we release them.
1783 * Fail silently without starting the shrinker
1785 mapping = file_inode(obj->base.filp)->i_mapping;
1786 gfp = mapping_gfp_mask(mapping);
1787 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1788 gfp &= ~(__GFP_IO | __GFP_WAIT);
1791 for (i = 0; i < page_count; i++) {
1792 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1794 i915_gem_purge(dev_priv, page_count);
1795 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1798 /* We've tried hard to allocate the memory by reaping
1799 * our own buffer, now let the real VM do its job and
1800 * go down in flames if truly OOM.
1802 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1803 gfp |= __GFP_IO | __GFP_WAIT;
1805 i915_gem_shrink_all(dev_priv);
1806 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1810 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1811 gfp &= ~(__GFP_IO | __GFP_WAIT);
1813 #ifdef CONFIG_SWIOTLB
1814 if (swiotlb_nr_tbl()) {
1816 sg_set_page(sg, page, PAGE_SIZE, 0);
1821 if (!i || page_to_pfn(page) != last_pfn + 1) {
1825 sg_set_page(sg, page, PAGE_SIZE, 0);
1827 sg->length += PAGE_SIZE;
1829 last_pfn = page_to_pfn(page);
1831 #ifdef CONFIG_SWIOTLB
1832 if (!swiotlb_nr_tbl())
1837 if (i915_gem_object_needs_bit17_swizzle(obj))
1838 i915_gem_object_do_bit_17_swizzle(obj);
1844 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1845 page_cache_release(sg_page_iter_page(&sg_iter));
1848 return PTR_ERR(page);
1851 /* Ensure that the associated pages are gathered from the backing storage
1852 * and pinned into our object. i915_gem_object_get_pages() may be called
1853 * multiple times before they are released by a single call to
1854 * i915_gem_object_put_pages() - once the pages are no longer referenced
1855 * either as a result of memory pressure (reaping pages under the shrinker)
1856 * or as the object is itself released.
1859 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1861 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1862 const struct drm_i915_gem_object_ops *ops = obj->ops;
1868 if (obj->madv != I915_MADV_WILLNEED) {
1869 DRM_ERROR("Attempting to obtain a purgeable object\n");
1873 BUG_ON(obj->pages_pin_count);
1875 ret = ops->get_pages(obj);
1879 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1884 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1885 struct intel_ring_buffer *ring)
1887 struct drm_device *dev = obj->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 u32 seqno = intel_ring_get_seqno(ring);
1891 BUG_ON(ring == NULL);
1892 if (obj->ring != ring && obj->last_write_seqno) {
1893 /* Keep the seqno relative to the current ring */
1894 obj->last_write_seqno = seqno;
1898 /* Add a reference if we're newly entering the active list. */
1900 drm_gem_object_reference(&obj->base);
1904 list_move_tail(&obj->ring_list, &ring->active_list);
1906 obj->last_read_seqno = seqno;
1908 if (obj->fenced_gpu_access) {
1909 obj->last_fenced_seqno = seqno;
1911 /* Bump MRU to take account of the delayed flush */
1912 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1913 struct drm_i915_fence_reg *reg;
1915 reg = &dev_priv->fence_regs[obj->fence_reg];
1916 list_move_tail(®->lru_list,
1917 &dev_priv->mm.fence_list);
1923 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1925 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1926 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1927 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1929 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1930 BUG_ON(!obj->active);
1932 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1934 list_del_init(&obj->ring_list);
1937 obj->last_read_seqno = 0;
1938 obj->last_write_seqno = 0;
1939 obj->base.write_domain = 0;
1941 obj->last_fenced_seqno = 0;
1942 obj->fenced_gpu_access = false;
1945 drm_gem_object_unreference(&obj->base);
1947 WARN_ON(i915_verify_lists(dev));
1951 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 struct intel_ring_buffer *ring;
1957 /* Carefully retire all requests without writing to the rings */
1958 for_each_ring(ring, dev_priv, i) {
1959 ret = intel_ring_idle(ring);
1963 i915_gem_retire_requests(dev);
1965 /* Finally reset hw state */
1966 for_each_ring(ring, dev_priv, i) {
1967 intel_ring_init_seqno(ring, seqno);
1969 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1970 ring->sync_seqno[j] = 0;
1976 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1984 /* HWS page needs to be set less than what we
1985 * will inject to ring
1987 ret = i915_gem_init_seqno(dev, seqno - 1);
1991 /* Carefully set the last_seqno value so that wrap
1992 * detection still works
1994 dev_priv->next_seqno = seqno;
1995 dev_priv->last_seqno = seqno - 1;
1996 if (dev_priv->last_seqno == 0)
1997 dev_priv->last_seqno--;
2003 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2007 /* reserve 0 for non-seqno */
2008 if (dev_priv->next_seqno == 0) {
2009 int ret = i915_gem_init_seqno(dev, 0);
2013 dev_priv->next_seqno = 1;
2016 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2020 int __i915_add_request(struct intel_ring_buffer *ring,
2021 struct drm_file *file,
2022 struct drm_i915_gem_object *obj,
2025 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2026 struct drm_i915_gem_request *request;
2027 u32 request_ring_position, request_start;
2031 request_start = intel_ring_get_tail(ring);
2033 * Emit any outstanding flushes - execbuf can fail to emit the flush
2034 * after having emitted the batchbuffer command. Hence we need to fix
2035 * things up similar to emitting the lazy request. The difference here
2036 * is that the flush _must_ happen before the next request, no matter
2039 ret = intel_ring_flush_all_caches(ring);
2043 request = kmalloc(sizeof(*request), GFP_KERNEL);
2044 if (request == NULL)
2048 /* Record the position of the start of the request so that
2049 * should we detect the updated seqno part-way through the
2050 * GPU processing the request, we never over-estimate the
2051 * position of the head.
2053 request_ring_position = intel_ring_get_tail(ring);
2055 ret = ring->add_request(ring);
2061 request->seqno = intel_ring_get_seqno(ring);
2062 request->ring = ring;
2063 request->head = request_start;
2064 request->tail = request_ring_position;
2065 request->ctx = ring->last_context;
2066 request->batch_obj = obj;
2068 /* Whilst this request exists, batch_obj will be on the
2069 * active_list, and so will hold the active reference. Only when this
2070 * request is retired will the the batch_obj be moved onto the
2071 * inactive_list and lose its active reference. Hence we do not need
2072 * to explicitly hold another reference here.
2076 i915_gem_context_reference(request->ctx);
2078 request->emitted_jiffies = jiffies;
2079 was_empty = list_empty(&ring->request_list);
2080 list_add_tail(&request->list, &ring->request_list);
2081 request->file_priv = NULL;
2084 struct drm_i915_file_private *file_priv = file->driver_priv;
2086 spin_lock(&file_priv->mm.lock);
2087 request->file_priv = file_priv;
2088 list_add_tail(&request->client_list,
2089 &file_priv->mm.request_list);
2090 spin_unlock(&file_priv->mm.lock);
2093 trace_i915_gem_request_add(ring, request->seqno);
2094 ring->outstanding_lazy_request = 0;
2096 if (!dev_priv->ums.mm_suspended) {
2097 i915_queue_hangcheck(ring->dev);
2100 queue_delayed_work(dev_priv->wq,
2101 &dev_priv->mm.retire_work,
2102 round_jiffies_up_relative(HZ));
2103 intel_mark_busy(dev_priv->dev);
2108 *out_seqno = request->seqno;
2113 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2115 struct drm_i915_file_private *file_priv = request->file_priv;
2120 spin_lock(&file_priv->mm.lock);
2121 if (request->file_priv) {
2122 list_del(&request->client_list);
2123 request->file_priv = NULL;
2125 spin_unlock(&file_priv->mm.lock);
2128 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2129 struct i915_address_space *vm)
2131 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2132 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2138 static bool i915_head_inside_request(const u32 acthd_unmasked,
2139 const u32 request_start,
2140 const u32 request_end)
2142 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2144 if (request_start < request_end) {
2145 if (acthd >= request_start && acthd < request_end)
2147 } else if (request_start > request_end) {
2148 if (acthd >= request_start || acthd < request_end)
2155 static struct i915_address_space *
2156 request_to_vm(struct drm_i915_gem_request *request)
2158 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2159 struct i915_address_space *vm;
2161 vm = &dev_priv->gtt.base;
2166 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2167 const u32 acthd, bool *inside)
2169 /* There is a possibility that unmasked head address
2170 * pointing inside the ring, matches the batch_obj address range.
2171 * However this is extremely unlikely.
2173 if (request->batch_obj) {
2174 if (i915_head_inside_object(acthd, request->batch_obj,
2175 request_to_vm(request))) {
2181 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2189 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2190 struct drm_i915_gem_request *request,
2193 struct i915_ctx_hang_stats *hs = NULL;
2194 bool inside, guilty;
2195 unsigned long offset = 0;
2197 /* Innocent until proven guilty */
2200 if (request->batch_obj)
2201 offset = i915_gem_obj_offset(request->batch_obj,
2202 request_to_vm(request));
2204 if (ring->hangcheck.action != wait &&
2205 i915_request_guilty(request, acthd, &inside)) {
2206 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2208 inside ? "inside" : "flushing",
2210 request->ctx ? request->ctx->id : 0,
2216 /* If contexts are disabled or this is the default context, use
2217 * file_priv->reset_state
2219 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2220 hs = &request->ctx->hang_stats;
2221 else if (request->file_priv)
2222 hs = &request->file_priv->hang_stats;
2228 hs->batch_pending++;
2232 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2234 list_del(&request->list);
2235 i915_gem_request_remove_from_client(request);
2238 i915_gem_context_unreference(request->ctx);
2243 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2244 struct intel_ring_buffer *ring)
2246 u32 completed_seqno;
2249 acthd = intel_ring_get_active_head(ring);
2250 completed_seqno = ring->get_seqno(ring, false);
2252 while (!list_empty(&ring->request_list)) {
2253 struct drm_i915_gem_request *request;
2255 request = list_first_entry(&ring->request_list,
2256 struct drm_i915_gem_request,
2259 if (request->seqno > completed_seqno)
2260 i915_set_reset_status(ring, request, acthd);
2262 i915_gem_free_request(request);
2265 while (!list_empty(&ring->active_list)) {
2266 struct drm_i915_gem_object *obj;
2268 obj = list_first_entry(&ring->active_list,
2269 struct drm_i915_gem_object,
2272 i915_gem_object_move_to_inactive(obj);
2276 void i915_gem_restore_fences(struct drm_device *dev)
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2281 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2282 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2285 * Commit delayed tiling changes if we have an object still
2286 * attached to the fence, otherwise just clear the fence.
2289 i915_gem_object_update_fence(reg->obj, reg,
2290 reg->obj->tiling_mode);
2292 i915_gem_write_fence(dev, i, NULL);
2297 void i915_gem_reset(struct drm_device *dev)
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 struct intel_ring_buffer *ring;
2303 for_each_ring(ring, dev_priv, i)
2304 i915_gem_reset_ring_lists(dev_priv, ring);
2306 i915_gem_restore_fences(dev);
2310 * This function clears the request list as sequence numbers are passed.
2313 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2317 if (list_empty(&ring->request_list))
2320 WARN_ON(i915_verify_lists(ring->dev));
2322 seqno = ring->get_seqno(ring, true);
2324 while (!list_empty(&ring->request_list)) {
2325 struct drm_i915_gem_request *request;
2327 request = list_first_entry(&ring->request_list,
2328 struct drm_i915_gem_request,
2331 if (!i915_seqno_passed(seqno, request->seqno))
2334 trace_i915_gem_request_retire(ring, request->seqno);
2335 /* We know the GPU must have read the request to have
2336 * sent us the seqno + interrupt, so use the position
2337 * of tail of the request to update the last known position
2340 ring->last_retired_head = request->tail;
2342 i915_gem_free_request(request);
2345 /* Move any buffers on the active list that are no longer referenced
2346 * by the ringbuffer to the flushing/inactive lists as appropriate.
2348 while (!list_empty(&ring->active_list)) {
2349 struct drm_i915_gem_object *obj;
2351 obj = list_first_entry(&ring->active_list,
2352 struct drm_i915_gem_object,
2355 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2358 i915_gem_object_move_to_inactive(obj);
2361 if (unlikely(ring->trace_irq_seqno &&
2362 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2363 ring->irq_put(ring);
2364 ring->trace_irq_seqno = 0;
2367 WARN_ON(i915_verify_lists(ring->dev));
2371 i915_gem_retire_requests(struct drm_device *dev)
2373 drm_i915_private_t *dev_priv = dev->dev_private;
2374 struct intel_ring_buffer *ring;
2377 for_each_ring(ring, dev_priv, i)
2378 i915_gem_retire_requests_ring(ring);
2382 i915_gem_retire_work_handler(struct work_struct *work)
2384 drm_i915_private_t *dev_priv;
2385 struct drm_device *dev;
2386 struct intel_ring_buffer *ring;
2390 dev_priv = container_of(work, drm_i915_private_t,
2391 mm.retire_work.work);
2392 dev = dev_priv->dev;
2394 /* Come back later if the device is busy... */
2395 if (!mutex_trylock(&dev->struct_mutex)) {
2396 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2397 round_jiffies_up_relative(HZ));
2401 i915_gem_retire_requests(dev);
2403 /* Send a periodic flush down the ring so we don't hold onto GEM
2404 * objects indefinitely.
2407 for_each_ring(ring, dev_priv, i) {
2408 if (ring->gpu_caches_dirty)
2409 i915_add_request(ring, NULL);
2411 idle &= list_empty(&ring->request_list);
2414 if (!dev_priv->ums.mm_suspended && !idle)
2415 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2416 round_jiffies_up_relative(HZ));
2418 intel_mark_idle(dev);
2420 mutex_unlock(&dev->struct_mutex);
2424 * Ensures that an object will eventually get non-busy by flushing any required
2425 * write domains, emitting any outstanding lazy request and retiring and
2426 * completed requests.
2429 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2434 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2438 i915_gem_retire_requests_ring(obj->ring);
2445 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2446 * @DRM_IOCTL_ARGS: standard ioctl arguments
2448 * Returns 0 if successful, else an error is returned with the remaining time in
2449 * the timeout parameter.
2450 * -ETIME: object is still busy after timeout
2451 * -ERESTARTSYS: signal interrupted the wait
2452 * -ENONENT: object doesn't exist
2453 * Also possible, but rare:
2454 * -EAGAIN: GPU wedged
2456 * -ENODEV: Internal IRQ fail
2457 * -E?: The add request failed
2459 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2460 * non-zero timeout parameter the wait ioctl will wait for the given number of
2461 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2462 * without holding struct_mutex the object may become re-busied before this
2463 * function completes. A similar but shorter * race condition exists in the busy
2467 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2469 drm_i915_private_t *dev_priv = dev->dev_private;
2470 struct drm_i915_gem_wait *args = data;
2471 struct drm_i915_gem_object *obj;
2472 struct intel_ring_buffer *ring = NULL;
2473 struct timespec timeout_stack, *timeout = NULL;
2474 unsigned reset_counter;
2478 if (args->timeout_ns >= 0) {
2479 timeout_stack = ns_to_timespec(args->timeout_ns);
2480 timeout = &timeout_stack;
2483 ret = i915_mutex_lock_interruptible(dev);
2487 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2488 if (&obj->base == NULL) {
2489 mutex_unlock(&dev->struct_mutex);
2493 /* Need to make sure the object gets inactive eventually. */
2494 ret = i915_gem_object_flush_active(obj);
2499 seqno = obj->last_read_seqno;
2506 /* Do this after OLR check to make sure we make forward progress polling
2507 * on this IOCTL with a 0 timeout (like busy ioctl)
2509 if (!args->timeout_ns) {
2514 drm_gem_object_unreference(&obj->base);
2515 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2516 mutex_unlock(&dev->struct_mutex);
2518 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2520 args->timeout_ns = timespec_to_ns(timeout);
2524 drm_gem_object_unreference(&obj->base);
2525 mutex_unlock(&dev->struct_mutex);
2530 * i915_gem_object_sync - sync an object to a ring.
2532 * @obj: object which may be in use on another ring.
2533 * @to: ring we wish to use the object on. May be NULL.
2535 * This code is meant to abstract object synchronization with the GPU.
2536 * Calling with NULL implies synchronizing the object with the CPU
2537 * rather than a particular GPU ring.
2539 * Returns 0 if successful, else propagates up the lower layer error.
2542 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2543 struct intel_ring_buffer *to)
2545 struct intel_ring_buffer *from = obj->ring;
2549 if (from == NULL || to == from)
2552 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2553 return i915_gem_object_wait_rendering(obj, false);
2555 idx = intel_ring_sync_index(from, to);
2557 seqno = obj->last_read_seqno;
2558 if (seqno <= from->sync_seqno[idx])
2561 ret = i915_gem_check_olr(obj->ring, seqno);
2565 ret = to->sync_to(to, from, seqno);
2567 /* We use last_read_seqno because sync_to()
2568 * might have just caused seqno wrap under
2571 from->sync_seqno[idx] = obj->last_read_seqno;
2576 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2578 u32 old_write_domain, old_read_domains;
2580 /* Force a pagefault for domain tracking on next user access */
2581 i915_gem_release_mmap(obj);
2583 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2586 /* Wait for any direct GTT access to complete */
2589 old_read_domains = obj->base.read_domains;
2590 old_write_domain = obj->base.write_domain;
2592 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2593 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2595 trace_i915_gem_object_change_domain(obj,
2600 int i915_vma_unbind(struct i915_vma *vma)
2602 struct drm_i915_gem_object *obj = vma->obj;
2603 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2606 if (list_empty(&vma->vma_link))
2612 BUG_ON(obj->pages == NULL);
2614 ret = i915_gem_object_finish_gpu(obj);
2617 /* Continue on if we fail due to EIO, the GPU is hung so we
2618 * should be safe and we need to cleanup or else we might
2619 * cause memory corruption through use-after-free.
2622 i915_gem_object_finish_gtt(obj);
2624 /* release the fence reg _after_ flushing */
2625 ret = i915_gem_object_put_fence(obj);
2629 trace_i915_vma_unbind(vma);
2631 if (obj->has_global_gtt_mapping)
2632 i915_gem_gtt_unbind_object(obj);
2633 if (obj->has_aliasing_ppgtt_mapping) {
2634 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2635 obj->has_aliasing_ppgtt_mapping = 0;
2637 i915_gem_gtt_finish_object(obj);
2638 i915_gem_object_unpin_pages(obj);
2640 list_del(&vma->mm_list);
2641 /* Avoid an unnecessary call to unbind on rebind. */
2642 if (i915_is_ggtt(vma->vm))
2643 obj->map_and_fenceable = true;
2645 list_del(&vma->vma_link);
2646 drm_mm_remove_node(&vma->node);
2647 i915_gem_vma_destroy(vma);
2649 /* Since the unbound list is global, only move to that list if
2650 * no more VMAs exist.
2651 * NB: Until we have real VMAs there will only ever be one */
2652 WARN_ON(!list_empty(&obj->vma_list));
2653 if (list_empty(&obj->vma_list))
2654 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2660 * Unbinds an object from the global GTT aperture.
2663 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2665 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2666 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2668 if (!i915_gem_obj_ggtt_bound(obj));
2674 BUG_ON(obj->pages == NULL);
2676 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2679 int i915_gpu_idle(struct drm_device *dev)
2681 drm_i915_private_t *dev_priv = dev->dev_private;
2682 struct intel_ring_buffer *ring;
2685 /* Flush everything onto the inactive list. */
2686 for_each_ring(ring, dev_priv, i) {
2687 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2691 ret = intel_ring_idle(ring);
2699 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2700 struct drm_i915_gem_object *obj)
2702 drm_i915_private_t *dev_priv = dev->dev_private;
2704 int fence_pitch_shift;
2706 if (INTEL_INFO(dev)->gen >= 6) {
2707 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2708 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2710 fence_reg = FENCE_REG_965_0;
2711 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2714 fence_reg += reg * 8;
2716 /* To w/a incoherency with non-atomic 64-bit register updates,
2717 * we split the 64-bit update into two 32-bit writes. In order
2718 * for a partial fence not to be evaluated between writes, we
2719 * precede the update with write to turn off the fence register,
2720 * and only enable the fence as the last step.
2722 * For extra levels of paranoia, we make sure each step lands
2723 * before applying the next step.
2725 I915_WRITE(fence_reg, 0);
2726 POSTING_READ(fence_reg);
2729 u32 size = i915_gem_obj_ggtt_size(obj);
2732 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2734 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2735 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2736 if (obj->tiling_mode == I915_TILING_Y)
2737 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2738 val |= I965_FENCE_REG_VALID;
2740 I915_WRITE(fence_reg + 4, val >> 32);
2741 POSTING_READ(fence_reg + 4);
2743 I915_WRITE(fence_reg + 0, val);
2744 POSTING_READ(fence_reg);
2746 I915_WRITE(fence_reg + 4, 0);
2747 POSTING_READ(fence_reg + 4);
2751 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2752 struct drm_i915_gem_object *obj)
2754 drm_i915_private_t *dev_priv = dev->dev_private;
2758 u32 size = i915_gem_obj_ggtt_size(obj);
2762 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2763 (size & -size) != size ||
2764 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2765 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2766 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2768 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2773 /* Note: pitch better be a power of two tile widths */
2774 pitch_val = obj->stride / tile_width;
2775 pitch_val = ffs(pitch_val) - 1;
2777 val = i915_gem_obj_ggtt_offset(obj);
2778 if (obj->tiling_mode == I915_TILING_Y)
2779 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2780 val |= I915_FENCE_SIZE_BITS(size);
2781 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2782 val |= I830_FENCE_REG_VALID;
2787 reg = FENCE_REG_830_0 + reg * 4;
2789 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2791 I915_WRITE(reg, val);
2795 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2796 struct drm_i915_gem_object *obj)
2798 drm_i915_private_t *dev_priv = dev->dev_private;
2802 u32 size = i915_gem_obj_ggtt_size(obj);
2805 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2806 (size & -size) != size ||
2807 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2808 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2809 i915_gem_obj_ggtt_offset(obj), size);
2811 pitch_val = obj->stride / 128;
2812 pitch_val = ffs(pitch_val) - 1;
2814 val = i915_gem_obj_ggtt_offset(obj);
2815 if (obj->tiling_mode == I915_TILING_Y)
2816 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2817 val |= I830_FENCE_SIZE_BITS(size);
2818 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2819 val |= I830_FENCE_REG_VALID;
2823 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2824 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2827 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2829 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2832 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2833 struct drm_i915_gem_object *obj)
2835 struct drm_i915_private *dev_priv = dev->dev_private;
2837 /* Ensure that all CPU reads are completed before installing a fence
2838 * and all writes before removing the fence.
2840 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2843 WARN(obj && (!obj->stride || !obj->tiling_mode),
2844 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2845 obj->stride, obj->tiling_mode);
2847 switch (INTEL_INFO(dev)->gen) {
2851 case 4: i965_write_fence_reg(dev, reg, obj); break;
2852 case 3: i915_write_fence_reg(dev, reg, obj); break;
2853 case 2: i830_write_fence_reg(dev, reg, obj); break;
2857 /* And similarly be paranoid that no direct access to this region
2858 * is reordered to before the fence is installed.
2860 if (i915_gem_object_needs_mb(obj))
2864 static inline int fence_number(struct drm_i915_private *dev_priv,
2865 struct drm_i915_fence_reg *fence)
2867 return fence - dev_priv->fence_regs;
2870 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2871 struct drm_i915_fence_reg *fence,
2874 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2875 int reg = fence_number(dev_priv, fence);
2877 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2880 obj->fence_reg = reg;
2882 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2884 obj->fence_reg = I915_FENCE_REG_NONE;
2886 list_del_init(&fence->lru_list);
2888 obj->fence_dirty = false;
2892 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2894 if (obj->last_fenced_seqno) {
2895 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2899 obj->last_fenced_seqno = 0;
2902 obj->fenced_gpu_access = false;
2907 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2909 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2910 struct drm_i915_fence_reg *fence;
2913 ret = i915_gem_object_wait_fence(obj);
2917 if (obj->fence_reg == I915_FENCE_REG_NONE)
2920 fence = &dev_priv->fence_regs[obj->fence_reg];
2922 i915_gem_object_fence_lost(obj);
2923 i915_gem_object_update_fence(obj, fence, false);
2928 static struct drm_i915_fence_reg *
2929 i915_find_fence_reg(struct drm_device *dev)
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 struct drm_i915_fence_reg *reg, *avail;
2935 /* First try to find a free reg */
2937 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2938 reg = &dev_priv->fence_regs[i];
2942 if (!reg->pin_count)
2949 /* None available, try to steal one or wait for a user to finish */
2950 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2961 * i915_gem_object_get_fence - set up fencing for an object
2962 * @obj: object to map through a fence reg
2964 * When mapping objects through the GTT, userspace wants to be able to write
2965 * to them without having to worry about swizzling if the object is tiled.
2966 * This function walks the fence regs looking for a free one for @obj,
2967 * stealing one if it can't find any.
2969 * It then sets up the reg based on the object's properties: address, pitch
2970 * and tiling format.
2972 * For an untiled surface, this removes any existing fence.
2975 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2977 struct drm_device *dev = obj->base.dev;
2978 struct drm_i915_private *dev_priv = dev->dev_private;
2979 bool enable = obj->tiling_mode != I915_TILING_NONE;
2980 struct drm_i915_fence_reg *reg;
2983 /* Have we updated the tiling parameters upon the object and so
2984 * will need to serialise the write to the associated fence register?
2986 if (obj->fence_dirty) {
2987 ret = i915_gem_object_wait_fence(obj);
2992 /* Just update our place in the LRU if our fence is getting reused. */
2993 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2994 reg = &dev_priv->fence_regs[obj->fence_reg];
2995 if (!obj->fence_dirty) {
2996 list_move_tail(®->lru_list,
2997 &dev_priv->mm.fence_list);
3000 } else if (enable) {
3001 reg = i915_find_fence_reg(dev);
3006 struct drm_i915_gem_object *old = reg->obj;
3008 ret = i915_gem_object_wait_fence(old);
3012 i915_gem_object_fence_lost(old);
3017 i915_gem_object_update_fence(obj, reg, enable);
3022 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3023 struct drm_mm_node *gtt_space,
3024 unsigned long cache_level)
3026 struct drm_mm_node *other;
3028 /* On non-LLC machines we have to be careful when putting differing
3029 * types of snoopable memory together to avoid the prefetcher
3030 * crossing memory domains and dying.
3035 if (!drm_mm_node_allocated(gtt_space))
3038 if (list_empty(>t_space->node_list))
3041 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3042 if (other->allocated && !other->hole_follows && other->color != cache_level)
3045 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3046 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3052 static void i915_gem_verify_gtt(struct drm_device *dev)
3055 struct drm_i915_private *dev_priv = dev->dev_private;
3056 struct drm_i915_gem_object *obj;
3059 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3060 if (obj->gtt_space == NULL) {
3061 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3066 if (obj->cache_level != obj->gtt_space->color) {
3067 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3068 i915_gem_obj_ggtt_offset(obj),
3069 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3071 obj->gtt_space->color);
3076 if (!i915_gem_valid_gtt_space(dev,
3078 obj->cache_level)) {
3079 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3080 i915_gem_obj_ggtt_offset(obj),
3081 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3093 * Finds free space in the GTT aperture and binds the object there.
3096 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3097 struct i915_address_space *vm,
3099 bool map_and_fenceable,
3102 struct drm_device *dev = obj->base.dev;
3103 drm_i915_private_t *dev_priv = dev->dev_private;
3104 u32 size, fence_size, fence_alignment, unfenced_alignment;
3105 bool mappable, fenceable;
3107 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3108 struct i915_vma *vma;
3111 if (WARN_ON(!list_empty(&obj->vma_list)))
3114 fence_size = i915_gem_get_gtt_size(dev,
3117 fence_alignment = i915_gem_get_gtt_alignment(dev,
3119 obj->tiling_mode, true);
3120 unfenced_alignment =
3121 i915_gem_get_gtt_alignment(dev,
3123 obj->tiling_mode, false);
3126 alignment = map_and_fenceable ? fence_alignment :
3128 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3129 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3133 size = map_and_fenceable ? fence_size : obj->base.size;
3135 /* If the object is bigger than the entire aperture, reject it early
3136 * before evicting everything in a vain attempt to find space.
3138 if (obj->base.size > gtt_max) {
3139 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3141 map_and_fenceable ? "mappable" : "total",
3146 ret = i915_gem_object_get_pages(obj);
3150 i915_gem_object_pin_pages(obj);
3152 /* FIXME: For now we only ever use 1 VMA per object */
3153 BUG_ON(!i915_is_ggtt(vm));
3154 WARN_ON(!list_empty(&obj->vma_list));
3156 vma = i915_gem_vma_create(obj, vm);
3163 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3165 obj->cache_level, 0, gtt_max);
3167 ret = i915_gem_evict_something(dev, vm, size, alignment,
3176 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3177 obj->cache_level))) {
3179 goto err_remove_node;
3182 ret = i915_gem_gtt_prepare_object(obj);
3184 goto err_remove_node;
3186 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3187 list_add_tail(&vma->mm_list, &vm->inactive_list);
3189 /* Keep GGTT vmas first to make debug easier */
3190 if (i915_is_ggtt(vm))
3191 list_add(&vma->vma_link, &obj->vma_list);
3193 list_add_tail(&vma->vma_link, &obj->vma_list);
3197 i915_gem_obj_ggtt_size(obj) == fence_size &&
3198 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3202 vma->node.start + obj->base.size <= dev_priv->gtt.mappable_end;
3204 /* Map and fenceable only changes if the VM is the global GGTT */
3205 if (i915_is_ggtt(vm))
3206 obj->map_and_fenceable = mappable && fenceable;
3208 trace_i915_vma_bind(vma, map_and_fenceable);
3209 i915_gem_verify_gtt(dev);
3213 drm_mm_remove_node(&vma->node);
3215 i915_gem_vma_destroy(vma);
3217 i915_gem_object_unpin_pages(obj);
3222 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3224 /* If we don't have a page list set up, then we're not pinned
3225 * to GPU, and we can ignore the cache flush because it'll happen
3226 * again at bind time.
3228 if (obj->pages == NULL)
3232 * Stolen memory is always coherent with the GPU as it is explicitly
3233 * marked as wc by the system, or the system is cache-coherent.
3238 /* If the GPU is snooping the contents of the CPU cache,
3239 * we do not need to manually clear the CPU cache lines. However,
3240 * the caches are only snooped when the render cache is
3241 * flushed/invalidated. As we always have to emit invalidations
3242 * and flushes when moving into and out of the RENDER domain, correct
3243 * snooping behaviour occurs naturally as the result of our domain
3246 if (obj->cache_level != I915_CACHE_NONE)
3249 trace_i915_gem_object_clflush(obj);
3251 drm_clflush_sg(obj->pages);
3254 /** Flushes the GTT write domain for the object if it's dirty. */
3256 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3258 uint32_t old_write_domain;
3260 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3263 /* No actual flushing is required for the GTT write domain. Writes
3264 * to it immediately go to main memory as far as we know, so there's
3265 * no chipset flush. It also doesn't land in render cache.
3267 * However, we do have to enforce the order so that all writes through
3268 * the GTT land before any writes to the device, such as updates to
3273 old_write_domain = obj->base.write_domain;
3274 obj->base.write_domain = 0;
3276 trace_i915_gem_object_change_domain(obj,
3277 obj->base.read_domains,
3281 /** Flushes the CPU write domain for the object if it's dirty. */
3283 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3285 uint32_t old_write_domain;
3287 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3290 i915_gem_clflush_object(obj);
3291 i915_gem_chipset_flush(obj->base.dev);
3292 old_write_domain = obj->base.write_domain;
3293 obj->base.write_domain = 0;
3295 trace_i915_gem_object_change_domain(obj,
3296 obj->base.read_domains,
3301 * Moves a single object to the GTT read, and possibly write domain.
3303 * This function returns when the move is complete, including waiting on
3307 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3309 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3310 uint32_t old_write_domain, old_read_domains;
3313 /* Not valid to be called on unbound objects. */
3314 if (!i915_gem_obj_bound_any(obj))
3317 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3320 ret = i915_gem_object_wait_rendering(obj, !write);
3324 i915_gem_object_flush_cpu_write_domain(obj);
3326 /* Serialise direct access to this object with the barriers for
3327 * coherent writes from the GPU, by effectively invalidating the
3328 * GTT domain upon first access.
3330 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3333 old_write_domain = obj->base.write_domain;
3334 old_read_domains = obj->base.read_domains;
3336 /* It should now be out of any other write domains, and we can update
3337 * the domain values for our changes.
3339 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3340 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3342 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3343 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3347 trace_i915_gem_object_change_domain(obj,
3351 /* And bump the LRU for this access */
3352 if (i915_gem_object_is_inactive(obj)) {
3353 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3354 &dev_priv->gtt.base);
3356 list_move_tail(&vma->mm_list,
3357 &dev_priv->gtt.base.inactive_list);
3364 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3365 enum i915_cache_level cache_level)
3367 struct drm_device *dev = obj->base.dev;
3368 drm_i915_private_t *dev_priv = dev->dev_private;
3369 struct i915_vma *vma;
3372 if (obj->cache_level == cache_level)
3375 if (obj->pin_count) {
3376 DRM_DEBUG("can not change the cache level of pinned objects\n");
3380 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3381 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3382 ret = i915_vma_unbind(vma);
3390 if (i915_gem_obj_bound_any(obj)) {
3391 ret = i915_gem_object_finish_gpu(obj);
3395 i915_gem_object_finish_gtt(obj);
3397 /* Before SandyBridge, you could not use tiling or fence
3398 * registers with snooped memory, so relinquish any fences
3399 * currently pointing to our region in the aperture.
3401 if (INTEL_INFO(dev)->gen < 6) {
3402 ret = i915_gem_object_put_fence(obj);
3407 if (obj->has_global_gtt_mapping)
3408 i915_gem_gtt_bind_object(obj, cache_level);
3409 if (obj->has_aliasing_ppgtt_mapping)
3410 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3414 if (cache_level == I915_CACHE_NONE) {
3415 u32 old_read_domains, old_write_domain;
3417 /* If we're coming from LLC cached, then we haven't
3418 * actually been tracking whether the data is in the
3419 * CPU cache or not, since we only allow one bit set
3420 * in obj->write_domain and have been skipping the clflushes.
3421 * Just set it to the CPU cache for now.
3423 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3424 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3426 old_read_domains = obj->base.read_domains;
3427 old_write_domain = obj->base.write_domain;
3429 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3430 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3432 trace_i915_gem_object_change_domain(obj,
3437 list_for_each_entry(vma, &obj->vma_list, vma_link)
3438 vma->node.color = cache_level;
3439 obj->cache_level = cache_level;
3440 i915_gem_verify_gtt(dev);
3444 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3445 struct drm_file *file)
3447 struct drm_i915_gem_caching *args = data;
3448 struct drm_i915_gem_object *obj;
3451 ret = i915_mutex_lock_interruptible(dev);
3455 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3456 if (&obj->base == NULL) {
3461 args->caching = obj->cache_level != I915_CACHE_NONE;
3463 drm_gem_object_unreference(&obj->base);
3465 mutex_unlock(&dev->struct_mutex);
3469 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3470 struct drm_file *file)
3472 struct drm_i915_gem_caching *args = data;
3473 struct drm_i915_gem_object *obj;
3474 enum i915_cache_level level;
3477 switch (args->caching) {
3478 case I915_CACHING_NONE:
3479 level = I915_CACHE_NONE;
3481 case I915_CACHING_CACHED:
3482 level = I915_CACHE_LLC;
3488 ret = i915_mutex_lock_interruptible(dev);
3492 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3493 if (&obj->base == NULL) {
3498 ret = i915_gem_object_set_cache_level(obj, level);
3500 drm_gem_object_unreference(&obj->base);
3502 mutex_unlock(&dev->struct_mutex);
3507 * Prepare buffer for display plane (scanout, cursors, etc).
3508 * Can be called from an uninterruptible phase (modesetting) and allows
3509 * any flushes to be pipelined (for pageflips).
3512 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3514 struct intel_ring_buffer *pipelined)
3516 u32 old_read_domains, old_write_domain;
3519 if (pipelined != obj->ring) {
3520 ret = i915_gem_object_sync(obj, pipelined);
3525 /* The display engine is not coherent with the LLC cache on gen6. As
3526 * a result, we make sure that the pinning that is about to occur is
3527 * done with uncached PTEs. This is lowest common denominator for all
3530 * However for gen6+, we could do better by using the GFDT bit instead
3531 * of uncaching, which would allow us to flush all the LLC-cached data
3532 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3534 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3538 /* As the user may map the buffer once pinned in the display plane
3539 * (e.g. libkms for the bootup splash), we have to ensure that we
3540 * always use map_and_fenceable for all scanout buffers.
3542 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3546 i915_gem_object_flush_cpu_write_domain(obj);
3548 old_write_domain = obj->base.write_domain;
3549 old_read_domains = obj->base.read_domains;
3551 /* It should now be out of any other write domains, and we can update
3552 * the domain values for our changes.
3554 obj->base.write_domain = 0;
3555 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3557 trace_i915_gem_object_change_domain(obj,
3565 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3569 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3572 ret = i915_gem_object_wait_rendering(obj, false);
3576 /* Ensure that we invalidate the GPU's caches and TLBs. */
3577 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3582 * Moves a single object to the CPU read, and possibly write domain.
3584 * This function returns when the move is complete, including waiting on
3588 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3590 uint32_t old_write_domain, old_read_domains;
3593 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3596 ret = i915_gem_object_wait_rendering(obj, !write);
3600 i915_gem_object_flush_gtt_write_domain(obj);
3602 old_write_domain = obj->base.write_domain;
3603 old_read_domains = obj->base.read_domains;
3605 /* Flush the CPU cache if it's still invalid. */
3606 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3607 i915_gem_clflush_object(obj);
3609 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3612 /* It should now be out of any other write domains, and we can update
3613 * the domain values for our changes.
3615 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3617 /* If we're writing through the CPU, then the GPU read domains will
3618 * need to be invalidated at next use.
3621 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3622 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3625 trace_i915_gem_object_change_domain(obj,
3632 /* Throttle our rendering by waiting until the ring has completed our requests
3633 * emitted over 20 msec ago.
3635 * Note that if we were to use the current jiffies each time around the loop,
3636 * we wouldn't escape the function with any frames outstanding if the time to
3637 * render a frame was over 20ms.
3639 * This should get us reasonable parallelism between CPU and GPU but also
3640 * relatively low latency when blocking on a particular request to finish.
3643 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 struct drm_i915_file_private *file_priv = file->driver_priv;
3647 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3648 struct drm_i915_gem_request *request;
3649 struct intel_ring_buffer *ring = NULL;
3650 unsigned reset_counter;
3654 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3658 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3662 spin_lock(&file_priv->mm.lock);
3663 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3664 if (time_after_eq(request->emitted_jiffies, recent_enough))
3667 ring = request->ring;
3668 seqno = request->seqno;
3670 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3671 spin_unlock(&file_priv->mm.lock);
3676 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3678 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3684 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3685 struct i915_address_space *vm,
3687 bool map_and_fenceable,
3690 struct i915_vma *vma;
3693 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3696 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3698 vma = i915_gem_obj_to_vma(obj, vm);
3702 vma->node.start & (alignment - 1)) ||
3703 (map_and_fenceable && !obj->map_and_fenceable)) {
3704 WARN(obj->pin_count,
3705 "bo is already pinned with incorrect alignment:"
3706 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3707 " obj->map_and_fenceable=%d\n",
3708 i915_gem_obj_offset(obj, vm), alignment,
3710 obj->map_and_fenceable);
3711 ret = i915_vma_unbind(vma);
3717 if (!i915_gem_obj_bound(obj, vm)) {
3718 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3720 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3726 if (!dev_priv->mm.aliasing_ppgtt)
3727 i915_gem_gtt_bind_object(obj, obj->cache_level);
3730 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3731 i915_gem_gtt_bind_object(obj, obj->cache_level);
3734 obj->pin_mappable |= map_and_fenceable;
3740 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3742 BUG_ON(obj->pin_count == 0);
3743 BUG_ON(!i915_gem_obj_bound_any(obj));
3745 if (--obj->pin_count == 0)
3746 obj->pin_mappable = false;
3750 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3751 struct drm_file *file)
3753 struct drm_i915_gem_pin *args = data;
3754 struct drm_i915_gem_object *obj;
3757 ret = i915_mutex_lock_interruptible(dev);
3761 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3762 if (&obj->base == NULL) {
3767 if (obj->madv != I915_MADV_WILLNEED) {
3768 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3773 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3774 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3780 if (obj->user_pin_count == 0) {
3781 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3786 obj->user_pin_count++;
3787 obj->pin_filp = file;
3789 /* XXX - flush the CPU caches for pinned objects
3790 * as the X server doesn't manage domains yet
3792 i915_gem_object_flush_cpu_write_domain(obj);
3793 args->offset = i915_gem_obj_ggtt_offset(obj);
3795 drm_gem_object_unreference(&obj->base);
3797 mutex_unlock(&dev->struct_mutex);
3802 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3803 struct drm_file *file)
3805 struct drm_i915_gem_pin *args = data;
3806 struct drm_i915_gem_object *obj;
3809 ret = i915_mutex_lock_interruptible(dev);
3813 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3814 if (&obj->base == NULL) {
3819 if (obj->pin_filp != file) {
3820 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3825 obj->user_pin_count--;
3826 if (obj->user_pin_count == 0) {
3827 obj->pin_filp = NULL;
3828 i915_gem_object_unpin(obj);
3832 drm_gem_object_unreference(&obj->base);
3834 mutex_unlock(&dev->struct_mutex);
3839 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3840 struct drm_file *file)
3842 struct drm_i915_gem_busy *args = data;
3843 struct drm_i915_gem_object *obj;
3846 ret = i915_mutex_lock_interruptible(dev);
3850 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3851 if (&obj->base == NULL) {
3856 /* Count all active objects as busy, even if they are currently not used
3857 * by the gpu. Users of this interface expect objects to eventually
3858 * become non-busy without any further actions, therefore emit any
3859 * necessary flushes here.
3861 ret = i915_gem_object_flush_active(obj);
3863 args->busy = obj->active;
3865 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3866 args->busy |= intel_ring_flag(obj->ring) << 16;
3869 drm_gem_object_unreference(&obj->base);
3871 mutex_unlock(&dev->struct_mutex);
3876 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3877 struct drm_file *file_priv)
3879 return i915_gem_ring_throttle(dev, file_priv);
3883 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3884 struct drm_file *file_priv)
3886 struct drm_i915_gem_madvise *args = data;
3887 struct drm_i915_gem_object *obj;
3890 switch (args->madv) {
3891 case I915_MADV_DONTNEED:
3892 case I915_MADV_WILLNEED:
3898 ret = i915_mutex_lock_interruptible(dev);
3902 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3903 if (&obj->base == NULL) {
3908 if (obj->pin_count) {
3913 if (obj->madv != __I915_MADV_PURGED)
3914 obj->madv = args->madv;
3916 /* if the object is no longer attached, discard its backing storage */
3917 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3918 i915_gem_object_truncate(obj);
3920 args->retained = obj->madv != __I915_MADV_PURGED;
3923 drm_gem_object_unreference(&obj->base);
3925 mutex_unlock(&dev->struct_mutex);
3929 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3930 const struct drm_i915_gem_object_ops *ops)
3932 INIT_LIST_HEAD(&obj->global_list);
3933 INIT_LIST_HEAD(&obj->ring_list);
3934 INIT_LIST_HEAD(&obj->exec_list);
3935 INIT_LIST_HEAD(&obj->vma_list);
3939 obj->fence_reg = I915_FENCE_REG_NONE;
3940 obj->madv = I915_MADV_WILLNEED;
3941 /* Avoid an unnecessary call to unbind on the first bind. */
3942 obj->map_and_fenceable = true;
3944 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3947 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3948 .get_pages = i915_gem_object_get_pages_gtt,
3949 .put_pages = i915_gem_object_put_pages_gtt,
3952 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3955 struct drm_i915_gem_object *obj;
3956 struct address_space *mapping;
3959 obj = i915_gem_object_alloc(dev);
3963 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3964 i915_gem_object_free(obj);
3968 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3969 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3970 /* 965gm cannot relocate objects above 4GiB. */
3971 mask &= ~__GFP_HIGHMEM;
3972 mask |= __GFP_DMA32;
3975 mapping = file_inode(obj->base.filp)->i_mapping;
3976 mapping_set_gfp_mask(mapping, mask);
3978 i915_gem_object_init(obj, &i915_gem_object_ops);
3980 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3981 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3984 /* On some devices, we can have the GPU use the LLC (the CPU
3985 * cache) for about a 10% performance improvement
3986 * compared to uncached. Graphics requests other than
3987 * display scanout are coherent with the CPU in
3988 * accessing this cache. This means in this mode we
3989 * don't need to clflush on the CPU side, and on the
3990 * GPU side we only need to flush internal caches to
3991 * get data visible to the CPU.
3993 * However, we maintain the display planes as UC, and so
3994 * need to rebind when first used as such.
3996 obj->cache_level = I915_CACHE_LLC;
3998 obj->cache_level = I915_CACHE_NONE;
4000 trace_i915_gem_object_create(obj);
4005 int i915_gem_init_object(struct drm_gem_object *obj)
4012 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4014 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4015 struct drm_device *dev = obj->base.dev;
4016 drm_i915_private_t *dev_priv = dev->dev_private;
4017 struct i915_vma *vma, *next;
4019 trace_i915_gem_object_destroy(obj);
4022 i915_gem_detach_phys_object(dev, obj);
4025 /* NB: 0 or 1 elements */
4026 WARN_ON(!list_empty(&obj->vma_list) &&
4027 !list_is_singular(&obj->vma_list));
4028 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4029 int ret = i915_vma_unbind(vma);
4030 if (WARN_ON(ret == -ERESTARTSYS)) {
4031 bool was_interruptible;
4033 was_interruptible = dev_priv->mm.interruptible;
4034 dev_priv->mm.interruptible = false;
4036 WARN_ON(i915_vma_unbind(vma));
4038 dev_priv->mm.interruptible = was_interruptible;
4042 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4043 * before progressing. */
4045 i915_gem_object_unpin_pages(obj);
4047 if (WARN_ON(obj->pages_pin_count))
4048 obj->pages_pin_count = 0;
4049 i915_gem_object_put_pages(obj);
4050 i915_gem_object_free_mmap_offset(obj);
4051 i915_gem_object_release_stolen(obj);
4055 if (obj->base.import_attach)
4056 drm_prime_gem_destroy(&obj->base, NULL);
4058 drm_gem_object_release(&obj->base);
4059 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4062 i915_gem_object_free(obj);
4065 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4066 struct i915_address_space *vm)
4068 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4070 return ERR_PTR(-ENOMEM);
4072 INIT_LIST_HEAD(&vma->vma_link);
4073 INIT_LIST_HEAD(&vma->mm_list);
4080 void i915_gem_vma_destroy(struct i915_vma *vma)
4082 WARN_ON(vma->node.allocated);
4087 i915_gem_idle(struct drm_device *dev)
4089 drm_i915_private_t *dev_priv = dev->dev_private;
4092 if (dev_priv->ums.mm_suspended) {
4093 mutex_unlock(&dev->struct_mutex);
4097 ret = i915_gpu_idle(dev);
4099 mutex_unlock(&dev->struct_mutex);
4102 i915_gem_retire_requests(dev);
4104 /* Under UMS, be paranoid and evict. */
4105 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4106 i915_gem_evict_everything(dev);
4108 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4110 i915_kernel_lost_context(dev);
4111 i915_gem_cleanup_ringbuffer(dev);
4113 /* Cancel the retire work handler, which should be idle now. */
4114 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4119 void i915_gem_l3_remap(struct drm_device *dev)
4121 drm_i915_private_t *dev_priv = dev->dev_private;
4125 if (!HAS_L3_GPU_CACHE(dev))
4128 if (!dev_priv->l3_parity.remap_info)
4131 misccpctl = I915_READ(GEN7_MISCCPCTL);
4132 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4133 POSTING_READ(GEN7_MISCCPCTL);
4135 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4136 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4137 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4138 DRM_DEBUG("0x%x was already programmed to %x\n",
4139 GEN7_L3LOG_BASE + i, remap);
4140 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4141 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4142 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4145 /* Make sure all the writes land before disabling dop clock gating */
4146 POSTING_READ(GEN7_L3LOG_BASE);
4148 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4151 void i915_gem_init_swizzling(struct drm_device *dev)
4153 drm_i915_private_t *dev_priv = dev->dev_private;
4155 if (INTEL_INFO(dev)->gen < 5 ||
4156 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4159 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4160 DISP_TILE_SURFACE_SWIZZLING);
4165 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4167 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4168 else if (IS_GEN7(dev))
4169 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4175 intel_enable_blt(struct drm_device *dev)
4180 /* The blitter was dysfunctional on early prototypes */
4181 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4182 DRM_INFO("BLT not supported on this pre-production hardware;"
4183 " graphics performance will be degraded.\n");
4190 static int i915_gem_init_rings(struct drm_device *dev)
4192 struct drm_i915_private *dev_priv = dev->dev_private;
4195 ret = intel_init_render_ring_buffer(dev);
4200 ret = intel_init_bsd_ring_buffer(dev);
4202 goto cleanup_render_ring;
4205 if (intel_enable_blt(dev)) {
4206 ret = intel_init_blt_ring_buffer(dev);
4208 goto cleanup_bsd_ring;
4211 if (HAS_VEBOX(dev)) {
4212 ret = intel_init_vebox_ring_buffer(dev);
4214 goto cleanup_blt_ring;
4218 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4220 goto cleanup_vebox_ring;
4225 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4227 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4229 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4230 cleanup_render_ring:
4231 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4237 i915_gem_init_hw(struct drm_device *dev)
4239 drm_i915_private_t *dev_priv = dev->dev_private;
4242 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4245 if (dev_priv->ellc_size)
4246 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4248 if (HAS_PCH_NOP(dev)) {
4249 u32 temp = I915_READ(GEN7_MSG_CTL);
4250 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4251 I915_WRITE(GEN7_MSG_CTL, temp);
4254 i915_gem_l3_remap(dev);
4256 i915_gem_init_swizzling(dev);
4258 ret = i915_gem_init_rings(dev);
4263 * XXX: There was some w/a described somewhere suggesting loading
4264 * contexts before PPGTT.
4266 i915_gem_context_init(dev);
4267 if (dev_priv->mm.aliasing_ppgtt) {
4268 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4270 i915_gem_cleanup_aliasing_ppgtt(dev);
4271 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4278 int i915_gem_init(struct drm_device *dev)
4280 struct drm_i915_private *dev_priv = dev->dev_private;
4283 mutex_lock(&dev->struct_mutex);
4285 if (IS_VALLEYVIEW(dev)) {
4286 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4287 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4288 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4289 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4292 i915_gem_init_global_gtt(dev);
4294 ret = i915_gem_init_hw(dev);
4295 mutex_unlock(&dev->struct_mutex);
4297 i915_gem_cleanup_aliasing_ppgtt(dev);
4301 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4302 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4303 dev_priv->dri1.allow_batchbuffer = 1;
4308 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4310 drm_i915_private_t *dev_priv = dev->dev_private;
4311 struct intel_ring_buffer *ring;
4314 for_each_ring(ring, dev_priv, i)
4315 intel_cleanup_ring_buffer(ring);
4319 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4320 struct drm_file *file_priv)
4322 struct drm_i915_private *dev_priv = dev->dev_private;
4325 if (drm_core_check_feature(dev, DRIVER_MODESET))
4328 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4329 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4330 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4333 mutex_lock(&dev->struct_mutex);
4334 dev_priv->ums.mm_suspended = 0;
4336 ret = i915_gem_init_hw(dev);
4338 mutex_unlock(&dev->struct_mutex);
4342 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4343 mutex_unlock(&dev->struct_mutex);
4345 ret = drm_irq_install(dev);
4347 goto cleanup_ringbuffer;
4352 mutex_lock(&dev->struct_mutex);
4353 i915_gem_cleanup_ringbuffer(dev);
4354 dev_priv->ums.mm_suspended = 1;
4355 mutex_unlock(&dev->struct_mutex);
4361 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4362 struct drm_file *file_priv)
4364 struct drm_i915_private *dev_priv = dev->dev_private;
4367 if (drm_core_check_feature(dev, DRIVER_MODESET))
4370 drm_irq_uninstall(dev);
4372 mutex_lock(&dev->struct_mutex);
4373 ret = i915_gem_idle(dev);
4375 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4376 * We need to replace this with a semaphore, or something.
4377 * And not confound ums.mm_suspended!
4380 dev_priv->ums.mm_suspended = 1;
4381 mutex_unlock(&dev->struct_mutex);
4387 i915_gem_lastclose(struct drm_device *dev)
4391 if (drm_core_check_feature(dev, DRIVER_MODESET))
4394 mutex_lock(&dev->struct_mutex);
4395 ret = i915_gem_idle(dev);
4397 DRM_ERROR("failed to idle hardware: %d\n", ret);
4398 mutex_unlock(&dev->struct_mutex);
4402 init_ring_lists(struct intel_ring_buffer *ring)
4404 INIT_LIST_HEAD(&ring->active_list);
4405 INIT_LIST_HEAD(&ring->request_list);
4408 static void i915_init_vm(struct drm_i915_private *dev_priv,
4409 struct i915_address_space *vm)
4411 vm->dev = dev_priv->dev;
4412 INIT_LIST_HEAD(&vm->active_list);
4413 INIT_LIST_HEAD(&vm->inactive_list);
4414 INIT_LIST_HEAD(&vm->global_link);
4415 list_add(&vm->global_link, &dev_priv->vm_list);
4419 i915_gem_load(struct drm_device *dev)
4421 drm_i915_private_t *dev_priv = dev->dev_private;
4425 kmem_cache_create("i915_gem_object",
4426 sizeof(struct drm_i915_gem_object), 0,
4430 INIT_LIST_HEAD(&dev_priv->vm_list);
4431 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4433 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4434 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4435 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4436 for (i = 0; i < I915_NUM_RINGS; i++)
4437 init_ring_lists(&dev_priv->ring[i]);
4438 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4439 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4440 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4441 i915_gem_retire_work_handler);
4442 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4444 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4446 I915_WRITE(MI_ARB_STATE,
4447 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4450 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4452 /* Old X drivers will take 0-2 for front, back, depth buffers */
4453 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4454 dev_priv->fence_reg_start = 3;
4456 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4457 dev_priv->num_fence_regs = 32;
4458 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4459 dev_priv->num_fence_regs = 16;
4461 dev_priv->num_fence_regs = 8;
4463 /* Initialize fence registers to zero */
4464 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4465 i915_gem_restore_fences(dev);
4467 i915_gem_detect_bit_6_swizzle(dev);
4468 init_waitqueue_head(&dev_priv->pending_flip_queue);
4470 dev_priv->mm.interruptible = true;
4472 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4473 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4474 register_shrinker(&dev_priv->mm.inactive_shrinker);
4478 * Create a physically contiguous memory object for this object
4479 * e.g. for cursor + overlay regs
4481 static int i915_gem_init_phys_object(struct drm_device *dev,
4482 int id, int size, int align)
4484 drm_i915_private_t *dev_priv = dev->dev_private;
4485 struct drm_i915_gem_phys_object *phys_obj;
4488 if (dev_priv->mm.phys_objs[id - 1] || !size)
4491 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4497 phys_obj->handle = drm_pci_alloc(dev, size, align);
4498 if (!phys_obj->handle) {
4503 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4506 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4514 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4516 drm_i915_private_t *dev_priv = dev->dev_private;
4517 struct drm_i915_gem_phys_object *phys_obj;
4519 if (!dev_priv->mm.phys_objs[id - 1])
4522 phys_obj = dev_priv->mm.phys_objs[id - 1];
4523 if (phys_obj->cur_obj) {
4524 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4528 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4530 drm_pci_free(dev, phys_obj->handle);
4532 dev_priv->mm.phys_objs[id - 1] = NULL;
4535 void i915_gem_free_all_phys_object(struct drm_device *dev)
4539 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4540 i915_gem_free_phys_object(dev, i);
4543 void i915_gem_detach_phys_object(struct drm_device *dev,
4544 struct drm_i915_gem_object *obj)
4546 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4553 vaddr = obj->phys_obj->handle->vaddr;
4555 page_count = obj->base.size / PAGE_SIZE;
4556 for (i = 0; i < page_count; i++) {
4557 struct page *page = shmem_read_mapping_page(mapping, i);
4558 if (!IS_ERR(page)) {
4559 char *dst = kmap_atomic(page);
4560 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4563 drm_clflush_pages(&page, 1);
4565 set_page_dirty(page);
4566 mark_page_accessed(page);
4567 page_cache_release(page);
4570 i915_gem_chipset_flush(dev);
4572 obj->phys_obj->cur_obj = NULL;
4573 obj->phys_obj = NULL;
4577 i915_gem_attach_phys_object(struct drm_device *dev,
4578 struct drm_i915_gem_object *obj,
4582 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4583 drm_i915_private_t *dev_priv = dev->dev_private;
4588 if (id > I915_MAX_PHYS_OBJECT)
4591 if (obj->phys_obj) {
4592 if (obj->phys_obj->id == id)
4594 i915_gem_detach_phys_object(dev, obj);
4597 /* create a new object */
4598 if (!dev_priv->mm.phys_objs[id - 1]) {
4599 ret = i915_gem_init_phys_object(dev, id,
4600 obj->base.size, align);
4602 DRM_ERROR("failed to init phys object %d size: %zu\n",
4603 id, obj->base.size);
4608 /* bind to the object */
4609 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4610 obj->phys_obj->cur_obj = obj;
4612 page_count = obj->base.size / PAGE_SIZE;
4614 for (i = 0; i < page_count; i++) {
4618 page = shmem_read_mapping_page(mapping, i);
4620 return PTR_ERR(page);
4622 src = kmap_atomic(page);
4623 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4624 memcpy(dst, src, PAGE_SIZE);
4627 mark_page_accessed(page);
4628 page_cache_release(page);
4635 i915_gem_phys_pwrite(struct drm_device *dev,
4636 struct drm_i915_gem_object *obj,
4637 struct drm_i915_gem_pwrite *args,
4638 struct drm_file *file_priv)
4640 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4641 char __user *user_data = to_user_ptr(args->data_ptr);
4643 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4644 unsigned long unwritten;
4646 /* The physical object once assigned is fixed for the lifetime
4647 * of the obj, so we can safely drop the lock and continue
4650 mutex_unlock(&dev->struct_mutex);
4651 unwritten = copy_from_user(vaddr, user_data, args->size);
4652 mutex_lock(&dev->struct_mutex);
4657 i915_gem_chipset_flush(dev);
4661 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4663 struct drm_i915_file_private *file_priv = file->driver_priv;
4665 /* Clean up our request list when the client is going away, so that
4666 * later retire_requests won't dereference our soon-to-be-gone
4669 spin_lock(&file_priv->mm.lock);
4670 while (!list_empty(&file_priv->mm.request_list)) {
4671 struct drm_i915_gem_request *request;
4673 request = list_first_entry(&file_priv->mm.request_list,
4674 struct drm_i915_gem_request,
4676 list_del(&request->client_list);
4677 request->file_priv = NULL;
4679 spin_unlock(&file_priv->mm.lock);
4682 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4684 if (!mutex_is_locked(mutex))
4687 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4688 return mutex->owner == task;
4690 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4696 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4698 struct drm_i915_private *dev_priv =
4699 container_of(shrinker,
4700 struct drm_i915_private,
4701 mm.inactive_shrinker);
4702 struct drm_device *dev = dev_priv->dev;
4703 struct drm_i915_gem_object *obj;
4704 int nr_to_scan = sc->nr_to_scan;
4708 if (!mutex_trylock(&dev->struct_mutex)) {
4709 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4712 if (dev_priv->mm.shrinker_no_lock_stealing)
4719 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4721 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4724 i915_gem_shrink_all(dev_priv);
4728 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4729 if (obj->pages_pin_count == 0)
4730 cnt += obj->base.size >> PAGE_SHIFT;
4732 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4736 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4737 cnt += obj->base.size >> PAGE_SHIFT;
4741 mutex_unlock(&dev->struct_mutex);
4745 /* All the new VM stuff */
4746 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4747 struct i915_address_space *vm)
4749 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4750 struct i915_vma *vma;
4752 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4753 vm = &dev_priv->gtt.base;
4755 BUG_ON(list_empty(&o->vma_list));
4756 list_for_each_entry(vma, &o->vma_list, vma_link) {
4758 return vma->node.start;
4764 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4765 struct i915_address_space *vm)
4767 struct i915_vma *vma;
4769 list_for_each_entry(vma, &o->vma_list, vma_link)
4776 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4778 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4779 struct i915_address_space *vm;
4781 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
4782 if (i915_gem_obj_bound(o, vm))
4788 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4789 struct i915_address_space *vm)
4791 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4792 struct i915_vma *vma;
4794 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4795 vm = &dev_priv->gtt.base;
4797 BUG_ON(list_empty(&o->vma_list));
4799 list_for_each_entry(vma, &o->vma_list, vma_link)
4801 return vma->node.size;
4806 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4807 struct i915_address_space *vm)
4809 struct i915_vma *vma;
4810 list_for_each_entry(vma, &obj->vma_list, vma_link)