drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct i915_gpu_error *error)
  91 {
  92         int ret;
  93
  94 #define EXIT_COND (!i915_reset_in_progress(error) || \
  95                    i915_terminally_wedged(error))
  96         if (EXIT_COND)
  97                 return 0;
  98
  99         /*
 100          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 101          * userspace. If it takes that long something really bad is going on and
 102          * we should simply try to bail out and fail as gracefully as possible.
 103          */
 104         ret = wait_event_interruptible_timeout(error->reset_queue,
 105                                                EXIT_COND,
 106                                                10*HZ);
 107         if (ret == 0) {
 108                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 109                 return -EIO;
 110         } else if (ret < 0) {
 111                 return ret;
 112         }
 113 #undef EXIT_COND
 114
 115         return 0;
 116 }
 117
 118 int i915_mutex_lock_interruptible(struct drm_device *dev)
 119 {
 120         struct drm_i915_private *dev_priv = dev->dev_private;
 121         int ret;
 122
 123         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 124         if (ret)
 125                 return ret;
 126
 127         ret = mutex_lock_interruptible(&dev->struct_mutex);
 128         if (ret)
 129                 return ret;
 130
 131         WARN_ON(i915_verify_lists(dev));
 132         return 0;
 133 }
 134
 135 static inline bool
 136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 137 {
 138         return i915_gem_obj_ggtt_bound(obj) && !obj->active;
 139 }
 140
 141 int
 142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 143                     struct drm_file *file)
 144 {
 145         struct drm_i915_private *dev_priv = dev->dev_private;
 146         struct drm_i915_gem_init *args = data;
 147
 148         if (drm_core_check_feature(dev, DRIVER_MODESET))
 149                 return -ENODEV;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         /* GEM with user mode setting was never supported on ilk and later. */
 156         if (INTEL_INFO(dev)->gen >= 5)
 157                 return -ENODEV;
 158
 159         mutex_lock(&dev->struct_mutex);
 160         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 161                                   args->gtt_end);
 162         dev_priv->gtt.mappable_end = args->gtt_end;
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         pinned = 0;
 178         mutex_lock(&dev->struct_mutex);
 179         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 180                 if (obj->pin_count)
 181                         pinned += i915_gem_obj_ggtt_size(obj);
 182         mutex_unlock(&dev->struct_mutex);
 183
 184         args->aper_size = dev_priv->gtt.base.total;
 185         args->aper_available_size = args->aper_size - pinned;
 186
 187         return 0;
 188 }
 189
 190 void *i915_gem_object_alloc(struct drm_device *dev)
 191 {
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
 194 }
 195
 196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 197 {
 198         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 199         kmem_cache_free(dev_priv->slab, obj);
 200 }
 201
 202 static int
 203 i915_gem_create(struct drm_file *file,
 204                 struct drm_device *dev,
 205                 uint64_t size,
 206                 uint32_t *handle_p)
 207 {
 208         struct drm_i915_gem_object *obj;
 209         int ret;
 210         u32 handle;
 211
 212         size = roundup(size, PAGE_SIZE);
 213         if (size == 0)
 214                 return -EINVAL;
 215
 216         /* Allocate the new object */
 217         obj = i915_gem_alloc_object(dev, size);
 218         if (obj == NULL)
 219                 return -ENOMEM;
 220
 221         ret = drm_gem_handle_create(file, &obj->base, &handle);
 222         /* drop reference from allocate - handle holds it now */
 223         drm_gem_object_unreference_unlocked(&obj->base);
 224         if (ret)
 225                 return ret;
 226
 227         *handle_p = handle;
 228         return 0;
 229 }
 230
 231 int
 232 i915_gem_dumb_create(struct drm_file *file,
 233                      struct drm_device *dev,
 234                      struct drm_mode_create_dumb *args)
 235 {
 236         /* have to work out size/pitch and return them */
 237         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 238         args->size = args->pitch * args->height;
 239         return i915_gem_create(file, dev,
 240                                args->size, &args->handle);
 241 }
 242
 243 int i915_gem_dumb_destroy(struct drm_file *file,
 244                           struct drm_device *dev,
 245                           uint32_t handle)
 246 {
 247         return drm_gem_handle_delete(file, handle);
 248 }
 249
 250 /**
 251  * Creates a new mm object and returns a handle to it.
 252  */
 253 int
 254 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 255                       struct drm_file *file)
 256 {
 257         struct drm_i915_gem_create *args = data;
 258
 259         return i915_gem_create(file, dev,
 260                                args->size, &args->handle);
 261 }
 262
 263 static inline int
 264 __copy_to_user_swizzled(char __user *cpu_vaddr,
 265                         const char *gpu_vaddr, int gpu_offset,
 266                         int length)
 267 {
 268         int ret, cpu_offset = 0;
 269
 270         while (length > 0) {
 271                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 272                 int this_length = min(cacheline_end - gpu_offset, length);
 273                 int swizzled_gpu_offset = gpu_offset ^ 64;
 274
 275                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 276                                      gpu_vaddr + swizzled_gpu_offset,
 277                                      this_length);
 278                 if (ret)
 279                         return ret + length;
 280
 281                 cpu_offset += this_length;
 282                 gpu_offset += this_length;
 283                 length -= this_length;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static inline int
 290 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 291                           const char __user *cpu_vaddr,
 292                           int length)
 293 {
 294         int ret, cpu_offset = 0;
 295
 296         while (length > 0) {
 297                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 298                 int this_length = min(cacheline_end - gpu_offset, length);
 299                 int swizzled_gpu_offset = gpu_offset ^ 64;
 300
 301                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 302                                        cpu_vaddr + cpu_offset,
 303                                        this_length);
 304                 if (ret)
 305                         return ret + length;
 306
 307                 cpu_offset += this_length;
 308                 gpu_offset += this_length;
 309                 length -= this_length;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /* Per-page copy function for the shmem pread fastpath.
 316  * Flushes invalid cachelines before reading the target if
 317  * needs_clflush is set. */
 318 static int
 319 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 320                  char __user *user_data,
 321                  bool page_do_bit17_swizzling, bool needs_clflush)
 322 {
 323         char *vaddr;
 324         int ret;
 325
 326         if (unlikely(page_do_bit17_swizzling))
 327                 return -EINVAL;
 328
 329         vaddr = kmap_atomic(page);
 330         if (needs_clflush)
 331                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 332                                        page_length);
 333         ret = __copy_to_user_inatomic(user_data,
 334                                       vaddr + shmem_page_offset,
 335                                       page_length);
 336         kunmap_atomic(vaddr);
 337
 338         return ret ? -EFAULT : 0;
 339 }
 340
 341 static void
 342 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 343                              bool swizzled)
 344 {
 345         if (unlikely(swizzled)) {
 346                 unsigned long start = (unsigned long) addr;
 347                 unsigned long end = (unsigned long) addr + length;
 348
 349                 /* For swizzling simply ensure that we always flush both
 350                  * channels. Lame, but simple and it works. Swizzled
 351                  * pwrite/pread is far from a hotpath - current userspace
 352                  * doesn't use it at all. */
 353                 start = round_down(start, 128);
 354                 end = round_up(end, 128);
 355
 356                 drm_clflush_virt_range((void *)start, end - start);
 357         } else {
 358                 drm_clflush_virt_range(addr, length);
 359         }
 360
 361 }
 362
 363 /* Only difference to the fast-path function is that this can handle bit17
 364  * and uses non-atomic copy and kmap functions. */
 365 static int
 366 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 367                  char __user *user_data,
 368                  bool page_do_bit17_swizzling, bool needs_clflush)
 369 {
 370         char *vaddr;
 371         int ret;
 372
 373         vaddr = kmap(page);
 374         if (needs_clflush)
 375                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 376                                              page_length,
 377                                              page_do_bit17_swizzling);
 378
 379         if (page_do_bit17_swizzling)
 380                 ret = __copy_to_user_swizzled(user_data,
 381                                               vaddr, shmem_page_offset,
 382                                               page_length);
 383         else
 384                 ret = __copy_to_user(user_data,
 385                                      vaddr + shmem_page_offset,
 386                                      page_length);
 387         kunmap(page);
 388
 389         return ret ? - EFAULT : 0;
 390 }
 391
 392 static int
 393 i915_gem_shmem_pread(struct drm_device *dev,
 394                      struct drm_i915_gem_object *obj,
 395                      struct drm_i915_gem_pread *args,
 396                      struct drm_file *file)
 397 {
 398         char __user *user_data;
 399         ssize_t remain;
 400         loff_t offset;
 401         int shmem_page_offset, page_length, ret = 0;
 402         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 403         int prefaulted = 0;
 404         int needs_clflush = 0;
 405         struct sg_page_iter sg_iter;
 406
 407         user_data = to_user_ptr(args->data_ptr);
 408         remain = args->size;
 409
 410         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 411
 412         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 413                 /* If we're not in the cpu read domain, set ourself into the gtt
 414                  * read domain and manually flush cachelines (if required). This
 415                  * optimizes for the case when the gpu will dirty the data
 416                  * anyway again before the next pread happens. */
 417                 if (obj->cache_level == I915_CACHE_NONE)
 418                         needs_clflush = 1;
 419                 if (i915_gem_obj_ggtt_bound(obj)) {
 420                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 421                         if (ret)
 422                                 return ret;
 423                 }
 424         }
 425
 426         ret = i915_gem_object_get_pages(obj);
 427         if (ret)
 428                 return ret;
 429
 430         i915_gem_object_pin_pages(obj);
 431
 432         offset = args->offset;
 433
 434         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 435                          offset >> PAGE_SHIFT) {
 436                 struct page *page = sg_page_iter_page(&sg_iter);
 437
 438                 if (remain <= 0)
 439                         break;
 440
 441                 /* Operation in this page
 442                  *
 443                  * shmem_page_offset = offset within page in shmem file
 444                  * page_length = bytes to copy for this page
 445                  */
 446                 shmem_page_offset = offset_in_page(offset);
 447                 page_length = remain;
 448                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 449                         page_length = PAGE_SIZE - shmem_page_offset;
 450
 451                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 452                         (page_to_phys(page) & (1 << 17)) != 0;
 453
 454                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 455                                        user_data, page_do_bit17_swizzling,
 456                                        needs_clflush);
 457                 if (ret == 0)
 458                         goto next_page;
 459
 460                 mutex_unlock(&dev->struct_mutex);
 461
 462                 if (likely(!i915_prefault_disable) && !prefaulted) {
 463                         ret = fault_in_multipages_writeable(user_data, remain);
 464                         /* Userspace is tricking us, but we've already clobbered
 465                          * its pages with the prefault and promised to write the
 466                          * data up to the first fault. Hence ignore any errors
 467                          * and just continue. */
 468                         (void)ret;
 469                         prefaulted = 1;
 470                 }
 471
 472                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 473                                        user_data, page_do_bit17_swizzling,
 474                                        needs_clflush);
 475
 476                 mutex_lock(&dev->struct_mutex);
 477
 478 next_page:
 479                 mark_page_accessed(page);
 480
 481                 if (ret)
 482                         goto out;
 483
 484                 remain -= page_length;
 485                 user_data += page_length;
 486                 offset += page_length;
 487         }
 488
 489 out:
 490         i915_gem_object_unpin_pages(obj);
 491
 492         return ret;
 493 }
 494
 495 /**
 496  * Reads data from the object referenced by handle.
 497  *
 498  * On error, the contents of *data are undefined.
 499  */
 500 int
 501 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 502                      struct drm_file *file)
 503 {
 504         struct drm_i915_gem_pread *args = data;
 505         struct drm_i915_gem_object *obj;
 506         int ret = 0;
 507
 508         if (args->size == 0)
 509                 return 0;
 510
 511         if (!access_ok(VERIFY_WRITE,
 512                        to_user_ptr(args->data_ptr),
 513                        args->size))
 514                 return -EFAULT;
 515
 516         ret = i915_mutex_lock_interruptible(dev);
 517         if (ret)
 518                 return ret;
 519
 520         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 521         if (&obj->base == NULL) {
 522                 ret = -ENOENT;
 523                 goto unlock;
 524         }
 525
 526         /* Bounds check source.  */
 527         if (args->offset > obj->base.size ||
 528             args->size > obj->base.size - args->offset) {
 529                 ret = -EINVAL;
 530                 goto out;
 531         }
 532
 533         /* prime objects have no backing filp to GEM pread/pwrite
 534          * pages from.
 535          */
 536         if (!obj->base.filp) {
 537                 ret = -EINVAL;
 538                 goto out;
 539         }
 540
 541         trace_i915_gem_object_pread(obj, args->offset, args->size);
 542
 543         ret = i915_gem_shmem_pread(dev, obj, args, file);
 544
 545 out:
 546         drm_gem_object_unreference(&obj->base);
 547 unlock:
 548         mutex_unlock(&dev->struct_mutex);
 549         return ret;
 550 }
 551
 552 /* This is the fast write path which cannot handle
 553  * page faults in the source data
 554  */
 555
 556 static inline int
 557 fast_user_write(struct io_mapping *mapping,
 558                 loff_t page_base, int page_offset,
 559                 char __user *user_data,
 560                 int length)
 561 {
 562         void __iomem *vaddr_atomic;
 563         void *vaddr;
 564         unsigned long unwritten;
 565
 566         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 567         /* We can use the cpu mem copy function because this is X86. */
 568         vaddr = (void __force*)vaddr_atomic + page_offset;
 569         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 570                                                       user_data, length);
 571         io_mapping_unmap_atomic(vaddr_atomic);
 572         return unwritten;
 573 }
 574
 575 /**
 576  * This is the fast pwrite path, where we copy the data directly from the
 577  * user into the GTT, uncached.
 578  */
 579 static int
 580 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 581                          struct drm_i915_gem_object *obj,
 582                          struct drm_i915_gem_pwrite *args,
 583                          struct drm_file *file)
 584 {
 585         drm_i915_private_t *dev_priv = dev->dev_private;
 586         ssize_t remain;
 587         loff_t offset, page_base;
 588         char __user *user_data;
 589         int page_offset, page_length, ret;
 590
 591         ret = i915_gem_object_pin(obj, 0, true, true);
 592         if (ret)
 593                 goto out;
 594
 595         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 596         if (ret)
 597                 goto out_unpin;
 598
 599         ret = i915_gem_object_put_fence(obj);
 600         if (ret)
 601                 goto out_unpin;
 602
 603         user_data = to_user_ptr(args->data_ptr);
 604         remain = args->size;
 605
 606         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 607
 608         while (remain > 0) {
 609                 /* Operation in this page
 610                  *
 611                  * page_base = page offset within aperture
 612                  * page_offset = offset within page
 613                  * page_length = bytes to copy for this page
 614                  */
 615                 page_base = offset & PAGE_MASK;
 616                 page_offset = offset_in_page(offset);
 617                 page_length = remain;
 618                 if ((page_offset + remain) > PAGE_SIZE)
 619                         page_length = PAGE_SIZE - page_offset;
 620
 621                 /* If we get a fault while copying data, then (presumably) our
 622                  * source page isn't available.  Return the error and we'll
 623                  * retry in the slow path.
 624                  */
 625                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 626                                     page_offset, user_data, page_length)) {
 627                         ret = -EFAULT;
 628                         goto out_unpin;
 629                 }
 630
 631                 remain -= page_length;
 632                 user_data += page_length;
 633                 offset += page_length;
 634         }
 635
 636 out_unpin:
 637         i915_gem_object_unpin(obj);
 638 out:
 639         return ret;
 640 }
 641
 642 /* Per-page copy function for the shmem pwrite fastpath.
 643  * Flushes invalid cachelines before writing to the target if
 644  * needs_clflush_before is set and flushes out any written cachelines after
 645  * writing if needs_clflush is set. */
 646 static int
 647 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 648                   char __user *user_data,
 649                   bool page_do_bit17_swizzling,
 650                   bool needs_clflush_before,
 651                   bool needs_clflush_after)
 652 {
 653         char *vaddr;
 654         int ret;
 655
 656         if (unlikely(page_do_bit17_swizzling))
 657                 return -EINVAL;
 658
 659         vaddr = kmap_atomic(page);
 660         if (needs_clflush_before)
 661                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 662                                        page_length);
 663         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 664                                                 user_data,
 665                                                 page_length);
 666         if (needs_clflush_after)
 667                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 668                                        page_length);
 669         kunmap_atomic(vaddr);
 670
 671         return ret ? -EFAULT : 0;
 672 }
 673
 674 /* Only difference to the fast-path function is that this can handle bit17
 675  * and uses non-atomic copy and kmap functions. */
 676 static int
 677 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 678                   char __user *user_data,
 679                   bool page_do_bit17_swizzling,
 680                   bool needs_clflush_before,
 681                   bool needs_clflush_after)
 682 {
 683         char *vaddr;
 684         int ret;
 685
 686         vaddr = kmap(page);
 687         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 688                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 689                                              page_length,
 690                                              page_do_bit17_swizzling);
 691         if (page_do_bit17_swizzling)
 692                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 693                                                 user_data,
 694                                                 page_length);
 695         else
 696                 ret = __copy_from_user(vaddr + shmem_page_offset,
 697                                        user_data,
 698                                        page_length);
 699         if (needs_clflush_after)
 700                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 701                                              page_length,
 702                                              page_do_bit17_swizzling);
 703         kunmap(page);
 704
 705         return ret ? -EFAULT : 0;
 706 }
 707
 708 static int
 709 i915_gem_shmem_pwrite(struct drm_device *dev,
 710                       struct drm_i915_gem_object *obj,
 711                       struct drm_i915_gem_pwrite *args,
 712                       struct drm_file *file)
 713 {
 714         ssize_t remain;
 715         loff_t offset;
 716         char __user *user_data;
 717         int shmem_page_offset, page_length, ret = 0;
 718         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 719         int hit_slowpath = 0;
 720         int needs_clflush_after = 0;
 721         int needs_clflush_before = 0;
 722         struct sg_page_iter sg_iter;
 723
 724         user_data = to_user_ptr(args->data_ptr);
 725         remain = args->size;
 726
 727         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 728
 729         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 730                 /* If we're not in the cpu write domain, set ourself into the gtt
 731                  * write domain and manually flush cachelines (if required). This
 732                  * optimizes for the case when the gpu will use the data
 733                  * right away and we therefore have to clflush anyway. */
 734                 if (obj->cache_level == I915_CACHE_NONE)
 735                         needs_clflush_after = 1;
 736                 if (i915_gem_obj_ggtt_bound(obj)) {
 737                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 738                         if (ret)
 739                                 return ret;
 740                 }
 741         }
 742         /* Same trick applies for invalidate partially written cachelines before
 743          * writing.  */
 744         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 745             && obj->cache_level == I915_CACHE_NONE)
 746                 needs_clflush_before = 1;
 747
 748         ret = i915_gem_object_get_pages(obj);
 749         if (ret)
 750                 return ret;
 751
 752         i915_gem_object_pin_pages(obj);
 753
 754         offset = args->offset;
 755         obj->dirty = 1;
 756
 757         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 758                          offset >> PAGE_SHIFT) {
 759                 struct page *page = sg_page_iter_page(&sg_iter);
 760                 int partial_cacheline_write;
 761
 762                 if (remain <= 0)
 763                         break;
 764
 765                 /* Operation in this page
 766                  *
 767                  * shmem_page_offset = offset within page in shmem file
 768                  * page_length = bytes to copy for this page
 769                  */
 770                 shmem_page_offset = offset_in_page(offset);
 771
 772                 page_length = remain;
 773                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 774                         page_length = PAGE_SIZE - shmem_page_offset;
 775
 776                 /* If we don't overwrite a cacheline completely we need to be
 777                  * careful to have up-to-date data by first clflushing. Don't
 778                  * overcomplicate things and flush the entire patch. */
 779                 partial_cacheline_write = needs_clflush_before &&
 780                         ((shmem_page_offset | page_length)
 781                                 & (boot_cpu_data.x86_clflush_size - 1));
 782
 783                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 784                         (page_to_phys(page) & (1 << 17)) != 0;
 785
 786                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 787                                         user_data, page_do_bit17_swizzling,
 788                                         partial_cacheline_write,
 789                                         needs_clflush_after);
 790                 if (ret == 0)
 791                         goto next_page;
 792
 793                 hit_slowpath = 1;
 794                 mutex_unlock(&dev->struct_mutex);
 795                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 796                                         user_data, page_do_bit17_swizzling,
 797                                         partial_cacheline_write,
 798                                         needs_clflush_after);
 799
 800                 mutex_lock(&dev->struct_mutex);
 801
 802 next_page:
 803                 set_page_dirty(page);
 804                 mark_page_accessed(page);
 805
 806                 if (ret)
 807                         goto out;
 808
 809                 remain -= page_length;
 810                 user_data += page_length;
 811                 offset += page_length;
 812         }
 813
 814 out:
 815         i915_gem_object_unpin_pages(obj);
 816
 817         if (hit_slowpath) {
 818                 /*
 819                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 820                  * cachelines in-line while writing and the object moved
 821                  * out of the cpu write domain while we've dropped the lock.
 822                  */
 823                 if (!needs_clflush_after &&
 824                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 825                         i915_gem_clflush_object(obj);
 826                         i915_gem_chipset_flush(dev);
 827                 }
 828         }
 829
 830         if (needs_clflush_after)
 831                 i915_gem_chipset_flush(dev);
 832
 833         return ret;
 834 }
 835
 836 /**
 837  * Writes data to the object referenced by handle.
 838  *
 839  * On error, the contents of the buffer that were to be modified are undefined.
 840  */
 841 int
 842 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 843                       struct drm_file *file)
 844 {
 845         struct drm_i915_gem_pwrite *args = data;
 846         struct drm_i915_gem_object *obj;
 847         int ret;
 848
 849         if (args->size == 0)
 850                 return 0;
 851
 852         if (!access_ok(VERIFY_READ,
 853                        to_user_ptr(args->data_ptr),
 854                        args->size))
 855                 return -EFAULT;
 856
 857         if (likely(!i915_prefault_disable)) {
 858                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
 859                                                    args->size);
 860                 if (ret)
 861                         return -EFAULT;
 862         }
 863
 864         ret = i915_mutex_lock_interruptible(dev);
 865         if (ret)
 866                 return ret;
 867
 868         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 869         if (&obj->base == NULL) {
 870                 ret = -ENOENT;
 871                 goto unlock;
 872         }
 873
 874         /* Bounds check destination. */
 875         if (args->offset > obj->base.size ||
 876             args->size > obj->base.size - args->offset) {
 877                 ret = -EINVAL;
 878                 goto out;
 879         }
 880
 881         /* prime objects have no backing filp to GEM pread/pwrite
 882          * pages from.
 883          */
 884         if (!obj->base.filp) {
 885                 ret = -EINVAL;
 886                 goto out;
 887         }
 888
 889         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 890
 891         ret = -EFAULT;
 892         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 893          * it would end up going through the fenced access, and we'll get
 894          * different detiling behavior between reading and writing.
 895          * pread/pwrite currently are reading and writing from the CPU
 896          * perspective, requiring manual detiling by the client.
 897          */
 898         if (obj->phys_obj) {
 899                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 900                 goto out;
 901         }
 902
 903         if (obj->cache_level == I915_CACHE_NONE &&
 904             obj->tiling_mode == I915_TILING_NONE &&
 905             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 906                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 907                 /* Note that the gtt paths might fail with non-page-backed user
 908                  * pointers (e.g. gtt mappings when moving data between
 909                  * textures). Fallback to the shmem path in that case. */
 910         }
 911
 912         if (ret == -EFAULT || ret == -ENOSPC)
 913                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 914
 915 out:
 916         drm_gem_object_unreference(&obj->base);
 917 unlock:
 918         mutex_unlock(&dev->struct_mutex);
 919         return ret;
 920 }
 921
 922 int
 923 i915_gem_check_wedge(struct i915_gpu_error *error,
 924                      bool interruptible)
 925 {
 926         if (i915_reset_in_progress(error)) {
 927                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 928                  * -EIO unconditionally for these. */
 929                 if (!interruptible)
 930                         return -EIO;
 931
 932                 /* Recovery complete, but the reset failed ... */
 933                 if (i915_terminally_wedged(error))
 934                         return -EIO;
 935
 936                 return -EAGAIN;
 937         }
 938
 939         return 0;
 940 }
 941
 942 /*
 943  * Compare seqno against outstanding lazy request. Emit a request if they are
 944  * equal.
 945  */
 946 static int
 947 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 948 {
 949         int ret;
 950
 951         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 952
 953         ret = 0;
 954         if (seqno == ring->outstanding_lazy_request)
 955                 ret = i915_add_request(ring, NULL);
 956
 957         return ret;
 958 }
 959
 960 /**
 961  * __wait_seqno - wait until execution of seqno has finished
 962  * @ring: the ring expected to report seqno
 963  * @seqno: duh!
 964  * @reset_counter: reset sequence associated with the given seqno
 965  * @interruptible: do an interruptible wait (normally yes)
 966  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 967  *
 968  * Note: It is of utmost importance that the passed in seqno and reset_counter
 969  * values have been read by the caller in an smp safe manner. Where read-side
 970  * locks are involved, it is sufficient to read the reset_counter before
 971  * unlocking the lock that protects the seqno. For lockless tricks, the
 972  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 973  * inserted.
 974  *
 975  * Returns 0 if the seqno was found within the alloted time. Else returns the
 976  * errno with remaining time filled in timeout argument.
 977  */
 978 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 979                         unsigned reset_counter,
 980                         bool interruptible, struct timespec *timeout)
 981 {
 982         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 983         struct timespec before, now, wait_time={1,0};
 984         unsigned long timeout_jiffies;
 985         long end;
 986         bool wait_forever = true;
 987         int ret;
 988
 989         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 990                 return 0;
 991
 992         trace_i915_gem_request_wait_begin(ring, seqno);
 993
 994         if (timeout != NULL) {
 995                 wait_time = *timeout;
 996                 wait_forever = false;
 997         }
 998
 999         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1000
1001         if (WARN_ON(!ring->irq_get(ring)))
1002                 return -ENODEV;
1003
1004         /* Record current time in case interrupted by signal, or wedged * */
1005         getrawmonotonic(&before);
1006
1007 #define EXIT_COND \
1008         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1009          i915_reset_in_progress(&dev_priv->gpu_error) || \
1010          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1011         do {
1012                 if (interruptible)
1013                         end = wait_event_interruptible_timeout(ring->irq_queue,
1014                                                                EXIT_COND,
1015                                                                timeout_jiffies);
1016                 else
1017                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1018                                                  timeout_jiffies);
1019
1020                 /* We need to check whether any gpu reset happened in between
1021                  * the caller grabbing the seqno and now ... */
1022                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1023                         end = -EAGAIN;
1024
1025                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1026                  * gone. */
1027                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1028                 if (ret)
1029                         end = ret;
1030         } while (end == 0 && wait_forever);
1031
1032         getrawmonotonic(&now);
1033
1034         ring->irq_put(ring);
1035         trace_i915_gem_request_wait_end(ring, seqno);
1036 #undef EXIT_COND
1037
1038         if (timeout) {
1039                 struct timespec sleep_time = timespec_sub(now, before);
1040                 *timeout = timespec_sub(*timeout, sleep_time);
1041                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1042                         set_normalized_timespec(timeout, 0, 0);
1043         }
1044
1045         switch (end) {
1046         case -EIO:
1047         case -EAGAIN: /* Wedged */
1048         case -ERESTARTSYS: /* Signal */
1049                 return (int)end;
1050         case 0: /* Timeout */
1051                 return -ETIME;
1052         default: /* Completed */
1053                 WARN_ON(end < 0); /* We're not aware of other errors */
1054                 return 0;
1055         }
1056 }
1057
1058 /**
1059  * Waits for a sequence number to be signaled, and cleans up the
1060  * request and object lists appropriately for that event.
1061  */
1062 int
1063 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1064 {
1065         struct drm_device *dev = ring->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         bool interruptible = dev_priv->mm.interruptible;
1068         int ret;
1069
1070         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1071         BUG_ON(seqno == 0);
1072
1073         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1074         if (ret)
1075                 return ret;
1076
1077         ret = i915_gem_check_olr(ring, seqno);
1078         if (ret)
1079                 return ret;
1080
1081         return __wait_seqno(ring, seqno,
1082                             atomic_read(&dev_priv->gpu_error.reset_counter),
1083                             interruptible, NULL);
1084 }
1085
1086 static int
1087 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1088                                      struct intel_ring_buffer *ring)
1089 {
1090         i915_gem_retire_requests_ring(ring);
1091
1092         /* Manually manage the write flush as we may have not yet
1093          * retired the buffer.
1094          *
1095          * Note that the last_write_seqno is always the earlier of
1096          * the two (read/write) seqno, so if we haved successfully waited,
1097          * we know we have passed the last write.
1098          */
1099         obj->last_write_seqno = 0;
1100         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1101
1102         return 0;
1103 }
1104
1105 /**
1106  * Ensures that all rendering to the object has completed and the object is
1107  * safe to unbind from the GTT or access from the CPU.
1108  */
1109 static __must_check int
1110 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1111                                bool readonly)
1112 {
1113         struct intel_ring_buffer *ring = obj->ring;
1114         u32 seqno;
1115         int ret;
1116
1117         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1118         if (seqno == 0)
1119                 return 0;
1120
1121         ret = i915_wait_seqno(ring, seqno);
1122         if (ret)
1123                 return ret;
1124
1125         return i915_gem_object_wait_rendering__tail(obj, ring);
1126 }
1127
1128 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1129  * as the object state may change during this call.
1130  */
1131 static __must_check int
1132 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1133                                             bool readonly)
1134 {
1135         struct drm_device *dev = obj->base.dev;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         struct intel_ring_buffer *ring = obj->ring;
1138         unsigned reset_counter;
1139         u32 seqno;
1140         int ret;
1141
1142         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1143         BUG_ON(!dev_priv->mm.interruptible);
1144
1145         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1146         if (seqno == 0)
1147                 return 0;
1148
1149         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1150         if (ret)
1151                 return ret;
1152
1153         ret = i915_gem_check_olr(ring, seqno);
1154         if (ret)
1155                 return ret;
1156
1157         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1158         mutex_unlock(&dev->struct_mutex);
1159         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1160         mutex_lock(&dev->struct_mutex);
1161         if (ret)
1162                 return ret;
1163
1164         return i915_gem_object_wait_rendering__tail(obj, ring);
1165 }
1166
1167 /**
1168  * Called when user space prepares to use an object with the CPU, either
1169  * through the mmap ioctl's mapping or a GTT mapping.
1170  */
1171 int
1172 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1173                           struct drm_file *file)
1174 {
1175         struct drm_i915_gem_set_domain *args = data;
1176         struct drm_i915_gem_object *obj;
1177         uint32_t read_domains = args->read_domains;
1178         uint32_t write_domain = args->write_domain;
1179         int ret;
1180
1181         /* Only handle setting domains to types used by the CPU. */
1182         if (write_domain & I915_GEM_GPU_DOMAINS)
1183                 return -EINVAL;
1184
1185         if (read_domains & I915_GEM_GPU_DOMAINS)
1186                 return -EINVAL;
1187
1188         /* Having something in the write domain implies it's in the read
1189          * domain, and only that read domain.  Enforce that in the request.
1190          */
1191         if (write_domain != 0 && read_domains != write_domain)
1192                 return -EINVAL;
1193
1194         ret = i915_mutex_lock_interruptible(dev);
1195         if (ret)
1196                 return ret;
1197
1198         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1199         if (&obj->base == NULL) {
1200                 ret = -ENOENT;
1201                 goto unlock;
1202         }
1203
1204         /* Try to flush the object off the GPU without holding the lock.
1205          * We will repeat the flush holding the lock in the normal manner
1206          * to catch cases where we are gazumped.
1207          */
1208         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1209         if (ret)
1210                 goto unref;
1211
1212         if (read_domains & I915_GEM_DOMAIN_GTT) {
1213                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1214
1215                 /* Silently promote "you're not bound, there was nothing to do"
1216                  * to success, since the client was just asking us to
1217                  * make sure everything was done.
1218                  */
1219                 if (ret == -EINVAL)
1220                         ret = 0;
1221         } else {
1222                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1223         }
1224
1225 unref:
1226         drm_gem_object_unreference(&obj->base);
1227 unlock:
1228         mutex_unlock(&dev->struct_mutex);
1229         return ret;
1230 }
1231
1232 /**
1233  * Called when user space has done writes to this buffer
1234  */
1235 int
1236 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1237                          struct drm_file *file)
1238 {
1239         struct drm_i915_gem_sw_finish *args = data;
1240         struct drm_i915_gem_object *obj;
1241         int ret = 0;
1242
1243         ret = i915_mutex_lock_interruptible(dev);
1244         if (ret)
1245                 return ret;
1246
1247         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1248         if (&obj->base == NULL) {
1249                 ret = -ENOENT;
1250                 goto unlock;
1251         }
1252
1253         /* Pinned buffers may be scanout, so flush the cache */
1254         if (obj->pin_count)
1255                 i915_gem_object_flush_cpu_write_domain(obj);
1256
1257         drm_gem_object_unreference(&obj->base);
1258 unlock:
1259         mutex_unlock(&dev->struct_mutex);
1260         return ret;
1261 }
1262
1263 /**
1264  * Maps the contents of an object, returning the address it is mapped
1265  * into.
1266  *
1267  * While the mapping holds a reference on the contents of the object, it doesn't
1268  * imply a ref on the object itself.
1269  */
1270 int
1271 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1272                     struct drm_file *file)
1273 {
1274         struct drm_i915_gem_mmap *args = data;
1275         struct drm_gem_object *obj;
1276         unsigned long addr;
1277
1278         obj = drm_gem_object_lookup(dev, file, args->handle);
1279         if (obj == NULL)
1280                 return -ENOENT;
1281
1282         /* prime objects have no backing filp to GEM mmap
1283          * pages from.
1284          */
1285         if (!obj->filp) {
1286                 drm_gem_object_unreference_unlocked(obj);
1287                 return -EINVAL;
1288         }
1289
1290         addr = vm_mmap(obj->filp, 0, args->size,
1291                        PROT_READ | PROT_WRITE, MAP_SHARED,
1292                        args->offset);
1293         drm_gem_object_unreference_unlocked(obj);
1294         if (IS_ERR((void *)addr))
1295                 return addr;
1296
1297         args->addr_ptr = (uint64_t) addr;
1298
1299         return 0;
1300 }
1301
1302 /**
1303  * i915_gem_fault - fault a page into the GTT
1304  * vma: VMA in question
1305  * vmf: fault info
1306  *
1307  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1308  * from userspace.  The fault handler takes care of binding the object to
1309  * the GTT (if needed), allocating and programming a fence register (again,
1310  * only if needed based on whether the old reg is still valid or the object
1311  * is tiled) and inserting a new PTE into the faulting process.
1312  *
1313  * Note that the faulting process may involve evicting existing objects
1314  * from the GTT and/or fence registers to make room.  So performance may
1315  * suffer if the GTT working set is large or there are few fence registers
1316  * left.
1317  */
1318 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1319 {
1320         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1321         struct drm_device *dev = obj->base.dev;
1322         drm_i915_private_t *dev_priv = dev->dev_private;
1323         pgoff_t page_offset;
1324         unsigned long pfn;
1325         int ret = 0;
1326         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1327
1328         /* We don't use vmf->pgoff since that has the fake offset */
1329         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1330                 PAGE_SHIFT;
1331
1332         ret = i915_mutex_lock_interruptible(dev);
1333         if (ret)
1334                 goto out;
1335
1336         trace_i915_gem_object_fault(obj, page_offset, true, write);
1337
1338         /* Access to snoopable pages through the GTT is incoherent. */
1339         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1340                 ret = -EINVAL;
1341                 goto unlock;
1342         }
1343
1344         /* Now bind it into the GTT if needed */
1345         ret = i915_gem_object_pin(obj, 0, true, false);
1346         if (ret)
1347                 goto unlock;
1348
1349         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1350         if (ret)
1351                 goto unpin;
1352
1353         ret = i915_gem_object_get_fence(obj);
1354         if (ret)
1355                 goto unpin;
1356
1357         obj->fault_mappable = true;
1358
1359         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1360         pfn >>= PAGE_SHIFT;
1361         pfn += page_offset;
1362
1363         /* Finally, remap it using the new GTT offset */
1364         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1365 unpin:
1366         i915_gem_object_unpin(obj);
1367 unlock:
1368         mutex_unlock(&dev->struct_mutex);
1369 out:
1370         switch (ret) {
1371         case -EIO:
1372                 /* If this -EIO is due to a gpu hang, give the reset code a
1373                  * chance to clean up the mess. Otherwise return the proper
1374                  * SIGBUS. */
1375                 if (i915_terminally_wedged(&dev_priv->gpu_error))
1376                         return VM_FAULT_SIGBUS;
1377         case -EAGAIN:
1378                 /* Give the error handler a chance to run and move the
1379                  * objects off the GPU active list. Next time we service the
1380                  * fault, we should be able to transition the page into the
1381                  * GTT without touching the GPU (and so avoid further
1382                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1383                  * with coherency, just lost writes.
1384                  */
1385                 set_need_resched();
1386         case 0:
1387         case -ERESTARTSYS:
1388         case -EINTR:
1389         case -EBUSY:
1390                 /*
1391                  * EBUSY is ok: this just means that another thread
1392                  * already did the job.
1393                  */
1394                 return VM_FAULT_NOPAGE;
1395         case -ENOMEM:
1396                 return VM_FAULT_OOM;
1397         case -ENOSPC:
1398                 return VM_FAULT_SIGBUS;
1399         default:
1400                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1401                 return VM_FAULT_SIGBUS;
1402         }
1403 }
1404
1405 /**
1406  * i915_gem_release_mmap - remove physical page mappings
1407  * @obj: obj in question
1408  *
1409  * Preserve the reservation of the mmapping with the DRM core code, but
1410  * relinquish ownership of the pages back to the system.
1411  *
1412  * It is vital that we remove the page mapping if we have mapped a tiled
1413  * object through the GTT and then lose the fence register due to
1414  * resource pressure. Similarly if the object has been moved out of the
1415  * aperture, than pages mapped into userspace must be revoked. Removing the
1416  * mapping will then trigger a page fault on the next user access, allowing
1417  * fixup by i915_gem_fault().
1418  */
1419 void
1420 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1421 {
1422         if (!obj->fault_mappable)
1423                 return;
1424
1425         if (obj->base.dev->dev_mapping)
1426                 unmap_mapping_range(obj->base.dev->dev_mapping,
1427                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1428                                     obj->base.size, 1);
1429
1430         obj->fault_mappable = false;
1431 }
1432
1433 uint32_t
1434 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1435 {
1436         uint32_t gtt_size;
1437
1438         if (INTEL_INFO(dev)->gen >= 4 ||
1439             tiling_mode == I915_TILING_NONE)
1440                 return size;
1441
1442         /* Previous chips need a power-of-two fence region when tiling */
1443         if (INTEL_INFO(dev)->gen == 3)
1444                 gtt_size = 1024*1024;
1445         else
1446                 gtt_size = 512*1024;
1447
1448         while (gtt_size < size)
1449                 gtt_size <<= 1;
1450
1451         return gtt_size;
1452 }
1453
1454 /**
1455  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1456  * @obj: object to check
1457  *
1458  * Return the required GTT alignment for an object, taking into account
1459  * potential fence register mapping.
1460  */
1461 uint32_t
1462 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1463                            int tiling_mode, bool fenced)
1464 {
1465         /*
1466          * Minimum alignment is 4k (GTT page size), but might be greater
1467          * if a fence register is needed for the object.
1468          */
1469         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1470             tiling_mode == I915_TILING_NONE)
1471                 return 4096;
1472
1473         /*
1474          * Previous chips need to be aligned to the size of the smallest
1475          * fence register that can contain the object.
1476          */
1477         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1478 }
1479
1480 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1481 {
1482         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1483         int ret;
1484
1485         if (obj->base.map_list.map)
1486                 return 0;
1487
1488         dev_priv->mm.shrinker_no_lock_stealing = true;
1489
1490         ret = drm_gem_create_mmap_offset(&obj->base);
1491         if (ret != -ENOSPC)
1492                 goto out;
1493
1494         /* Badly fragmented mmap space? The only way we can recover
1495          * space is by destroying unwanted objects. We can't randomly release
1496          * mmap_offsets as userspace expects them to be persistent for the
1497          * lifetime of the objects. The closest we can is to release the
1498          * offsets on purgeable objects by truncating it and marking it purged,
1499          * which prevents userspace from ever using that object again.
1500          */
1501         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1502         ret = drm_gem_create_mmap_offset(&obj->base);
1503         if (ret != -ENOSPC)
1504                 goto out;
1505
1506         i915_gem_shrink_all(dev_priv);
1507         ret = drm_gem_create_mmap_offset(&obj->base);
1508 out:
1509         dev_priv->mm.shrinker_no_lock_stealing = false;
1510
1511         return ret;
1512 }
1513
1514 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1515 {
1516         if (!obj->base.map_list.map)
1517                 return;
1518
1519         drm_gem_free_mmap_offset(&obj->base);
1520 }
1521
1522 int
1523 i915_gem_mmap_gtt(struct drm_file *file,
1524                   struct drm_device *dev,
1525                   uint32_t handle,
1526                   uint64_t *offset)
1527 {
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         struct drm_i915_gem_object *obj;
1530         int ret;
1531
1532         ret = i915_mutex_lock_interruptible(dev);
1533         if (ret)
1534                 return ret;
1535
1536         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1537         if (&obj->base == NULL) {
1538                 ret = -ENOENT;
1539                 goto unlock;
1540         }
1541
1542         if (obj->base.size > dev_priv->gtt.mappable_end) {
1543                 ret = -E2BIG;
1544                 goto out;
1545         }
1546
1547         if (obj->madv != I915_MADV_WILLNEED) {
1548                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1549                 ret = -EINVAL;
1550                 goto out;
1551         }
1552
1553         ret = i915_gem_object_create_mmap_offset(obj);
1554         if (ret)
1555                 goto out;
1556
1557         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1558
1559 out:
1560         drm_gem_object_unreference(&obj->base);
1561 unlock:
1562         mutex_unlock(&dev->struct_mutex);
1563         return ret;
1564 }
1565
1566 /**
1567  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1568  * @dev: DRM device
1569  * @data: GTT mapping ioctl data
1570  * @file: GEM object info
1571  *
1572  * Simply returns the fake offset to userspace so it can mmap it.
1573  * The mmap call will end up in drm_gem_mmap(), which will set things
1574  * up so we can get faults in the handler above.
1575  *
1576  * The fault handler will take care of binding the object into the GTT
1577  * (since it may have been evicted to make room for something), allocating
1578  * a fence register, and mapping the appropriate aperture address into
1579  * userspace.
1580  */
1581 int
1582 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1583                         struct drm_file *file)
1584 {
1585         struct drm_i915_gem_mmap_gtt *args = data;
1586
1587         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1588 }
1589
1590 /* Immediately discard the backing storage */
1591 static void
1592 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1593 {
1594         struct inode *inode;
1595
1596         i915_gem_object_free_mmap_offset(obj);
1597
1598         if (obj->base.filp == NULL)
1599                 return;
1600
1601         /* Our goal here is to return as much of the memory as
1602          * is possible back to the system as we are called from OOM.
1603          * To do this we must instruct the shmfs to drop all of its
1604          * backing pages, *now*.
1605          */
1606         inode = file_inode(obj->base.filp);
1607         shmem_truncate_range(inode, 0, (loff_t)-1);
1608
1609         obj->madv = __I915_MADV_PURGED;
1610 }
1611
1612 static inline int
1613 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1614 {
1615         return obj->madv == I915_MADV_DONTNEED;
1616 }
1617
1618 static void
1619 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1620 {
1621         struct sg_page_iter sg_iter;
1622         int ret;
1623
1624         BUG_ON(obj->madv == __I915_MADV_PURGED);
1625
1626         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1627         if (ret) {
1628                 /* In the event of a disaster, abandon all caches and
1629                  * hope for the best.
1630                  */
1631                 WARN_ON(ret != -EIO);
1632                 i915_gem_clflush_object(obj);
1633                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1634         }
1635
1636         if (i915_gem_object_needs_bit17_swizzle(obj))
1637                 i915_gem_object_save_bit_17_swizzle(obj);
1638
1639         if (obj->madv == I915_MADV_DONTNEED)
1640                 obj->dirty = 0;
1641
1642         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1643                 struct page *page = sg_page_iter_page(&sg_iter);
1644
1645                 if (obj->dirty)
1646                         set_page_dirty(page);
1647
1648                 if (obj->madv == I915_MADV_WILLNEED)
1649                         mark_page_accessed(page);
1650
1651                 page_cache_release(page);
1652         }
1653         obj->dirty = 0;
1654
1655         sg_free_table(obj->pages);
1656         kfree(obj->pages);
1657 }
1658
1659 int
1660 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1661 {
1662         const struct drm_i915_gem_object_ops *ops = obj->ops;
1663
1664         if (obj->pages == NULL)
1665                 return 0;
1666
1667         BUG_ON(i915_gem_obj_ggtt_bound(obj));
1668
1669         if (obj->pages_pin_count)
1670                 return -EBUSY;
1671
1672         /* ->put_pages might need to allocate memory for the bit17 swizzle
1673          * array, hence protect them from being reaped by removing them from gtt
1674          * lists early. */
1675         list_del(&obj->global_list);
1676
1677         ops->put_pages(obj);
1678         obj->pages = NULL;
1679
1680         if (i915_gem_object_is_purgeable(obj))
1681                 i915_gem_object_truncate(obj);
1682
1683         return 0;
1684 }
1685
1686 static long
1687 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1688                   bool purgeable_only)
1689 {
1690         struct drm_i915_gem_object *obj, *next;
1691         struct i915_address_space *vm = &dev_priv->gtt.base;
1692         long count = 0;
1693
1694         list_for_each_entry_safe(obj, next,
1695                                  &dev_priv->mm.unbound_list,
1696                                  global_list) {
1697                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1698                     i915_gem_object_put_pages(obj) == 0) {
1699                         count += obj->base.size >> PAGE_SHIFT;
1700                         if (count >= target)
1701                                 return count;
1702                 }
1703         }
1704
1705         list_for_each_entry_safe(obj, next, &vm->inactive_list, mm_list) {
1706                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1707                     i915_gem_object_unbind(obj) == 0 &&
1708                     i915_gem_object_put_pages(obj) == 0) {
1709                         count += obj->base.size >> PAGE_SHIFT;
1710                         if (count >= target)
1711                                 return count;
1712                 }
1713         }
1714
1715         return count;
1716 }
1717
1718 static long
1719 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1720 {
1721         return __i915_gem_shrink(dev_priv, target, true);
1722 }
1723
1724 static void
1725 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1726 {
1727         struct drm_i915_gem_object *obj, *next;
1728
1729         i915_gem_evict_everything(dev_priv->dev);
1730
1731         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1732                                  global_list)
1733                 i915_gem_object_put_pages(obj);
1734 }
1735
1736 static int
1737 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1738 {
1739         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1740         int page_count, i;
1741         struct address_space *mapping;
1742         struct sg_table *st;
1743         struct scatterlist *sg;
1744         struct sg_page_iter sg_iter;
1745         struct page *page;
1746         unsigned long last_pfn = 0;     /* suppress gcc warning */
1747         gfp_t gfp;
1748
1749         /* Assert that the object is not currently in any GPU domain. As it
1750          * wasn't in the GTT, there shouldn't be any way it could have been in
1751          * a GPU cache
1752          */
1753         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1754         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1755
1756         st = kmalloc(sizeof(*st), GFP_KERNEL);
1757         if (st == NULL)
1758                 return -ENOMEM;
1759
1760         page_count = obj->base.size / PAGE_SIZE;
1761         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1762                 sg_free_table(st);
1763                 kfree(st);
1764                 return -ENOMEM;
1765         }
1766
1767         /* Get the list of pages out of our struct file.  They'll be pinned
1768          * at this point until we release them.
1769          *
1770          * Fail silently without starting the shrinker
1771          */
1772         mapping = file_inode(obj->base.filp)->i_mapping;
1773         gfp = mapping_gfp_mask(mapping);
1774         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1775         gfp &= ~(__GFP_IO | __GFP_WAIT);
1776         sg = st->sgl;
1777         st->nents = 0;
1778         for (i = 0; i < page_count; i++) {
1779                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1780                 if (IS_ERR(page)) {
1781                         i915_gem_purge(dev_priv, page_count);
1782                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1783                 }
1784                 if (IS_ERR(page)) {
1785                         /* We've tried hard to allocate the memory by reaping
1786                          * our own buffer, now let the real VM do its job and
1787                          * go down in flames if truly OOM.
1788                          */
1789                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1790                         gfp |= __GFP_IO | __GFP_WAIT;
1791
1792                         i915_gem_shrink_all(dev_priv);
1793                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1794                         if (IS_ERR(page))
1795                                 goto err_pages;
1796
1797                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1798                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1799                 }
1800 #ifdef CONFIG_SWIOTLB
1801                 if (swiotlb_nr_tbl()) {
1802                         st->nents++;
1803                         sg_set_page(sg, page, PAGE_SIZE, 0);
1804                         sg = sg_next(sg);
1805                         continue;
1806                 }
1807 #endif
1808                 if (!i || page_to_pfn(page) != last_pfn + 1) {
1809                         if (i)
1810                                 sg = sg_next(sg);
1811                         st->nents++;
1812                         sg_set_page(sg, page, PAGE_SIZE, 0);
1813                 } else {
1814                         sg->length += PAGE_SIZE;
1815                 }
1816                 last_pfn = page_to_pfn(page);
1817         }
1818 #ifdef CONFIG_SWIOTLB
1819         if (!swiotlb_nr_tbl())
1820 #endif
1821                 sg_mark_end(sg);
1822         obj->pages = st;
1823
1824         if (i915_gem_object_needs_bit17_swizzle(obj))
1825                 i915_gem_object_do_bit_17_swizzle(obj);
1826
1827         return 0;
1828
1829 err_pages:
1830         sg_mark_end(sg);
1831         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1832                 page_cache_release(sg_page_iter_page(&sg_iter));
1833         sg_free_table(st);
1834         kfree(st);
1835         return PTR_ERR(page);
1836 }
1837
1838 /* Ensure that the associated pages are gathered from the backing storage
1839  * and pinned into our object. i915_gem_object_get_pages() may be called
1840  * multiple times before they are released by a single call to
1841  * i915_gem_object_put_pages() - once the pages are no longer referenced
1842  * either as a result of memory pressure (reaping pages under the shrinker)
1843  * or as the object is itself released.
1844  */
1845 int
1846 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1847 {
1848         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1849         const struct drm_i915_gem_object_ops *ops = obj->ops;
1850         int ret;
1851
1852         if (obj->pages)
1853                 return 0;
1854
1855         if (obj->madv != I915_MADV_WILLNEED) {
1856                 DRM_ERROR("Attempting to obtain a purgeable object\n");
1857                 return -EINVAL;
1858         }
1859
1860         BUG_ON(obj->pages_pin_count);
1861
1862         ret = ops->get_pages(obj);
1863         if (ret)
1864                 return ret;
1865
1866         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1867         return 0;
1868 }
1869
1870 void
1871 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1872                                struct intel_ring_buffer *ring)
1873 {
1874         struct drm_device *dev = obj->base.dev;
1875         struct drm_i915_private *dev_priv = dev->dev_private;
1876         struct i915_address_space *vm = &dev_priv->gtt.base;
1877         u32 seqno = intel_ring_get_seqno(ring);
1878
1879         BUG_ON(ring == NULL);
1880         if (obj->ring != ring && obj->last_write_seqno) {
1881                 /* Keep the seqno relative to the current ring */
1882                 obj->last_write_seqno = seqno;
1883         }
1884         obj->ring = ring;
1885
1886         /* Add a reference if we're newly entering the active list. */
1887         if (!obj->active) {
1888                 drm_gem_object_reference(&obj->base);
1889                 obj->active = 1;
1890         }
1891
1892         /* Move from whatever list we were on to the tail of execution. */
1893         list_move_tail(&obj->mm_list, &vm->active_list);
1894         list_move_tail(&obj->ring_list, &ring->active_list);
1895
1896         obj->last_read_seqno = seqno;
1897
1898         if (obj->fenced_gpu_access) {
1899                 obj->last_fenced_seqno = seqno;
1900
1901                 /* Bump MRU to take account of the delayed flush */
1902                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1903                         struct drm_i915_fence_reg *reg;
1904
1905                         reg = &dev_priv->fence_regs[obj->fence_reg];
1906                         list_move_tail(&reg->lru_list,
1907                                        &dev_priv->mm.fence_list);
1908                 }
1909         }
1910 }
1911
1912 static void
1913 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1914 {
1915         struct drm_device *dev = obj->base.dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct i915_address_space *vm = &dev_priv->gtt.base;
1918
1919         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1920         BUG_ON(!obj->active);
1921
1922         list_move_tail(&obj->mm_list, &vm->inactive_list);
1923
1924         list_del_init(&obj->ring_list);
1925         obj->ring = NULL;
1926
1927         obj->last_read_seqno = 0;
1928         obj->last_write_seqno = 0;
1929         obj->base.write_domain = 0;
1930
1931         obj->last_fenced_seqno = 0;
1932         obj->fenced_gpu_access = false;
1933
1934         obj->active = 0;
1935         drm_gem_object_unreference(&obj->base);
1936
1937         WARN_ON(i915_verify_lists(dev));
1938 }
1939
1940 static int
1941 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1942 {
1943         struct drm_i915_private *dev_priv = dev->dev_private;
1944         struct intel_ring_buffer *ring;
1945         int ret, i, j;
1946
1947         /* Carefully retire all requests without writing to the rings */
1948         for_each_ring(ring, dev_priv, i) {
1949                 ret = intel_ring_idle(ring);
1950                 if (ret)
1951                         return ret;
1952         }
1953         i915_gem_retire_requests(dev);
1954
1955         /* Finally reset hw state */
1956         for_each_ring(ring, dev_priv, i) {
1957                 intel_ring_init_seqno(ring, seqno);
1958
1959                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1960                         ring->sync_seqno[j] = 0;
1961         }
1962
1963         return 0;
1964 }
1965
1966 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         int ret;
1970
1971         if (seqno == 0)
1972                 return -EINVAL;
1973
1974         /* HWS page needs to be set less than what we
1975          * will inject to ring
1976          */
1977         ret = i915_gem_init_seqno(dev, seqno - 1);
1978         if (ret)
1979                 return ret;
1980
1981         /* Carefully set the last_seqno value so that wrap
1982          * detection still works
1983          */
1984         dev_priv->next_seqno = seqno;
1985         dev_priv->last_seqno = seqno - 1;
1986         if (dev_priv->last_seqno == 0)
1987                 dev_priv->last_seqno--;
1988
1989         return 0;
1990 }
1991
1992 int
1993 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1994 {
1995         struct drm_i915_private *dev_priv = dev->dev_private;
1996
1997         /* reserve 0 for non-seqno */
1998         if (dev_priv->next_seqno == 0) {
1999                 int ret = i915_gem_init_seqno(dev, 0);
2000                 if (ret)
2001                         return ret;
2002
2003                 dev_priv->next_seqno = 1;
2004         }
2005
2006         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2007         return 0;
2008 }
2009
2010 int __i915_add_request(struct intel_ring_buffer *ring,
2011                        struct drm_file *file,
2012                        struct drm_i915_gem_object *obj,
2013                        u32 *out_seqno)
2014 {
2015         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2016         struct drm_i915_gem_request *request;
2017         u32 request_ring_position, request_start;
2018         int was_empty;
2019         int ret;
2020
2021         request_start = intel_ring_get_tail(ring);
2022         /*
2023          * Emit any outstanding flushes - execbuf can fail to emit the flush
2024          * after having emitted the batchbuffer command. Hence we need to fix
2025          * things up similar to emitting the lazy request. The difference here
2026          * is that the flush _must_ happen before the next request, no matter
2027          * what.
2028          */
2029         ret = intel_ring_flush_all_caches(ring);
2030         if (ret)
2031                 return ret;
2032
2033         request = kmalloc(sizeof(*request), GFP_KERNEL);
2034         if (request == NULL)
2035                 return -ENOMEM;
2036
2037
2038         /* Record the position of the start of the request so that
2039          * should we detect the updated seqno part-way through the
2040          * GPU processing the request, we never over-estimate the
2041          * position of the head.
2042          */
2043         request_ring_position = intel_ring_get_tail(ring);
2044
2045         ret = ring->add_request(ring);
2046         if (ret) {
2047                 kfree(request);
2048                 return ret;
2049         }
2050
2051         request->seqno = intel_ring_get_seqno(ring);
2052         request->ring = ring;
2053         request->head = request_start;
2054         request->tail = request_ring_position;
2055         request->ctx = ring->last_context;
2056         request->batch_obj = obj;
2057
2058         /* Whilst this request exists, batch_obj will be on the
2059          * active_list, and so will hold the active reference. Only when this
2060          * request is retired will the the batch_obj be moved onto the
2061          * inactive_list and lose its active reference. Hence we do not need
2062          * to explicitly hold another reference here.
2063          */
2064
2065         if (request->ctx)
2066                 i915_gem_context_reference(request->ctx);
2067
2068         request->emitted_jiffies = jiffies;
2069         was_empty = list_empty(&ring->request_list);
2070         list_add_tail(&request->list, &ring->request_list);
2071         request->file_priv = NULL;
2072
2073         if (file) {
2074                 struct drm_i915_file_private *file_priv = file->driver_priv;
2075
2076                 spin_lock(&file_priv->mm.lock);
2077                 request->file_priv = file_priv;
2078                 list_add_tail(&request->client_list,
2079                               &file_priv->mm.request_list);
2080                 spin_unlock(&file_priv->mm.lock);
2081         }
2082
2083         trace_i915_gem_request_add(ring, request->seqno);
2084         ring->outstanding_lazy_request = 0;
2085
2086         if (!dev_priv->ums.mm_suspended) {
2087                 i915_queue_hangcheck(ring->dev);
2088
2089                 if (was_empty) {
2090                         queue_delayed_work(dev_priv->wq,
2091                                            &dev_priv->mm.retire_work,
2092                                            round_jiffies_up_relative(HZ));
2093                         intel_mark_busy(dev_priv->dev);
2094                 }
2095         }
2096
2097         if (out_seqno)
2098                 *out_seqno = request->seqno;
2099         return 0;
2100 }
2101
2102 static inline void
2103 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2104 {
2105         struct drm_i915_file_private *file_priv = request->file_priv;
2106
2107         if (!file_priv)
2108                 return;
2109
2110         spin_lock(&file_priv->mm.lock);
2111         if (request->file_priv) {
2112                 list_del(&request->client_list);
2113                 request->file_priv = NULL;
2114         }
2115         spin_unlock(&file_priv->mm.lock);
2116 }
2117
2118 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2119 {
2120         if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
2121             acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
2122                 return true;
2123
2124         return false;
2125 }
2126
2127 static bool i915_head_inside_request(const u32 acthd_unmasked,
2128                                      const u32 request_start,
2129                                      const u32 request_end)
2130 {
2131         const u32 acthd = acthd_unmasked & HEAD_ADDR;
2132
2133         if (request_start < request_end) {
2134                 if (acthd >= request_start && acthd < request_end)
2135                         return true;
2136         } else if (request_start > request_end) {
2137                 if (acthd >= request_start || acthd < request_end)
2138                         return true;
2139         }
2140
2141         return false;
2142 }
2143
2144 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2145                                 const u32 acthd, bool *inside)
2146 {
2147         /* There is a possibility that unmasked head address
2148          * pointing inside the ring, matches the batch_obj address range.
2149          * However this is extremely unlikely.
2150          */
2151
2152         if (request->batch_obj) {
2153                 if (i915_head_inside_object(acthd, request->batch_obj)) {
2154                         *inside = true;
2155                         return true;
2156                 }
2157         }
2158
2159         if (i915_head_inside_request(acthd, request->head, request->tail)) {
2160                 *inside = false;
2161                 return true;
2162         }
2163
2164         return false;
2165 }
2166
2167 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2168                                   struct drm_i915_gem_request *request,
2169                                   u32 acthd)
2170 {
2171         struct i915_ctx_hang_stats *hs = NULL;
2172         bool inside, guilty;
2173
2174         /* Innocent until proven guilty */
2175         guilty = false;
2176
2177         if (ring->hangcheck.action != wait &&
2178             i915_request_guilty(request, acthd, &inside)) {
2179                 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2180                           ring->name,
2181                           inside ? "inside" : "flushing",
2182                           request->batch_obj ?
2183                           i915_gem_obj_ggtt_offset(request->batch_obj) : 0,
2184                           request->ctx ? request->ctx->id : 0,
2185                           acthd);
2186
2187                 guilty = true;
2188         }
2189
2190         /* If contexts are disabled or this is the default context, use
2191          * file_priv->reset_state
2192          */
2193         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2194                 hs = &request->ctx->hang_stats;
2195         else if (request->file_priv)
2196                 hs = &request->file_priv->hang_stats;
2197
2198         if (hs) {
2199                 if (guilty)
2200                         hs->batch_active++;
2201                 else
2202                         hs->batch_pending++;
2203         }
2204 }
2205
2206 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2207 {
2208         list_del(&request->list);
2209         i915_gem_request_remove_from_client(request);
2210
2211         if (request->ctx)
2212                 i915_gem_context_unreference(request->ctx);
2213
2214         kfree(request);
2215 }
2216
2217 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2218                                       struct intel_ring_buffer *ring)
2219 {
2220         u32 completed_seqno;
2221         u32 acthd;
2222
2223         acthd = intel_ring_get_active_head(ring);
2224         completed_seqno = ring->get_seqno(ring, false);
2225
2226         while (!list_empty(&ring->request_list)) {
2227                 struct drm_i915_gem_request *request;
2228
2229                 request = list_first_entry(&ring->request_list,
2230                                            struct drm_i915_gem_request,
2231                                            list);
2232
2233                 if (request->seqno > completed_seqno)
2234                         i915_set_reset_status(ring, request, acthd);
2235
2236                 i915_gem_free_request(request);
2237         }
2238
2239         while (!list_empty(&ring->active_list)) {
2240                 struct drm_i915_gem_object *obj;
2241
2242                 obj = list_first_entry(&ring->active_list,
2243                                        struct drm_i915_gem_object,
2244                                        ring_list);
2245
2246                 i915_gem_object_move_to_inactive(obj);
2247         }
2248 }
2249
2250 void i915_gem_restore_fences(struct drm_device *dev)
2251 {
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         int i;
2254
2255         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2256                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2257
2258                 /*
2259                  * Commit delayed tiling changes if we have an object still
2260                  * attached to the fence, otherwise just clear the fence.
2261                  */
2262                 if (reg->obj) {
2263                         i915_gem_object_update_fence(reg->obj, reg,
2264                                                      reg->obj->tiling_mode);
2265                 } else {
2266                         i915_gem_write_fence(dev, i, NULL);
2267                 }
2268         }
2269 }
2270
2271 void i915_gem_reset(struct drm_device *dev)
2272 {
2273         struct drm_i915_private *dev_priv = dev->dev_private;
2274         struct i915_address_space *vm = &dev_priv->gtt.base;
2275         struct drm_i915_gem_object *obj;
2276         struct intel_ring_buffer *ring;
2277         int i;
2278
2279         for_each_ring(ring, dev_priv, i)
2280                 i915_gem_reset_ring_lists(dev_priv, ring);
2281
2282         /* Move everything out of the GPU domains to ensure we do any
2283          * necessary invalidation upon reuse.
2284          */
2285         list_for_each_entry(obj, &vm->inactive_list, mm_list)
2286                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2287
2288         i915_gem_restore_fences(dev);
2289 }
2290
2291 /**
2292  * This function clears the request list as sequence numbers are passed.
2293  */
2294 void
2295 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2296 {
2297         uint32_t seqno;
2298
2299         if (list_empty(&ring->request_list))
2300                 return;
2301
2302         WARN_ON(i915_verify_lists(ring->dev));
2303
2304         seqno = ring->get_seqno(ring, true);
2305
2306         while (!list_empty(&ring->request_list)) {
2307                 struct drm_i915_gem_request *request;
2308
2309                 request = list_first_entry(&ring->request_list,
2310                                            struct drm_i915_gem_request,
2311                                            list);
2312
2313                 if (!i915_seqno_passed(seqno, request->seqno))
2314                         break;
2315
2316                 trace_i915_gem_request_retire(ring, request->seqno);
2317                 /* We know the GPU must have read the request to have
2318                  * sent us the seqno + interrupt, so use the position
2319                  * of tail of the request to update the last known position
2320                  * of the GPU head.
2321                  */
2322                 ring->last_retired_head = request->tail;
2323
2324                 i915_gem_free_request(request);
2325         }
2326
2327         /* Move any buffers on the active list that are no longer referenced
2328          * by the ringbuffer to the flushing/inactive lists as appropriate.
2329          */
2330         while (!list_empty(&ring->active_list)) {
2331                 struct drm_i915_gem_object *obj;
2332
2333                 obj = list_first_entry(&ring->active_list,
2334                                       struct drm_i915_gem_object,
2335                                       ring_list);
2336
2337                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2338                         break;
2339
2340                 i915_gem_object_move_to_inactive(obj);
2341         }
2342
2343         if (unlikely(ring->trace_irq_seqno &&
2344                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2345                 ring->irq_put(ring);
2346                 ring->trace_irq_seqno = 0;
2347         }
2348
2349         WARN_ON(i915_verify_lists(ring->dev));
2350 }
2351
2352 void
2353 i915_gem_retire_requests(struct drm_device *dev)
2354 {
2355         drm_i915_private_t *dev_priv = dev->dev_private;
2356         struct intel_ring_buffer *ring;
2357         int i;
2358
2359         for_each_ring(ring, dev_priv, i)
2360                 i915_gem_retire_requests_ring(ring);
2361 }
2362
2363 static void
2364 i915_gem_retire_work_handler(struct work_struct *work)
2365 {
2366         drm_i915_private_t *dev_priv;
2367         struct drm_device *dev;
2368         struct intel_ring_buffer *ring;
2369         bool idle;
2370         int i;
2371
2372         dev_priv = container_of(work, drm_i915_private_t,
2373                                 mm.retire_work.work);
2374         dev = dev_priv->dev;
2375
2376         /* Come back later if the device is busy... */
2377         if (!mutex_trylock(&dev->struct_mutex)) {
2378                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2379                                    round_jiffies_up_relative(HZ));
2380                 return;
2381         }
2382
2383         i915_gem_retire_requests(dev);
2384
2385         /* Send a periodic flush down the ring so we don't hold onto GEM
2386          * objects indefinitely.
2387          */
2388         idle = true;
2389         for_each_ring(ring, dev_priv, i) {
2390                 if (ring->gpu_caches_dirty)
2391                         i915_add_request(ring, NULL);
2392
2393                 idle &= list_empty(&ring->request_list);
2394         }
2395
2396         if (!dev_priv->ums.mm_suspended && !idle)
2397                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2398                                    round_jiffies_up_relative(HZ));
2399         if (idle)
2400                 intel_mark_idle(dev);
2401
2402         mutex_unlock(&dev->struct_mutex);
2403 }
2404
2405 /**
2406  * Ensures that an object will eventually get non-busy by flushing any required
2407  * write domains, emitting any outstanding lazy request and retiring and
2408  * completed requests.
2409  */
2410 static int
2411 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2412 {
2413         int ret;
2414
2415         if (obj->active) {
2416                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2417                 if (ret)
2418                         return ret;
2419
2420                 i915_gem_retire_requests_ring(obj->ring);
2421         }
2422
2423         return 0;
2424 }
2425
2426 /**
2427  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2428  * @DRM_IOCTL_ARGS: standard ioctl arguments
2429  *
2430  * Returns 0 if successful, else an error is returned with the remaining time in
2431  * the timeout parameter.
2432  *  -ETIME: object is still busy after timeout
2433  *  -ERESTARTSYS: signal interrupted the wait
2434  *  -ENONENT: object doesn't exist
2435  * Also possible, but rare:
2436  *  -EAGAIN: GPU wedged
2437  *  -ENOMEM: damn
2438  *  -ENODEV: Internal IRQ fail
2439  *  -E?: The add request failed
2440  *
2441  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2442  * non-zero timeout parameter the wait ioctl will wait for the given number of
2443  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2444  * without holding struct_mutex the object may become re-busied before this
2445  * function completes. A similar but shorter * race condition exists in the busy
2446  * ioctl
2447  */
2448 int
2449 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2450 {
2451         drm_i915_private_t *dev_priv = dev->dev_private;
2452         struct drm_i915_gem_wait *args = data;
2453         struct drm_i915_gem_object *obj;
2454         struct intel_ring_buffer *ring = NULL;
2455         struct timespec timeout_stack, *timeout = NULL;
2456         unsigned reset_counter;
2457         u32 seqno = 0;
2458         int ret = 0;
2459
2460         if (args->timeout_ns >= 0) {
2461                 timeout_stack = ns_to_timespec(args->timeout_ns);
2462                 timeout = &timeout_stack;
2463         }
2464
2465         ret = i915_mutex_lock_interruptible(dev);
2466         if (ret)
2467                 return ret;
2468
2469         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2470         if (&obj->base == NULL) {
2471                 mutex_unlock(&dev->struct_mutex);
2472                 return -ENOENT;
2473         }
2474
2475         /* Need to make sure the object gets inactive eventually. */
2476         ret = i915_gem_object_flush_active(obj);
2477         if (ret)
2478                 goto out;
2479
2480         if (obj->active) {
2481                 seqno = obj->last_read_seqno;
2482                 ring = obj->ring;
2483         }
2484
2485         if (seqno == 0)
2486                  goto out;
2487
2488         /* Do this after OLR check to make sure we make forward progress polling
2489          * on this IOCTL with a 0 timeout (like busy ioctl)
2490          */
2491         if (!args->timeout_ns) {
2492                 ret = -ETIME;
2493                 goto out;
2494         }
2495
2496         drm_gem_object_unreference(&obj->base);
2497         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2498         mutex_unlock(&dev->struct_mutex);
2499
2500         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2501         if (timeout)
2502                 args->timeout_ns = timespec_to_ns(timeout);
2503         return ret;
2504
2505 out:
2506         drm_gem_object_unreference(&obj->base);
2507         mutex_unlock(&dev->struct_mutex);
2508         return ret;
2509 }
2510
2511 /**
2512  * i915_gem_object_sync - sync an object to a ring.
2513  *
2514  * @obj: object which may be in use on another ring.
2515  * @to: ring we wish to use the object on. May be NULL.
2516  *
2517  * This code is meant to abstract object synchronization with the GPU.
2518  * Calling with NULL implies synchronizing the object with the CPU
2519  * rather than a particular GPU ring.
2520  *
2521  * Returns 0 if successful, else propagates up the lower layer error.
2522  */
2523 int
2524 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2525                      struct intel_ring_buffer *to)
2526 {
2527         struct intel_ring_buffer *from = obj->ring;
2528         u32 seqno;
2529         int ret, idx;
2530
2531         if (from == NULL || to == from)
2532                 return 0;
2533
2534         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2535                 return i915_gem_object_wait_rendering(obj, false);
2536
2537         idx = intel_ring_sync_index(from, to);
2538
2539         seqno = obj->last_read_seqno;
2540         if (seqno <= from->sync_seqno[idx])
2541                 return 0;
2542
2543         ret = i915_gem_check_olr(obj->ring, seqno);
2544         if (ret)
2545                 return ret;
2546
2547         ret = to->sync_to(to, from, seqno);
2548         if (!ret)
2549                 /* We use last_read_seqno because sync_to()
2550                  * might have just caused seqno wrap under
2551                  * the radar.
2552                  */
2553                 from->sync_seqno[idx] = obj->last_read_seqno;
2554
2555         return ret;
2556 }
2557
2558 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2559 {
2560         u32 old_write_domain, old_read_domains;
2561
2562         /* Force a pagefault for domain tracking on next user access */
2563         i915_gem_release_mmap(obj);
2564
2565         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2566                 return;
2567
2568         /* Wait for any direct GTT access to complete */
2569         mb();
2570
2571         old_read_domains = obj->base.read_domains;
2572         old_write_domain = obj->base.write_domain;
2573
2574         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2575         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2576
2577         trace_i915_gem_object_change_domain(obj,
2578                                             old_read_domains,
2579                                             old_write_domain);
2580 }
2581
2582 /**
2583  * Unbinds an object from the GTT aperture.
2584  */
2585 int
2586 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2587 {
2588         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2589         struct i915_vma *vma;
2590         int ret;
2591
2592         if (!i915_gem_obj_ggtt_bound(obj))
2593                 return 0;
2594
2595         if (obj->pin_count)
2596                 return -EBUSY;
2597
2598         BUG_ON(obj->pages == NULL);
2599
2600         ret = i915_gem_object_finish_gpu(obj);
2601         if (ret)
2602                 return ret;
2603         /* Continue on if we fail due to EIO, the GPU is hung so we
2604          * should be safe and we need to cleanup or else we might
2605          * cause memory corruption through use-after-free.
2606          */
2607
2608         i915_gem_object_finish_gtt(obj);
2609
2610         /* release the fence reg _after_ flushing */
2611         ret = i915_gem_object_put_fence(obj);
2612         if (ret)
2613                 return ret;
2614
2615         trace_i915_gem_object_unbind(obj);
2616
2617         if (obj->has_global_gtt_mapping)
2618                 i915_gem_gtt_unbind_object(obj);
2619         if (obj->has_aliasing_ppgtt_mapping) {
2620                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2621                 obj->has_aliasing_ppgtt_mapping = 0;
2622         }
2623         i915_gem_gtt_finish_object(obj);
2624         i915_gem_object_unpin_pages(obj);
2625
2626         list_del(&obj->mm_list);
2627         /* Avoid an unnecessary call to unbind on rebind. */
2628         obj->map_and_fenceable = true;
2629
2630         vma = __i915_gem_obj_to_vma(obj);
2631         list_del(&vma->vma_link);
2632         drm_mm_remove_node(&vma->node);
2633         i915_gem_vma_destroy(vma);
2634
2635         /* Since the unbound list is global, only move to that list if
2636          * no more VMAs exist.
2637          * NB: Until we have real VMAs there will only ever be one */
2638         WARN_ON(!list_empty(&obj->vma_list));
2639         if (list_empty(&obj->vma_list))
2640                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2641
2642         return 0;
2643 }
2644
2645 int i915_gpu_idle(struct drm_device *dev)
2646 {
2647         drm_i915_private_t *dev_priv = dev->dev_private;
2648         struct intel_ring_buffer *ring;
2649         int ret, i;
2650
2651         /* Flush everything onto the inactive list. */
2652         for_each_ring(ring, dev_priv, i) {
2653                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2654                 if (ret)
2655                         return ret;
2656
2657                 ret = intel_ring_idle(ring);
2658                 if (ret)
2659                         return ret;
2660         }
2661
2662         return 0;
2663 }
2664
2665 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2666                                  struct drm_i915_gem_object *obj)
2667 {
2668         drm_i915_private_t *dev_priv = dev->dev_private;
2669         int fence_reg;
2670         int fence_pitch_shift;
2671
2672         if (INTEL_INFO(dev)->gen >= 6) {
2673                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2674                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2675         } else {
2676                 fence_reg = FENCE_REG_965_0;
2677                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2678         }
2679
2680         fence_reg += reg * 8;
2681
2682         /* To w/a incoherency with non-atomic 64-bit register updates,
2683          * we split the 64-bit update into two 32-bit writes. In order
2684          * for a partial fence not to be evaluated between writes, we
2685          * precede the update with write to turn off the fence register,
2686          * and only enable the fence as the last step.
2687          *
2688          * For extra levels of paranoia, we make sure each step lands
2689          * before applying the next step.
2690          */
2691         I915_WRITE(fence_reg, 0);
2692         POSTING_READ(fence_reg);
2693
2694         if (obj) {
2695                 u32 size = i915_gem_obj_ggtt_size(obj);
2696                 uint64_t val;
2697
2698                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2699                                  0xfffff000) << 32;
2700                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2701                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2702                 if (obj->tiling_mode == I915_TILING_Y)
2703                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2704                 val |= I965_FENCE_REG_VALID;
2705
2706                 I915_WRITE(fence_reg + 4, val >> 32);
2707                 POSTING_READ(fence_reg + 4);
2708
2709                 I915_WRITE(fence_reg + 0, val);
2710                 POSTING_READ(fence_reg);
2711         } else {
2712                 I915_WRITE(fence_reg + 4, 0);
2713                 POSTING_READ(fence_reg + 4);
2714         }
2715 }
2716
2717 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2718                                  struct drm_i915_gem_object *obj)
2719 {
2720         drm_i915_private_t *dev_priv = dev->dev_private;
2721         u32 val;
2722
2723         if (obj) {
2724                 u32 size = i915_gem_obj_ggtt_size(obj);
2725                 int pitch_val;
2726                 int tile_width;
2727
2728                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2729                      (size & -size) != size ||
2730                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2731                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2732                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2733
2734                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2735                         tile_width = 128;
2736                 else
2737                         tile_width = 512;
2738
2739                 /* Note: pitch better be a power of two tile widths */
2740                 pitch_val = obj->stride / tile_width;
2741                 pitch_val = ffs(pitch_val) - 1;
2742
2743                 val = i915_gem_obj_ggtt_offset(obj);
2744                 if (obj->tiling_mode == I915_TILING_Y)
2745                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2746                 val |= I915_FENCE_SIZE_BITS(size);
2747                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2748                 val |= I830_FENCE_REG_VALID;
2749         } else
2750                 val = 0;
2751
2752         if (reg < 8)
2753                 reg = FENCE_REG_830_0 + reg * 4;
2754         else
2755                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2756
2757         I915_WRITE(reg, val);
2758         POSTING_READ(reg);
2759 }
2760
2761 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2762                                 struct drm_i915_gem_object *obj)
2763 {
2764         drm_i915_private_t *dev_priv = dev->dev_private;
2765         uint32_t val;
2766
2767         if (obj) {
2768                 u32 size = i915_gem_obj_ggtt_size(obj);
2769                 uint32_t pitch_val;
2770
2771                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2772                      (size & -size) != size ||
2773                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2774                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2775                      i915_gem_obj_ggtt_offset(obj), size);
2776
2777                 pitch_val = obj->stride / 128;
2778                 pitch_val = ffs(pitch_val) - 1;
2779
2780                 val = i915_gem_obj_ggtt_offset(obj);
2781                 if (obj->tiling_mode == I915_TILING_Y)
2782                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2783                 val |= I830_FENCE_SIZE_BITS(size);
2784                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2785                 val |= I830_FENCE_REG_VALID;
2786         } else
2787                 val = 0;
2788
2789         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2790         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2791 }
2792
2793 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2794 {
2795         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2796 }
2797
2798 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2799                                  struct drm_i915_gem_object *obj)
2800 {
2801         struct drm_i915_private *dev_priv = dev->dev_private;
2802
2803         /* Ensure that all CPU reads are completed before installing a fence
2804          * and all writes before removing the fence.
2805          */
2806         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2807                 mb();
2808
2809         WARN(obj && (!obj->stride || !obj->tiling_mode),
2810              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2811              obj->stride, obj->tiling_mode);
2812
2813         switch (INTEL_INFO(dev)->gen) {
2814         case 7:
2815         case 6:
2816         case 5:
2817         case 4: i965_write_fence_reg(dev, reg, obj); break;
2818         case 3: i915_write_fence_reg(dev, reg, obj); break;
2819         case 2: i830_write_fence_reg(dev, reg, obj); break;
2820         default: BUG();
2821         }
2822
2823         /* And similarly be paranoid that no direct access to this region
2824          * is reordered to before the fence is installed.
2825          */
2826         if (i915_gem_object_needs_mb(obj))
2827                 mb();
2828 }
2829
2830 static inline int fence_number(struct drm_i915_private *dev_priv,
2831                                struct drm_i915_fence_reg *fence)
2832 {
2833         return fence - dev_priv->fence_regs;
2834 }
2835
2836 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2837                                          struct drm_i915_fence_reg *fence,
2838                                          bool enable)
2839 {
2840         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2841         int reg = fence_number(dev_priv, fence);
2842
2843         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2844
2845         if (enable) {
2846                 obj->fence_reg = reg;
2847                 fence->obj = obj;
2848                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2849         } else {
2850                 obj->fence_reg = I915_FENCE_REG_NONE;
2851                 fence->obj = NULL;
2852                 list_del_init(&fence->lru_list);
2853         }
2854         obj->fence_dirty = false;
2855 }
2856
2857 static int
2858 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2859 {
2860         if (obj->last_fenced_seqno) {
2861                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2862                 if (ret)
2863                         return ret;
2864
2865                 obj->last_fenced_seqno = 0;
2866         }
2867
2868         obj->fenced_gpu_access = false;
2869         return 0;
2870 }
2871
2872 int
2873 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2874 {
2875         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2876         struct drm_i915_fence_reg *fence;
2877         int ret;
2878
2879         ret = i915_gem_object_wait_fence(obj);
2880         if (ret)
2881                 return ret;
2882
2883         if (obj->fence_reg == I915_FENCE_REG_NONE)
2884                 return 0;
2885
2886         fence = &dev_priv->fence_regs[obj->fence_reg];
2887
2888         i915_gem_object_fence_lost(obj);
2889         i915_gem_object_update_fence(obj, fence, false);
2890
2891         return 0;
2892 }
2893
2894 static struct drm_i915_fence_reg *
2895 i915_find_fence_reg(struct drm_device *dev)
2896 {
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         struct drm_i915_fence_reg *reg, *avail;
2899         int i;
2900
2901         /* First try to find a free reg */
2902         avail = NULL;
2903         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2904                 reg = &dev_priv->fence_regs[i];
2905                 if (!reg->obj)
2906                         return reg;
2907
2908                 if (!reg->pin_count)
2909                         avail = reg;
2910         }
2911
2912         if (avail == NULL)
2913                 return NULL;
2914
2915         /* None available, try to steal one or wait for a user to finish */
2916         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2917                 if (reg->pin_count)
2918                         continue;
2919
2920                 return reg;
2921         }
2922
2923         return NULL;
2924 }
2925
2926 /**
2927  * i915_gem_object_get_fence - set up fencing for an object
2928  * @obj: object to map through a fence reg
2929  *
2930  * When mapping objects through the GTT, userspace wants to be able to write
2931  * to them without having to worry about swizzling if the object is tiled.
2932  * This function walks the fence regs looking for a free one for @obj,
2933  * stealing one if it can't find any.
2934  *
2935  * It then sets up the reg based on the object's properties: address, pitch
2936  * and tiling format.
2937  *
2938  * For an untiled surface, this removes any existing fence.
2939  */
2940 int
2941 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2942 {
2943         struct drm_device *dev = obj->base.dev;
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         bool enable = obj->tiling_mode != I915_TILING_NONE;
2946         struct drm_i915_fence_reg *reg;
2947         int ret;
2948
2949         /* Have we updated the tiling parameters upon the object and so
2950          * will need to serialise the write to the associated fence register?
2951          */
2952         if (obj->fence_dirty) {
2953                 ret = i915_gem_object_wait_fence(obj);
2954                 if (ret)
2955                         return ret;
2956         }
2957
2958         /* Just update our place in the LRU if our fence is getting reused. */
2959         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2960                 reg = &dev_priv->fence_regs[obj->fence_reg];
2961                 if (!obj->fence_dirty) {
2962                         list_move_tail(&reg->lru_list,
2963                                        &dev_priv->mm.fence_list);
2964                         return 0;
2965                 }
2966         } else if (enable) {
2967                 reg = i915_find_fence_reg(dev);
2968                 if (reg == NULL)
2969                         return -EDEADLK;
2970
2971                 if (reg->obj) {
2972                         struct drm_i915_gem_object *old = reg->obj;
2973
2974                         ret = i915_gem_object_wait_fence(old);
2975                         if (ret)
2976                                 return ret;
2977
2978                         i915_gem_object_fence_lost(old);
2979                 }
2980         } else
2981                 return 0;
2982
2983         i915_gem_object_update_fence(obj, reg, enable);
2984
2985         return 0;
2986 }
2987
2988 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2989                                      struct drm_mm_node *gtt_space,
2990                                      unsigned long cache_level)
2991 {
2992         struct drm_mm_node *other;
2993
2994         /* On non-LLC machines we have to be careful when putting differing
2995          * types of snoopable memory together to avoid the prefetcher
2996          * crossing memory domains and dying.
2997          */
2998         if (HAS_LLC(dev))
2999                 return true;
3000
3001         if (!drm_mm_node_allocated(gtt_space))
3002                 return true;
3003
3004         if (list_empty(&gtt_space->node_list))
3005                 return true;
3006
3007         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3008         if (other->allocated && !other->hole_follows && other->color != cache_level)
3009                 return false;
3010
3011         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3012         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3013                 return false;
3014
3015         return true;
3016 }
3017
3018 static void i915_gem_verify_gtt(struct drm_device *dev)
3019 {
3020 #if WATCH_GTT
3021         struct drm_i915_private *dev_priv = dev->dev_private;
3022         struct drm_i915_gem_object *obj;
3023         int err = 0;
3024
3025         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3026                 if (obj->gtt_space == NULL) {
3027                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3028                         err++;
3029                         continue;
3030                 }
3031
3032                 if (obj->cache_level != obj->gtt_space->color) {
3033                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3034                                i915_gem_obj_ggtt_offset(obj),
3035                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3036                                obj->cache_level,
3037                                obj->gtt_space->color);
3038                         err++;
3039                         continue;
3040                 }
3041
3042                 if (!i915_gem_valid_gtt_space(dev,
3043                                               obj->gtt_space,
3044                                               obj->cache_level)) {
3045                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3046                                i915_gem_obj_ggtt_offset(obj),
3047                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3048                                obj->cache_level);
3049                         err++;
3050                         continue;
3051                 }
3052         }
3053
3054         WARN_ON(err);
3055 #endif
3056 }
3057
3058 /**
3059  * Finds free space in the GTT aperture and binds the object there.
3060  */
3061 static int
3062 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3063                             unsigned alignment,
3064                             bool map_and_fenceable,
3065                             bool nonblocking)
3066 {
3067         struct drm_device *dev = obj->base.dev;
3068         drm_i915_private_t *dev_priv = dev->dev_private;
3069         struct i915_address_space *vm = &dev_priv->gtt.base;
3070         u32 size, fence_size, fence_alignment, unfenced_alignment;
3071         bool mappable, fenceable;
3072         size_t gtt_max = map_and_fenceable ?
3073                 dev_priv->gtt.mappable_end : dev_priv->gtt.base.total;
3074         struct i915_vma *vma;
3075         int ret;
3076
3077         if (WARN_ON(!list_empty(&obj->vma_list)))
3078                 return -EBUSY;
3079
3080         fence_size = i915_gem_get_gtt_size(dev,
3081                                            obj->base.size,
3082                                            obj->tiling_mode);
3083         fence_alignment = i915_gem_get_gtt_alignment(dev,
3084                                                      obj->base.size,
3085                                                      obj->tiling_mode, true);
3086         unfenced_alignment =
3087                 i915_gem_get_gtt_alignment(dev,
3088                                                     obj->base.size,
3089                                                     obj->tiling_mode, false);
3090
3091         if (alignment == 0)
3092                 alignment = map_and_fenceable ? fence_alignment :
3093                                                 unfenced_alignment;
3094         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3095                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3096                 return -EINVAL;
3097         }
3098
3099         size = map_and_fenceable ? fence_size : obj->base.size;
3100
3101         /* If the object is bigger than the entire aperture, reject it early
3102          * before evicting everything in a vain attempt to find space.
3103          */
3104         if (obj->base.size > gtt_max) {
3105                 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3106                           obj->base.size,
3107                           map_and_fenceable ? "mappable" : "total",
3108                           gtt_max);
3109                 return -E2BIG;
3110         }
3111
3112         ret = i915_gem_object_get_pages(obj);
3113         if (ret)
3114                 return ret;
3115
3116         i915_gem_object_pin_pages(obj);
3117
3118         vma = i915_gem_vma_create(obj, &dev_priv->gtt.base);
3119         if (IS_ERR(vma)) {
3120                 ret = PTR_ERR(vma);
3121                 goto err_unpin;
3122         }
3123
3124 search_free:
3125         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
3126                                                   &vma->node,
3127                                                   size, alignment,
3128                                                   obj->cache_level, 0, gtt_max);
3129         if (ret) {
3130                 ret = i915_gem_evict_something(dev, size, alignment,
3131                                                obj->cache_level,
3132                                                map_and_fenceable,
3133                                                nonblocking);
3134                 if (ret == 0)
3135                         goto search_free;
3136
3137                 goto err_free_vma;
3138         }
3139         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3140                                               obj->cache_level))) {
3141                 ret = -EINVAL;
3142                 goto err_remove_node;
3143         }
3144
3145         ret = i915_gem_gtt_prepare_object(obj);
3146         if (ret)
3147                 goto err_remove_node;
3148
3149         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3150         list_add_tail(&obj->mm_list, &vm->inactive_list);
3151         list_add(&vma->vma_link, &obj->vma_list);
3152
3153         fenceable =
3154                 i915_gem_obj_ggtt_size(obj) == fence_size &&
3155                 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3156
3157         mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <=
3158                 dev_priv->gtt.mappable_end;
3159
3160         obj->map_and_fenceable = mappable && fenceable;
3161
3162         trace_i915_gem_object_bind(obj, map_and_fenceable);
3163         i915_gem_verify_gtt(dev);
3164         return 0;
3165
3166 err_remove_node:
3167         drm_mm_remove_node(&vma->node);
3168 err_free_vma:
3169         i915_gem_vma_destroy(vma);
3170 err_unpin:
3171         i915_gem_object_unpin_pages(obj);
3172         return ret;
3173 }
3174
3175 void
3176 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3177 {
3178         /* If we don't have a page list set up, then we're not pinned
3179          * to GPU, and we can ignore the cache flush because it'll happen
3180          * again at bind time.
3181          */
3182         if (obj->pages == NULL)
3183                 return;
3184
3185         /*
3186          * Stolen memory is always coherent with the GPU as it is explicitly
3187          * marked as wc by the system, or the system is cache-coherent.
3188          */
3189         if (obj->stolen)
3190                 return;
3191
3192         /* If the GPU is snooping the contents of the CPU cache,
3193          * we do not need to manually clear the CPU cache lines.  However,
3194          * the caches are only snooped when the render cache is
3195          * flushed/invalidated.  As we always have to emit invalidations
3196          * and flushes when moving into and out of the RENDER domain, correct
3197          * snooping behaviour occurs naturally as the result of our domain
3198          * tracking.
3199          */
3200         if (obj->cache_level != I915_CACHE_NONE)
3201                 return;
3202
3203         trace_i915_gem_object_clflush(obj);
3204
3205         drm_clflush_sg(obj->pages);
3206 }
3207
3208 /** Flushes the GTT write domain for the object if it's dirty. */
3209 static void
3210 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3211 {
3212         uint32_t old_write_domain;
3213
3214         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3215                 return;
3216
3217         /* No actual flushing is required for the GTT write domain.  Writes
3218          * to it immediately go to main memory as far as we know, so there's
3219          * no chipset flush.  It also doesn't land in render cache.
3220          *
3221          * However, we do have to enforce the order so that all writes through
3222          * the GTT land before any writes to the device, such as updates to
3223          * the GATT itself.
3224          */
3225         wmb();
3226
3227         old_write_domain = obj->base.write_domain;
3228         obj->base.write_domain = 0;
3229
3230         trace_i915_gem_object_change_domain(obj,
3231                                             obj->base.read_domains,
3232                                             old_write_domain);
3233 }
3234
3235 /** Flushes the CPU write domain for the object if it's dirty. */
3236 static void
3237 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3238 {
3239         uint32_t old_write_domain;
3240
3241         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3242                 return;
3243
3244         i915_gem_clflush_object(obj);
3245         i915_gem_chipset_flush(obj->base.dev);
3246         old_write_domain = obj->base.write_domain;
3247         obj->base.write_domain = 0;
3248
3249         trace_i915_gem_object_change_domain(obj,
3250                                             obj->base.read_domains,
3251                                             old_write_domain);
3252 }
3253
3254 /**
3255  * Moves a single object to the GTT read, and possibly write domain.
3256  *
3257  * This function returns when the move is complete, including waiting on
3258  * flushes to occur.
3259  */
3260 int
3261 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3262 {
3263         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3264         uint32_t old_write_domain, old_read_domains;
3265         int ret;
3266
3267         /* Not valid to be called on unbound objects. */
3268         if (!i915_gem_obj_ggtt_bound(obj))
3269                 return -EINVAL;
3270
3271         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3272                 return 0;
3273
3274         ret = i915_gem_object_wait_rendering(obj, !write);
3275         if (ret)
3276                 return ret;
3277
3278         i915_gem_object_flush_cpu_write_domain(obj);
3279
3280         /* Serialise direct access to this object with the barriers for
3281          * coherent writes from the GPU, by effectively invalidating the
3282          * GTT domain upon first access.
3283          */
3284         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3285                 mb();
3286
3287         old_write_domain = obj->base.write_domain;
3288         old_read_domains = obj->base.read_domains;
3289
3290         /* It should now be out of any other write domains, and we can update
3291          * the domain values for our changes.
3292          */
3293         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3294         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3295         if (write) {
3296                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3297                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3298                 obj->dirty = 1;
3299         }
3300
3301         trace_i915_gem_object_change_domain(obj,
3302                                             old_read_domains,
3303                                             old_write_domain);
3304
3305         /* And bump the LRU for this access */
3306         if (i915_gem_object_is_inactive(obj))
3307                 list_move_tail(&obj->mm_list,
3308                                &dev_priv->gtt.base.inactive_list);
3309
3310         return 0;
3311 }
3312
3313 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3314                                     enum i915_cache_level cache_level)
3315 {
3316         struct drm_device *dev = obj->base.dev;
3317         drm_i915_private_t *dev_priv = dev->dev_private;
3318         struct i915_vma *vma = __i915_gem_obj_to_vma(obj);
3319         int ret;
3320
3321         if (obj->cache_level == cache_level)
3322                 return 0;
3323
3324         if (obj->pin_count) {
3325                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3326                 return -EBUSY;
3327         }
3328
3329         if (vma && !i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3330                 ret = i915_gem_object_unbind(obj);
3331                 if (ret)
3332                         return ret;
3333         }
3334
3335         if (i915_gem_obj_ggtt_bound(obj)) {
3336                 ret = i915_gem_object_finish_gpu(obj);
3337                 if (ret)
3338                         return ret;
3339
3340                 i915_gem_object_finish_gtt(obj);
3341
3342                 /* Before SandyBridge, you could not use tiling or fence
3343                  * registers with snooped memory, so relinquish any fences
3344                  * currently pointing to our region in the aperture.
3345                  */
3346                 if (INTEL_INFO(dev)->gen < 6) {
3347                         ret = i915_gem_object_put_fence(obj);
3348                         if (ret)
3349                                 return ret;
3350                 }
3351
3352                 if (obj->has_global_gtt_mapping)
3353                         i915_gem_gtt_bind_object(obj, cache_level);
3354                 if (obj->has_aliasing_ppgtt_mapping)
3355                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3356                                                obj, cache_level);
3357
3358                 i915_gem_obj_ggtt_set_color(obj, cache_level);
3359         }
3360
3361         if (cache_level == I915_CACHE_NONE) {
3362                 u32 old_read_domains, old_write_domain;
3363
3364                 /* If we're coming from LLC cached, then we haven't
3365                  * actually been tracking whether the data is in the
3366                  * CPU cache or not, since we only allow one bit set
3367                  * in obj->write_domain and have been skipping the clflushes.
3368                  * Just set it to the CPU cache for now.
3369                  */
3370                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3371                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3372
3373                 old_read_domains = obj->base.read_domains;
3374                 old_write_domain = obj->base.write_domain;
3375
3376                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3377                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3378
3379                 trace_i915_gem_object_change_domain(obj,
3380                                                     old_read_domains,
3381                                                     old_write_domain);
3382         }
3383
3384         obj->cache_level = cache_level;
3385         i915_gem_verify_gtt(dev);
3386         return 0;
3387 }
3388
3389 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3390                                struct drm_file *file)
3391 {
3392         struct drm_i915_gem_caching *args = data;
3393         struct drm_i915_gem_object *obj;
3394         int ret;
3395
3396         ret = i915_mutex_lock_interruptible(dev);
3397         if (ret)
3398                 return ret;
3399
3400         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3401         if (&obj->base == NULL) {
3402                 ret = -ENOENT;
3403                 goto unlock;
3404         }
3405
3406         args->caching = obj->cache_level != I915_CACHE_NONE;
3407
3408         drm_gem_object_unreference(&obj->base);
3409 unlock:
3410         mutex_unlock(&dev->struct_mutex);
3411         return ret;
3412 }
3413
3414 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3415                                struct drm_file *file)
3416 {
3417         struct drm_i915_gem_caching *args = data;
3418         struct drm_i915_gem_object *obj;
3419         enum i915_cache_level level;
3420         int ret;
3421
3422         switch (args->caching) {
3423         case I915_CACHING_NONE:
3424                 level = I915_CACHE_NONE;
3425                 break;
3426         case I915_CACHING_CACHED:
3427                 level = I915_CACHE_LLC;
3428                 break;
3429         default:
3430                 return -EINVAL;
3431         }
3432
3433         ret = i915_mutex_lock_interruptible(dev);
3434         if (ret)
3435                 return ret;
3436
3437         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3438         if (&obj->base == NULL) {
3439                 ret = -ENOENT;
3440                 goto unlock;
3441         }
3442
3443         ret = i915_gem_object_set_cache_level(obj, level);
3444
3445         drm_gem_object_unreference(&obj->base);
3446 unlock:
3447         mutex_unlock(&dev->struct_mutex);
3448         return ret;
3449 }
3450
3451 /*
3452  * Prepare buffer for display plane (scanout, cursors, etc).
3453  * Can be called from an uninterruptible phase (modesetting) and allows
3454  * any flushes to be pipelined (for pageflips).
3455  */
3456 int
3457 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3458                                      u32 alignment,
3459                                      struct intel_ring_buffer *pipelined)
3460 {
3461         u32 old_read_domains, old_write_domain;
3462         int ret;
3463
3464         if (pipelined != obj->ring) {
3465                 ret = i915_gem_object_sync(obj, pipelined);
3466                 if (ret)
3467                         return ret;
3468         }
3469
3470         /* The display engine is not coherent with the LLC cache on gen6.  As
3471          * a result, we make sure that the pinning that is about to occur is
3472          * done with uncached PTEs. This is lowest common denominator for all
3473          * chipsets.
3474          *
3475          * However for gen6+, we could do better by using the GFDT bit instead
3476          * of uncaching, which would allow us to flush all the LLC-cached data
3477          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3478          */
3479         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3480         if (ret)
3481                 return ret;
3482
3483         /* As the user may map the buffer once pinned in the display plane
3484          * (e.g. libkms for the bootup splash), we have to ensure that we
3485          * always use map_and_fenceable for all scanout buffers.
3486          */
3487         ret = i915_gem_object_pin(obj, alignment, true, false);
3488         if (ret)
3489                 return ret;
3490
3491         i915_gem_object_flush_cpu_write_domain(obj);
3492
3493         old_write_domain = obj->base.write_domain;
3494         old_read_domains = obj->base.read_domains;
3495
3496         /* It should now be out of any other write domains, and we can update
3497          * the domain values for our changes.
3498          */
3499         obj->base.write_domain = 0;
3500         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3501
3502         trace_i915_gem_object_change_domain(obj,
3503                                             old_read_domains,
3504                                             old_write_domain);
3505
3506         return 0;
3507 }
3508
3509 int
3510 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3511 {
3512         int ret;
3513
3514         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3515                 return 0;
3516
3517         ret = i915_gem_object_wait_rendering(obj, false);
3518         if (ret)
3519                 return ret;
3520
3521         /* Ensure that we invalidate the GPU's caches and TLBs. */
3522         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3523         return 0;
3524 }
3525
3526 /**
3527  * Moves a single object to the CPU read, and possibly write domain.
3528  *
3529  * This function returns when the move is complete, including waiting on
3530  * flushes to occur.
3531  */
3532 int
3533 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3534 {
3535         uint32_t old_write_domain, old_read_domains;
3536         int ret;
3537
3538         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3539                 return 0;
3540
3541         ret = i915_gem_object_wait_rendering(obj, !write);
3542         if (ret)
3543                 return ret;
3544
3545         i915_gem_object_flush_gtt_write_domain(obj);
3546
3547         old_write_domain = obj->base.write_domain;
3548         old_read_domains = obj->base.read_domains;
3549
3550         /* Flush the CPU cache if it's still invalid. */
3551         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3552                 i915_gem_clflush_object(obj);
3553
3554                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3555         }
3556
3557         /* It should now be out of any other write domains, and we can update
3558          * the domain values for our changes.
3559          */
3560         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3561
3562         /* If we're writing through the CPU, then the GPU read domains will
3563          * need to be invalidated at next use.
3564          */
3565         if (write) {
3566                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3567                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3568         }
3569
3570         trace_i915_gem_object_change_domain(obj,
3571                                             old_read_domains,
3572                                             old_write_domain);
3573
3574         return 0;
3575 }
3576
3577 /* Throttle our rendering by waiting until the ring has completed our requests
3578  * emitted over 20 msec ago.
3579  *
3580  * Note that if we were to use the current jiffies each time around the loop,
3581  * we wouldn't escape the function with any frames outstanding if the time to
3582  * render a frame was over 20ms.
3583  *
3584  * This should get us reasonable parallelism between CPU and GPU but also
3585  * relatively low latency when blocking on a particular request to finish.
3586  */
3587 static int
3588 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3589 {
3590         struct drm_i915_private *dev_priv = dev->dev_private;
3591         struct drm_i915_file_private *file_priv = file->driver_priv;
3592         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3593         struct drm_i915_gem_request *request;
3594         struct intel_ring_buffer *ring = NULL;
3595         unsigned reset_counter;
3596         u32 seqno = 0;
3597         int ret;
3598
3599         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3600         if (ret)
3601                 return ret;
3602
3603         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3604         if (ret)
3605                 return ret;
3606
3607         spin_lock(&file_priv->mm.lock);
3608         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3609                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3610                         break;
3611
3612                 ring = request->ring;
3613                 seqno = request->seqno;
3614         }
3615         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3616         spin_unlock(&file_priv->mm.lock);
3617
3618         if (seqno == 0)
3619                 return 0;
3620
3621         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3622         if (ret == 0)
3623                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3624
3625         return ret;
3626 }
3627
3628 int
3629 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3630                     uint32_t alignment,
3631                     bool map_and_fenceable,
3632                     bool nonblocking)
3633 {
3634         int ret;
3635
3636         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3637                 return -EBUSY;
3638
3639         if (i915_gem_obj_ggtt_bound(obj)) {
3640                 if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) ||
3641                     (map_and_fenceable && !obj->map_and_fenceable)) {
3642                         WARN(obj->pin_count,
3643                              "bo is already pinned with incorrect alignment:"
3644                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3645                              " obj->map_and_fenceable=%d\n",
3646                              i915_gem_obj_ggtt_offset(obj), alignment,
3647                              map_and_fenceable,
3648                              obj->map_and_fenceable);
3649                         ret = i915_gem_object_unbind(obj);
3650                         if (ret)
3651                                 return ret;
3652                 }
3653         }
3654
3655         if (!i915_gem_obj_ggtt_bound(obj)) {
3656                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3657
3658                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3659                                                   map_and_fenceable,
3660                                                   nonblocking);
3661                 if (ret)
3662                         return ret;
3663
3664                 if (!dev_priv->mm.aliasing_ppgtt)
3665                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3666         }
3667
3668         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3669                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3670
3671         obj->pin_count++;
3672         obj->pin_mappable |= map_and_fenceable;
3673
3674         return 0;
3675 }
3676
3677 void
3678 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3679 {
3680         BUG_ON(obj->pin_count == 0);
3681         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3682
3683         if (--obj->pin_count == 0)
3684                 obj->pin_mappable = false;
3685 }
3686
3687 int
3688 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3689                    struct drm_file *file)
3690 {
3691         struct drm_i915_gem_pin *args = data;
3692         struct drm_i915_gem_object *obj;
3693         int ret;
3694
3695         ret = i915_mutex_lock_interruptible(dev);
3696         if (ret)
3697                 return ret;
3698
3699         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3700         if (&obj->base == NULL) {
3701                 ret = -ENOENT;
3702                 goto unlock;
3703         }
3704
3705         if (obj->madv != I915_MADV_WILLNEED) {
3706                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3707                 ret = -EINVAL;
3708                 goto out;
3709         }
3710
3711         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3712                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3713                           args->handle);
3714                 ret = -EINVAL;
3715                 goto out;
3716         }
3717
3718         if (obj->user_pin_count == 0) {
3719                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3720                 if (ret)
3721                         goto out;
3722         }
3723
3724         obj->user_pin_count++;
3725         obj->pin_filp = file;
3726
3727         /* XXX - flush the CPU caches for pinned objects
3728          * as the X server doesn't manage domains yet
3729          */
3730         i915_gem_object_flush_cpu_write_domain(obj);
3731         args->offset = i915_gem_obj_ggtt_offset(obj);
3732 out:
3733         drm_gem_object_unreference(&obj->base);
3734 unlock:
3735         mutex_unlock(&dev->struct_mutex);
3736         return ret;
3737 }
3738
3739 int
3740 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3741                      struct drm_file *file)
3742 {
3743         struct drm_i915_gem_pin *args = data;
3744         struct drm_i915_gem_object *obj;
3745         int ret;
3746
3747         ret = i915_mutex_lock_interruptible(dev);
3748         if (ret)
3749                 return ret;
3750
3751         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3752         if (&obj->base == NULL) {
3753                 ret = -ENOENT;
3754                 goto unlock;
3755         }
3756
3757         if (obj->pin_filp != file) {
3758                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3759                           args->handle);
3760                 ret = -EINVAL;
3761                 goto out;
3762         }
3763         obj->user_pin_count--;
3764         if (obj->user_pin_count == 0) {
3765                 obj->pin_filp = NULL;
3766                 i915_gem_object_unpin(obj);
3767         }
3768
3769 out:
3770         drm_gem_object_unreference(&obj->base);
3771 unlock:
3772         mutex_unlock(&dev->struct_mutex);
3773         return ret;
3774 }
3775
3776 int
3777 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3778                     struct drm_file *file)
3779 {
3780         struct drm_i915_gem_busy *args = data;
3781         struct drm_i915_gem_object *obj;
3782         int ret;
3783
3784         ret = i915_mutex_lock_interruptible(dev);
3785         if (ret)
3786                 return ret;
3787
3788         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3789         if (&obj->base == NULL) {
3790                 ret = -ENOENT;
3791                 goto unlock;
3792         }
3793
3794         /* Count all active objects as busy, even if they are currently not used
3795          * by the gpu. Users of this interface expect objects to eventually
3796          * become non-busy without any further actions, therefore emit any
3797          * necessary flushes here.
3798          */
3799         ret = i915_gem_object_flush_active(obj);
3800
3801         args->busy = obj->active;
3802         if (obj->ring) {
3803                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3804                 args->busy |= intel_ring_flag(obj->ring) << 16;
3805         }
3806
3807         drm_gem_object_unreference(&obj->base);
3808 unlock:
3809         mutex_unlock(&dev->struct_mutex);
3810         return ret;
3811 }
3812
3813 int
3814 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3815                         struct drm_file *file_priv)
3816 {
3817         return i915_gem_ring_throttle(dev, file_priv);
3818 }
3819
3820 int
3821 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3822                        struct drm_file *file_priv)
3823 {
3824         struct drm_i915_gem_madvise *args = data;
3825         struct drm_i915_gem_object *obj;
3826         int ret;
3827
3828         switch (args->madv) {
3829         case I915_MADV_DONTNEED:
3830         case I915_MADV_WILLNEED:
3831             break;
3832         default:
3833             return -EINVAL;
3834         }
3835
3836         ret = i915_mutex_lock_interruptible(dev);
3837         if (ret)
3838                 return ret;
3839
3840         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3841         if (&obj->base == NULL) {
3842                 ret = -ENOENT;
3843                 goto unlock;
3844         }
3845
3846         if (obj->pin_count) {
3847                 ret = -EINVAL;
3848                 goto out;
3849         }
3850
3851         if (obj->madv != __I915_MADV_PURGED)
3852                 obj->madv = args->madv;
3853
3854         /* if the object is no longer attached, discard its backing storage */
3855         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3856                 i915_gem_object_truncate(obj);
3857
3858         args->retained = obj->madv != __I915_MADV_PURGED;
3859
3860 out:
3861         drm_gem_object_unreference(&obj->base);
3862 unlock:
3863         mutex_unlock(&dev->struct_mutex);
3864         return ret;
3865 }
3866
3867 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3868                           const struct drm_i915_gem_object_ops *ops)
3869 {
3870         INIT_LIST_HEAD(&obj->mm_list);
3871         INIT_LIST_HEAD(&obj->global_list);
3872         INIT_LIST_HEAD(&obj->ring_list);
3873         INIT_LIST_HEAD(&obj->exec_list);
3874         INIT_LIST_HEAD(&obj->vma_list);
3875
3876         obj->ops = ops;
3877
3878         obj->fence_reg = I915_FENCE_REG_NONE;
3879         obj->madv = I915_MADV_WILLNEED;
3880         /* Avoid an unnecessary call to unbind on the first bind. */
3881         obj->map_and_fenceable = true;
3882
3883         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3884 }
3885
3886 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3887         .get_pages = i915_gem_object_get_pages_gtt,
3888         .put_pages = i915_gem_object_put_pages_gtt,
3889 };
3890
3891 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3892                                                   size_t size)
3893 {
3894         struct drm_i915_gem_object *obj;
3895         struct address_space *mapping;
3896         gfp_t mask;
3897
3898         obj = i915_gem_object_alloc(dev);
3899         if (obj == NULL)
3900                 return NULL;
3901
3902         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3903                 i915_gem_object_free(obj);
3904                 return NULL;
3905         }
3906
3907         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3908         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3909                 /* 965gm cannot relocate objects above 4GiB. */
3910                 mask &= ~__GFP_HIGHMEM;
3911                 mask |= __GFP_DMA32;
3912         }
3913
3914         mapping = file_inode(obj->base.filp)->i_mapping;
3915         mapping_set_gfp_mask(mapping, mask);
3916
3917         i915_gem_object_init(obj, &i915_gem_object_ops);
3918
3919         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3920         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3921
3922         if (HAS_LLC(dev)) {
3923                 /* On some devices, we can have the GPU use the LLC (the CPU
3924                  * cache) for about a 10% performance improvement
3925                  * compared to uncached.  Graphics requests other than
3926                  * display scanout are coherent with the CPU in
3927                  * accessing this cache.  This means in this mode we
3928                  * don't need to clflush on the CPU side, and on the
3929                  * GPU side we only need to flush internal caches to
3930                  * get data visible to the CPU.
3931                  *
3932                  * However, we maintain the display planes as UC, and so
3933                  * need to rebind when first used as such.
3934                  */
3935                 obj->cache_level = I915_CACHE_LLC;
3936         } else
3937                 obj->cache_level = I915_CACHE_NONE;
3938
3939         trace_i915_gem_object_create(obj);
3940
3941         return obj;
3942 }
3943
3944 int i915_gem_init_object(struct drm_gem_object *obj)
3945 {
3946         BUG();
3947
3948         return 0;
3949 }
3950
3951 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3952 {
3953         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3954         struct drm_device *dev = obj->base.dev;
3955         drm_i915_private_t *dev_priv = dev->dev_private;
3956
3957         trace_i915_gem_object_destroy(obj);
3958
3959         if (obj->phys_obj)
3960                 i915_gem_detach_phys_object(dev, obj);
3961
3962         obj->pin_count = 0;
3963         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3964                 bool was_interruptible;
3965
3966                 was_interruptible = dev_priv->mm.interruptible;
3967                 dev_priv->mm.interruptible = false;
3968
3969                 WARN_ON(i915_gem_object_unbind(obj));
3970
3971                 dev_priv->mm.interruptible = was_interruptible;
3972         }
3973
3974         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3975          * before progressing. */
3976         if (obj->stolen)
3977                 i915_gem_object_unpin_pages(obj);
3978
3979         if (WARN_ON(obj->pages_pin_count))
3980                 obj->pages_pin_count = 0;
3981         i915_gem_object_put_pages(obj);
3982         i915_gem_object_free_mmap_offset(obj);
3983         i915_gem_object_release_stolen(obj);
3984
3985         BUG_ON(obj->pages);
3986
3987         if (obj->base.import_attach)
3988                 drm_prime_gem_destroy(&obj->base, NULL);
3989
3990         drm_gem_object_release(&obj->base);
3991         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3992
3993         kfree(obj->bit_17);
3994         i915_gem_object_free(obj);
3995 }
3996
3997 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
3998                                      struct i915_address_space *vm)
3999 {
4000         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4001         if (vma == NULL)
4002                 return ERR_PTR(-ENOMEM);
4003
4004         INIT_LIST_HEAD(&vma->vma_link);
4005         vma->vm = vm;
4006         vma->obj = obj;
4007
4008         return vma;
4009 }
4010
4011 void i915_gem_vma_destroy(struct i915_vma *vma)
4012 {
4013         WARN_ON(vma->node.allocated);
4014         kfree(vma);
4015 }
4016
4017 int
4018 i915_gem_idle(struct drm_device *dev)
4019 {
4020         drm_i915_private_t *dev_priv = dev->dev_private;
4021         int ret;
4022
4023         if (dev_priv->ums.mm_suspended) {
4024                 mutex_unlock(&dev->struct_mutex);
4025                 return 0;
4026         }
4027
4028         ret = i915_gpu_idle(dev);
4029         if (ret) {
4030                 mutex_unlock(&dev->struct_mutex);
4031                 return ret;
4032         }
4033         i915_gem_retire_requests(dev);
4034
4035         /* Under UMS, be paranoid and evict. */
4036         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4037                 i915_gem_evict_everything(dev);
4038
4039         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4040
4041         i915_kernel_lost_context(dev);
4042         i915_gem_cleanup_ringbuffer(dev);
4043
4044         /* Cancel the retire work handler, which should be idle now. */
4045         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4046
4047         return 0;
4048 }
4049
4050 void i915_gem_l3_remap(struct drm_device *dev)
4051 {
4052         drm_i915_private_t *dev_priv = dev->dev_private;
4053         u32 misccpctl;
4054         int i;
4055
4056         if (!HAS_L3_GPU_CACHE(dev))
4057                 return;
4058
4059         if (!dev_priv->l3_parity.remap_info)
4060                 return;
4061
4062         misccpctl = I915_READ(GEN7_MISCCPCTL);
4063         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4064         POSTING_READ(GEN7_MISCCPCTL);
4065
4066         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4067                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4068                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4069                         DRM_DEBUG("0x%x was already programmed to %x\n",
4070                                   GEN7_L3LOG_BASE + i, remap);
4071                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4072                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
4073                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4074         }
4075
4076         /* Make sure all the writes land before disabling dop clock gating */
4077         POSTING_READ(GEN7_L3LOG_BASE);
4078
4079         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4080 }
4081
4082 void i915_gem_init_swizzling(struct drm_device *dev)
4083 {
4084         drm_i915_private_t *dev_priv = dev->dev_private;
4085
4086         if (INTEL_INFO(dev)->gen < 5 ||
4087             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4088                 return;
4089
4090         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4091                                  DISP_TILE_SURFACE_SWIZZLING);
4092
4093         if (IS_GEN5(dev))
4094                 return;
4095
4096         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4097         if (IS_GEN6(dev))
4098                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4099         else if (IS_GEN7(dev))
4100                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4101         else
4102                 BUG();
4103 }
4104
4105 static bool
4106 intel_enable_blt(struct drm_device *dev)
4107 {
4108         if (!HAS_BLT(dev))
4109                 return false;
4110
4111         /* The blitter was dysfunctional on early prototypes */
4112         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4113                 DRM_INFO("BLT not supported on this pre-production hardware;"
4114                          " graphics performance will be degraded.\n");
4115                 return false;
4116         }
4117
4118         return true;
4119 }
4120
4121 static int i915_gem_init_rings(struct drm_device *dev)
4122 {
4123         struct drm_i915_private *dev_priv = dev->dev_private;
4124         int ret;
4125
4126         ret = intel_init_render_ring_buffer(dev);
4127         if (ret)
4128                 return ret;
4129
4130         if (HAS_BSD(dev)) {
4131                 ret = intel_init_bsd_ring_buffer(dev);
4132                 if (ret)
4133                         goto cleanup_render_ring;
4134         }
4135
4136         if (intel_enable_blt(dev)) {
4137                 ret = intel_init_blt_ring_buffer(dev);
4138                 if (ret)
4139                         goto cleanup_bsd_ring;
4140         }
4141
4142         if (HAS_VEBOX(dev)) {
4143                 ret = intel_init_vebox_ring_buffer(dev);
4144                 if (ret)
4145                         goto cleanup_blt_ring;
4146         }
4147
4148
4149         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4150         if (ret)
4151                 goto cleanup_vebox_ring;
4152
4153         return 0;
4154
4155 cleanup_vebox_ring:
4156         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4157 cleanup_blt_ring:
4158         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4159 cleanup_bsd_ring:
4160         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4161 cleanup_render_ring:
4162         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4163
4164         return ret;
4165 }
4166
4167 int
4168 i915_gem_init_hw(struct drm_device *dev)
4169 {
4170         drm_i915_private_t *dev_priv = dev->dev_private;
4171         int ret;
4172
4173         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4174                 return -EIO;
4175
4176         if (dev_priv->ellc_size)
4177                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4178
4179         if (HAS_PCH_NOP(dev)) {
4180                 u32 temp = I915_READ(GEN7_MSG_CTL);
4181                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4182                 I915_WRITE(GEN7_MSG_CTL, temp);
4183         }
4184
4185         i915_gem_l3_remap(dev);
4186
4187         i915_gem_init_swizzling(dev);
4188
4189         ret = i915_gem_init_rings(dev);
4190         if (ret)
4191                 return ret;
4192
4193         /*
4194          * XXX: There was some w/a described somewhere suggesting loading
4195          * contexts before PPGTT.
4196          */
4197         i915_gem_context_init(dev);
4198         if (dev_priv->mm.aliasing_ppgtt) {
4199                 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4200                 if (ret) {
4201                         i915_gem_cleanup_aliasing_ppgtt(dev);
4202                         DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4203                 }
4204         }
4205
4206         return 0;
4207 }
4208
4209 int i915_gem_init(struct drm_device *dev)
4210 {
4211         struct drm_i915_private *dev_priv = dev->dev_private;
4212         int ret;
4213
4214         mutex_lock(&dev->struct_mutex);
4215
4216         if (IS_VALLEYVIEW(dev)) {
4217                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4218                 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4219                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4220                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4221         }
4222
4223         i915_gem_init_global_gtt(dev);
4224
4225         ret = i915_gem_init_hw(dev);
4226         mutex_unlock(&dev->struct_mutex);
4227         if (ret) {
4228                 i915_gem_cleanup_aliasing_ppgtt(dev);
4229                 return ret;
4230         }
4231
4232         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4233         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4234                 dev_priv->dri1.allow_batchbuffer = 1;
4235         return 0;
4236 }
4237
4238 void
4239 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4240 {
4241         drm_i915_private_t *dev_priv = dev->dev_private;
4242         struct intel_ring_buffer *ring;
4243         int i;
4244
4245         for_each_ring(ring, dev_priv, i)
4246                 intel_cleanup_ring_buffer(ring);
4247 }
4248
4249 int
4250 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4251                        struct drm_file *file_priv)
4252 {
4253         struct drm_i915_private *dev_priv = dev->dev_private;
4254         int ret;
4255
4256         if (drm_core_check_feature(dev, DRIVER_MODESET))
4257                 return 0;
4258
4259         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4260                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4261                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4262         }
4263
4264         mutex_lock(&dev->struct_mutex);
4265         dev_priv->ums.mm_suspended = 0;
4266
4267         ret = i915_gem_init_hw(dev);
4268         if (ret != 0) {
4269                 mutex_unlock(&dev->struct_mutex);
4270                 return ret;
4271         }
4272
4273         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4274         mutex_unlock(&dev->struct_mutex);
4275
4276         ret = drm_irq_install(dev);
4277         if (ret)
4278                 goto cleanup_ringbuffer;
4279
4280         return 0;
4281
4282 cleanup_ringbuffer:
4283         mutex_lock(&dev->struct_mutex);
4284         i915_gem_cleanup_ringbuffer(dev);
4285         dev_priv->ums.mm_suspended = 1;
4286         mutex_unlock(&dev->struct_mutex);
4287
4288         return ret;
4289 }
4290
4291 int
4292 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4293                        struct drm_file *file_priv)
4294 {
4295         struct drm_i915_private *dev_priv = dev->dev_private;
4296         int ret;
4297
4298         if (drm_core_check_feature(dev, DRIVER_MODESET))
4299                 return 0;
4300
4301         drm_irq_uninstall(dev);
4302
4303         mutex_lock(&dev->struct_mutex);
4304         ret =  i915_gem_idle(dev);
4305
4306         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4307          * We need to replace this with a semaphore, or something.
4308          * And not confound ums.mm_suspended!
4309          */
4310         if (ret != 0)
4311                 dev_priv->ums.mm_suspended = 1;
4312         mutex_unlock(&dev->struct_mutex);
4313
4314         return ret;
4315 }
4316
4317 void
4318 i915_gem_lastclose(struct drm_device *dev)
4319 {
4320         int ret;
4321
4322         if (drm_core_check_feature(dev, DRIVER_MODESET))
4323                 return;
4324
4325         mutex_lock(&dev->struct_mutex);
4326         ret = i915_gem_idle(dev);
4327         if (ret)
4328                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4329         mutex_unlock(&dev->struct_mutex);
4330 }
4331
4332 static void
4333 init_ring_lists(struct intel_ring_buffer *ring)
4334 {
4335         INIT_LIST_HEAD(&ring->active_list);
4336         INIT_LIST_HEAD(&ring->request_list);
4337 }
4338
4339 void
4340 i915_gem_load(struct drm_device *dev)
4341 {
4342         drm_i915_private_t *dev_priv = dev->dev_private;
4343         int i;
4344
4345         dev_priv->slab =
4346                 kmem_cache_create("i915_gem_object",
4347                                   sizeof(struct drm_i915_gem_object), 0,
4348                                   SLAB_HWCACHE_ALIGN,
4349                                   NULL);
4350
4351         INIT_LIST_HEAD(&dev_priv->gtt.base.active_list);
4352         INIT_LIST_HEAD(&dev_priv->gtt.base.inactive_list);
4353         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4354         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4355         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4356         for (i = 0; i < I915_NUM_RINGS; i++)
4357                 init_ring_lists(&dev_priv->ring[i]);
4358         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4359                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4360         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4361                           i915_gem_retire_work_handler);
4362         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4363
4364         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4365         if (IS_GEN3(dev)) {
4366                 I915_WRITE(MI_ARB_STATE,
4367                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4368         }
4369
4370         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4371
4372         /* Old X drivers will take 0-2 for front, back, depth buffers */
4373         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4374                 dev_priv->fence_reg_start = 3;
4375
4376         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4377                 dev_priv->num_fence_regs = 32;
4378         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4379                 dev_priv->num_fence_regs = 16;
4380         else
4381                 dev_priv->num_fence_regs = 8;
4382
4383         /* Initialize fence registers to zero */
4384         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4385         i915_gem_restore_fences(dev);
4386
4387         i915_gem_detect_bit_6_swizzle(dev);
4388         init_waitqueue_head(&dev_priv->pending_flip_queue);
4389
4390         dev_priv->mm.interruptible = true;
4391
4392         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4393         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4394         register_shrinker(&dev_priv->mm.inactive_shrinker);
4395 }
4396
4397 /*
4398  * Create a physically contiguous memory object for this object
4399  * e.g. for cursor + overlay regs
4400  */
4401 static int i915_gem_init_phys_object(struct drm_device *dev,
4402                                      int id, int size, int align)
4403 {
4404         drm_i915_private_t *dev_priv = dev->dev_private;
4405         struct drm_i915_gem_phys_object *phys_obj;
4406         int ret;
4407
4408         if (dev_priv->mm.phys_objs[id - 1] || !size)
4409                 return 0;
4410
4411         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4412         if (!phys_obj)
4413                 return -ENOMEM;
4414
4415         phys_obj->id = id;
4416
4417         phys_obj->handle = drm_pci_alloc(dev, size, align);
4418         if (!phys_obj->handle) {
4419                 ret = -ENOMEM;
4420                 goto kfree_obj;
4421         }
4422 #ifdef CONFIG_X86
4423         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4424 #endif
4425
4426         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4427
4428         return 0;
4429 kfree_obj:
4430         kfree(phys_obj);
4431         return ret;
4432 }
4433
4434 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4435 {
4436         drm_i915_private_t *dev_priv = dev->dev_private;
4437         struct drm_i915_gem_phys_object *phys_obj;
4438
4439         if (!dev_priv->mm.phys_objs[id - 1])
4440                 return;
4441
4442         phys_obj = dev_priv->mm.phys_objs[id - 1];
4443         if (phys_obj->cur_obj) {
4444                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4445         }
4446
4447 #ifdef CONFIG_X86
4448         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4449 #endif
4450         drm_pci_free(dev, phys_obj->handle);
4451         kfree(phys_obj);
4452         dev_priv->mm.phys_objs[id - 1] = NULL;
4453 }
4454
4455 void i915_gem_free_all_phys_object(struct drm_device *dev)
4456 {
4457         int i;
4458
4459         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4460                 i915_gem_free_phys_object(dev, i);
4461 }
4462
4463 void i915_gem_detach_phys_object(struct drm_device *dev,
4464                                  struct drm_i915_gem_object *obj)
4465 {
4466         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4467         char *vaddr;
4468         int i;
4469         int page_count;
4470
4471         if (!obj->phys_obj)
4472                 return;
4473         vaddr = obj->phys_obj->handle->vaddr;
4474
4475         page_count = obj->base.size / PAGE_SIZE;
4476         for (i = 0; i < page_count; i++) {
4477                 struct page *page = shmem_read_mapping_page(mapping, i);
4478                 if (!IS_ERR(page)) {
4479                         char *dst = kmap_atomic(page);
4480                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4481                         kunmap_atomic(dst);
4482
4483                         drm_clflush_pages(&page, 1);
4484
4485                         set_page_dirty(page);
4486                         mark_page_accessed(page);
4487                         page_cache_release(page);
4488                 }
4489         }
4490         i915_gem_chipset_flush(dev);
4491
4492         obj->phys_obj->cur_obj = NULL;
4493         obj->phys_obj = NULL;
4494 }
4495
4496 int
4497 i915_gem_attach_phys_object(struct drm_device *dev,
4498                             struct drm_i915_gem_object *obj,
4499                             int id,
4500                             int align)
4501 {
4502         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4503         drm_i915_private_t *dev_priv = dev->dev_private;
4504         int ret = 0;
4505         int page_count;
4506         int i;
4507
4508         if (id > I915_MAX_PHYS_OBJECT)
4509                 return -EINVAL;
4510
4511         if (obj->phys_obj) {
4512                 if (obj->phys_obj->id == id)
4513                         return 0;
4514                 i915_gem_detach_phys_object(dev, obj);
4515         }
4516
4517         /* create a new object */
4518         if (!dev_priv->mm.phys_objs[id - 1]) {
4519                 ret = i915_gem_init_phys_object(dev, id,
4520                                                 obj->base.size, align);
4521                 if (ret) {
4522                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4523                                   id, obj->base.size);
4524                         return ret;
4525                 }
4526         }
4527
4528         /* bind to the object */
4529         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4530         obj->phys_obj->cur_obj = obj;
4531
4532         page_count = obj->base.size / PAGE_SIZE;
4533
4534         for (i = 0; i < page_count; i++) {
4535                 struct page *page;
4536                 char *dst, *src;
4537
4538                 page = shmem_read_mapping_page(mapping, i);
4539                 if (IS_ERR(page))
4540                         return PTR_ERR(page);
4541
4542                 src = kmap_atomic(page);
4543                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4544                 memcpy(dst, src, PAGE_SIZE);
4545                 kunmap_atomic(src);
4546
4547                 mark_page_accessed(page);
4548                 page_cache_release(page);
4549         }
4550
4551         return 0;
4552 }
4553
4554 static int
4555 i915_gem_phys_pwrite(struct drm_device *dev,
4556                      struct drm_i915_gem_object *obj,
4557                      struct drm_i915_gem_pwrite *args,
4558                      struct drm_file *file_priv)
4559 {
4560         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4561         char __user *user_data = to_user_ptr(args->data_ptr);
4562
4563         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4564                 unsigned long unwritten;
4565
4566                 /* The physical object once assigned is fixed for the lifetime
4567                  * of the obj, so we can safely drop the lock and continue
4568                  * to access vaddr.
4569                  */
4570                 mutex_unlock(&dev->struct_mutex);
4571                 unwritten = copy_from_user(vaddr, user_data, args->size);
4572                 mutex_lock(&dev->struct_mutex);
4573                 if (unwritten)
4574                         return -EFAULT;
4575         }
4576
4577         i915_gem_chipset_flush(dev);
4578         return 0;
4579 }
4580
4581 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4582 {
4583         struct drm_i915_file_private *file_priv = file->driver_priv;
4584
4585         /* Clean up our request list when the client is going away, so that
4586          * later retire_requests won't dereference our soon-to-be-gone
4587          * file_priv.
4588          */
4589         spin_lock(&file_priv->mm.lock);
4590         while (!list_empty(&file_priv->mm.request_list)) {
4591                 struct drm_i915_gem_request *request;
4592
4593                 request = list_first_entry(&file_priv->mm.request_list,
4594                                            struct drm_i915_gem_request,
4595                                            client_list);
4596                 list_del(&request->client_list);
4597                 request->file_priv = NULL;
4598         }
4599         spin_unlock(&file_priv->mm.lock);
4600 }
4601
4602 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4603 {
4604         if (!mutex_is_locked(mutex))
4605                 return false;
4606
4607 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4608         return mutex->owner == task;
4609 #else
4610         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4611         return false;
4612 #endif
4613 }
4614
4615 static int
4616 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4617 {
4618         struct drm_i915_private *dev_priv =
4619                 container_of(shrinker,
4620                              struct drm_i915_private,
4621                              mm.inactive_shrinker);
4622         struct drm_device *dev = dev_priv->dev;
4623         struct i915_address_space *vm = &dev_priv->gtt.base;
4624         struct drm_i915_gem_object *obj;
4625         int nr_to_scan = sc->nr_to_scan;
4626         bool unlock = true;
4627         int cnt;
4628
4629         if (!mutex_trylock(&dev->struct_mutex)) {
4630                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4631                         return 0;
4632
4633                 if (dev_priv->mm.shrinker_no_lock_stealing)
4634                         return 0;
4635
4636                 unlock = false;
4637         }
4638
4639         if (nr_to_scan) {
4640                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4641                 if (nr_to_scan > 0)
4642                         nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4643                                                         false);
4644                 if (nr_to_scan > 0)
4645                         i915_gem_shrink_all(dev_priv);
4646         }
4647
4648         cnt = 0;
4649         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4650                 if (obj->pages_pin_count == 0)
4651                         cnt += obj->base.size >> PAGE_SHIFT;
4652         list_for_each_entry(obj, &vm->inactive_list, mm_list)
4653                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4654                         cnt += obj->base.size >> PAGE_SHIFT;
4655
4656         if (unlock)
4657                 mutex_unlock(&dev->struct_mutex);
4658         return cnt;
4659 }