2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
88 #include <linux/log2.h>
90 #include <drm/i915_drm.h>
92 #include "i915_trace.h"
94 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
96 /* Initial size (as log2) to preallocate the handle->object hashtable */
97 #define VMA_HT_BITS 2u /* 4 x 2 pointers, 64 bytes minimum */
99 static void resize_vma_ht(struct work_struct *work)
101 struct i915_gem_context_vma_lut *lut =
102 container_of(work, typeof(*lut), resize);
103 unsigned int bits, new_bits, size, i;
104 struct hlist_head *new_ht;
106 GEM_BUG_ON(!(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS));
108 bits = 1 + ilog2(4*lut->ht_count/3 + 1);
109 new_bits = min_t(unsigned int,
110 max(bits, VMA_HT_BITS),
111 sizeof(unsigned int) * BITS_PER_BYTE - 1);
112 if (new_bits == lut->ht_bits)
115 new_ht = kzalloc(sizeof(*new_ht)<<new_bits, GFP_KERNEL | __GFP_NOWARN);
117 new_ht = vzalloc(sizeof(*new_ht)<<new_bits);
119 /* Pretend resize succeeded and stop calling us for a bit! */
122 size = BIT(lut->ht_bits);
123 for (i = 0; i < size; i++) {
124 struct i915_vma *vma;
125 struct hlist_node *tmp;
127 hlist_for_each_entry_safe(vma, tmp, &lut->ht[i], ctx_node)
128 hlist_add_head(&vma->ctx_node,
129 &new_ht[hash_32(vma->ctx_handle,
134 lut->ht_bits = new_bits;
136 smp_store_release(&lut->ht_size, BIT(bits));
137 GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS);
140 static void vma_lut_free(struct i915_gem_context *ctx)
142 struct i915_gem_context_vma_lut *lut = &ctx->vma_lut;
143 unsigned int i, size;
145 if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)
146 cancel_work_sync(&lut->resize);
148 size = BIT(lut->ht_bits);
149 for (i = 0; i < size; i++) {
150 struct i915_vma *vma;
152 hlist_for_each_entry(vma, &lut->ht[i], ctx_node) {
153 vma->obj->vma_hashed = NULL;
160 void i915_gem_context_free(struct kref *ctx_ref)
162 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
165 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
166 trace_i915_context_free(ctx);
167 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
170 i915_ppgtt_put(ctx->ppgtt);
172 for (i = 0; i < I915_NUM_ENGINES; i++) {
173 struct intel_context *ce = &ctx->engine[i];
178 WARN_ON(ce->pin_count);
180 intel_ring_free(ce->ring);
182 __i915_gem_object_release_unless_active(ce->state->obj);
188 list_del(&ctx->link);
190 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
194 static void context_close(struct i915_gem_context *ctx)
196 i915_gem_context_set_closed(ctx);
198 i915_ppgtt_close(&ctx->ppgtt->base);
199 ctx->file_priv = ERR_PTR(-EBADF);
200 i915_gem_context_put(ctx);
203 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
207 ret = ida_simple_get(&dev_priv->context_hw_ida,
208 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
210 /* Contexts are only released when no longer active.
211 * Flush any pending retires to hopefully release some
212 * stale contexts and try again.
214 i915_gem_retire_requests(dev_priv);
215 ret = ida_simple_get(&dev_priv->context_hw_ida,
216 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
225 static u32 default_desc_template(const struct drm_i915_private *i915,
226 const struct i915_hw_ppgtt *ppgtt)
231 desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
233 address_mode = INTEL_LEGACY_32B_CONTEXT;
234 if (ppgtt && i915_vm_is_48bit(&ppgtt->base))
235 address_mode = INTEL_LEGACY_64B_CONTEXT;
236 desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
239 desc |= GEN8_CTX_L3LLC_COHERENT;
241 /* TODO: WaDisableLiteRestore when we start using semaphore
242 * signalling between Command Streamers
243 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
249 static struct i915_gem_context *
250 __create_hw_context(struct drm_i915_private *dev_priv,
251 struct drm_i915_file_private *file_priv)
253 struct i915_gem_context *ctx;
256 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
258 return ERR_PTR(-ENOMEM);
260 ret = assign_hw_id(dev_priv, &ctx->hw_id);
266 kref_init(&ctx->ref);
267 list_add_tail(&ctx->link, &dev_priv->context_list);
268 ctx->i915 = dev_priv;
269 ctx->priority = I915_PRIORITY_NORMAL;
271 ctx->vma_lut.ht_bits = VMA_HT_BITS;
272 ctx->vma_lut.ht_size = BIT(VMA_HT_BITS);
273 BUILD_BUG_ON(BIT(VMA_HT_BITS) == I915_CTX_RESIZE_IN_PROGRESS);
274 ctx->vma_lut.ht = kcalloc(ctx->vma_lut.ht_size,
275 sizeof(*ctx->vma_lut.ht),
277 if (!ctx->vma_lut.ht)
280 INIT_WORK(&ctx->vma_lut.resize, resize_vma_ht);
282 /* Default context will never have a file_priv */
283 ret = DEFAULT_CONTEXT_HANDLE;
285 ret = idr_alloc(&file_priv->context_idr, ctx,
286 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
290 ctx->user_handle = ret;
292 ctx->file_priv = file_priv;
294 ctx->pid = get_task_pid(current, PIDTYPE_PID);
295 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
305 /* NB: Mark all slices as needing a remap so that when the context first
306 * loads it will restore whatever remap state already exists. If there
307 * is no remap info, it will be a NOP. */
308 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
310 i915_gem_context_set_bannable(ctx);
311 ctx->ring_size = 4 * PAGE_SIZE;
313 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
315 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
316 * present or not in use we still need a small bias as ring wraparound
317 * at offset 0 sometimes hangs. No idea why.
319 if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
320 ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
322 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
328 idr_remove(&file_priv->context_idr, ctx->user_handle);
330 kvfree(ctx->vma_lut.ht);
336 static void __destroy_hw_context(struct i915_gem_context *ctx,
337 struct drm_i915_file_private *file_priv)
339 idr_remove(&file_priv->context_idr, ctx->user_handle);
344 * The default context needs to exist per ring that uses contexts. It stores the
345 * context state of the GPU for applications that don't utilize HW contexts, as
346 * well as an idle case.
348 static struct i915_gem_context *
349 i915_gem_create_context(struct drm_i915_private *dev_priv,
350 struct drm_i915_file_private *file_priv)
352 struct i915_gem_context *ctx;
354 lockdep_assert_held(&dev_priv->drm.struct_mutex);
356 ctx = __create_hw_context(dev_priv, file_priv);
360 if (USES_FULL_PPGTT(dev_priv)) {
361 struct i915_hw_ppgtt *ppgtt;
363 ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name);
365 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
367 __destroy_hw_context(ctx, file_priv);
368 return ERR_CAST(ppgtt);
372 ctx->desc_template = default_desc_template(dev_priv, ppgtt);
375 trace_i915_context_create(ctx);
381 * i915_gem_context_create_gvt - create a GVT GEM context
384 * This function is used to create a GVT specific GEM context.
387 * pointer to i915_gem_context on success, error pointer if failed
390 struct i915_gem_context *
391 i915_gem_context_create_gvt(struct drm_device *dev)
393 struct i915_gem_context *ctx;
396 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
397 return ERR_PTR(-ENODEV);
399 ret = i915_mutex_lock_interruptible(dev);
403 ctx = __create_hw_context(to_i915(dev), NULL);
407 ctx->file_priv = ERR_PTR(-EBADF);
408 i915_gem_context_set_closed(ctx); /* not user accessible */
409 i915_gem_context_clear_bannable(ctx);
410 i915_gem_context_set_force_single_submission(ctx);
411 if (!i915.enable_guc_submission)
412 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
414 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
416 mutex_unlock(&dev->struct_mutex);
420 int i915_gem_context_init(struct drm_i915_private *dev_priv)
422 struct i915_gem_context *ctx;
424 /* Init should only be called once per module load. Eventually the
425 * restriction on the context_disabled check can be loosened. */
426 if (WARN_ON(dev_priv->kernel_context))
429 if (intel_vgpu_active(dev_priv) &&
430 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
431 if (!i915.enable_execlists) {
432 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
437 /* Using the simple ida interface, the max is limited by sizeof(int) */
438 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
439 ida_init(&dev_priv->context_hw_ida);
441 ctx = i915_gem_create_context(dev_priv, NULL);
443 DRM_ERROR("Failed to create default global context (error %ld)\n",
448 /* For easy recognisablity, we want the kernel context to be 0 and then
449 * all user contexts will have non-zero hw_id.
451 GEM_BUG_ON(ctx->hw_id);
453 i915_gem_context_clear_bannable(ctx);
454 ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
455 dev_priv->kernel_context = ctx;
457 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
459 DRM_DEBUG_DRIVER("%s context support initialized\n",
460 dev_priv->engine[RCS]->context_size ? "logical" :
465 void i915_gem_context_lost(struct drm_i915_private *dev_priv)
467 struct intel_engine_cs *engine;
468 enum intel_engine_id id;
470 lockdep_assert_held(&dev_priv->drm.struct_mutex);
472 for_each_engine(engine, dev_priv, id) {
473 engine->legacy_active_context = NULL;
475 if (!engine->last_retired_context)
478 engine->context_unpin(engine, engine->last_retired_context);
479 engine->last_retired_context = NULL;
482 /* Force the GPU state to be restored on enabling */
483 if (!i915.enable_execlists) {
484 struct i915_gem_context *ctx;
486 list_for_each_entry(ctx, &dev_priv->context_list, link) {
487 if (!i915_gem_context_is_default(ctx))
490 for_each_engine(engine, dev_priv, id)
491 ctx->engine[engine->id].initialised = false;
493 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
496 for_each_engine(engine, dev_priv, id) {
497 struct intel_context *kce =
498 &dev_priv->kernel_context->engine[engine->id];
500 kce->initialised = true;
505 void i915_gem_context_fini(struct drm_i915_private *dev_priv)
507 struct i915_gem_context *dctx = dev_priv->kernel_context;
509 lockdep_assert_held(&dev_priv->drm.struct_mutex);
511 GEM_BUG_ON(!i915_gem_context_is_kernel(dctx));
514 dev_priv->kernel_context = NULL;
516 ida_destroy(&dev_priv->context_hw_ida);
519 static int context_idr_cleanup(int id, void *p, void *data)
521 struct i915_gem_context *ctx = p;
527 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
529 struct drm_i915_file_private *file_priv = file->driver_priv;
530 struct i915_gem_context *ctx;
532 idr_init(&file_priv->context_idr);
534 mutex_lock(&dev->struct_mutex);
535 ctx = i915_gem_create_context(to_i915(dev), file_priv);
536 mutex_unlock(&dev->struct_mutex);
538 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
541 idr_destroy(&file_priv->context_idr);
548 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
550 struct drm_i915_file_private *file_priv = file->driver_priv;
552 lockdep_assert_held(&dev->struct_mutex);
554 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
555 idr_destroy(&file_priv->context_idr);
559 mi_set_context(struct drm_i915_gem_request *req, u32 flags)
561 struct drm_i915_private *dev_priv = req->i915;
562 struct intel_engine_cs *engine = req->engine;
563 enum intel_engine_id id;
564 const int num_rings =
565 /* Use an extended w/a on gen7 if signalling from other rings */
566 (i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
567 INTEL_INFO(dev_priv)->num_rings - 1 :
572 flags |= MI_MM_SPACE_GTT;
573 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
574 /* These flags are for resource streamer on HSW+ */
575 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
577 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
580 if (INTEL_GEN(dev_priv) >= 7)
581 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
583 cs = intel_ring_begin(req, len);
587 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
588 if (INTEL_GEN(dev_priv) >= 7) {
589 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
591 struct intel_engine_cs *signaller;
593 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
594 for_each_engine(signaller, dev_priv, id) {
595 if (signaller == engine)
598 *cs++ = i915_mmio_reg_offset(
599 RING_PSMI_CTL(signaller->mmio_base));
600 *cs++ = _MASKED_BIT_ENABLE(
601 GEN6_PSMI_SLEEP_MSG_DISABLE);
607 *cs++ = MI_SET_CONTEXT;
608 *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
610 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
611 * WaMiSetContext_Hang:snb,ivb,vlv
615 if (INTEL_GEN(dev_priv) >= 7) {
617 struct intel_engine_cs *signaller;
618 i915_reg_t last_reg = {}; /* keep gcc quiet */
620 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
621 for_each_engine(signaller, dev_priv, id) {
622 if (signaller == engine)
625 last_reg = RING_PSMI_CTL(signaller->mmio_base);
626 *cs++ = i915_mmio_reg_offset(last_reg);
627 *cs++ = _MASKED_BIT_DISABLE(
628 GEN6_PSMI_SLEEP_MSG_DISABLE);
631 /* Insert a delay before the next switch! */
632 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
633 *cs++ = i915_mmio_reg_offset(last_reg);
634 *cs++ = i915_ggtt_offset(engine->scratch);
637 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
640 intel_ring_advance(req, cs);
645 static int remap_l3(struct drm_i915_gem_request *req, int slice)
647 u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
653 cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
658 * Note: We do not worry about the concurrent register cacheline hang
659 * here because no other code should access these registers other than
660 * at initialization time.
662 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
663 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
664 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
665 *cs++ = remap_info[i];
668 intel_ring_advance(req, cs);
673 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
674 struct intel_engine_cs *engine,
675 struct i915_gem_context *to)
680 if (!to->engine[RCS].initialised)
683 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
686 return to == engine->legacy_active_context;
690 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
691 struct intel_engine_cs *engine,
692 struct i915_gem_context *to)
697 /* Always load the ppgtt on first use */
698 if (!engine->legacy_active_context)
701 /* Same context without new entries, skip */
702 if (engine->legacy_active_context == to &&
703 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
706 if (engine->id != RCS)
709 if (INTEL_GEN(engine->i915) < 8)
716 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
717 struct i915_gem_context *to,
723 if (!IS_GEN8(to->i915))
726 if (hw_flags & MI_RESTORE_INHIBIT)
732 static int do_rcs_switch(struct drm_i915_gem_request *req)
734 struct i915_gem_context *to = req->ctx;
735 struct intel_engine_cs *engine = req->engine;
736 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
737 struct i915_gem_context *from = engine->legacy_active_context;
741 GEM_BUG_ON(engine->id != RCS);
743 if (skip_rcs_switch(ppgtt, engine, to))
746 if (needs_pd_load_pre(ppgtt, engine, to)) {
747 /* Older GENs and non render rings still want the load first,
748 * "PP_DCLV followed by PP_DIR_BASE register through Load
749 * Register Immediate commands in Ring Buffer before submitting
751 trace_switch_mm(engine, to);
752 ret = ppgtt->switch_mm(ppgtt, req);
757 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
758 /* NB: If we inhibit the restore, the context is not allowed to
759 * die because future work may end up depending on valid address
760 * space. This means we must enforce that a page table load
761 * occur when this occurs. */
762 hw_flags = MI_RESTORE_INHIBIT;
763 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
764 hw_flags = MI_FORCE_RESTORE;
768 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
769 ret = mi_set_context(req, hw_flags);
773 engine->legacy_active_context = to;
776 /* GEN8 does *not* require an explicit reload if the PDPs have been
777 * setup, and we do not wish to move them.
779 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
780 trace_switch_mm(engine, to);
781 ret = ppgtt->switch_mm(ppgtt, req);
782 /* The hardware context switch is emitted, but we haven't
783 * actually changed the state - so it's probably safe to bail
784 * here. Still, let the user know something dangerous has
792 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
794 for (i = 0; i < MAX_L3_SLICES; i++) {
795 if (!(to->remap_slice & (1<<i)))
798 ret = remap_l3(req, i);
802 to->remap_slice &= ~(1<<i);
805 if (!to->engine[RCS].initialised) {
806 if (engine->init_context) {
807 ret = engine->init_context(req);
811 to->engine[RCS].initialised = true;
818 * i915_switch_context() - perform a GPU context switch.
819 * @req: request for which we'll execute the context switch
821 * The context life cycle is simple. The context refcount is incremented and
822 * decremented by 1 and create and destroy. If the context is in use by the GPU,
823 * it will have a refcount > 1. This allows us to destroy the context abstract
824 * object while letting the normal object tracking destroy the backing BO.
826 * This function should not be used in execlists mode. Instead the context is
827 * switched by writing to the ELSP and requests keep a reference to their
830 int i915_switch_context(struct drm_i915_gem_request *req)
832 struct intel_engine_cs *engine = req->engine;
834 lockdep_assert_held(&req->i915->drm.struct_mutex);
835 if (i915.enable_execlists)
838 if (!req->ctx->engine[engine->id].state) {
839 struct i915_gem_context *to = req->ctx;
840 struct i915_hw_ppgtt *ppgtt =
841 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
843 if (needs_pd_load_pre(ppgtt, engine, to)) {
846 trace_switch_mm(engine, to);
847 ret = ppgtt->switch_mm(ppgtt, req);
851 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
857 return do_rcs_switch(req);
860 static bool engine_has_kernel_context(struct intel_engine_cs *engine)
862 struct i915_gem_timeline *timeline;
864 list_for_each_entry(timeline, &engine->i915->gt.timelines, link) {
865 struct intel_timeline *tl;
867 if (timeline == &engine->i915->gt.global_timeline)
870 tl = &timeline->engine[engine->id];
871 if (i915_gem_active_peek(&tl->last_request,
872 &engine->i915->drm.struct_mutex))
876 return (!engine->last_retired_context ||
877 i915_gem_context_is_kernel(engine->last_retired_context));
880 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
882 struct intel_engine_cs *engine;
883 struct i915_gem_timeline *timeline;
884 enum intel_engine_id id;
886 lockdep_assert_held(&dev_priv->drm.struct_mutex);
888 i915_gem_retire_requests(dev_priv);
890 for_each_engine(engine, dev_priv, id) {
891 struct drm_i915_gem_request *req;
894 if (engine_has_kernel_context(engine))
897 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
901 /* Queue this switch after all other activity */
902 list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
903 struct drm_i915_gem_request *prev;
904 struct intel_timeline *tl;
906 tl = &timeline->engine[engine->id];
907 prev = i915_gem_active_raw(&tl->last_request,
908 &dev_priv->drm.struct_mutex);
910 i915_sw_fence_await_sw_fence_gfp(&req->submit,
915 ret = i915_switch_context(req);
916 i915_add_request(req);
924 static bool client_is_banned(struct drm_i915_file_private *file_priv)
926 return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS;
929 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
930 struct drm_file *file)
932 struct drm_i915_private *dev_priv = to_i915(dev);
933 struct drm_i915_gem_context_create *args = data;
934 struct drm_i915_file_private *file_priv = file->driver_priv;
935 struct i915_gem_context *ctx;
938 if (!dev_priv->engine[RCS]->context_size)
944 if (client_is_banned(file_priv)) {
945 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
947 pid_nr(get_task_pid(current, PIDTYPE_PID)));
952 ret = i915_mutex_lock_interruptible(dev);
956 ctx = i915_gem_create_context(dev_priv, file_priv);
957 mutex_unlock(&dev->struct_mutex);
961 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
963 args->ctx_id = ctx->user_handle;
964 DRM_DEBUG("HW context %d created\n", args->ctx_id);
969 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
970 struct drm_file *file)
972 struct drm_i915_gem_context_destroy *args = data;
973 struct drm_i915_file_private *file_priv = file->driver_priv;
974 struct i915_gem_context *ctx;
980 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
983 ret = i915_mutex_lock_interruptible(dev);
987 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
989 mutex_unlock(&dev->struct_mutex);
993 __destroy_hw_context(ctx, file_priv);
994 mutex_unlock(&dev->struct_mutex);
996 DRM_DEBUG("HW context %d destroyed\n", args->ctx_id);
1000 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1001 struct drm_file *file)
1003 struct drm_i915_file_private *file_priv = file->driver_priv;
1004 struct drm_i915_gem_context_param *args = data;
1005 struct i915_gem_context *ctx;
1008 ret = i915_mutex_lock_interruptible(dev);
1012 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1014 mutex_unlock(&dev->struct_mutex);
1015 return PTR_ERR(ctx);
1019 switch (args->param) {
1020 case I915_CONTEXT_PARAM_BAN_PERIOD:
1023 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1024 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1026 case I915_CONTEXT_PARAM_GTT_SIZE:
1028 args->value = ctx->ppgtt->base.total;
1029 else if (to_i915(dev)->mm.aliasing_ppgtt)
1030 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1032 args->value = to_i915(dev)->ggtt.base.total;
1034 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1035 args->value = i915_gem_context_no_error_capture(ctx);
1037 case I915_CONTEXT_PARAM_BANNABLE:
1038 args->value = i915_gem_context_is_bannable(ctx);
1044 mutex_unlock(&dev->struct_mutex);
1049 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1050 struct drm_file *file)
1052 struct drm_i915_file_private *file_priv = file->driver_priv;
1053 struct drm_i915_gem_context_param *args = data;
1054 struct i915_gem_context *ctx;
1057 ret = i915_mutex_lock_interruptible(dev);
1061 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1063 mutex_unlock(&dev->struct_mutex);
1064 return PTR_ERR(ctx);
1067 switch (args->param) {
1068 case I915_CONTEXT_PARAM_BAN_PERIOD:
1071 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1075 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1076 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1079 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1082 else if (args->value)
1083 i915_gem_context_set_no_error_capture(ctx);
1085 i915_gem_context_clear_no_error_capture(ctx);
1087 case I915_CONTEXT_PARAM_BANNABLE:
1090 else if (!capable(CAP_SYS_ADMIN) && !args->value)
1092 else if (args->value)
1093 i915_gem_context_set_bannable(ctx);
1095 i915_gem_context_clear_bannable(ctx);
1101 mutex_unlock(&dev->struct_mutex);
1106 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1107 void *data, struct drm_file *file)
1109 struct drm_i915_private *dev_priv = to_i915(dev);
1110 struct drm_i915_reset_stats *args = data;
1111 struct i915_gem_context *ctx;
1114 if (args->flags || args->pad)
1117 ret = i915_mutex_lock_interruptible(dev);
1121 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1123 mutex_unlock(&dev->struct_mutex);
1124 return PTR_ERR(ctx);
1127 if (capable(CAP_SYS_ADMIN))
1128 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1130 args->reset_count = 0;
1132 args->batch_active = ctx->guilty_count;
1133 args->batch_pending = ctx->active_count;
1135 mutex_unlock(&dev->struct_mutex);
1140 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1141 #include "selftests/mock_context.c"
1142 #include "selftests/i915_gem_context.c"