2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 static int get_context_size(struct drm_i915_private *dev_priv)
100 switch (INTEL_GEN(dev_priv)) {
102 reg = I915_READ(CXT_SIZE);
103 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
106 reg = I915_READ(GEN7_CXT_SIZE);
107 if (IS_HASWELL(dev_priv))
108 ret = HSW_CXT_TOTAL_SIZE;
110 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
113 ret = GEN8_CXT_TOTAL_SIZE;
122 void i915_gem_context_free(struct kref *ctx_ref)
124 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
127 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
128 trace_i915_context_free(ctx);
129 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
131 i915_ppgtt_put(ctx->ppgtt);
133 for (i = 0; i < I915_NUM_ENGINES; i++) {
134 struct intel_context *ce = &ctx->engine[i];
139 WARN_ON(ce->pin_count);
141 intel_ring_free(ce->ring);
143 __i915_gem_object_release_unless_active(ce->state->obj);
148 list_del(&ctx->link);
150 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
154 static struct drm_i915_gem_object *
155 alloc_context_obj(struct drm_i915_private *dev_priv, u64 size)
157 struct drm_i915_gem_object *obj;
160 lockdep_assert_held(&dev_priv->drm.struct_mutex);
162 obj = i915_gem_object_create(dev_priv, size);
167 * Try to make the context utilize L3 as well as LLC.
169 * On VLV we don't have L3 controls in the PTEs so we
170 * shouldn't touch the cache level, especially as that
171 * would make the object snooped which might have a
172 * negative performance impact.
174 * Snooping is required on non-llc platforms in execlist
175 * mode, but since all GGTT accesses use PAT entry 0 we
176 * get snooping anyway regardless of cache_level.
178 * This is only applicable for Ivy Bridge devices since
179 * later platforms don't have L3 control bits in the PTE.
181 if (IS_IVYBRIDGE(dev_priv)) {
182 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
183 /* Failure shouldn't ever happen this early */
185 i915_gem_object_put(obj);
193 static void context_close(struct i915_gem_context *ctx)
195 i915_gem_context_set_closed(ctx);
197 i915_ppgtt_close(&ctx->ppgtt->base);
198 ctx->file_priv = ERR_PTR(-EBADF);
199 i915_gem_context_put(ctx);
202 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
206 ret = ida_simple_get(&dev_priv->context_hw_ida,
207 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
209 /* Contexts are only released when no longer active.
210 * Flush any pending retires to hopefully release some
211 * stale contexts and try again.
213 i915_gem_retire_requests(dev_priv);
214 ret = ida_simple_get(&dev_priv->context_hw_ida,
215 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
224 static u32 default_desc_template(const struct drm_i915_private *i915,
225 const struct i915_hw_ppgtt *ppgtt)
230 desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
232 address_mode = INTEL_LEGACY_32B_CONTEXT;
233 if (ppgtt && i915_vm_is_48bit(&ppgtt->base))
234 address_mode = INTEL_LEGACY_64B_CONTEXT;
235 desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
238 desc |= GEN8_CTX_L3LLC_COHERENT;
240 /* TODO: WaDisableLiteRestore when we start using semaphore
241 * signalling between Command Streamers
242 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
248 static struct i915_gem_context *
249 __create_hw_context(struct drm_i915_private *dev_priv,
250 struct drm_i915_file_private *file_priv)
252 struct i915_gem_context *ctx;
255 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
257 return ERR_PTR(-ENOMEM);
259 ret = assign_hw_id(dev_priv, &ctx->hw_id);
265 kref_init(&ctx->ref);
266 list_add_tail(&ctx->link, &dev_priv->context_list);
267 ctx->i915 = dev_priv;
269 if (dev_priv->hw_context_size) {
270 struct drm_i915_gem_object *obj;
271 struct i915_vma *vma;
273 obj = alloc_context_obj(dev_priv, dev_priv->hw_context_size);
279 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
281 i915_gem_object_put(obj);
286 ctx->engine[RCS].state = vma;
289 /* Default context will never have a file_priv */
290 ret = DEFAULT_CONTEXT_HANDLE;
292 ret = idr_alloc(&file_priv->context_idr, ctx,
293 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
297 ctx->user_handle = ret;
299 ctx->file_priv = file_priv;
301 ctx->pid = get_task_pid(current, PIDTYPE_PID);
302 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
312 /* NB: Mark all slices as needing a remap so that when the context first
313 * loads it will restore whatever remap state already exists. If there
314 * is no remap info, it will be a NOP. */
315 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
317 i915_gem_context_set_bannable(ctx);
318 ctx->ring_size = 4 * PAGE_SIZE;
320 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
322 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
323 * present or not in use we still need a small bias as ring wraparound
324 * at offset 0 sometimes hangs. No idea why.
326 if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
327 ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
329 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
335 idr_remove(&file_priv->context_idr, ctx->user_handle);
341 static void __destroy_hw_context(struct i915_gem_context *ctx,
342 struct drm_i915_file_private *file_priv)
344 idr_remove(&file_priv->context_idr, ctx->user_handle);
349 * The default context needs to exist per ring that uses contexts. It stores the
350 * context state of the GPU for applications that don't utilize HW contexts, as
351 * well as an idle case.
353 static struct i915_gem_context *
354 i915_gem_create_context(struct drm_i915_private *dev_priv,
355 struct drm_i915_file_private *file_priv)
357 struct i915_gem_context *ctx;
359 lockdep_assert_held(&dev_priv->drm.struct_mutex);
361 ctx = __create_hw_context(dev_priv, file_priv);
365 if (USES_FULL_PPGTT(dev_priv)) {
366 struct i915_hw_ppgtt *ppgtt;
368 ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name);
370 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
372 __destroy_hw_context(ctx, file_priv);
373 return ERR_CAST(ppgtt);
377 ctx->desc_template = default_desc_template(dev_priv, ppgtt);
380 trace_i915_context_create(ctx);
386 * i915_gem_context_create_gvt - create a GVT GEM context
389 * This function is used to create a GVT specific GEM context.
392 * pointer to i915_gem_context on success, error pointer if failed
395 struct i915_gem_context *
396 i915_gem_context_create_gvt(struct drm_device *dev)
398 struct i915_gem_context *ctx;
401 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
402 return ERR_PTR(-ENODEV);
404 ret = i915_mutex_lock_interruptible(dev);
408 ctx = __create_hw_context(to_i915(dev), NULL);
412 ctx->file_priv = ERR_PTR(-EBADF);
413 i915_gem_context_set_closed(ctx); /* not user accessible */
414 i915_gem_context_clear_bannable(ctx);
415 i915_gem_context_set_force_single_submission(ctx);
416 if (!i915.enable_guc_submission)
417 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
419 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
421 mutex_unlock(&dev->struct_mutex);
425 int i915_gem_context_init(struct drm_i915_private *dev_priv)
427 struct i915_gem_context *ctx;
429 /* Init should only be called once per module load. Eventually the
430 * restriction on the context_disabled check can be loosened. */
431 if (WARN_ON(dev_priv->kernel_context))
434 if (intel_vgpu_active(dev_priv) &&
435 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
436 if (!i915.enable_execlists) {
437 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
442 /* Using the simple ida interface, the max is limited by sizeof(int) */
443 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
444 ida_init(&dev_priv->context_hw_ida);
446 if (i915.enable_execlists) {
447 /* NB: intentionally left blank. We will allocate our own
448 * backing objects as we need them, thank you very much */
449 dev_priv->hw_context_size = 0;
450 } else if (HAS_HW_CONTEXTS(dev_priv)) {
451 dev_priv->hw_context_size =
452 round_up(get_context_size(dev_priv),
454 if (dev_priv->hw_context_size > (1<<20)) {
455 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
456 dev_priv->hw_context_size);
457 dev_priv->hw_context_size = 0;
461 ctx = i915_gem_create_context(dev_priv, NULL);
463 DRM_ERROR("Failed to create default global context (error %ld)\n",
468 /* For easy recognisablity, we want the kernel context to be 0 and then
469 * all user contexts will have non-zero hw_id.
471 GEM_BUG_ON(ctx->hw_id);
473 i915_gem_context_clear_bannable(ctx);
474 ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
475 dev_priv->kernel_context = ctx;
477 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
479 DRM_DEBUG_DRIVER("%s context support initialized\n",
480 i915.enable_execlists ? "LR" :
481 dev_priv->hw_context_size ? "HW" : "fake");
485 void i915_gem_context_lost(struct drm_i915_private *dev_priv)
487 struct intel_engine_cs *engine;
488 enum intel_engine_id id;
490 lockdep_assert_held(&dev_priv->drm.struct_mutex);
492 for_each_engine(engine, dev_priv, id) {
493 engine->legacy_active_context = NULL;
495 if (!engine->last_retired_context)
498 engine->context_unpin(engine, engine->last_retired_context);
499 engine->last_retired_context = NULL;
502 /* Force the GPU state to be restored on enabling */
503 if (!i915.enable_execlists) {
504 struct i915_gem_context *ctx;
506 list_for_each_entry(ctx, &dev_priv->context_list, link) {
507 if (!i915_gem_context_is_default(ctx))
510 for_each_engine(engine, dev_priv, id)
511 ctx->engine[engine->id].initialised = false;
513 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
516 for_each_engine(engine, dev_priv, id) {
517 struct intel_context *kce =
518 &dev_priv->kernel_context->engine[engine->id];
520 kce->initialised = true;
525 void i915_gem_context_fini(struct drm_i915_private *dev_priv)
527 struct i915_gem_context *dctx = dev_priv->kernel_context;
529 lockdep_assert_held(&dev_priv->drm.struct_mutex);
531 GEM_BUG_ON(!i915_gem_context_is_kernel(dctx));
534 dev_priv->kernel_context = NULL;
536 ida_destroy(&dev_priv->context_hw_ida);
539 static int context_idr_cleanup(int id, void *p, void *data)
541 struct i915_gem_context *ctx = p;
547 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
549 struct drm_i915_file_private *file_priv = file->driver_priv;
550 struct i915_gem_context *ctx;
552 idr_init(&file_priv->context_idr);
554 mutex_lock(&dev->struct_mutex);
555 ctx = i915_gem_create_context(to_i915(dev), file_priv);
556 mutex_unlock(&dev->struct_mutex);
558 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
561 idr_destroy(&file_priv->context_idr);
568 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
570 struct drm_i915_file_private *file_priv = file->driver_priv;
572 lockdep_assert_held(&dev->struct_mutex);
574 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
575 idr_destroy(&file_priv->context_idr);
579 mi_set_context(struct drm_i915_gem_request *req, u32 flags)
581 struct drm_i915_private *dev_priv = req->i915;
582 struct intel_engine_cs *engine = req->engine;
583 enum intel_engine_id id;
584 const int num_rings =
585 /* Use an extended w/a on gen7 if signalling from other rings */
586 (i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
587 INTEL_INFO(dev_priv)->num_rings - 1 :
592 flags |= MI_MM_SPACE_GTT;
593 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
594 /* These flags are for resource streamer on HSW+ */
595 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
597 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
600 if (INTEL_GEN(dev_priv) >= 7)
601 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
603 cs = intel_ring_begin(req, len);
607 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
608 if (INTEL_GEN(dev_priv) >= 7) {
609 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
611 struct intel_engine_cs *signaller;
613 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
614 for_each_engine(signaller, dev_priv, id) {
615 if (signaller == engine)
618 *cs++ = i915_mmio_reg_offset(
619 RING_PSMI_CTL(signaller->mmio_base));
620 *cs++ = _MASKED_BIT_ENABLE(
621 GEN6_PSMI_SLEEP_MSG_DISABLE);
627 *cs++ = MI_SET_CONTEXT;
628 *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
630 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
631 * WaMiSetContext_Hang:snb,ivb,vlv
635 if (INTEL_GEN(dev_priv) >= 7) {
637 struct intel_engine_cs *signaller;
638 i915_reg_t last_reg = {}; /* keep gcc quiet */
640 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
641 for_each_engine(signaller, dev_priv, id) {
642 if (signaller == engine)
645 last_reg = RING_PSMI_CTL(signaller->mmio_base);
646 *cs++ = i915_mmio_reg_offset(last_reg);
647 *cs++ = _MASKED_BIT_DISABLE(
648 GEN6_PSMI_SLEEP_MSG_DISABLE);
651 /* Insert a delay before the next switch! */
652 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
653 *cs++ = i915_mmio_reg_offset(last_reg);
654 *cs++ = i915_ggtt_offset(engine->scratch);
657 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
660 intel_ring_advance(req, cs);
665 static int remap_l3(struct drm_i915_gem_request *req, int slice)
667 u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
673 cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
678 * Note: We do not worry about the concurrent register cacheline hang
679 * here because no other code should access these registers other than
680 * at initialization time.
682 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
683 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
684 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
685 *cs++ = remap_info[i];
688 intel_ring_advance(req, cs);
693 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
694 struct intel_engine_cs *engine,
695 struct i915_gem_context *to)
700 if (!to->engine[RCS].initialised)
703 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
706 return to == engine->legacy_active_context;
710 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
711 struct intel_engine_cs *engine,
712 struct i915_gem_context *to)
717 /* Always load the ppgtt on first use */
718 if (!engine->legacy_active_context)
721 /* Same context without new entries, skip */
722 if (engine->legacy_active_context == to &&
723 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
726 if (engine->id != RCS)
729 if (INTEL_GEN(engine->i915) < 8)
736 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
737 struct i915_gem_context *to,
743 if (!IS_GEN8(to->i915))
746 if (hw_flags & MI_RESTORE_INHIBIT)
752 static int do_rcs_switch(struct drm_i915_gem_request *req)
754 struct i915_gem_context *to = req->ctx;
755 struct intel_engine_cs *engine = req->engine;
756 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
757 struct i915_gem_context *from = engine->legacy_active_context;
761 GEM_BUG_ON(engine->id != RCS);
763 if (skip_rcs_switch(ppgtt, engine, to))
766 if (needs_pd_load_pre(ppgtt, engine, to)) {
767 /* Older GENs and non render rings still want the load first,
768 * "PP_DCLV followed by PP_DIR_BASE register through Load
769 * Register Immediate commands in Ring Buffer before submitting
771 trace_switch_mm(engine, to);
772 ret = ppgtt->switch_mm(ppgtt, req);
777 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
778 /* NB: If we inhibit the restore, the context is not allowed to
779 * die because future work may end up depending on valid address
780 * space. This means we must enforce that a page table load
781 * occur when this occurs. */
782 hw_flags = MI_RESTORE_INHIBIT;
783 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
784 hw_flags = MI_FORCE_RESTORE;
788 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
789 ret = mi_set_context(req, hw_flags);
793 engine->legacy_active_context = to;
796 /* GEN8 does *not* require an explicit reload if the PDPs have been
797 * setup, and we do not wish to move them.
799 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
800 trace_switch_mm(engine, to);
801 ret = ppgtt->switch_mm(ppgtt, req);
802 /* The hardware context switch is emitted, but we haven't
803 * actually changed the state - so it's probably safe to bail
804 * here. Still, let the user know something dangerous has
812 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
814 for (i = 0; i < MAX_L3_SLICES; i++) {
815 if (!(to->remap_slice & (1<<i)))
818 ret = remap_l3(req, i);
822 to->remap_slice &= ~(1<<i);
825 if (!to->engine[RCS].initialised) {
826 if (engine->init_context) {
827 ret = engine->init_context(req);
831 to->engine[RCS].initialised = true;
838 * i915_switch_context() - perform a GPU context switch.
839 * @req: request for which we'll execute the context switch
841 * The context life cycle is simple. The context refcount is incremented and
842 * decremented by 1 and create and destroy. If the context is in use by the GPU,
843 * it will have a refcount > 1. This allows us to destroy the context abstract
844 * object while letting the normal object tracking destroy the backing BO.
846 * This function should not be used in execlists mode. Instead the context is
847 * switched by writing to the ELSP and requests keep a reference to their
850 int i915_switch_context(struct drm_i915_gem_request *req)
852 struct intel_engine_cs *engine = req->engine;
854 lockdep_assert_held(&req->i915->drm.struct_mutex);
855 if (i915.enable_execlists)
858 if (!req->ctx->engine[engine->id].state) {
859 struct i915_gem_context *to = req->ctx;
860 struct i915_hw_ppgtt *ppgtt =
861 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
863 if (needs_pd_load_pre(ppgtt, engine, to)) {
866 trace_switch_mm(engine, to);
867 ret = ppgtt->switch_mm(ppgtt, req);
871 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
877 return do_rcs_switch(req);
880 static bool engine_has_kernel_context(struct intel_engine_cs *engine)
882 struct i915_gem_timeline *timeline;
884 list_for_each_entry(timeline, &engine->i915->gt.timelines, link) {
885 struct intel_timeline *tl;
887 if (timeline == &engine->i915->gt.global_timeline)
890 tl = &timeline->engine[engine->id];
891 if (i915_gem_active_peek(&tl->last_request,
892 &engine->i915->drm.struct_mutex))
896 return (!engine->last_retired_context ||
897 i915_gem_context_is_kernel(engine->last_retired_context));
900 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
902 struct intel_engine_cs *engine;
903 struct i915_gem_timeline *timeline;
904 enum intel_engine_id id;
906 lockdep_assert_held(&dev_priv->drm.struct_mutex);
908 i915_gem_retire_requests(dev_priv);
910 for_each_engine(engine, dev_priv, id) {
911 struct drm_i915_gem_request *req;
914 if (engine_has_kernel_context(engine))
917 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
921 /* Queue this switch after all other activity */
922 list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
923 struct drm_i915_gem_request *prev;
924 struct intel_timeline *tl;
926 tl = &timeline->engine[engine->id];
927 prev = i915_gem_active_raw(&tl->last_request,
928 &dev_priv->drm.struct_mutex);
930 i915_sw_fence_await_sw_fence_gfp(&req->submit,
935 ret = i915_switch_context(req);
936 i915_add_request(req);
944 static bool contexts_enabled(struct drm_device *dev)
946 return i915.enable_execlists || to_i915(dev)->hw_context_size;
949 static bool client_is_banned(struct drm_i915_file_private *file_priv)
951 return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS;
954 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
955 struct drm_file *file)
957 struct drm_i915_gem_context_create *args = data;
958 struct drm_i915_file_private *file_priv = file->driver_priv;
959 struct i915_gem_context *ctx;
962 if (!contexts_enabled(dev))
968 if (client_is_banned(file_priv)) {
969 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
971 pid_nr(get_task_pid(current, PIDTYPE_PID)));
976 ret = i915_mutex_lock_interruptible(dev);
980 ctx = i915_gem_create_context(to_i915(dev), file_priv);
981 mutex_unlock(&dev->struct_mutex);
985 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
987 args->ctx_id = ctx->user_handle;
988 DRM_DEBUG("HW context %d created\n", args->ctx_id);
993 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
994 struct drm_file *file)
996 struct drm_i915_gem_context_destroy *args = data;
997 struct drm_i915_file_private *file_priv = file->driver_priv;
998 struct i915_gem_context *ctx;
1004 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
1007 ret = i915_mutex_lock_interruptible(dev);
1011 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1013 mutex_unlock(&dev->struct_mutex);
1014 return PTR_ERR(ctx);
1017 __destroy_hw_context(ctx, file_priv);
1018 mutex_unlock(&dev->struct_mutex);
1020 DRM_DEBUG("HW context %d destroyed\n", args->ctx_id);
1024 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file)
1027 struct drm_i915_file_private *file_priv = file->driver_priv;
1028 struct drm_i915_gem_context_param *args = data;
1029 struct i915_gem_context *ctx;
1032 ret = i915_mutex_lock_interruptible(dev);
1036 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1038 mutex_unlock(&dev->struct_mutex);
1039 return PTR_ERR(ctx);
1043 switch (args->param) {
1044 case I915_CONTEXT_PARAM_BAN_PERIOD:
1047 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1048 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1050 case I915_CONTEXT_PARAM_GTT_SIZE:
1052 args->value = ctx->ppgtt->base.total;
1053 else if (to_i915(dev)->mm.aliasing_ppgtt)
1054 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1056 args->value = to_i915(dev)->ggtt.base.total;
1058 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1059 args->value = i915_gem_context_no_error_capture(ctx);
1061 case I915_CONTEXT_PARAM_BANNABLE:
1062 args->value = i915_gem_context_is_bannable(ctx);
1068 mutex_unlock(&dev->struct_mutex);
1073 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1074 struct drm_file *file)
1076 struct drm_i915_file_private *file_priv = file->driver_priv;
1077 struct drm_i915_gem_context_param *args = data;
1078 struct i915_gem_context *ctx;
1081 ret = i915_mutex_lock_interruptible(dev);
1085 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1087 mutex_unlock(&dev->struct_mutex);
1088 return PTR_ERR(ctx);
1091 switch (args->param) {
1092 case I915_CONTEXT_PARAM_BAN_PERIOD:
1095 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1099 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1100 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1103 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1106 else if (args->value)
1107 i915_gem_context_set_no_error_capture(ctx);
1109 i915_gem_context_clear_no_error_capture(ctx);
1111 case I915_CONTEXT_PARAM_BANNABLE:
1114 else if (!capable(CAP_SYS_ADMIN) && !args->value)
1116 else if (args->value)
1117 i915_gem_context_set_bannable(ctx);
1119 i915_gem_context_clear_bannable(ctx);
1125 mutex_unlock(&dev->struct_mutex);
1130 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1131 void *data, struct drm_file *file)
1133 struct drm_i915_private *dev_priv = to_i915(dev);
1134 struct drm_i915_reset_stats *args = data;
1135 struct i915_gem_context *ctx;
1138 if (args->flags || args->pad)
1141 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1144 ret = i915_mutex_lock_interruptible(dev);
1148 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1150 mutex_unlock(&dev->struct_mutex);
1151 return PTR_ERR(ctx);
1154 if (capable(CAP_SYS_ADMIN))
1155 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1157 args->reset_count = 0;
1159 args->batch_active = ctx->guilty_count;
1160 args->batch_pending = ctx->active_count;
1162 mutex_unlock(&dev->struct_mutex);
1167 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1168 #include "selftests/mock_context.c"
1169 #include "selftests/i915_gem_context.c"