2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 #define GEN6_PPGTT_PD_ENTRIES 512
32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
33 typedef uint64_t gen8_gtt_pte_t;
34 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
37 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
38 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
40 #define GEN6_PDE_VALID (1 << 0)
41 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
42 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
44 #define GEN6_PTE_VALID (1 << 0)
45 #define GEN6_PTE_UNCACHED (1 << 1)
46 #define HSW_PTE_UNCACHED (0)
47 #define GEN6_PTE_CACHE_LLC (2 << 1)
48 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
49 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
50 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
52 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
53 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
55 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
56 (((bits) & 0x8) << (11 - 3)))
57 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
58 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
59 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
60 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
61 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
62 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
64 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
65 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
66 #define GEN8_LEGACY_PDPS 4
68 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
69 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
70 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
71 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
73 static void ppgtt_bind_vma(struct i915_vma *vma,
74 enum i915_cache_level cache_level,
76 static void ppgtt_unbind_vma(struct i915_vma *vma);
77 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
79 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
80 enum i915_cache_level level,
83 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
85 if (level != I915_CACHE_NONE)
86 pte |= PPAT_CACHED_INDEX;
88 pte |= PPAT_UNCACHED_INDEX;
92 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
94 enum i915_cache_level level)
96 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
98 if (level != I915_CACHE_NONE)
99 pde |= PPAT_CACHED_PDE_INDEX;
101 pde |= PPAT_UNCACHED_INDEX;
105 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
106 enum i915_cache_level level,
109 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
110 pte |= GEN6_PTE_ADDR_ENCODE(addr);
113 case I915_CACHE_L3_LLC:
115 pte |= GEN6_PTE_CACHE_LLC;
117 case I915_CACHE_NONE:
118 pte |= GEN6_PTE_UNCACHED;
127 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
128 enum i915_cache_level level,
131 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
132 pte |= GEN6_PTE_ADDR_ENCODE(addr);
135 case I915_CACHE_L3_LLC:
136 pte |= GEN7_PTE_CACHE_L3_LLC;
139 pte |= GEN6_PTE_CACHE_LLC;
141 case I915_CACHE_NONE:
142 pte |= GEN6_PTE_UNCACHED;
151 #define BYT_PTE_WRITEABLE (1 << 1)
152 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
154 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
155 enum i915_cache_level level,
158 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
159 pte |= GEN6_PTE_ADDR_ENCODE(addr);
161 /* Mark the page as writeable. Other platforms don't have a
162 * setting for read-only/writable, so this matches that behavior.
164 pte |= BYT_PTE_WRITEABLE;
166 if (level != I915_CACHE_NONE)
167 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
172 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
173 enum i915_cache_level level,
176 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
177 pte |= HSW_PTE_ADDR_ENCODE(addr);
179 if (level != I915_CACHE_NONE)
180 pte |= HSW_WB_LLC_AGE3;
185 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
186 enum i915_cache_level level,
189 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
190 pte |= HSW_PTE_ADDR_ENCODE(addr);
193 case I915_CACHE_NONE:
196 pte |= HSW_WT_ELLC_LLC_AGE3;
199 pte |= HSW_WB_ELLC_LLC_AGE3;
206 /* Broadwell Page Directory Pointer Descriptors */
207 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
208 uint64_t val, bool synchronous)
210 struct drm_i915_private *dev_priv = ring->dev->dev_private;
216 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
217 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
221 ret = intel_ring_begin(ring, 6);
225 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
226 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
227 intel_ring_emit(ring, (u32)(val >> 32));
228 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
229 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
230 intel_ring_emit(ring, (u32)(val));
231 intel_ring_advance(ring);
236 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
237 struct intel_ring_buffer *ring,
242 /* bit of a hack to find the actual last used pd */
243 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
245 for (i = used_pd - 1; i >= 0; i--) {
246 dma_addr_t addr = ppgtt->pd_dma_addr[i];
247 ret = gen8_write_pdp(ring, i, addr, synchronous);
255 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
256 unsigned first_entry,
257 unsigned num_entries,
260 struct i915_hw_ppgtt *ppgtt =
261 container_of(vm, struct i915_hw_ppgtt, base);
262 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
263 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
264 unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
265 unsigned last_pte, i;
267 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
268 I915_CACHE_LLC, use_scratch);
270 while (num_entries) {
271 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
273 last_pte = first_pte + num_entries;
274 if (last_pte > GEN8_PTES_PER_PAGE)
275 last_pte = GEN8_PTES_PER_PAGE;
277 pt_vaddr = kmap_atomic(page_table);
279 for (i = first_pte; i < last_pte; i++)
280 pt_vaddr[i] = scratch_pte;
282 kunmap_atomic(pt_vaddr);
284 num_entries -= last_pte - first_pte;
290 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
291 struct sg_table *pages,
292 unsigned first_entry,
293 enum i915_cache_level cache_level)
295 struct i915_hw_ppgtt *ppgtt =
296 container_of(vm, struct i915_hw_ppgtt, base);
297 gen8_gtt_pte_t *pt_vaddr;
298 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
299 unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
300 struct sg_page_iter sg_iter;
302 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
303 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
304 dma_addr_t page_addr;
306 page_addr = sg_dma_address(sg_iter.sg) +
307 (sg_iter.sg_pgoffset << PAGE_SHIFT);
308 pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level,
310 if (++act_pte == GEN8_PTES_PER_PAGE) {
311 kunmap_atomic(pt_vaddr);
313 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
318 kunmap_atomic(pt_vaddr);
321 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
323 struct i915_hw_ppgtt *ppgtt =
324 container_of(vm, struct i915_hw_ppgtt, base);
327 drm_mm_takedown(&vm->mm);
329 for (i = 0; i < ppgtt->num_pd_pages ; i++) {
330 if (ppgtt->pd_dma_addr[i]) {
331 pci_unmap_page(ppgtt->base.dev->pdev,
332 ppgtt->pd_dma_addr[i],
333 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
335 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
336 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
338 pci_unmap_page(ppgtt->base.dev->pdev,
341 PCI_DMA_BIDIRECTIONAL);
345 kfree(ppgtt->gen8_pt_dma_addr[i]);
348 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
349 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
353 * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
354 * net effect resembling a 2-level page table in normal x86 terms. Each PDP
355 * represents 1GB of memory
356 * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
358 * TODO: Do something with the size parameter
360 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
362 struct page *pt_pages;
363 int i, j, ret = -ENOMEM;
364 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
365 const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
368 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
370 /* FIXME: split allocation into smaller pieces. For now we only ever do
371 * this once, but with full PPGTT, the multiple contiguous allocations
374 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
375 if (!ppgtt->pd_pages)
378 pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
380 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
384 ppgtt->gen8_pt_pages = pt_pages;
385 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
386 ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
387 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
388 ppgtt->enable = gen8_ppgtt_enable;
389 ppgtt->switch_mm = gen8_mm_switch;
390 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
391 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
392 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
393 ppgtt->base.start = 0;
394 ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
396 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
399 * - Create a mapping for the page directories.
400 * - For each page directory:
401 * allocate space for page table mappings.
402 * map each page table
404 for (i = 0; i < max_pdp; i++) {
406 temp = pci_map_page(ppgtt->base.dev->pdev,
407 &ppgtt->pd_pages[i], 0,
408 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
409 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
412 ppgtt->pd_dma_addr[i] = temp;
414 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
415 if (!ppgtt->gen8_pt_dma_addr[i])
418 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
419 struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
420 temp = pci_map_page(ppgtt->base.dev->pdev,
422 PCI_DMA_BIDIRECTIONAL);
424 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
427 ppgtt->gen8_pt_dma_addr[i][j] = temp;
431 /* For now, the PPGTT helper functions all require that the PDEs are
432 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
433 * will never need to touch the PDEs again */
434 for (i = 0; i < max_pdp; i++) {
435 gen8_ppgtt_pde_t *pd_vaddr;
436 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
437 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
438 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
439 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
442 kunmap_atomic(pd_vaddr);
445 ppgtt->base.clear_range(&ppgtt->base, 0,
446 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
449 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
450 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
451 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
453 (ppgtt->num_pt_pages - num_pt_pages) +
458 ppgtt->base.cleanup(&ppgtt->base);
462 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
464 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
465 gen6_gtt_pte_t __iomem *pd_addr;
469 WARN_ON(ppgtt->pd_offset & 0x3f);
470 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
471 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
472 for (i = 0; i < ppgtt->num_pd_entries; i++) {
475 pt_addr = ppgtt->pt_dma_addr[i];
476 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
477 pd_entry |= GEN6_PDE_VALID;
479 writel(pd_entry, pd_addr + i);
484 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
486 BUG_ON(ppgtt->pd_offset & 0x3f);
488 return (ppgtt->pd_offset / 64) << 16;
491 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
492 struct intel_ring_buffer *ring,
495 struct drm_device *dev = ppgtt->base.dev;
496 struct drm_i915_private *dev_priv = dev->dev_private;
499 /* If we're in reset, we can assume the GPU is sufficiently idle to
500 * manually frob these bits. Ideally we could use the ring functions,
501 * except our error handling makes it quite difficult (can't use
502 * intel_ring_begin, ring->flush, or intel_ring_advance)
504 * FIXME: We should try not to special case reset
507 i915_reset_in_progress(&dev_priv->gpu_error)) {
508 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
509 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
510 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
511 POSTING_READ(RING_PP_DIR_BASE(ring));
515 /* NB: TLBs must be flushed and invalidated before a switch */
516 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
520 ret = intel_ring_begin(ring, 6);
524 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
525 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
526 intel_ring_emit(ring, PP_DIR_DCLV_2G);
527 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
528 intel_ring_emit(ring, get_pd_offset(ppgtt));
529 intel_ring_emit(ring, MI_NOOP);
530 intel_ring_advance(ring);
535 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
536 struct intel_ring_buffer *ring,
539 struct drm_device *dev = ppgtt->base.dev;
540 struct drm_i915_private *dev_priv = dev->dev_private;
543 /* If we're in reset, we can assume the GPU is sufficiently idle to
544 * manually frob these bits. Ideally we could use the ring functions,
545 * except our error handling makes it quite difficult (can't use
546 * intel_ring_begin, ring->flush, or intel_ring_advance)
548 * FIXME: We should try not to special case reset
551 i915_reset_in_progress(&dev_priv->gpu_error)) {
552 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
553 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
554 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
555 POSTING_READ(RING_PP_DIR_BASE(ring));
559 /* NB: TLBs must be flushed and invalidated before a switch */
560 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
564 ret = intel_ring_begin(ring, 6);
568 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
569 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
570 intel_ring_emit(ring, PP_DIR_DCLV_2G);
571 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
572 intel_ring_emit(ring, get_pd_offset(ppgtt));
573 intel_ring_emit(ring, MI_NOOP);
574 intel_ring_advance(ring);
576 /* XXX: RCS is the only one to auto invalidate the TLBs? */
577 if (ring->id != RCS) {
578 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
586 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
587 struct intel_ring_buffer *ring,
590 struct drm_device *dev = ppgtt->base.dev;
591 struct drm_i915_private *dev_priv = dev->dev_private;
596 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
597 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
599 POSTING_READ(RING_PP_DIR_DCLV(ring));
604 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
606 struct drm_device *dev = ppgtt->base.dev;
607 struct drm_i915_private *dev_priv = dev->dev_private;
608 struct intel_ring_buffer *ring;
611 for_each_ring(ring, dev_priv, j) {
612 I915_WRITE(RING_MODE_GEN7(ring),
613 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
614 ret = ppgtt->switch_mm(ppgtt, ring, true);
622 for_each_ring(ring, dev_priv, j)
623 I915_WRITE(RING_MODE_GEN7(ring),
624 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
628 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
630 struct drm_device *dev = ppgtt->base.dev;
631 drm_i915_private_t *dev_priv = dev->dev_private;
632 struct intel_ring_buffer *ring;
633 uint32_t ecochk, ecobits;
636 ecobits = I915_READ(GAC_ECO_BITS);
637 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
639 ecochk = I915_READ(GAM_ECOCHK);
640 if (IS_HASWELL(dev)) {
641 ecochk |= ECOCHK_PPGTT_WB_HSW;
643 ecochk |= ECOCHK_PPGTT_LLC_IVB;
644 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
646 I915_WRITE(GAM_ECOCHK, ecochk);
648 for_each_ring(ring, dev_priv, i) {
650 /* GFX_MODE is per-ring on gen7+ */
651 I915_WRITE(RING_MODE_GEN7(ring),
652 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
653 ret = ppgtt->switch_mm(ppgtt, ring, true);
661 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
663 struct drm_device *dev = ppgtt->base.dev;
664 drm_i915_private_t *dev_priv = dev->dev_private;
665 struct intel_ring_buffer *ring;
666 uint32_t ecochk, gab_ctl, ecobits;
669 ecobits = I915_READ(GAC_ECO_BITS);
670 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
671 ECOBITS_PPGTT_CACHE64B);
673 gab_ctl = I915_READ(GAB_CTL);
674 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
676 ecochk = I915_READ(GAM_ECOCHK);
677 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
679 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
681 for_each_ring(ring, dev_priv, i) {
682 int ret = ppgtt->switch_mm(ppgtt, ring, true);
690 /* PPGTT support for Sandybdrige/Gen6 and later */
691 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
692 unsigned first_entry,
693 unsigned num_entries,
696 struct i915_hw_ppgtt *ppgtt =
697 container_of(vm, struct i915_hw_ppgtt, base);
698 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
699 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
700 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
701 unsigned last_pte, i;
703 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
705 while (num_entries) {
706 last_pte = first_pte + num_entries;
707 if (last_pte > I915_PPGTT_PT_ENTRIES)
708 last_pte = I915_PPGTT_PT_ENTRIES;
710 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
712 for (i = first_pte; i < last_pte; i++)
713 pt_vaddr[i] = scratch_pte;
715 kunmap_atomic(pt_vaddr);
717 num_entries -= last_pte - first_pte;
723 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
724 struct sg_table *pages,
725 unsigned first_entry,
726 enum i915_cache_level cache_level)
728 struct i915_hw_ppgtt *ppgtt =
729 container_of(vm, struct i915_hw_ppgtt, base);
730 gen6_gtt_pte_t *pt_vaddr;
731 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
732 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
733 struct sg_page_iter sg_iter;
735 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
736 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
737 dma_addr_t page_addr;
739 page_addr = sg_page_iter_dma_address(&sg_iter);
740 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
741 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
742 kunmap_atomic(pt_vaddr);
744 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
749 kunmap_atomic(pt_vaddr);
752 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
754 struct i915_hw_ppgtt *ppgtt =
755 container_of(vm, struct i915_hw_ppgtt, base);
758 drm_mm_takedown(&ppgtt->base.mm);
759 drm_mm_remove_node(&ppgtt->node);
761 if (ppgtt->pt_dma_addr) {
762 for (i = 0; i < ppgtt->num_pd_entries; i++)
763 pci_unmap_page(ppgtt->base.dev->pdev,
764 ppgtt->pt_dma_addr[i],
765 4096, PCI_DMA_BIDIRECTIONAL);
768 kfree(ppgtt->pt_dma_addr);
769 for (i = 0; i < ppgtt->num_pd_entries; i++)
770 __free_page(ppgtt->pt_pages[i]);
771 kfree(ppgtt->pt_pages);
775 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
777 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
778 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
779 struct drm_device *dev = ppgtt->base.dev;
780 struct drm_i915_private *dev_priv = dev->dev_private;
781 bool retried = false;
784 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
785 * allocator works in address space sizes, so it's multiplied by page
786 * size. We allocate at the top of the GTT to avoid fragmentation.
788 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
790 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
791 &ppgtt->node, GEN6_PD_SIZE,
793 0, dev_priv->gtt.base.total,
794 DRM_MM_SEARCH_DEFAULT);
795 if (ret == -ENOSPC && !retried) {
796 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
797 GEN6_PD_SIZE, GEN6_PD_ALIGN,
798 I915_CACHE_NONE, false, true);
806 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
807 DRM_DEBUG("Forced to use aperture for PDEs\n");
809 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
810 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
812 ppgtt->enable = gen6_ppgtt_enable;
813 ppgtt->switch_mm = gen6_mm_switch;
814 } else if (IS_HASWELL(dev)) {
815 ppgtt->enable = gen7_ppgtt_enable;
816 ppgtt->switch_mm = hsw_mm_switch;
817 } else if (IS_GEN7(dev)) {
818 ppgtt->enable = gen7_ppgtt_enable;
819 ppgtt->switch_mm = gen7_mm_switch;
822 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
823 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
824 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
825 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
826 ppgtt->base.start = 0;
827 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
828 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
830 if (!ppgtt->pt_pages) {
831 drm_mm_remove_node(&ppgtt->node);
835 for (i = 0; i < ppgtt->num_pd_entries; i++) {
836 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
837 if (!ppgtt->pt_pages[i])
841 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
843 if (!ppgtt->pt_dma_addr)
846 for (i = 0; i < ppgtt->num_pd_entries; i++) {
849 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
850 PCI_DMA_BIDIRECTIONAL);
852 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
857 ppgtt->pt_dma_addr[i] = pt_addr;
860 ppgtt->base.clear_range(&ppgtt->base, 0,
861 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
863 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
864 ppgtt->node.size >> 20,
865 ppgtt->node.start / PAGE_SIZE);
867 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
872 if (ppgtt->pt_dma_addr) {
873 for (i--; i >= 0; i--)
874 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
875 4096, PCI_DMA_BIDIRECTIONAL);
878 kfree(ppgtt->pt_dma_addr);
879 for (i = 0; i < ppgtt->num_pd_entries; i++) {
880 if (ppgtt->pt_pages[i])
881 __free_page(ppgtt->pt_pages[i]);
883 kfree(ppgtt->pt_pages);
884 drm_mm_remove_node(&ppgtt->node);
889 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
891 struct drm_i915_private *dev_priv = dev->dev_private;
894 ppgtt->base.dev = dev;
896 if (INTEL_INFO(dev)->gen < 8)
897 ret = gen6_ppgtt_init(ppgtt);
898 else if (IS_GEN8(dev))
899 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
904 kref_init(&ppgtt->ref);
905 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
907 if (INTEL_INFO(dev)->gen < 8)
908 gen6_write_pdes(ppgtt);
914 static void __always_unused
915 ppgtt_bind_vma(struct i915_vma *vma,
916 enum i915_cache_level cache_level,
919 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
923 vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level);
926 static void __always_unused ppgtt_unbind_vma(struct i915_vma *vma)
928 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
930 vma->vm->clear_range(vma->vm,
932 vma->obj->base.size >> PAGE_SHIFT,
936 extern int intel_iommu_gfx_mapped;
937 /* Certain Gen5 chipsets require require idling the GPU before
938 * unmapping anything from the GTT when VT-d is enabled.
940 static inline bool needs_idle_maps(struct drm_device *dev)
942 #ifdef CONFIG_INTEL_IOMMU
943 /* Query intel_iommu to see if we need the workaround. Presumably that
946 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
952 static bool do_idling(struct drm_i915_private *dev_priv)
954 bool ret = dev_priv->mm.interruptible;
956 if (unlikely(dev_priv->gtt.do_idle_maps)) {
957 dev_priv->mm.interruptible = false;
958 if (i915_gpu_idle(dev_priv->dev)) {
959 DRM_ERROR("Couldn't idle GPU\n");
960 /* Wait a bit, in hopes it avoids the hang */
968 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
970 if (unlikely(dev_priv->gtt.do_idle_maps))
971 dev_priv->mm.interruptible = interruptible;
974 void i915_check_and_clear_faults(struct drm_device *dev)
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 struct intel_ring_buffer *ring;
980 if (INTEL_INFO(dev)->gen < 6)
983 for_each_ring(ring, dev_priv, i) {
985 fault_reg = I915_READ(RING_FAULT_REG(ring));
986 if (fault_reg & RING_FAULT_VALID) {
987 DRM_DEBUG_DRIVER("Unexpected fault\n"
989 "\tAddress space: %s\n"
992 fault_reg & PAGE_MASK,
993 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
994 RING_FAULT_SRCID(fault_reg),
995 RING_FAULT_FAULT_TYPE(fault_reg));
996 I915_WRITE(RING_FAULT_REG(ring),
997 fault_reg & ~RING_FAULT_VALID);
1000 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1003 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1005 struct drm_i915_private *dev_priv = dev->dev_private;
1007 /* Don't bother messing with faults pre GEN6 as we have little
1008 * documentation supporting that it's a good idea.
1010 if (INTEL_INFO(dev)->gen < 6)
1013 i915_check_and_clear_faults(dev);
1015 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1016 dev_priv->gtt.base.start / PAGE_SIZE,
1017 dev_priv->gtt.base.total / PAGE_SIZE,
1021 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 struct drm_i915_gem_object *obj;
1025 struct i915_address_space *vm;
1027 i915_check_and_clear_faults(dev);
1029 /* First fill our portion of the GTT with scratch pages */
1030 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1031 dev_priv->gtt.base.start / PAGE_SIZE,
1032 dev_priv->gtt.base.total / PAGE_SIZE,
1035 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1036 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1037 &dev_priv->gtt.base);
1041 i915_gem_clflush_object(obj, obj->pin_display);
1042 /* The bind_vma code tries to be smart about tracking mappings.
1043 * Unfortunately above, we've just wiped out the mappings
1044 * without telling our object about it. So we need to fake it.
1046 obj->has_global_gtt_mapping = 0;
1047 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1051 if (INTEL_INFO(dev)->gen >= 8)
1054 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1055 /* TODO: Perhaps it shouldn't be gen6 specific */
1056 if (i915_is_ggtt(vm)) {
1057 if (dev_priv->mm.aliasing_ppgtt)
1058 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1062 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1065 i915_gem_chipset_flush(dev);
1068 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1070 if (obj->has_dma_mapping)
1073 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1074 obj->pages->sgl, obj->pages->nents,
1075 PCI_DMA_BIDIRECTIONAL))
1081 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1086 iowrite32((u32)pte, addr);
1087 iowrite32(pte >> 32, addr + 4);
1091 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1092 struct sg_table *st,
1093 unsigned int first_entry,
1094 enum i915_cache_level level)
1096 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1097 gen8_gtt_pte_t __iomem *gtt_entries =
1098 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1100 struct sg_page_iter sg_iter;
1103 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1104 addr = sg_dma_address(sg_iter.sg) +
1105 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1106 gen8_set_pte(>t_entries[i],
1107 gen8_pte_encode(addr, level, true));
1112 * XXX: This serves as a posting read to make sure that the PTE has
1113 * actually been updated. There is some concern that even though
1114 * registers and PTEs are within the same BAR that they are potentially
1115 * of NUMA access patterns. Therefore, even with the way we assume
1116 * hardware should work, we must keep this posting read for paranoia.
1119 WARN_ON(readq(>t_entries[i-1])
1120 != gen8_pte_encode(addr, level, true));
1122 #if 0 /* TODO: Still needed on GEN8? */
1123 /* This next bit makes the above posting read even more important. We
1124 * want to flush the TLBs only after we're certain all the PTE updates
1127 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1128 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1133 * Binds an object into the global gtt with the specified cache level. The object
1134 * will be accessible to the GPU via commands whose operands reference offsets
1135 * within the global GTT as well as accessible by the GPU through the GMADR
1136 * mapped BAR (dev_priv->mm.gtt->gtt).
1138 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1139 struct sg_table *st,
1140 unsigned int first_entry,
1141 enum i915_cache_level level)
1143 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1144 gen6_gtt_pte_t __iomem *gtt_entries =
1145 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1147 struct sg_page_iter sg_iter;
1150 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1151 addr = sg_page_iter_dma_address(&sg_iter);
1152 iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]);
1156 /* XXX: This serves as a posting read to make sure that the PTE has
1157 * actually been updated. There is some concern that even though
1158 * registers and PTEs are within the same BAR that they are potentially
1159 * of NUMA access patterns. Therefore, even with the way we assume
1160 * hardware should work, we must keep this posting read for paranoia.
1163 WARN_ON(readl(>t_entries[i-1]) !=
1164 vm->pte_encode(addr, level, true));
1166 /* This next bit makes the above posting read even more important. We
1167 * want to flush the TLBs only after we're certain all the PTE updates
1170 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1171 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1174 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1175 unsigned int first_entry,
1176 unsigned int num_entries,
1179 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1180 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1181 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1182 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1185 if (WARN(num_entries > max_entries,
1186 "First entry = %d; Num entries = %d (max=%d)\n",
1187 first_entry, num_entries, max_entries))
1188 num_entries = max_entries;
1190 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1193 for (i = 0; i < num_entries; i++)
1194 gen8_set_pte(>t_base[i], scratch_pte);
1198 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1199 unsigned int first_entry,
1200 unsigned int num_entries,
1203 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1204 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1205 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1206 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1209 if (WARN(num_entries > max_entries,
1210 "First entry = %d; Num entries = %d (max=%d)\n",
1211 first_entry, num_entries, max_entries))
1212 num_entries = max_entries;
1214 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1216 for (i = 0; i < num_entries; i++)
1217 iowrite32(scratch_pte, >t_base[i]);
1222 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1223 enum i915_cache_level cache_level,
1226 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1227 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1228 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1230 BUG_ON(!i915_is_ggtt(vma->vm));
1231 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1232 vma->obj->has_global_gtt_mapping = 1;
1235 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1236 unsigned int first_entry,
1237 unsigned int num_entries,
1240 intel_gtt_clear_range(first_entry, num_entries);
1243 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1245 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1246 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1248 BUG_ON(!i915_is_ggtt(vma->vm));
1249 vma->obj->has_global_gtt_mapping = 0;
1250 intel_gtt_clear_range(first, size);
1253 static void ggtt_bind_vma(struct i915_vma *vma,
1254 enum i915_cache_level cache_level,
1257 struct drm_device *dev = vma->vm->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 struct drm_i915_gem_object *obj = vma->obj;
1260 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1262 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1263 * or we have a global mapping already but the cacheability flags have
1264 * changed, set the global PTEs.
1266 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1267 * instead if none of the above hold true.
1269 * NB: A global mapping should only be needed for special regions like
1270 * "gtt mappable", SNB errata, or if specified via special execbuf
1271 * flags. At all other times, the GPU will use the aliasing PPGTT.
1273 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1274 if (!obj->has_global_gtt_mapping ||
1275 (cache_level != obj->cache_level)) {
1276 vma->vm->insert_entries(vma->vm, obj->pages, entry,
1278 obj->has_global_gtt_mapping = 1;
1282 if (dev_priv->mm.aliasing_ppgtt &&
1283 (!obj->has_aliasing_ppgtt_mapping ||
1284 (cache_level != obj->cache_level))) {
1285 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1286 appgtt->base.insert_entries(&appgtt->base,
1287 vma->obj->pages, entry, cache_level);
1288 vma->obj->has_aliasing_ppgtt_mapping = 1;
1292 static void ggtt_unbind_vma(struct i915_vma *vma)
1294 struct drm_device *dev = vma->vm->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 struct drm_i915_gem_object *obj = vma->obj;
1297 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1299 if (obj->has_global_gtt_mapping) {
1300 vma->vm->clear_range(vma->vm, entry,
1301 vma->obj->base.size >> PAGE_SHIFT,
1303 obj->has_global_gtt_mapping = 0;
1306 if (obj->has_aliasing_ppgtt_mapping) {
1307 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1308 appgtt->base.clear_range(&appgtt->base,
1310 obj->base.size >> PAGE_SHIFT,
1312 obj->has_aliasing_ppgtt_mapping = 0;
1316 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1318 struct drm_device *dev = obj->base.dev;
1319 struct drm_i915_private *dev_priv = dev->dev_private;
1322 interruptible = do_idling(dev_priv);
1324 if (!obj->has_dma_mapping)
1325 dma_unmap_sg(&dev->pdev->dev,
1326 obj->pages->sgl, obj->pages->nents,
1327 PCI_DMA_BIDIRECTIONAL);
1329 undo_idling(dev_priv, interruptible);
1332 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1333 unsigned long color,
1334 unsigned long *start,
1337 if (node->color != color)
1340 if (!list_empty(&node->node_list)) {
1341 node = list_entry(node->node_list.next,
1344 if (node->allocated && node->color != color)
1349 void i915_gem_setup_global_gtt(struct drm_device *dev,
1350 unsigned long start,
1351 unsigned long mappable_end,
1354 /* Let GEM Manage all of the aperture.
1356 * However, leave one page at the end still bound to the scratch page.
1357 * There are a number of places where the hardware apparently prefetches
1358 * past the end of the object, and we've seen multiple hangs with the
1359 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1360 * aperture. One page should be enough to keep any prefetching inside
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1365 struct drm_mm_node *entry;
1366 struct drm_i915_gem_object *obj;
1367 unsigned long hole_start, hole_end;
1369 BUG_ON(mappable_end > end);
1371 /* Subtract the guard page ... */
1372 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1374 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1376 /* Mark any preallocated objects as occupied */
1377 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1378 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1380 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1381 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1383 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1384 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1386 DRM_DEBUG_KMS("Reservation failed\n");
1387 obj->has_global_gtt_mapping = 1;
1390 dev_priv->gtt.base.start = start;
1391 dev_priv->gtt.base.total = end - start;
1393 /* Clear any non-preallocated blocks */
1394 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1395 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1396 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1397 hole_start, hole_end);
1398 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1401 /* And finally clear the reserved guard page */
1402 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1405 void i915_gem_init_global_gtt(struct drm_device *dev)
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 unsigned long gtt_size, mappable_size;
1410 gtt_size = dev_priv->gtt.base.total;
1411 mappable_size = dev_priv->gtt.mappable_end;
1413 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1416 static int setup_scratch_page(struct drm_device *dev)
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1420 dma_addr_t dma_addr;
1422 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1426 set_pages_uc(page, 1);
1428 #ifdef CONFIG_INTEL_IOMMU
1429 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1430 PCI_DMA_BIDIRECTIONAL);
1431 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1434 dma_addr = page_to_phys(page);
1436 dev_priv->gtt.base.scratch.page = page;
1437 dev_priv->gtt.base.scratch.addr = dma_addr;
1442 static void teardown_scratch_page(struct drm_device *dev)
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 struct page *page = dev_priv->gtt.base.scratch.page;
1447 set_pages_wb(page, 1);
1448 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1449 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1454 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1456 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1457 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1458 return snb_gmch_ctl << 20;
1461 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1463 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1464 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1466 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1467 if (bdw_gmch_ctl > 4) {
1468 WARN_ON(!i915_preliminary_hw_support);
1472 return bdw_gmch_ctl << 20;
1475 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1477 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1478 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1479 return snb_gmch_ctl << 25; /* 32 MB units */
1482 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1484 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1485 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1486 return bdw_gmch_ctl << 25; /* 32 MB units */
1489 static int ggtt_probe_common(struct drm_device *dev,
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 phys_addr_t gtt_bus_addr;
1496 /* For Modern GENs the PTEs and register space are split in the BAR */
1497 gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1498 (pci_resource_len(dev->pdev, 0) / 2);
1500 dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1501 if (!dev_priv->gtt.gsm) {
1502 DRM_ERROR("Failed to map the gtt page table\n");
1506 ret = setup_scratch_page(dev);
1508 DRM_ERROR("Scratch setup failed\n");
1509 /* iounmap will also get called at remove, but meh */
1510 iounmap(dev_priv->gtt.gsm);
1516 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1517 * bits. When using advanced contexts each context stores its own PAT, but
1518 * writing this data shouldn't be harmful even in those cases. */
1519 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1521 #define GEN8_PPAT_UC (0<<0)
1522 #define GEN8_PPAT_WC (1<<0)
1523 #define GEN8_PPAT_WT (2<<0)
1524 #define GEN8_PPAT_WB (3<<0)
1525 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1526 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1527 #define GEN8_PPAT_LLC (1<<2)
1528 #define GEN8_PPAT_LLCELLC (2<<2)
1529 #define GEN8_PPAT_LLCeLLC (3<<2)
1530 #define GEN8_PPAT_AGE(x) (x<<4)
1531 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1534 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1535 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1536 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1537 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1538 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1539 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1540 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1541 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1543 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1544 * write would work. */
1545 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1546 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1549 static int gen8_gmch_probe(struct drm_device *dev,
1552 phys_addr_t *mappable_base,
1553 unsigned long *mappable_end)
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 unsigned int gtt_size;
1560 /* TODO: We're not aware of mappable constraints on gen8 yet */
1561 *mappable_base = pci_resource_start(dev->pdev, 2);
1562 *mappable_end = pci_resource_len(dev->pdev, 2);
1564 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1565 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1567 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1569 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1571 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1572 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1574 gen8_setup_private_ppat(dev_priv);
1576 ret = ggtt_probe_common(dev, gtt_size);
1578 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1579 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1584 static int gen6_gmch_probe(struct drm_device *dev,
1587 phys_addr_t *mappable_base,
1588 unsigned long *mappable_end)
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591 unsigned int gtt_size;
1595 *mappable_base = pci_resource_start(dev->pdev, 2);
1596 *mappable_end = pci_resource_len(dev->pdev, 2);
1598 /* 64/512MB is the current min/max we actually know of, but this is just
1599 * a coarse sanity check.
1601 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1602 DRM_ERROR("Unknown GMADR size (%lx)\n",
1603 dev_priv->gtt.mappable_end);
1607 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1608 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1609 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1611 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1613 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1614 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1616 ret = ggtt_probe_common(dev, gtt_size);
1618 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1619 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1624 static void gen6_gmch_remove(struct i915_address_space *vm)
1627 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1629 drm_mm_takedown(&vm->mm);
1631 teardown_scratch_page(vm->dev);
1634 static int i915_gmch_probe(struct drm_device *dev,
1637 phys_addr_t *mappable_base,
1638 unsigned long *mappable_end)
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1643 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1645 DRM_ERROR("failed to set up gmch\n");
1649 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1651 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1652 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1657 static void i915_gmch_remove(struct i915_address_space *vm)
1659 intel_gmch_remove();
1662 int i915_gem_gtt_init(struct drm_device *dev)
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 struct i915_gtt *gtt = &dev_priv->gtt;
1668 if (INTEL_INFO(dev)->gen <= 5) {
1669 gtt->gtt_probe = i915_gmch_probe;
1670 gtt->base.cleanup = i915_gmch_remove;
1671 } else if (INTEL_INFO(dev)->gen < 8) {
1672 gtt->gtt_probe = gen6_gmch_probe;
1673 gtt->base.cleanup = gen6_gmch_remove;
1674 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1675 gtt->base.pte_encode = iris_pte_encode;
1676 else if (IS_HASWELL(dev))
1677 gtt->base.pte_encode = hsw_pte_encode;
1678 else if (IS_VALLEYVIEW(dev))
1679 gtt->base.pte_encode = byt_pte_encode;
1680 else if (INTEL_INFO(dev)->gen >= 7)
1681 gtt->base.pte_encode = ivb_pte_encode;
1683 gtt->base.pte_encode = snb_pte_encode;
1685 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1686 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1689 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
1690 >t->mappable_base, >t->mappable_end);
1694 gtt->base.dev = dev;
1696 /* GMADR is the PCI mmio aperture into the global GTT. */
1697 DRM_INFO("Memory usable by graphics device = %zdM\n",
1698 gtt->base.total >> 20);
1699 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1700 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1705 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
1706 struct i915_address_space *vm)
1708 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
1710 return ERR_PTR(-ENOMEM);
1712 INIT_LIST_HEAD(&vma->vma_link);
1713 INIT_LIST_HEAD(&vma->mm_list);
1714 INIT_LIST_HEAD(&vma->exec_list);
1718 switch (INTEL_INFO(vm->dev)->gen) {
1722 vma->unbind_vma = ggtt_unbind_vma;
1723 vma->bind_vma = ggtt_bind_vma;
1729 BUG_ON(!i915_is_ggtt(vm));
1730 vma->unbind_vma = i915_ggtt_unbind_vma;
1731 vma->bind_vma = i915_ggtt_bind_vma;
1737 /* Keep GGTT vmas first to make debug easier */
1738 if (i915_is_ggtt(vm))
1739 list_add(&vma->vma_link, &obj->vma_list);
1741 list_add_tail(&vma->vma_link, &obj->vma_list);
1747 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1748 struct i915_address_space *vm)
1750 struct i915_vma *vma;
1752 vma = i915_gem_obj_to_vma(obj, vm);
1754 vma = __i915_gem_vma_create(obj, vm);