2 * Copyright © 2008-2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
27 #include <linux/sched.h>
28 #include <linux/sched/clock.h>
32 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
37 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
39 return to_request(fence)->timeline->common->name;
42 static bool i915_fence_signaled(struct dma_fence *fence)
44 return i915_gem_request_completed(to_request(fence));
47 static bool i915_fence_enable_signaling(struct dma_fence *fence)
49 if (i915_fence_signaled(fence))
52 intel_engine_enable_signaling(to_request(fence));
56 static signed long i915_fence_wait(struct dma_fence *fence,
60 return i915_wait_request(to_request(fence), interruptible, timeout);
63 static void i915_fence_release(struct dma_fence *fence)
65 struct drm_i915_gem_request *req = to_request(fence);
67 /* The request is put onto a RCU freelist (i.e. the address
68 * is immediately reused), mark the fences as being freed now.
69 * Otherwise the debugobjects for the fences are only marked as
70 * freed when the slab cache itself is freed, and so we would get
71 * caught trying to reuse dead objects.
73 i915_sw_fence_fini(&req->submit);
74 i915_sw_fence_fini(&req->execute);
76 kmem_cache_free(req->i915->requests, req);
79 const struct dma_fence_ops i915_fence_ops = {
80 .get_driver_name = i915_fence_get_driver_name,
81 .get_timeline_name = i915_fence_get_timeline_name,
82 .enable_signaling = i915_fence_enable_signaling,
83 .signaled = i915_fence_signaled,
84 .wait = i915_fence_wait,
85 .release = i915_fence_release,
88 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
89 struct drm_file *file)
91 struct drm_i915_private *dev_private;
92 struct drm_i915_file_private *file_priv;
94 WARN_ON(!req || !file || req->file_priv);
102 dev_private = req->i915;
103 file_priv = file->driver_priv;
105 spin_lock(&file_priv->mm.lock);
106 req->file_priv = file_priv;
107 list_add_tail(&req->client_list, &file_priv->mm.request_list);
108 spin_unlock(&file_priv->mm.lock);
114 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
116 struct drm_i915_file_private *file_priv = request->file_priv;
121 spin_lock(&file_priv->mm.lock);
122 list_del(&request->client_list);
123 request->file_priv = NULL;
124 spin_unlock(&file_priv->mm.lock);
127 static struct i915_dependency *
128 i915_dependency_alloc(struct drm_i915_private *i915)
130 return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
134 i915_dependency_free(struct drm_i915_private *i915,
135 struct i915_dependency *dep)
137 kmem_cache_free(i915->dependencies, dep);
141 __i915_priotree_add_dependency(struct i915_priotree *pt,
142 struct i915_priotree *signal,
143 struct i915_dependency *dep,
146 INIT_LIST_HEAD(&dep->dfs_link);
147 list_add(&dep->wait_link, &signal->waiters_list);
148 list_add(&dep->signal_link, &pt->signalers_list);
149 dep->signaler = signal;
154 i915_priotree_add_dependency(struct drm_i915_private *i915,
155 struct i915_priotree *pt,
156 struct i915_priotree *signal)
158 struct i915_dependency *dep;
160 dep = i915_dependency_alloc(i915);
164 __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC);
169 i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt)
171 struct i915_dependency *dep, *next;
173 GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node));
175 /* Everyone we depended upon (the fences we wait to be signaled)
176 * should retire before us and remove themselves from our list.
177 * However, retirement is run independently on each timeline and
178 * so we may be called out-of-order.
180 list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) {
181 list_del(&dep->wait_link);
182 if (dep->flags & I915_DEPENDENCY_ALLOC)
183 i915_dependency_free(i915, dep);
186 /* Remove ourselves from everyone who depends upon us */
187 list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) {
188 list_del(&dep->signal_link);
189 if (dep->flags & I915_DEPENDENCY_ALLOC)
190 i915_dependency_free(i915, dep);
195 i915_priotree_init(struct i915_priotree *pt)
197 INIT_LIST_HEAD(&pt->signalers_list);
198 INIT_LIST_HEAD(&pt->waiters_list);
199 RB_CLEAR_NODE(&pt->node);
200 pt->priority = INT_MIN;
203 void i915_gem_retire_noop(struct i915_gem_active *active,
204 struct drm_i915_gem_request *request)
206 /* Space left intentionally blank */
209 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
211 struct intel_engine_cs *engine = request->engine;
212 struct i915_gem_active *active, *next;
214 lockdep_assert_held(&request->i915->drm.struct_mutex);
215 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
216 GEM_BUG_ON(!i915_sw_fence_signaled(&request->execute));
217 GEM_BUG_ON(!i915_gem_request_completed(request));
218 GEM_BUG_ON(!request->i915->gt.active_requests);
220 trace_i915_gem_request_retire(request);
222 spin_lock_irq(&engine->timeline->lock);
223 list_del_init(&request->link);
224 spin_unlock_irq(&engine->timeline->lock);
226 /* We know the GPU must have read the request to have
227 * sent us the seqno + interrupt, so use the position
228 * of tail of the request to update the last known position
231 * Note this requires that we are always called in request
234 list_del(&request->ring_link);
235 request->ring->last_retired_head = request->postfix;
236 if (!--request->i915->gt.active_requests) {
237 GEM_BUG_ON(!request->i915->gt.awake);
238 mod_delayed_work(request->i915->wq,
239 &request->i915->gt.idle_work,
240 msecs_to_jiffies(100));
243 /* Walk through the active list, calling retire on each. This allows
244 * objects to track their GPU activity and mark themselves as idle
245 * when their *last* active request is completed (updating state
246 * tracking lists for eviction, active references for GEM, etc).
248 * As the ->retire() may free the node, we decouple it first and
249 * pass along the auxiliary information (to avoid dereferencing
250 * the node after the callback).
252 list_for_each_entry_safe(active, next, &request->active_list, link) {
253 /* In microbenchmarks or focusing upon time inside the kernel,
254 * we may spend an inordinate amount of time simply handling
255 * the retirement of requests and processing their callbacks.
256 * Of which, this loop itself is particularly hot due to the
257 * cache misses when jumping around the list of i915_gem_active.
258 * So we try to keep this loop as streamlined as possible and
259 * also prefetch the next i915_gem_active to try and hide
260 * the likely cache miss.
264 INIT_LIST_HEAD(&active->link);
265 RCU_INIT_POINTER(active->request, NULL);
267 active->retire(active, request);
270 i915_gem_request_remove_from_client(request);
272 /* Retirement decays the ban score as it is a sign of ctx progress */
273 if (request->ctx->ban_score > 0)
274 request->ctx->ban_score--;
276 /* The backing object for the context is done after switching to the
277 * *next* context. Therefore we cannot retire the previous context until
278 * the next context has already started running. However, since we
279 * cannot take the required locks at i915_gem_request_submit() we
280 * defer the unpinning of the active context to now, retirement of
281 * the subsequent request.
283 if (engine->last_retired_context)
284 engine->context_unpin(engine, engine->last_retired_context);
285 engine->last_retired_context = request->ctx;
287 dma_fence_signal(&request->fence);
289 i915_priotree_fini(request->i915, &request->priotree);
290 i915_gem_request_put(request);
293 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
295 struct intel_engine_cs *engine = req->engine;
296 struct drm_i915_gem_request *tmp;
298 lockdep_assert_held(&req->i915->drm.struct_mutex);
299 GEM_BUG_ON(!i915_gem_request_completed(req));
301 if (list_empty(&req->link))
305 tmp = list_first_entry(&engine->timeline->requests,
308 i915_gem_request_retire(tmp);
309 } while (tmp != req);
312 static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno)
314 struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
315 struct intel_engine_cs *engine;
316 enum intel_engine_id id;
319 /* Carefully retire all requests without writing to the rings */
320 ret = i915_gem_wait_for_idle(i915,
321 I915_WAIT_INTERRUPTIBLE |
326 i915_gem_retire_requests(i915);
327 GEM_BUG_ON(i915->gt.active_requests > 1);
329 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
330 if (!i915_seqno_passed(seqno, atomic_read(&timeline->seqno))) {
331 while (intel_breadcrumbs_busy(i915))
332 cond_resched(); /* spin until threads are complete */
334 atomic_set(&timeline->seqno, seqno);
336 /* Finally reset hw state */
337 for_each_engine(engine, i915, id)
338 intel_engine_init_global_seqno(engine, seqno);
340 list_for_each_entry(timeline, &i915->gt.timelines, link) {
341 for_each_engine(engine, i915, id) {
342 struct intel_timeline *tl = &timeline->engine[id];
344 memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
351 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
353 struct drm_i915_private *dev_priv = to_i915(dev);
355 lockdep_assert_held(&dev_priv->drm.struct_mutex);
360 /* HWS page needs to be set less than what we
361 * will inject to ring
363 return i915_gem_init_global_seqno(dev_priv, seqno - 1);
366 static int reserve_global_seqno(struct drm_i915_private *i915)
368 u32 active_requests = ++i915->gt.active_requests;
369 u32 seqno = atomic_read(&i915->gt.global_timeline.seqno);
372 /* Reservation is fine until we need to wrap around */
373 if (likely(seqno + active_requests > seqno))
376 ret = i915_gem_init_global_seqno(i915, 0);
378 i915->gt.active_requests--;
385 static u32 __timeline_get_seqno(struct i915_gem_timeline *tl)
387 /* seqno only incremented under a mutex */
388 return ++tl->seqno.counter;
391 static u32 timeline_get_seqno(struct i915_gem_timeline *tl)
393 return atomic_inc_return(&tl->seqno);
396 void __i915_gem_request_submit(struct drm_i915_gem_request *request)
398 struct intel_engine_cs *engine = request->engine;
399 struct intel_timeline *timeline;
402 /* Transfer from per-context onto the global per-engine timeline */
403 timeline = engine->timeline;
404 GEM_BUG_ON(timeline == request->timeline);
405 assert_spin_locked(&timeline->lock);
407 seqno = timeline_get_seqno(timeline->common);
409 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
411 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, seqno));
412 request->previous_seqno = timeline->last_submitted_seqno;
413 timeline->last_submitted_seqno = seqno;
415 /* We may be recursing from the signal callback of another i915 fence */
416 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
417 request->global_seqno = seqno;
418 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
419 intel_engine_enable_signaling(request);
420 spin_unlock(&request->lock);
422 GEM_BUG_ON(!request->global_seqno);
423 engine->emit_breadcrumb(request,
424 request->ring->vaddr + request->postfix);
426 spin_lock(&request->timeline->lock);
427 list_move_tail(&request->link, &timeline->requests);
428 spin_unlock(&request->timeline->lock);
430 i915_sw_fence_commit(&request->execute);
433 void i915_gem_request_submit(struct drm_i915_gem_request *request)
435 struct intel_engine_cs *engine = request->engine;
438 /* Will be called from irq-context when using foreign fences. */
439 spin_lock_irqsave(&engine->timeline->lock, flags);
441 __i915_gem_request_submit(request);
443 spin_unlock_irqrestore(&engine->timeline->lock, flags);
446 static int __i915_sw_fence_call
447 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
449 struct drm_i915_gem_request *request =
450 container_of(fence, typeof(*request), submit);
454 request->engine->submit_request(request);
458 i915_gem_request_put(request);
465 static int __i915_sw_fence_call
466 execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
468 struct drm_i915_gem_request *request =
469 container_of(fence, typeof(*request), execute);
476 i915_gem_request_put(request);
484 * i915_gem_request_alloc - allocate a request structure
486 * @engine: engine that we wish to issue the request on.
487 * @ctx: context that the request will be associated with.
488 * This can be NULL if the request is not directly related to
489 * any specific user context, in which case this function will
490 * choose an appropriate context to use.
492 * Returns a pointer to the allocated request if successful,
493 * or an error code if not.
495 struct drm_i915_gem_request *
496 i915_gem_request_alloc(struct intel_engine_cs *engine,
497 struct i915_gem_context *ctx)
499 struct drm_i915_private *dev_priv = engine->i915;
500 struct drm_i915_gem_request *req;
503 lockdep_assert_held(&dev_priv->drm.struct_mutex);
505 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
506 * EIO if the GPU is already wedged.
508 if (i915_terminally_wedged(&dev_priv->gpu_error))
509 return ERR_PTR(-EIO);
511 /* Pinning the contexts may generate requests in order to acquire
512 * GGTT space, so do this first before we reserve a seqno for
515 ret = engine->context_pin(engine, ctx);
519 ret = reserve_global_seqno(dev_priv);
523 /* Move the oldest request to the slab-cache (if not in use!) */
524 req = list_first_entry_or_null(&engine->timeline->requests,
526 if (req && __i915_gem_request_completed(req))
527 i915_gem_request_retire(req);
529 /* Beware: Dragons be flying overhead.
531 * We use RCU to look up requests in flight. The lookups may
532 * race with the request being allocated from the slab freelist.
533 * That is the request we are writing to here, may be in the process
534 * of being read by __i915_gem_active_get_rcu(). As such,
535 * we have to be very careful when overwriting the contents. During
536 * the RCU lookup, we change chase the request->engine pointer,
537 * read the request->global_seqno and increment the reference count.
539 * The reference count is incremented atomically. If it is zero,
540 * the lookup knows the request is unallocated and complete. Otherwise,
541 * it is either still in use, or has been reallocated and reset
542 * with dma_fence_init(). This increment is safe for release as we
543 * check that the request we have a reference to and matches the active
546 * Before we increment the refcount, we chase the request->engine
547 * pointer. We must not call kmem_cache_zalloc() or else we set
548 * that pointer to NULL and cause a crash during the lookup. If
549 * we see the request is completed (based on the value of the
550 * old engine and seqno), the lookup is complete and reports NULL.
551 * If we decide the request is not completed (new engine or seqno),
552 * then we grab a reference and double check that it is still the
553 * active request - which it won't be and restart the lookup.
555 * Do not use kmem_cache_zalloc() here!
557 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
563 req->timeline = i915_gem_context_lookup_timeline(ctx, engine);
564 GEM_BUG_ON(req->timeline == engine->timeline);
566 spin_lock_init(&req->lock);
567 dma_fence_init(&req->fence,
570 req->timeline->fence_context,
571 __timeline_get_seqno(req->timeline->common));
573 /* We bump the ref for the fence chain */
574 i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
575 i915_sw_fence_init(&i915_gem_request_get(req)->execute, execute_notify);
577 /* Ensure that the execute fence completes after the submit fence -
578 * as we complete the execute fence from within the submit fence
579 * callback, its completion would otherwise be visible first.
581 i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq);
583 i915_priotree_init(&req->priotree);
585 INIT_LIST_HEAD(&req->active_list);
586 req->i915 = dev_priv;
587 req->engine = engine;
590 /* No zalloc, must clear what we need by hand */
591 req->global_seqno = 0;
592 req->file_priv = NULL;
596 * Reserve space in the ring buffer for all the commands required to
597 * eventually emit this request. This is to guarantee that the
598 * i915_add_request() call can't fail. Note that the reserve may need
599 * to be redone if the request is not actually submitted straight
600 * away, e.g. because a GPU scheduler has deferred it.
602 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
603 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
605 ret = engine->request_alloc(req);
609 /* Record the position of the start of the request so that
610 * should we detect the updated seqno part-way through the
611 * GPU processing the request, we never over-estimate the
612 * position of the head.
614 req->head = req->ring->tail;
619 /* Make sure we didn't add ourselves to external state before freeing */
620 GEM_BUG_ON(!list_empty(&req->active_list));
621 GEM_BUG_ON(!list_empty(&req->priotree.signalers_list));
622 GEM_BUG_ON(!list_empty(&req->priotree.waiters_list));
624 kmem_cache_free(dev_priv->requests, req);
626 dev_priv->gt.active_requests--;
628 engine->context_unpin(engine, ctx);
633 i915_gem_request_await_request(struct drm_i915_gem_request *to,
634 struct drm_i915_gem_request *from)
638 GEM_BUG_ON(to == from);
640 if (to->engine->schedule) {
641 ret = i915_priotree_add_dependency(to->i915,
648 if (to->timeline == from->timeline)
651 if (to->engine == from->engine) {
652 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
655 return ret < 0 ? ret : 0;
658 if (!from->global_seqno) {
659 ret = i915_sw_fence_await_dma_fence(&to->submit,
662 return ret < 0 ? ret : 0;
665 if (from->global_seqno <= to->timeline->sync_seqno[from->engine->id])
668 trace_i915_gem_ring_sync_to(to, from);
669 if (!i915.semaphores) {
670 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
671 ret = i915_sw_fence_await_dma_fence(&to->submit,
678 ret = to->engine->semaphore.sync_to(to, from);
683 to->timeline->sync_seqno[from->engine->id] = from->global_seqno;
688 i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
689 struct dma_fence *fence)
691 struct dma_fence_array *array;
695 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
698 if (dma_fence_is_i915(fence))
699 return i915_gem_request_await_request(req, to_request(fence));
701 if (!dma_fence_is_array(fence)) {
702 ret = i915_sw_fence_await_dma_fence(&req->submit,
703 fence, I915_FENCE_TIMEOUT,
705 return ret < 0 ? ret : 0;
708 /* Note that if the fence-array was created in signal-on-any mode,
709 * we should *not* decompose it into its individual fences. However,
710 * we don't currently store which mode the fence-array is operating
711 * in. Fortunately, the only user of signal-on-any is private to
712 * amdgpu and we should not see any incoming fence-array from
713 * sync-file being in signal-on-any mode.
716 array = to_dma_fence_array(fence);
717 for (i = 0; i < array->num_fences; i++) {
718 struct dma_fence *child = array->fences[i];
720 if (dma_fence_is_i915(child))
721 ret = i915_gem_request_await_request(req,
724 ret = i915_sw_fence_await_dma_fence(&req->submit,
725 child, I915_FENCE_TIMEOUT,
735 * i915_gem_request_await_object - set this request to (async) wait upon a bo
737 * @to: request we are wishing to use
738 * @obj: object which may be in use on another ring.
740 * This code is meant to abstract object synchronization with the GPU.
741 * Conceptually we serialise writes between engines inside the GPU.
742 * We only allow one engine to write into a buffer at any time, but
743 * multiple readers. To ensure each has a coherent view of memory, we must:
745 * - If there is an outstanding write request to the object, the new
746 * request must wait for it to complete (either CPU or in hw, requests
747 * on the same ring will be naturally ordered).
749 * - If we are a write request (pending_write_domain is set), the new
750 * request must wait for outstanding read requests to complete.
752 * Returns 0 if successful, else propagates up the lower layer error.
755 i915_gem_request_await_object(struct drm_i915_gem_request *to,
756 struct drm_i915_gem_object *obj,
759 struct dma_fence *excl;
763 struct dma_fence **shared;
764 unsigned int count, i;
766 ret = reservation_object_get_fences_rcu(obj->resv,
767 &excl, &count, &shared);
771 for (i = 0; i < count; i++) {
772 ret = i915_gem_request_await_dma_fence(to, shared[i]);
776 dma_fence_put(shared[i]);
779 for (; i < count; i++)
780 dma_fence_put(shared[i]);
783 excl = reservation_object_get_excl_rcu(obj->resv);
788 ret = i915_gem_request_await_dma_fence(to, excl);
796 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
798 struct drm_i915_private *dev_priv = engine->i915;
800 if (dev_priv->gt.awake)
803 GEM_BUG_ON(!dev_priv->gt.active_requests);
805 intel_runtime_pm_get_noresume(dev_priv);
806 dev_priv->gt.awake = true;
808 intel_enable_gt_powersave(dev_priv);
809 i915_update_gfx_val(dev_priv);
810 if (INTEL_GEN(dev_priv) >= 6)
811 gen6_rps_busy(dev_priv);
813 queue_delayed_work(dev_priv->wq,
814 &dev_priv->gt.retire_work,
815 round_jiffies_up_relative(HZ));
819 * NB: This function is not allowed to fail. Doing so would mean the the
820 * request is not being tracked for completion but the work itself is
821 * going to happen on the hardware. This would be a Bad Thing(tm).
823 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
825 struct intel_engine_cs *engine = request->engine;
826 struct intel_ring *ring = request->ring;
827 struct intel_timeline *timeline = request->timeline;
828 struct drm_i915_gem_request *prev;
831 lockdep_assert_held(&request->i915->drm.struct_mutex);
832 trace_i915_gem_request_add(request);
834 /* Make sure that no request gazumped us - if it was allocated after
835 * our i915_gem_request_alloc() and called __i915_add_request() before
836 * us, the timeline will hold its seqno which is later than ours.
838 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
839 request->fence.seqno));
842 * To ensure that this call will not fail, space for its emissions
843 * should already have been reserved in the ring buffer. Let the ring
844 * know that it is time to use that space up.
846 request->reserved_space = 0;
849 * Emit any outstanding flushes - execbuf can fail to emit the flush
850 * after having emitted the batchbuffer command. Hence we need to fix
851 * things up similar to emitting the lazy request. The difference here
852 * is that the flush _must_ happen before the next request, no matter
856 err = engine->emit_flush(request, EMIT_FLUSH);
858 /* Not allowed to fail! */
859 WARN(err, "engine->emit_flush() failed: %d!\n", err);
862 /* Record the position of the start of the breadcrumb so that
863 * should we detect the updated seqno part-way through the
864 * GPU processing the request, we never over-estimate the
865 * position of the ring's HEAD.
867 err = intel_ring_begin(request, engine->emit_breadcrumb_sz);
869 request->postfix = ring->tail;
870 ring->tail += engine->emit_breadcrumb_sz * sizeof(u32);
872 /* Seal the request and mark it as pending execution. Note that
873 * we may inspect this state, without holding any locks, during
874 * hangcheck. Hence we apply the barrier to ensure that we do not
875 * see a more recent value in the hws than we are tracking.
878 prev = i915_gem_active_raw(&timeline->last_request,
879 &request->i915->drm.struct_mutex);
881 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
883 if (engine->schedule)
884 __i915_priotree_add_dependency(&request->priotree,
890 spin_lock_irq(&timeline->lock);
891 list_add_tail(&request->link, &timeline->requests);
892 spin_unlock_irq(&timeline->lock);
894 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
895 request->fence.seqno));
897 timeline->last_submitted_seqno = request->fence.seqno;
898 i915_gem_active_set(&timeline->last_request, request);
900 list_add_tail(&request->ring_link, &ring->request_list);
901 request->emitted_jiffies = jiffies;
903 i915_gem_mark_busy(engine);
905 /* Let the backend know a new request has arrived that may need
906 * to adjust the existing execution schedule due to a high priority
907 * request - i.e. we may want to preempt the current request in order
908 * to run a high priority dependency chain *before* we can execute this
911 * This is called before the request is ready to run so that we can
912 * decide whether to preempt the entire chain so that it is ready to
913 * run at the earliest possible convenience.
915 if (engine->schedule)
916 engine->schedule(request, request->ctx->priority);
919 i915_sw_fence_commit(&request->submit);
920 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
923 static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
927 spin_lock_irqsave(&q->lock, flags);
928 if (list_empty(&wait->task_list))
929 __add_wait_queue(q, wait);
930 spin_unlock_irqrestore(&q->lock, flags);
933 static unsigned long local_clock_us(unsigned int *cpu)
937 /* Cheaply and approximately convert from nanoseconds to microseconds.
938 * The result and subsequent calculations are also defined in the same
939 * approximate microseconds units. The principal source of timing
940 * error here is from the simple truncation.
942 * Note that local_clock() is only defined wrt to the current CPU;
943 * the comparisons are no longer valid if we switch CPUs. Instead of
944 * blocking preemption for the entire busywait, we can detect the CPU
945 * switch and use that as indicator of system load and a reason to
946 * stop busywaiting, see busywait_stop().
949 t = local_clock() >> 10;
955 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
957 unsigned int this_cpu;
959 if (time_after(local_clock_us(&this_cpu), timeout))
962 return this_cpu != cpu;
965 bool __i915_spin_request(const struct drm_i915_gem_request *req,
966 int state, unsigned long timeout_us)
970 /* When waiting for high frequency requests, e.g. during synchronous
971 * rendering split between the CPU and GPU, the finite amount of time
972 * required to set up the irq and wait upon it limits the response
973 * rate. By busywaiting on the request completion for a short while we
974 * can service the high frequency waits as quick as possible. However,
975 * if it is a slow request, we want to sleep as quickly as possible.
976 * The tradeoff between waiting and sleeping is roughly the time it
977 * takes to sleep on a request, on the order of a microsecond.
980 timeout_us += local_clock_us(&cpu);
982 if (__i915_gem_request_completed(req))
985 if (signal_pending_state(state, current))
988 if (busywait_stop(timeout_us, cpu))
992 } while (!need_resched());
998 __i915_request_wait_for_execute(struct drm_i915_gem_request *request,
1002 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1003 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1004 wait_queue_head_t *q = &request->i915->gpu_error.wait_queue;
1008 if (flags & I915_WAIT_LOCKED)
1009 add_wait_queue(q, &reset);
1012 prepare_to_wait(&request->execute.wait, &wait, state);
1014 if (i915_sw_fence_done(&request->execute))
1017 if (flags & I915_WAIT_LOCKED &&
1018 i915_reset_in_progress(&request->i915->gpu_error)) {
1019 __set_current_state(TASK_RUNNING);
1020 i915_reset(request->i915);
1021 reset_wait_queue(q, &reset);
1025 if (signal_pending_state(state, current)) {
1026 timeout = -ERESTARTSYS;
1035 timeout = io_schedule_timeout(timeout);
1037 finish_wait(&request->execute.wait, &wait);
1039 if (flags & I915_WAIT_LOCKED)
1040 remove_wait_queue(q, &reset);
1046 * i915_wait_request - wait until execution of request has finished
1047 * @req: the request to wait upon
1048 * @flags: how to wait
1049 * @timeout: how long to wait in jiffies
1051 * i915_wait_request() waits for the request to be completed, for a
1052 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1055 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1056 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1057 * must not specify that the wait is locked.
1059 * Returns the remaining time (in jiffies) if the request completed, which may
1060 * be zero or -ETIME if the request is unfinished after the timeout expires.
1061 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1062 * pending before the request completes.
1064 long i915_wait_request(struct drm_i915_gem_request *req,
1068 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1069 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1071 struct intel_wait wait;
1074 #if IS_ENABLED(CONFIG_LOCKDEP)
1075 GEM_BUG_ON(debug_locks &&
1076 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
1077 !!(flags & I915_WAIT_LOCKED));
1079 GEM_BUG_ON(timeout < 0);
1081 if (i915_gem_request_completed(req))
1087 trace_i915_gem_request_wait_begin(req);
1089 if (!i915_sw_fence_done(&req->execute)) {
1090 timeout = __i915_request_wait_for_execute(req, flags, timeout);
1094 GEM_BUG_ON(!i915_sw_fence_done(&req->execute));
1096 GEM_BUG_ON(!i915_sw_fence_done(&req->submit));
1097 GEM_BUG_ON(!req->global_seqno);
1099 /* Optimistic short spin before touching IRQs */
1100 if (i915_spin_request(req, state, 5))
1103 set_current_state(state);
1104 if (flags & I915_WAIT_LOCKED)
1105 add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1107 intel_wait_init(&wait, req->global_seqno);
1108 if (intel_engine_add_wait(req->engine, &wait))
1109 /* In order to check that we haven't missed the interrupt
1110 * as we enabled it, we need to kick ourselves to do a
1111 * coherent check on the seqno before we sleep.
1116 if (signal_pending_state(state, current)) {
1117 timeout = -ERESTARTSYS;
1126 timeout = io_schedule_timeout(timeout);
1128 if (intel_wait_complete(&wait))
1131 set_current_state(state);
1134 /* Carefully check if the request is complete, giving time
1135 * for the seqno to be visible following the interrupt.
1136 * We also have to check in case we are kicked by the GPU
1137 * reset in order to drop the struct_mutex.
1139 if (__i915_request_irq_complete(req))
1142 /* If the GPU is hung, and we hold the lock, reset the GPU
1143 * and then check for completion. On a full reset, the engine's
1144 * HW seqno will be advanced passed us and we are complete.
1145 * If we do a partial reset, we have to wait for the GPU to
1146 * resume and update the breadcrumb.
1148 * If we don't hold the mutex, we can just wait for the worker
1149 * to come along and update the breadcrumb (either directly
1150 * itself, or indirectly by recovering the GPU).
1152 if (flags & I915_WAIT_LOCKED &&
1153 i915_reset_in_progress(&req->i915->gpu_error)) {
1154 __set_current_state(TASK_RUNNING);
1155 i915_reset(req->i915);
1156 reset_wait_queue(&req->i915->gpu_error.wait_queue,
1161 /* Only spin if we know the GPU is processing this request */
1162 if (i915_spin_request(req, state, 2))
1166 intel_engine_remove_wait(req->engine, &wait);
1167 if (flags & I915_WAIT_LOCKED)
1168 remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1169 __set_current_state(TASK_RUNNING);
1172 trace_i915_gem_request_wait_end(req);
1177 static void engine_retire_requests(struct intel_engine_cs *engine)
1179 struct drm_i915_gem_request *request, *next;
1181 list_for_each_entry_safe(request, next,
1182 &engine->timeline->requests, link) {
1183 if (!__i915_gem_request_completed(request))
1186 i915_gem_request_retire(request);
1190 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
1192 struct intel_engine_cs *engine;
1193 enum intel_engine_id id;
1195 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1197 if (!dev_priv->gt.active_requests)
1200 for_each_engine(engine, dev_priv, id)
1201 engine_retire_requests(engine);