1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 /* For display hotplug interrupt */
41 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
51 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
61 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63 u32 reg = PIPESTAT(pipe);
64 u32 pipestat = I915_READ(reg) & 0x7fff0000;
66 if ((pipestat & mask) == mask)
69 /* Enable the interrupt, clear any pending status */
70 pipestat |= mask | (mask >> 16);
71 I915_WRITE(reg, pipestat);
76 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
78 u32 reg = PIPESTAT(pipe);
79 u32 pipestat = I915_READ(reg) & 0x7fff0000;
81 if ((pipestat & mask) == 0)
85 I915_WRITE(reg, pipestat);
90 * intel_enable_asle - enable ASLE interrupt for OpRegion
92 void intel_enable_asle(struct drm_device *dev)
94 drm_i915_private_t *dev_priv = dev->dev_private;
95 unsigned long irqflags;
97 /* FIXME: opregion/asle for VLV */
98 if (IS_VALLEYVIEW(dev))
101 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
103 if (HAS_PCH_SPLIT(dev))
104 ironlake_enable_display_irq(dev_priv, DE_GSE);
106 i915_enable_pipestat(dev_priv, 1,
107 PIPE_LEGACY_BLC_EVENT_ENABLE);
108 if (INTEL_INFO(dev)->gen >= 4)
109 i915_enable_pipestat(dev_priv, 0,
110 PIPE_LEGACY_BLC_EVENT_ENABLE);
113 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
117 * i915_pipe_enabled - check if a pipe is enabled
119 * @pipe: pipe to check
121 * Reading certain registers when the pipe is disabled can hang the chip.
122 * Use this routine to make sure the PLL is running and the pipe is active
123 * before reading such registers if unsure.
126 i915_pipe_enabled(struct drm_device *dev, int pipe)
128 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
129 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
132 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
135 /* Called from drm generic code, passed a 'crtc', which
136 * we use as a pipe index
138 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
140 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
141 unsigned long high_frame;
142 unsigned long low_frame;
143 u32 high1, high2, low;
145 if (!i915_pipe_enabled(dev, pipe)) {
146 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
147 "pipe %c\n", pipe_name(pipe));
151 high_frame = PIPEFRAME(pipe);
152 low_frame = PIPEFRAMEPIXEL(pipe);
155 * High & low register fields aren't synchronized, so make sure
156 * we get a low value that's stable across two reads of the high
160 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
161 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
162 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
163 } while (high1 != high2);
165 high1 >>= PIPE_FRAME_HIGH_SHIFT;
166 low >>= PIPE_FRAME_LOW_SHIFT;
167 return (high1 << 8) | low;
170 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
172 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
173 int reg = PIPE_FRMCOUNT_GM45(pipe);
175 if (!i915_pipe_enabled(dev, pipe)) {
176 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
177 "pipe %c\n", pipe_name(pipe));
181 return I915_READ(reg);
184 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
185 int *vpos, int *hpos)
187 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
188 u32 vbl = 0, position = 0;
189 int vbl_start, vbl_end, htotal, vtotal;
192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
195 if (!i915_pipe_enabled(dev, pipe)) {
196 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
197 "pipe %c\n", pipe_name(pipe));
202 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
204 if (INTEL_INFO(dev)->gen >= 4) {
205 /* No obvious pixelcount register. Only query vertical
206 * scanout position from Display scan line register.
208 position = I915_READ(PIPEDSL(pipe));
210 /* Decode into vertical scanout position. Don't have
211 * horizontal scanout position.
213 *vpos = position & 0x1fff;
216 /* Have access to pixelcount since start of frame.
217 * We can split this into vertical and horizontal
220 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
222 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
223 *vpos = position / htotal;
224 *hpos = position - (*vpos * htotal);
227 /* Query vblank area. */
228 vbl = I915_READ(VBLANK(cpu_transcoder));
230 /* Test position against vblank region. */
231 vbl_start = vbl & 0x1fff;
232 vbl_end = (vbl >> 16) & 0x1fff;
234 if ((*vpos < vbl_start) || (*vpos > vbl_end))
237 /* Inside "upper part" of vblank area? Apply corrective offset: */
238 if (in_vbl && (*vpos >= vbl_start))
239 *vpos = *vpos - vtotal;
241 /* Readouts valid? */
243 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
247 ret |= DRM_SCANOUTPOS_INVBL;
252 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
254 struct timeval *vblank_time,
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 struct drm_crtc *crtc;
260 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
261 DRM_ERROR("Invalid crtc %d\n", pipe);
265 /* Get drm_crtc to timestamp: */
266 crtc = intel_get_crtc_for_pipe(dev, pipe);
268 DRM_ERROR("Invalid crtc %d\n", pipe);
272 if (!crtc->enabled) {
273 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
277 /* Helper routine in DRM core does all the work: */
278 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
284 * Handle hotplug events outside the interrupt handler proper.
286 static void i915_hotplug_work_func(struct work_struct *work)
288 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
290 struct drm_device *dev = dev_priv->dev;
291 struct drm_mode_config *mode_config = &dev->mode_config;
292 struct intel_encoder *encoder;
294 /* HPD irq before everything is fully set up. */
295 if (!dev_priv->enable_hotplug_processing)
298 mutex_lock(&mode_config->mutex);
299 DRM_DEBUG_KMS("running encoder hotplug functions\n");
301 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
302 if (encoder->hot_plug)
303 encoder->hot_plug(encoder);
305 mutex_unlock(&mode_config->mutex);
307 /* Just fire off a uevent and let userspace tell us what to do */
308 drm_helper_hpd_irq_event(dev);
311 static void ironlake_handle_rps_change(struct drm_device *dev)
313 drm_i915_private_t *dev_priv = dev->dev_private;
314 u32 busy_up, busy_down, max_avg, min_avg;
318 spin_lock_irqsave(&mchdev_lock, flags);
320 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
322 new_delay = dev_priv->ips.cur_delay;
324 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
325 busy_up = I915_READ(RCPREVBSYTUPAVG);
326 busy_down = I915_READ(RCPREVBSYTDNAVG);
327 max_avg = I915_READ(RCBMAXAVG);
328 min_avg = I915_READ(RCBMINAVG);
330 /* Handle RCS change request from hw */
331 if (busy_up > max_avg) {
332 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
333 new_delay = dev_priv->ips.cur_delay - 1;
334 if (new_delay < dev_priv->ips.max_delay)
335 new_delay = dev_priv->ips.max_delay;
336 } else if (busy_down < min_avg) {
337 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
338 new_delay = dev_priv->ips.cur_delay + 1;
339 if (new_delay > dev_priv->ips.min_delay)
340 new_delay = dev_priv->ips.min_delay;
343 if (ironlake_set_drps(dev, new_delay))
344 dev_priv->ips.cur_delay = new_delay;
346 spin_unlock_irqrestore(&mchdev_lock, flags);
351 static void notify_ring(struct drm_device *dev,
352 struct intel_ring_buffer *ring)
354 struct drm_i915_private *dev_priv = dev->dev_private;
356 if (ring->obj == NULL)
359 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
361 wake_up_all(&ring->irq_queue);
362 if (i915_enable_hangcheck) {
363 dev_priv->gpu_error.hangcheck_count = 0;
364 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
365 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
369 static void gen6_pm_rps_work(struct work_struct *work)
371 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
376 spin_lock_irq(&dev_priv->rps.lock);
377 pm_iir = dev_priv->rps.pm_iir;
378 dev_priv->rps.pm_iir = 0;
379 pm_imr = I915_READ(GEN6_PMIMR);
380 I915_WRITE(GEN6_PMIMR, 0);
381 spin_unlock_irq(&dev_priv->rps.lock);
383 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
386 mutex_lock(&dev_priv->rps.hw_lock);
388 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
389 new_delay = dev_priv->rps.cur_delay + 1;
391 new_delay = dev_priv->rps.cur_delay - 1;
393 /* sysfs frequency interfaces may have snuck in while servicing the
396 if (!(new_delay > dev_priv->rps.max_delay ||
397 new_delay < dev_priv->rps.min_delay)) {
398 gen6_set_rps(dev_priv->dev, new_delay);
401 mutex_unlock(&dev_priv->rps.hw_lock);
406 * ivybridge_parity_work - Workqueue called when a parity error interrupt
408 * @work: workqueue struct
410 * Doesn't actually do anything except notify userspace. As a consequence of
411 * this event, userspace should try to remap the bad rows since statistically
412 * it is likely the same row is more likely to go bad again.
414 static void ivybridge_parity_work(struct work_struct *work)
416 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
417 l3_parity.error_work);
418 u32 error_status, row, bank, subbank;
419 char *parity_event[5];
423 /* We must turn off DOP level clock gating to access the L3 registers.
424 * In order to prevent a get/put style interface, acquire struct mutex
425 * any time we access those registers.
427 mutex_lock(&dev_priv->dev->struct_mutex);
429 misccpctl = I915_READ(GEN7_MISCCPCTL);
430 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
431 POSTING_READ(GEN7_MISCCPCTL);
433 error_status = I915_READ(GEN7_L3CDERRST1);
434 row = GEN7_PARITY_ERROR_ROW(error_status);
435 bank = GEN7_PARITY_ERROR_BANK(error_status);
436 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
438 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
439 GEN7_L3CDERRST1_ENABLE);
440 POSTING_READ(GEN7_L3CDERRST1);
442 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
444 spin_lock_irqsave(&dev_priv->irq_lock, flags);
445 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
446 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
447 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
449 mutex_unlock(&dev_priv->dev->struct_mutex);
451 parity_event[0] = "L3_PARITY_ERROR=1";
452 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
453 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
454 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
455 parity_event[4] = NULL;
457 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
458 KOBJ_CHANGE, parity_event);
460 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
463 kfree(parity_event[3]);
464 kfree(parity_event[2]);
465 kfree(parity_event[1]);
468 static void ivybridge_handle_parity_error(struct drm_device *dev)
470 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
473 if (!HAS_L3_GPU_CACHE(dev))
476 spin_lock_irqsave(&dev_priv->irq_lock, flags);
477 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
478 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
479 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
481 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
484 static void snb_gt_irq_handler(struct drm_device *dev,
485 struct drm_i915_private *dev_priv,
489 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
490 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
491 notify_ring(dev, &dev_priv->ring[RCS]);
492 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
493 notify_ring(dev, &dev_priv->ring[VCS]);
494 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
495 notify_ring(dev, &dev_priv->ring[BCS]);
497 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
498 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
499 GT_RENDER_CS_ERROR_INTERRUPT)) {
500 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
501 i915_handle_error(dev, false);
504 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
505 ivybridge_handle_parity_error(dev);
508 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
514 * IIR bits should never already be set because IMR should
515 * prevent an interrupt from being shown in IIR. The warning
516 * displays a case where we've unsafely cleared
517 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
518 * type is not a problem, it displays a problem in the logic.
520 * The mask bit in IMR is cleared by dev_priv->rps.work.
523 spin_lock_irqsave(&dev_priv->rps.lock, flags);
524 dev_priv->rps.pm_iir |= pm_iir;
525 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
526 POSTING_READ(GEN6_PMIMR);
527 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
529 queue_work(dev_priv->wq, &dev_priv->rps.work);
532 static void gmbus_irq_handler(struct drm_device *dev)
534 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
536 wake_up_all(&dev_priv->gmbus_wait_queue);
539 static void dp_aux_irq_handler(struct drm_device *dev)
541 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
543 wake_up_all(&dev_priv->gmbus_wait_queue);
546 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
548 struct drm_device *dev = (struct drm_device *) arg;
549 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
550 u32 iir, gt_iir, pm_iir;
551 irqreturn_t ret = IRQ_NONE;
552 unsigned long irqflags;
554 u32 pipe_stats[I915_MAX_PIPES];
556 atomic_inc(&dev_priv->irq_received);
559 iir = I915_READ(VLV_IIR);
560 gt_iir = I915_READ(GTIIR);
561 pm_iir = I915_READ(GEN6_PMIIR);
563 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
568 snb_gt_irq_handler(dev, dev_priv, gt_iir);
570 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
571 for_each_pipe(pipe) {
572 int reg = PIPESTAT(pipe);
573 pipe_stats[pipe] = I915_READ(reg);
576 * Clear the PIPE*STAT regs before the IIR
578 if (pipe_stats[pipe] & 0x8000ffff) {
579 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
580 DRM_DEBUG_DRIVER("pipe %c underrun\n",
582 I915_WRITE(reg, pipe_stats[pipe]);
585 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
587 for_each_pipe(pipe) {
588 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
589 drm_handle_vblank(dev, pipe);
591 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
592 intel_prepare_page_flip(dev, pipe);
593 intel_finish_page_flip(dev, pipe);
597 /* Consume port. Then clear IIR or we'll miss events */
598 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
599 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
601 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
603 if (hotplug_status & dev_priv->hotplug_supported_mask)
604 queue_work(dev_priv->wq,
605 &dev_priv->hotplug_work);
607 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
608 I915_READ(PORT_HOTPLUG_STAT);
611 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
612 gmbus_irq_handler(dev);
614 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
615 gen6_queue_rps_work(dev_priv, pm_iir);
617 I915_WRITE(GTIIR, gt_iir);
618 I915_WRITE(GEN6_PMIIR, pm_iir);
619 I915_WRITE(VLV_IIR, iir);
626 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
628 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
631 if (pch_iir & SDE_HOTPLUG_MASK)
632 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
634 if (pch_iir & SDE_AUDIO_POWER_MASK)
635 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
636 (pch_iir & SDE_AUDIO_POWER_MASK) >>
637 SDE_AUDIO_POWER_SHIFT);
639 if (pch_iir & SDE_AUX_MASK)
640 dp_aux_irq_handler(dev);
642 if (pch_iir & SDE_GMBUS)
643 gmbus_irq_handler(dev);
645 if (pch_iir & SDE_AUDIO_HDCP_MASK)
646 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
648 if (pch_iir & SDE_AUDIO_TRANS_MASK)
649 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
651 if (pch_iir & SDE_POISON)
652 DRM_ERROR("PCH poison interrupt\n");
654 if (pch_iir & SDE_FDI_MASK)
656 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
658 I915_READ(FDI_RX_IIR(pipe)));
660 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
661 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
663 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
664 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
666 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
667 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
668 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
669 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
672 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
674 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
677 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
678 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
680 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
681 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
682 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
683 SDE_AUDIO_POWER_SHIFT_CPT);
685 if (pch_iir & SDE_AUX_MASK_CPT)
686 dp_aux_irq_handler(dev);
688 if (pch_iir & SDE_GMBUS_CPT)
689 gmbus_irq_handler(dev);
691 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
692 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
694 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
695 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
697 if (pch_iir & SDE_FDI_MASK_CPT)
699 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
701 I915_READ(FDI_RX_IIR(pipe)));
704 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
706 struct drm_device *dev = (struct drm_device *) arg;
707 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
708 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
709 irqreturn_t ret = IRQ_NONE;
712 atomic_inc(&dev_priv->irq_received);
714 /* disable master interrupt before clearing iir */
715 de_ier = I915_READ(DEIER);
716 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
718 /* Disable south interrupts. We'll only write to SDEIIR once, so further
719 * interrupts will will be stored on its back queue, and then we'll be
720 * able to process them after we restore SDEIER (as soon as we restore
721 * it, we'll get an interrupt if SDEIIR still has something to process
722 * due to its back queue). */
723 sde_ier = I915_READ(SDEIER);
724 I915_WRITE(SDEIER, 0);
725 POSTING_READ(SDEIER);
727 gt_iir = I915_READ(GTIIR);
729 snb_gt_irq_handler(dev, dev_priv, gt_iir);
730 I915_WRITE(GTIIR, gt_iir);
734 de_iir = I915_READ(DEIIR);
736 if (de_iir & DE_AUX_CHANNEL_A_IVB)
737 dp_aux_irq_handler(dev);
739 if (de_iir & DE_GSE_IVB)
740 intel_opregion_gse_intr(dev);
742 for (i = 0; i < 3; i++) {
743 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
744 drm_handle_vblank(dev, i);
745 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
746 intel_prepare_page_flip(dev, i);
747 intel_finish_page_flip_plane(dev, i);
751 /* check event from PCH */
752 if (de_iir & DE_PCH_EVENT_IVB) {
753 u32 pch_iir = I915_READ(SDEIIR);
755 cpt_irq_handler(dev, pch_iir);
757 /* clear PCH hotplug event before clear CPU irq */
758 I915_WRITE(SDEIIR, pch_iir);
761 I915_WRITE(DEIIR, de_iir);
765 pm_iir = I915_READ(GEN6_PMIIR);
767 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
768 gen6_queue_rps_work(dev_priv, pm_iir);
769 I915_WRITE(GEN6_PMIIR, pm_iir);
773 I915_WRITE(DEIER, de_ier);
775 I915_WRITE(SDEIER, sde_ier);
776 POSTING_READ(SDEIER);
781 static void ilk_gt_irq_handler(struct drm_device *dev,
782 struct drm_i915_private *dev_priv,
785 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
786 notify_ring(dev, &dev_priv->ring[RCS]);
787 if (gt_iir & GT_BSD_USER_INTERRUPT)
788 notify_ring(dev, &dev_priv->ring[VCS]);
791 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
793 struct drm_device *dev = (struct drm_device *) arg;
794 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
796 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
798 atomic_inc(&dev_priv->irq_received);
800 /* disable master interrupt before clearing iir */
801 de_ier = I915_READ(DEIER);
802 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
805 /* Disable south interrupts. We'll only write to SDEIIR once, so further
806 * interrupts will will be stored on its back queue, and then we'll be
807 * able to process them after we restore SDEIER (as soon as we restore
808 * it, we'll get an interrupt if SDEIIR still has something to process
809 * due to its back queue). */
810 sde_ier = I915_READ(SDEIER);
811 I915_WRITE(SDEIER, 0);
812 POSTING_READ(SDEIER);
814 de_iir = I915_READ(DEIIR);
815 gt_iir = I915_READ(GTIIR);
816 pm_iir = I915_READ(GEN6_PMIIR);
818 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
824 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
826 snb_gt_irq_handler(dev, dev_priv, gt_iir);
828 if (de_iir & DE_AUX_CHANNEL_A)
829 dp_aux_irq_handler(dev);
832 intel_opregion_gse_intr(dev);
834 if (de_iir & DE_PIPEA_VBLANK)
835 drm_handle_vblank(dev, 0);
837 if (de_iir & DE_PIPEB_VBLANK)
838 drm_handle_vblank(dev, 1);
840 if (de_iir & DE_PLANEA_FLIP_DONE) {
841 intel_prepare_page_flip(dev, 0);
842 intel_finish_page_flip_plane(dev, 0);
845 if (de_iir & DE_PLANEB_FLIP_DONE) {
846 intel_prepare_page_flip(dev, 1);
847 intel_finish_page_flip_plane(dev, 1);
850 /* check event from PCH */
851 if (de_iir & DE_PCH_EVENT) {
852 u32 pch_iir = I915_READ(SDEIIR);
854 if (HAS_PCH_CPT(dev))
855 cpt_irq_handler(dev, pch_iir);
857 ibx_irq_handler(dev, pch_iir);
859 /* should clear PCH hotplug event before clear CPU irq */
860 I915_WRITE(SDEIIR, pch_iir);
863 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
864 ironlake_handle_rps_change(dev);
866 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
867 gen6_queue_rps_work(dev_priv, pm_iir);
869 I915_WRITE(GTIIR, gt_iir);
870 I915_WRITE(DEIIR, de_iir);
871 I915_WRITE(GEN6_PMIIR, pm_iir);
874 I915_WRITE(DEIER, de_ier);
876 I915_WRITE(SDEIER, sde_ier);
877 POSTING_READ(SDEIER);
883 * i915_error_work_func - do process context error handling work
886 * Fire an error uevent so userspace can see that a hang or error
889 static void i915_error_work_func(struct work_struct *work)
891 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
893 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
895 struct drm_device *dev = dev_priv->dev;
896 struct intel_ring_buffer *ring;
897 char *error_event[] = { "ERROR=1", NULL };
898 char *reset_event[] = { "RESET=1", NULL };
899 char *reset_done_event[] = { "ERROR=0", NULL };
902 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
905 * Note that there's only one work item which does gpu resets, so we
906 * need not worry about concurrent gpu resets potentially incrementing
907 * error->reset_counter twice. We only need to take care of another
908 * racing irq/hangcheck declaring the gpu dead for a second time. A
909 * quick check for that is good enough: schedule_work ensures the
910 * correct ordering between hang detection and this work item, and since
911 * the reset in-progress bit is only ever set by code outside of this
912 * work we don't need to worry about any other races.
914 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
915 DRM_DEBUG_DRIVER("resetting chip\n");
916 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
919 ret = i915_reset(dev);
923 * After all the gem state is reset, increment the reset
924 * counter and wake up everyone waiting for the reset to
927 * Since unlock operations are a one-sided barrier only,
928 * we need to insert a barrier here to order any seqno
930 * the counter increment.
932 smp_mb__before_atomic_inc();
933 atomic_inc(&dev_priv->gpu_error.reset_counter);
935 kobject_uevent_env(&dev->primary->kdev.kobj,
936 KOBJ_CHANGE, reset_done_event);
938 atomic_set(&error->reset_counter, I915_WEDGED);
941 for_each_ring(ring, dev_priv, i)
942 wake_up_all(&ring->irq_queue);
944 intel_display_handle_reset(dev);
946 wake_up_all(&dev_priv->gpu_error.reset_queue);
950 /* NB: please notice the memset */
951 static void i915_get_extra_instdone(struct drm_device *dev,
954 struct drm_i915_private *dev_priv = dev->dev_private;
955 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
957 switch(INTEL_INFO(dev)->gen) {
960 instdone[0] = I915_READ(INSTDONE);
965 instdone[0] = I915_READ(INSTDONE_I965);
966 instdone[1] = I915_READ(INSTDONE1);
969 WARN_ONCE(1, "Unsupported platform\n");
971 instdone[0] = I915_READ(GEN7_INSTDONE_1);
972 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
973 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
974 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
979 #ifdef CONFIG_DEBUG_FS
980 static struct drm_i915_error_object *
981 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
982 struct drm_i915_gem_object *src,
985 struct drm_i915_error_object *dst;
989 if (src == NULL || src->pages == NULL)
992 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
996 reloc_offset = src->gtt_offset;
997 for (i = 0; i < num_pages; i++) {
1001 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1005 local_irq_save(flags);
1006 if (reloc_offset < dev_priv->gtt.mappable_end &&
1007 src->has_global_gtt_mapping) {
1010 /* Simply ignore tiling or any overlapping fence.
1011 * It's part of the error state, and this hopefully
1012 * captures what the GPU read.
1015 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1017 memcpy_fromio(d, s, PAGE_SIZE);
1018 io_mapping_unmap_atomic(s);
1019 } else if (src->stolen) {
1020 unsigned long offset;
1022 offset = dev_priv->mm.stolen_base;
1023 offset += src->stolen->start;
1024 offset += i << PAGE_SHIFT;
1026 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1031 page = i915_gem_object_get_page(src, i);
1033 drm_clflush_pages(&page, 1);
1035 s = kmap_atomic(page);
1036 memcpy(d, s, PAGE_SIZE);
1039 drm_clflush_pages(&page, 1);
1041 local_irq_restore(flags);
1045 reloc_offset += PAGE_SIZE;
1047 dst->page_count = num_pages;
1048 dst->gtt_offset = src->gtt_offset;
1054 kfree(dst->pages[i]);
1058 #define i915_error_object_create(dev_priv, src) \
1059 i915_error_object_create_sized((dev_priv), (src), \
1060 (src)->base.size>>PAGE_SHIFT)
1063 i915_error_object_free(struct drm_i915_error_object *obj)
1070 for (page = 0; page < obj->page_count; page++)
1071 kfree(obj->pages[page]);
1077 i915_error_state_free(struct kref *error_ref)
1079 struct drm_i915_error_state *error = container_of(error_ref,
1080 typeof(*error), ref);
1083 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1084 i915_error_object_free(error->ring[i].batchbuffer);
1085 i915_error_object_free(error->ring[i].ringbuffer);
1086 kfree(error->ring[i].requests);
1089 kfree(error->active_bo);
1090 kfree(error->overlay);
1093 static void capture_bo(struct drm_i915_error_buffer *err,
1094 struct drm_i915_gem_object *obj)
1096 err->size = obj->base.size;
1097 err->name = obj->base.name;
1098 err->rseqno = obj->last_read_seqno;
1099 err->wseqno = obj->last_write_seqno;
1100 err->gtt_offset = obj->gtt_offset;
1101 err->read_domains = obj->base.read_domains;
1102 err->write_domain = obj->base.write_domain;
1103 err->fence_reg = obj->fence_reg;
1105 if (obj->pin_count > 0)
1107 if (obj->user_pin_count > 0)
1109 err->tiling = obj->tiling_mode;
1110 err->dirty = obj->dirty;
1111 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1112 err->ring = obj->ring ? obj->ring->id : -1;
1113 err->cache_level = obj->cache_level;
1116 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1117 int count, struct list_head *head)
1119 struct drm_i915_gem_object *obj;
1122 list_for_each_entry(obj, head, mm_list) {
1123 capture_bo(err++, obj);
1131 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1132 int count, struct list_head *head)
1134 struct drm_i915_gem_object *obj;
1137 list_for_each_entry(obj, head, gtt_list) {
1138 if (obj->pin_count == 0)
1141 capture_bo(err++, obj);
1149 static void i915_gem_record_fences(struct drm_device *dev,
1150 struct drm_i915_error_state *error)
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1156 switch (INTEL_INFO(dev)->gen) {
1159 for (i = 0; i < 16; i++)
1160 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1164 for (i = 0; i < 16; i++)
1165 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1168 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1169 for (i = 0; i < 8; i++)
1170 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1172 for (i = 0; i < 8; i++)
1173 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1181 static struct drm_i915_error_object *
1182 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1183 struct intel_ring_buffer *ring)
1185 struct drm_i915_gem_object *obj;
1188 if (!ring->get_seqno)
1191 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1192 u32 acthd = I915_READ(ACTHD);
1194 if (WARN_ON(ring->id != RCS))
1197 obj = ring->private;
1198 if (acthd >= obj->gtt_offset &&
1199 acthd < obj->gtt_offset + obj->base.size)
1200 return i915_error_object_create(dev_priv, obj);
1203 seqno = ring->get_seqno(ring, false);
1204 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1205 if (obj->ring != ring)
1208 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1211 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1214 /* We need to copy these to an anonymous buffer as the simplest
1215 * method to avoid being overwritten by userspace.
1217 return i915_error_object_create(dev_priv, obj);
1223 static void i915_record_ring_state(struct drm_device *dev,
1224 struct drm_i915_error_state *error,
1225 struct intel_ring_buffer *ring)
1227 struct drm_i915_private *dev_priv = dev->dev_private;
1229 if (INTEL_INFO(dev)->gen >= 6) {
1230 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1231 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1232 error->semaphore_mboxes[ring->id][0]
1233 = I915_READ(RING_SYNC_0(ring->mmio_base));
1234 error->semaphore_mboxes[ring->id][1]
1235 = I915_READ(RING_SYNC_1(ring->mmio_base));
1236 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1237 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1240 if (INTEL_INFO(dev)->gen >= 4) {
1241 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1242 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1243 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1244 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1245 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1246 if (ring->id == RCS)
1247 error->bbaddr = I915_READ64(BB_ADDR);
1249 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1250 error->ipeir[ring->id] = I915_READ(IPEIR);
1251 error->ipehr[ring->id] = I915_READ(IPEHR);
1252 error->instdone[ring->id] = I915_READ(INSTDONE);
1255 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1256 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1257 error->seqno[ring->id] = ring->get_seqno(ring, false);
1258 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1259 error->head[ring->id] = I915_READ_HEAD(ring);
1260 error->tail[ring->id] = I915_READ_TAIL(ring);
1261 error->ctl[ring->id] = I915_READ_CTL(ring);
1263 error->cpu_ring_head[ring->id] = ring->head;
1264 error->cpu_ring_tail[ring->id] = ring->tail;
1268 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1269 struct drm_i915_error_state *error,
1270 struct drm_i915_error_ring *ering)
1272 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1273 struct drm_i915_gem_object *obj;
1275 /* Currently render ring is the only HW context user */
1276 if (ring->id != RCS || !error->ccid)
1279 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1280 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1281 ering->ctx = i915_error_object_create_sized(dev_priv,
1287 static void i915_gem_record_rings(struct drm_device *dev,
1288 struct drm_i915_error_state *error)
1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 struct intel_ring_buffer *ring;
1292 struct drm_i915_gem_request *request;
1295 for_each_ring(ring, dev_priv, i) {
1296 i915_record_ring_state(dev, error, ring);
1298 error->ring[i].batchbuffer =
1299 i915_error_first_batchbuffer(dev_priv, ring);
1301 error->ring[i].ringbuffer =
1302 i915_error_object_create(dev_priv, ring->obj);
1305 i915_gem_record_active_context(ring, error, &error->ring[i]);
1308 list_for_each_entry(request, &ring->request_list, list)
1311 error->ring[i].num_requests = count;
1312 error->ring[i].requests =
1313 kmalloc(count*sizeof(struct drm_i915_error_request),
1315 if (error->ring[i].requests == NULL) {
1316 error->ring[i].num_requests = 0;
1321 list_for_each_entry(request, &ring->request_list, list) {
1322 struct drm_i915_error_request *erq;
1324 erq = &error->ring[i].requests[count++];
1325 erq->seqno = request->seqno;
1326 erq->jiffies = request->emitted_jiffies;
1327 erq->tail = request->tail;
1333 * i915_capture_error_state - capture an error record for later analysis
1336 * Should be called when an error is detected (either a hang or an error
1337 * interrupt) to capture error state from the time of the error. Fills
1338 * out a structure which becomes available in debugfs for user level tools
1341 static void i915_capture_error_state(struct drm_device *dev)
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 struct drm_i915_gem_object *obj;
1345 struct drm_i915_error_state *error;
1346 unsigned long flags;
1349 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1350 error = dev_priv->gpu_error.first_error;
1351 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1355 /* Account for pipe specific data like PIPE*STAT */
1356 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1358 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1362 DRM_INFO("capturing error event; look for more information in "
1363 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1364 dev->primary->index);
1366 kref_init(&error->ref);
1367 error->eir = I915_READ(EIR);
1368 error->pgtbl_er = I915_READ(PGTBL_ER);
1369 if (HAS_HW_CONTEXTS(dev))
1370 error->ccid = I915_READ(CCID);
1372 if (HAS_PCH_SPLIT(dev))
1373 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1374 else if (IS_VALLEYVIEW(dev))
1375 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1376 else if (IS_GEN2(dev))
1377 error->ier = I915_READ16(IER);
1379 error->ier = I915_READ(IER);
1381 if (INTEL_INFO(dev)->gen >= 6)
1382 error->derrmr = I915_READ(DERRMR);
1384 if (IS_VALLEYVIEW(dev))
1385 error->forcewake = I915_READ(FORCEWAKE_VLV);
1386 else if (INTEL_INFO(dev)->gen >= 7)
1387 error->forcewake = I915_READ(FORCEWAKE_MT);
1388 else if (INTEL_INFO(dev)->gen == 6)
1389 error->forcewake = I915_READ(FORCEWAKE);
1392 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1394 if (INTEL_INFO(dev)->gen >= 6) {
1395 error->error = I915_READ(ERROR_GEN6);
1396 error->done_reg = I915_READ(DONE_REG);
1399 if (INTEL_INFO(dev)->gen == 7)
1400 error->err_int = I915_READ(GEN7_ERR_INT);
1402 i915_get_extra_instdone(dev, error->extra_instdone);
1404 i915_gem_record_fences(dev, error);
1405 i915_gem_record_rings(dev, error);
1407 /* Record buffers on the active and pinned lists. */
1408 error->active_bo = NULL;
1409 error->pinned_bo = NULL;
1412 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1414 error->active_bo_count = i;
1415 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1418 error->pinned_bo_count = i - error->active_bo_count;
1420 error->active_bo = NULL;
1421 error->pinned_bo = NULL;
1423 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1425 if (error->active_bo)
1427 error->active_bo + error->active_bo_count;
1430 if (error->active_bo)
1431 error->active_bo_count =
1432 capture_active_bo(error->active_bo,
1433 error->active_bo_count,
1434 &dev_priv->mm.active_list);
1436 if (error->pinned_bo)
1437 error->pinned_bo_count =
1438 capture_pinned_bo(error->pinned_bo,
1439 error->pinned_bo_count,
1440 &dev_priv->mm.bound_list);
1442 do_gettimeofday(&error->time);
1444 error->overlay = intel_overlay_capture_error_state(dev);
1445 error->display = intel_display_capture_error_state(dev);
1447 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1448 if (dev_priv->gpu_error.first_error == NULL) {
1449 dev_priv->gpu_error.first_error = error;
1452 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1455 i915_error_state_free(&error->ref);
1458 void i915_destroy_error_state(struct drm_device *dev)
1460 struct drm_i915_private *dev_priv = dev->dev_private;
1461 struct drm_i915_error_state *error;
1462 unsigned long flags;
1464 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1465 error = dev_priv->gpu_error.first_error;
1466 dev_priv->gpu_error.first_error = NULL;
1467 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1470 kref_put(&error->ref, i915_error_state_free);
1473 #define i915_capture_error_state(x)
1476 static void i915_report_and_clear_eir(struct drm_device *dev)
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1479 uint32_t instdone[I915_NUM_INSTDONE_REG];
1480 u32 eir = I915_READ(EIR);
1486 pr_err("render error detected, EIR: 0x%08x\n", eir);
1488 i915_get_extra_instdone(dev, instdone);
1491 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1492 u32 ipeir = I915_READ(IPEIR_I965);
1494 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1495 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1496 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1497 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1498 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1499 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1500 I915_WRITE(IPEIR_I965, ipeir);
1501 POSTING_READ(IPEIR_I965);
1503 if (eir & GM45_ERROR_PAGE_TABLE) {
1504 u32 pgtbl_err = I915_READ(PGTBL_ER);
1505 pr_err("page table error\n");
1506 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1507 I915_WRITE(PGTBL_ER, pgtbl_err);
1508 POSTING_READ(PGTBL_ER);
1512 if (!IS_GEN2(dev)) {
1513 if (eir & I915_ERROR_PAGE_TABLE) {
1514 u32 pgtbl_err = I915_READ(PGTBL_ER);
1515 pr_err("page table error\n");
1516 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1517 I915_WRITE(PGTBL_ER, pgtbl_err);
1518 POSTING_READ(PGTBL_ER);
1522 if (eir & I915_ERROR_MEMORY_REFRESH) {
1523 pr_err("memory refresh error:\n");
1525 pr_err("pipe %c stat: 0x%08x\n",
1526 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1527 /* pipestat has already been acked */
1529 if (eir & I915_ERROR_INSTRUCTION) {
1530 pr_err("instruction error\n");
1531 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1532 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1533 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1534 if (INTEL_INFO(dev)->gen < 4) {
1535 u32 ipeir = I915_READ(IPEIR);
1537 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1538 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1539 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1540 I915_WRITE(IPEIR, ipeir);
1541 POSTING_READ(IPEIR);
1543 u32 ipeir = I915_READ(IPEIR_I965);
1545 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1546 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1547 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1548 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1549 I915_WRITE(IPEIR_I965, ipeir);
1550 POSTING_READ(IPEIR_I965);
1554 I915_WRITE(EIR, eir);
1556 eir = I915_READ(EIR);
1559 * some errors might have become stuck,
1562 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1563 I915_WRITE(EMR, I915_READ(EMR) | eir);
1564 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1569 * i915_handle_error - handle an error interrupt
1572 * Do some basic checking of regsiter state at error interrupt time and
1573 * dump it to the syslog. Also call i915_capture_error_state() to make
1574 * sure we get a record and make it available in debugfs. Fire a uevent
1575 * so userspace knows something bad happened (should trigger collection
1576 * of a ring dump etc.).
1578 void i915_handle_error(struct drm_device *dev, bool wedged)
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 struct intel_ring_buffer *ring;
1584 i915_capture_error_state(dev);
1585 i915_report_and_clear_eir(dev);
1588 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1589 &dev_priv->gpu_error.reset_counter);
1592 * Wakeup waiting processes so that the reset work item
1593 * doesn't deadlock trying to grab various locks.
1595 for_each_ring(ring, dev_priv, i)
1596 wake_up_all(&ring->irq_queue);
1599 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1602 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1604 drm_i915_private_t *dev_priv = dev->dev_private;
1605 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1607 struct drm_i915_gem_object *obj;
1608 struct intel_unpin_work *work;
1609 unsigned long flags;
1610 bool stall_detected;
1612 /* Ignore early vblank irqs */
1613 if (intel_crtc == NULL)
1616 spin_lock_irqsave(&dev->event_lock, flags);
1617 work = intel_crtc->unpin_work;
1620 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1621 !work->enable_stall_check) {
1622 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1623 spin_unlock_irqrestore(&dev->event_lock, flags);
1627 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1628 obj = work->pending_flip_obj;
1629 if (INTEL_INFO(dev)->gen >= 4) {
1630 int dspsurf = DSPSURF(intel_crtc->plane);
1631 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1634 int dspaddr = DSPADDR(intel_crtc->plane);
1635 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1636 crtc->y * crtc->fb->pitches[0] +
1637 crtc->x * crtc->fb->bits_per_pixel/8);
1640 spin_unlock_irqrestore(&dev->event_lock, flags);
1642 if (stall_detected) {
1643 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1644 intel_prepare_page_flip(dev, intel_crtc->plane);
1648 /* Called from drm generic code, passed 'crtc' which
1649 * we use as a pipe index
1651 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1653 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1654 unsigned long irqflags;
1656 if (!i915_pipe_enabled(dev, pipe))
1659 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1660 if (INTEL_INFO(dev)->gen >= 4)
1661 i915_enable_pipestat(dev_priv, pipe,
1662 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1664 i915_enable_pipestat(dev_priv, pipe,
1665 PIPE_VBLANK_INTERRUPT_ENABLE);
1667 /* maintain vblank delivery even in deep C-states */
1668 if (dev_priv->info->gen == 3)
1669 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1670 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1675 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1677 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1678 unsigned long irqflags;
1680 if (!i915_pipe_enabled(dev, pipe))
1683 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1684 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1685 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1686 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1691 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1693 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1694 unsigned long irqflags;
1696 if (!i915_pipe_enabled(dev, pipe))
1699 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1700 ironlake_enable_display_irq(dev_priv,
1701 DE_PIPEA_VBLANK_IVB << (5 * pipe));
1702 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1707 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1709 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1710 unsigned long irqflags;
1713 if (!i915_pipe_enabled(dev, pipe))
1716 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1717 imr = I915_READ(VLV_IMR);
1719 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1721 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1722 I915_WRITE(VLV_IMR, imr);
1723 i915_enable_pipestat(dev_priv, pipe,
1724 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1725 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1730 /* Called from drm generic code, passed 'crtc' which
1731 * we use as a pipe index
1733 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1735 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1736 unsigned long irqflags;
1738 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1739 if (dev_priv->info->gen == 3)
1740 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1742 i915_disable_pipestat(dev_priv, pipe,
1743 PIPE_VBLANK_INTERRUPT_ENABLE |
1744 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1745 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1748 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1750 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1751 unsigned long irqflags;
1753 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1754 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1755 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1756 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1759 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1761 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1762 unsigned long irqflags;
1764 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1765 ironlake_disable_display_irq(dev_priv,
1766 DE_PIPEA_VBLANK_IVB << (pipe * 5));
1767 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1770 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1772 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1773 unsigned long irqflags;
1776 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1777 i915_disable_pipestat(dev_priv, pipe,
1778 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1779 imr = I915_READ(VLV_IMR);
1781 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1783 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1784 I915_WRITE(VLV_IMR, imr);
1785 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1789 ring_last_seqno(struct intel_ring_buffer *ring)
1791 return list_entry(ring->request_list.prev,
1792 struct drm_i915_gem_request, list)->seqno;
1795 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1797 if (list_empty(&ring->request_list) ||
1798 i915_seqno_passed(ring->get_seqno(ring, false),
1799 ring_last_seqno(ring))) {
1800 /* Issue a wake-up to catch stuck h/w. */
1801 if (waitqueue_active(&ring->irq_queue)) {
1802 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1804 wake_up_all(&ring->irq_queue);
1812 static bool semaphore_passed(struct intel_ring_buffer *ring)
1814 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1815 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1816 struct intel_ring_buffer *signaller;
1817 u32 cmd, ipehr, acthd_min;
1819 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1820 if ((ipehr & ~(0x3 << 16)) !=
1821 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1824 /* ACTHD is likely pointing to the dword after the actual command,
1825 * so scan backwards until we find the MBOX.
1827 acthd_min = max((int)acthd - 3 * 4, 0);
1829 cmd = ioread32(ring->virtual_start + acthd);
1834 if (acthd < acthd_min)
1838 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1839 return i915_seqno_passed(signaller->get_seqno(signaller, false),
1840 ioread32(ring->virtual_start+acthd+4)+1);
1843 static bool kick_ring(struct intel_ring_buffer *ring)
1845 struct drm_device *dev = ring->dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
1847 u32 tmp = I915_READ_CTL(ring);
1848 if (tmp & RING_WAIT) {
1849 DRM_ERROR("Kicking stuck wait on %s\n",
1851 I915_WRITE_CTL(ring, tmp);
1855 if (INTEL_INFO(dev)->gen >= 6 &&
1856 tmp & RING_WAIT_SEMAPHORE &&
1857 semaphore_passed(ring)) {
1858 DRM_ERROR("Kicking stuck semaphore on %s\n",
1860 I915_WRITE_CTL(ring, tmp);
1866 static bool i915_hangcheck_hung(struct drm_device *dev)
1868 drm_i915_private_t *dev_priv = dev->dev_private;
1870 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1873 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1874 i915_handle_error(dev, true);
1876 if (!IS_GEN2(dev)) {
1877 struct intel_ring_buffer *ring;
1880 /* Is the chip hanging on a WAIT_FOR_EVENT?
1881 * If so we can simply poke the RB_WAIT bit
1882 * and break the hang. This should work on
1883 * all but the second generation chipsets.
1885 for_each_ring(ring, dev_priv, i)
1886 hung &= !kick_ring(ring);
1896 * This is called when the chip hasn't reported back with completed
1897 * batchbuffers in a long time. The first time this is called we simply record
1898 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1899 * again, we assume the chip is wedged and try to fix it.
1901 void i915_hangcheck_elapsed(unsigned long data)
1903 struct drm_device *dev = (struct drm_device *)data;
1904 drm_i915_private_t *dev_priv = dev->dev_private;
1905 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1906 struct intel_ring_buffer *ring;
1907 bool err = false, idle;
1910 if (!i915_enable_hangcheck)
1913 memset(acthd, 0, sizeof(acthd));
1915 for_each_ring(ring, dev_priv, i) {
1916 idle &= i915_hangcheck_ring_idle(ring, &err);
1917 acthd[i] = intel_ring_get_active_head(ring);
1920 /* If all work is done then ACTHD clearly hasn't advanced. */
1923 if (i915_hangcheck_hung(dev))
1929 dev_priv->gpu_error.hangcheck_count = 0;
1933 i915_get_extra_instdone(dev, instdone);
1934 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1935 sizeof(acthd)) == 0 &&
1936 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1937 sizeof(instdone)) == 0) {
1938 if (i915_hangcheck_hung(dev))
1941 dev_priv->gpu_error.hangcheck_count = 0;
1943 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1945 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1950 /* Reset timer case chip hangs without another request being added */
1951 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1952 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1957 static void ironlake_irq_preinstall(struct drm_device *dev)
1959 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1961 atomic_set(&dev_priv->irq_received, 0);
1963 I915_WRITE(HWSTAM, 0xeffe);
1965 /* XXX hotplug from PCH */
1967 I915_WRITE(DEIMR, 0xffffffff);
1968 I915_WRITE(DEIER, 0x0);
1969 POSTING_READ(DEIER);
1972 I915_WRITE(GTIMR, 0xffffffff);
1973 I915_WRITE(GTIER, 0x0);
1974 POSTING_READ(GTIER);
1976 /* south display irq */
1977 I915_WRITE(SDEIMR, 0xffffffff);
1978 I915_WRITE(SDEIER, 0x0);
1979 POSTING_READ(SDEIER);
1982 static void valleyview_irq_preinstall(struct drm_device *dev)
1984 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1987 atomic_set(&dev_priv->irq_received, 0);
1990 I915_WRITE(VLV_IMR, 0);
1991 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1992 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1993 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1996 I915_WRITE(GTIIR, I915_READ(GTIIR));
1997 I915_WRITE(GTIIR, I915_READ(GTIIR));
1998 I915_WRITE(GTIMR, 0xffffffff);
1999 I915_WRITE(GTIER, 0x0);
2000 POSTING_READ(GTIER);
2002 I915_WRITE(DPINVGTT, 0xff);
2004 I915_WRITE(PORT_HOTPLUG_EN, 0);
2005 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2007 I915_WRITE(PIPESTAT(pipe), 0xffff);
2008 I915_WRITE(VLV_IIR, 0xffffffff);
2009 I915_WRITE(VLV_IMR, 0xffffffff);
2010 I915_WRITE(VLV_IER, 0x0);
2011 POSTING_READ(VLV_IER);
2015 * Enable digital hotplug on the PCH, and configure the DP short pulse
2016 * duration to 2ms (which is the minimum in the Display Port spec)
2018 * This register is the same on all known PCH chips.
2021 static void ibx_enable_hotplug(struct drm_device *dev)
2023 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2026 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2027 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2028 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2029 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2030 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2031 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2034 static void ibx_irq_postinstall(struct drm_device *dev)
2036 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2039 if (HAS_PCH_IBX(dev))
2040 mask = SDE_HOTPLUG_MASK |
2044 mask = SDE_HOTPLUG_MASK_CPT |
2048 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2049 I915_WRITE(SDEIMR, ~mask);
2050 I915_WRITE(SDEIER, mask);
2051 POSTING_READ(SDEIER);
2053 ibx_enable_hotplug(dev);
2056 static int ironlake_irq_postinstall(struct drm_device *dev)
2058 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2059 /* enable kind of interrupts always enabled */
2060 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2061 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2065 dev_priv->irq_mask = ~display_mask;
2067 /* should always can generate irq */
2068 I915_WRITE(DEIIR, I915_READ(DEIIR));
2069 I915_WRITE(DEIMR, dev_priv->irq_mask);
2070 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2071 POSTING_READ(DEIER);
2073 dev_priv->gt_irq_mask = ~0;
2075 I915_WRITE(GTIIR, I915_READ(GTIIR));
2076 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2081 GEN6_BSD_USER_INTERRUPT |
2082 GEN6_BLITTER_USER_INTERRUPT;
2087 GT_BSD_USER_INTERRUPT;
2088 I915_WRITE(GTIER, render_irqs);
2089 POSTING_READ(GTIER);
2091 ibx_irq_postinstall(dev);
2093 if (IS_IRONLAKE_M(dev)) {
2094 /* Clear & enable PCU event interrupts */
2095 I915_WRITE(DEIIR, DE_PCU_EVENT);
2096 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2097 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2103 static int ivybridge_irq_postinstall(struct drm_device *dev)
2105 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2106 /* enable kind of interrupts always enabled */
2108 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2109 DE_PLANEC_FLIP_DONE_IVB |
2110 DE_PLANEB_FLIP_DONE_IVB |
2111 DE_PLANEA_FLIP_DONE_IVB |
2112 DE_AUX_CHANNEL_A_IVB;
2115 dev_priv->irq_mask = ~display_mask;
2117 /* should always can generate irq */
2118 I915_WRITE(DEIIR, I915_READ(DEIIR));
2119 I915_WRITE(DEIMR, dev_priv->irq_mask);
2122 DE_PIPEC_VBLANK_IVB |
2123 DE_PIPEB_VBLANK_IVB |
2124 DE_PIPEA_VBLANK_IVB);
2125 POSTING_READ(DEIER);
2127 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2129 I915_WRITE(GTIIR, I915_READ(GTIIR));
2130 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2132 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2133 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2134 I915_WRITE(GTIER, render_irqs);
2135 POSTING_READ(GTIER);
2137 ibx_irq_postinstall(dev);
2142 static int valleyview_irq_postinstall(struct drm_device *dev)
2144 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2146 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2150 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2151 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2152 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2153 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2154 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2157 *Leave vblank interrupts masked initially. enable/disable will
2158 * toggle them based on usage.
2160 dev_priv->irq_mask = (~enable_mask) |
2161 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2162 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2164 /* Hack for broken MSIs on VLV */
2165 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2166 pci_read_config_word(dev->pdev, 0x98, &msid);
2167 msid &= 0xff; /* mask out delivery bits */
2169 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2171 I915_WRITE(PORT_HOTPLUG_EN, 0);
2172 POSTING_READ(PORT_HOTPLUG_EN);
2174 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2175 I915_WRITE(VLV_IER, enable_mask);
2176 I915_WRITE(VLV_IIR, 0xffffffff);
2177 I915_WRITE(PIPESTAT(0), 0xffff);
2178 I915_WRITE(PIPESTAT(1), 0xffff);
2179 POSTING_READ(VLV_IER);
2181 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2182 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2183 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2185 I915_WRITE(VLV_IIR, 0xffffffff);
2186 I915_WRITE(VLV_IIR, 0xffffffff);
2188 I915_WRITE(GTIIR, I915_READ(GTIIR));
2189 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2191 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2192 GEN6_BLITTER_USER_INTERRUPT;
2193 I915_WRITE(GTIER, render_irqs);
2194 POSTING_READ(GTIER);
2196 /* ack & enable invalid PTE error interrupts */
2197 #if 0 /* FIXME: add support to irq handler for checking these bits */
2198 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2199 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2202 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2207 static void valleyview_hpd_irq_setup(struct drm_device *dev)
2209 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2210 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2212 /* Note HDMI and DP share bits */
2213 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2214 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2215 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2216 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2217 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2218 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2219 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2220 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2221 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2222 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2223 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2224 hotplug_en |= CRT_HOTPLUG_INT_EN;
2225 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2228 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2231 static void valleyview_irq_uninstall(struct drm_device *dev)
2233 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2240 I915_WRITE(PIPESTAT(pipe), 0xffff);
2242 I915_WRITE(HWSTAM, 0xffffffff);
2243 I915_WRITE(PORT_HOTPLUG_EN, 0);
2244 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2246 I915_WRITE(PIPESTAT(pipe), 0xffff);
2247 I915_WRITE(VLV_IIR, 0xffffffff);
2248 I915_WRITE(VLV_IMR, 0xffffffff);
2249 I915_WRITE(VLV_IER, 0x0);
2250 POSTING_READ(VLV_IER);
2253 static void ironlake_irq_uninstall(struct drm_device *dev)
2255 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2260 I915_WRITE(HWSTAM, 0xffffffff);
2262 I915_WRITE(DEIMR, 0xffffffff);
2263 I915_WRITE(DEIER, 0x0);
2264 I915_WRITE(DEIIR, I915_READ(DEIIR));
2266 I915_WRITE(GTIMR, 0xffffffff);
2267 I915_WRITE(GTIER, 0x0);
2268 I915_WRITE(GTIIR, I915_READ(GTIIR));
2270 I915_WRITE(SDEIMR, 0xffffffff);
2271 I915_WRITE(SDEIER, 0x0);
2272 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2275 static void i8xx_irq_preinstall(struct drm_device * dev)
2277 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2280 atomic_set(&dev_priv->irq_received, 0);
2283 I915_WRITE(PIPESTAT(pipe), 0);
2284 I915_WRITE16(IMR, 0xffff);
2285 I915_WRITE16(IER, 0x0);
2286 POSTING_READ16(IER);
2289 static int i8xx_irq_postinstall(struct drm_device *dev)
2291 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2294 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2296 /* Unmask the interrupts that we always want on. */
2297 dev_priv->irq_mask =
2298 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2299 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2300 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2301 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2302 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2303 I915_WRITE16(IMR, dev_priv->irq_mask);
2306 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2307 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2308 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2309 I915_USER_INTERRUPT);
2310 POSTING_READ16(IER);
2316 * Returns true when a page flip has completed.
2318 static bool i8xx_handle_vblank(struct drm_device *dev,
2321 drm_i915_private_t *dev_priv = dev->dev_private;
2322 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2324 if (!drm_handle_vblank(dev, pipe))
2327 if ((iir & flip_pending) == 0)
2330 intel_prepare_page_flip(dev, pipe);
2332 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2333 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2334 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2335 * the flip is completed (no longer pending). Since this doesn't raise
2336 * an interrupt per se, we watch for the change at vblank.
2338 if (I915_READ16(ISR) & flip_pending)
2341 intel_finish_page_flip(dev, pipe);
2346 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2348 struct drm_device *dev = (struct drm_device *) arg;
2349 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2352 unsigned long irqflags;
2356 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2357 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2359 atomic_inc(&dev_priv->irq_received);
2361 iir = I915_READ16(IIR);
2365 while (iir & ~flip_mask) {
2366 /* Can't rely on pipestat interrupt bit in iir as it might
2367 * have been cleared after the pipestat interrupt was received.
2368 * It doesn't set the bit in iir again, but it still produces
2369 * interrupts (for non-MSI).
2371 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2372 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2373 i915_handle_error(dev, false);
2375 for_each_pipe(pipe) {
2376 int reg = PIPESTAT(pipe);
2377 pipe_stats[pipe] = I915_READ(reg);
2380 * Clear the PIPE*STAT regs before the IIR
2382 if (pipe_stats[pipe] & 0x8000ffff) {
2383 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2384 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2386 I915_WRITE(reg, pipe_stats[pipe]);
2390 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2392 I915_WRITE16(IIR, iir & ~flip_mask);
2393 new_iir = I915_READ16(IIR); /* Flush posted writes */
2395 i915_update_dri1_breadcrumb(dev);
2397 if (iir & I915_USER_INTERRUPT)
2398 notify_ring(dev, &dev_priv->ring[RCS]);
2400 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2401 i8xx_handle_vblank(dev, 0, iir))
2402 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2404 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2405 i8xx_handle_vblank(dev, 1, iir))
2406 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2414 static void i8xx_irq_uninstall(struct drm_device * dev)
2416 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2419 for_each_pipe(pipe) {
2420 /* Clear enable bits; then clear status bits */
2421 I915_WRITE(PIPESTAT(pipe), 0);
2422 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2424 I915_WRITE16(IMR, 0xffff);
2425 I915_WRITE16(IER, 0x0);
2426 I915_WRITE16(IIR, I915_READ16(IIR));
2429 static void i915_irq_preinstall(struct drm_device * dev)
2431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2434 atomic_set(&dev_priv->irq_received, 0);
2436 if (I915_HAS_HOTPLUG(dev)) {
2437 I915_WRITE(PORT_HOTPLUG_EN, 0);
2438 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2441 I915_WRITE16(HWSTAM, 0xeffe);
2443 I915_WRITE(PIPESTAT(pipe), 0);
2444 I915_WRITE(IMR, 0xffffffff);
2445 I915_WRITE(IER, 0x0);
2449 static int i915_irq_postinstall(struct drm_device *dev)
2451 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2454 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2456 /* Unmask the interrupts that we always want on. */
2457 dev_priv->irq_mask =
2458 ~(I915_ASLE_INTERRUPT |
2459 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2460 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2461 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2462 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2463 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2466 I915_ASLE_INTERRUPT |
2467 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2468 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2469 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2470 I915_USER_INTERRUPT;
2472 if (I915_HAS_HOTPLUG(dev)) {
2473 I915_WRITE(PORT_HOTPLUG_EN, 0);
2474 POSTING_READ(PORT_HOTPLUG_EN);
2476 /* Enable in IER... */
2477 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2478 /* and unmask in IMR */
2479 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2482 I915_WRITE(IMR, dev_priv->irq_mask);
2483 I915_WRITE(IER, enable_mask);
2486 intel_opregion_enable_asle(dev);
2491 static void i915_hpd_irq_setup(struct drm_device *dev)
2493 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2496 if (I915_HAS_HOTPLUG(dev)) {
2497 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2499 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2500 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2501 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2502 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2503 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2504 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2505 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2506 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2507 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2508 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2509 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2510 hotplug_en |= CRT_HOTPLUG_INT_EN;
2511 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2514 /* Ignore TV since it's buggy */
2516 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2521 * Returns true when a page flip has completed.
2523 static bool i915_handle_vblank(struct drm_device *dev,
2524 int plane, int pipe, u32 iir)
2526 drm_i915_private_t *dev_priv = dev->dev_private;
2527 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2529 if (!drm_handle_vblank(dev, pipe))
2532 if ((iir & flip_pending) == 0)
2535 intel_prepare_page_flip(dev, plane);
2537 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2538 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2539 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2540 * the flip is completed (no longer pending). Since this doesn't raise
2541 * an interrupt per se, we watch for the change at vblank.
2543 if (I915_READ(ISR) & flip_pending)
2546 intel_finish_page_flip(dev, pipe);
2551 static irqreturn_t i915_irq_handler(int irq, void *arg)
2553 struct drm_device *dev = (struct drm_device *) arg;
2554 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2555 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2556 unsigned long irqflags;
2558 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2559 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2560 int pipe, ret = IRQ_NONE;
2562 atomic_inc(&dev_priv->irq_received);
2564 iir = I915_READ(IIR);
2566 bool irq_received = (iir & ~flip_mask) != 0;
2567 bool blc_event = false;
2569 /* Can't rely on pipestat interrupt bit in iir as it might
2570 * have been cleared after the pipestat interrupt was received.
2571 * It doesn't set the bit in iir again, but it still produces
2572 * interrupts (for non-MSI).
2574 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2575 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2576 i915_handle_error(dev, false);
2578 for_each_pipe(pipe) {
2579 int reg = PIPESTAT(pipe);
2580 pipe_stats[pipe] = I915_READ(reg);
2582 /* Clear the PIPE*STAT regs before the IIR */
2583 if (pipe_stats[pipe] & 0x8000ffff) {
2584 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2585 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2587 I915_WRITE(reg, pipe_stats[pipe]);
2588 irq_received = true;
2591 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2596 /* Consume port. Then clear IIR or we'll miss events */
2597 if ((I915_HAS_HOTPLUG(dev)) &&
2598 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2599 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2601 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2603 if (hotplug_status & dev_priv->hotplug_supported_mask)
2604 queue_work(dev_priv->wq,
2605 &dev_priv->hotplug_work);
2607 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2608 POSTING_READ(PORT_HOTPLUG_STAT);
2611 I915_WRITE(IIR, iir & ~flip_mask);
2612 new_iir = I915_READ(IIR); /* Flush posted writes */
2614 if (iir & I915_USER_INTERRUPT)
2615 notify_ring(dev, &dev_priv->ring[RCS]);
2617 for_each_pipe(pipe) {
2622 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2623 i915_handle_vblank(dev, plane, pipe, iir))
2624 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2626 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2630 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2631 intel_opregion_asle_intr(dev);
2633 /* With MSI, interrupts are only generated when iir
2634 * transitions from zero to nonzero. If another bit got
2635 * set while we were handling the existing iir bits, then
2636 * we would never get another interrupt.
2638 * This is fine on non-MSI as well, as if we hit this path
2639 * we avoid exiting the interrupt handler only to generate
2642 * Note that for MSI this could cause a stray interrupt report
2643 * if an interrupt landed in the time between writing IIR and
2644 * the posting read. This should be rare enough to never
2645 * trigger the 99% of 100,000 interrupts test for disabling
2650 } while (iir & ~flip_mask);
2652 i915_update_dri1_breadcrumb(dev);
2657 static void i915_irq_uninstall(struct drm_device * dev)
2659 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2662 if (I915_HAS_HOTPLUG(dev)) {
2663 I915_WRITE(PORT_HOTPLUG_EN, 0);
2664 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2667 I915_WRITE16(HWSTAM, 0xffff);
2668 for_each_pipe(pipe) {
2669 /* Clear enable bits; then clear status bits */
2670 I915_WRITE(PIPESTAT(pipe), 0);
2671 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2673 I915_WRITE(IMR, 0xffffffff);
2674 I915_WRITE(IER, 0x0);
2676 I915_WRITE(IIR, I915_READ(IIR));
2679 static void i965_irq_preinstall(struct drm_device * dev)
2681 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2684 atomic_set(&dev_priv->irq_received, 0);
2686 I915_WRITE(PORT_HOTPLUG_EN, 0);
2687 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2689 I915_WRITE(HWSTAM, 0xeffe);
2691 I915_WRITE(PIPESTAT(pipe), 0);
2692 I915_WRITE(IMR, 0xffffffff);
2693 I915_WRITE(IER, 0x0);
2697 static int i965_irq_postinstall(struct drm_device *dev)
2699 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2703 /* Unmask the interrupts that we always want on. */
2704 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2705 I915_DISPLAY_PORT_INTERRUPT |
2706 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2707 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2708 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2709 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2710 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2712 enable_mask = ~dev_priv->irq_mask;
2713 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2714 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2715 enable_mask |= I915_USER_INTERRUPT;
2718 enable_mask |= I915_BSD_USER_INTERRUPT;
2720 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2723 * Enable some error detection, note the instruction error mask
2724 * bit is reserved, so we leave it masked.
2727 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2728 GM45_ERROR_MEM_PRIV |
2729 GM45_ERROR_CP_PRIV |
2730 I915_ERROR_MEMORY_REFRESH);
2732 error_mask = ~(I915_ERROR_PAGE_TABLE |
2733 I915_ERROR_MEMORY_REFRESH);
2735 I915_WRITE(EMR, error_mask);
2737 I915_WRITE(IMR, dev_priv->irq_mask);
2738 I915_WRITE(IER, enable_mask);
2741 I915_WRITE(PORT_HOTPLUG_EN, 0);
2742 POSTING_READ(PORT_HOTPLUG_EN);
2744 intel_opregion_enable_asle(dev);
2749 static void i965_hpd_irq_setup(struct drm_device *dev)
2751 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2754 /* Note HDMI and DP share hotplug bits */
2756 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2757 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2758 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2759 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2760 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2761 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2763 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2764 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2765 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2766 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2768 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2769 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2770 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2771 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2773 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2774 hotplug_en |= CRT_HOTPLUG_INT_EN;
2776 /* Programming the CRT detection parameters tends
2777 to generate a spurious hotplug event about three
2778 seconds later. So just do it once.
2781 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2782 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2785 /* Ignore TV since it's buggy */
2787 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2790 static irqreturn_t i965_irq_handler(int irq, void *arg)
2792 struct drm_device *dev = (struct drm_device *) arg;
2793 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2795 u32 pipe_stats[I915_MAX_PIPES];
2796 unsigned long irqflags;
2798 int ret = IRQ_NONE, pipe;
2800 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2801 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2803 atomic_inc(&dev_priv->irq_received);
2805 iir = I915_READ(IIR);
2808 bool blc_event = false;
2810 irq_received = (iir & ~flip_mask) != 0;
2812 /* Can't rely on pipestat interrupt bit in iir as it might
2813 * have been cleared after the pipestat interrupt was received.
2814 * It doesn't set the bit in iir again, but it still produces
2815 * interrupts (for non-MSI).
2817 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2818 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2819 i915_handle_error(dev, false);
2821 for_each_pipe(pipe) {
2822 int reg = PIPESTAT(pipe);
2823 pipe_stats[pipe] = I915_READ(reg);
2826 * Clear the PIPE*STAT regs before the IIR
2828 if (pipe_stats[pipe] & 0x8000ffff) {
2829 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2830 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2832 I915_WRITE(reg, pipe_stats[pipe]);
2836 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2843 /* Consume port. Then clear IIR or we'll miss events */
2844 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2845 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2847 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2849 if (hotplug_status & dev_priv->hotplug_supported_mask)
2850 queue_work(dev_priv->wq,
2851 &dev_priv->hotplug_work);
2853 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2854 I915_READ(PORT_HOTPLUG_STAT);
2857 I915_WRITE(IIR, iir & ~flip_mask);
2858 new_iir = I915_READ(IIR); /* Flush posted writes */
2860 if (iir & I915_USER_INTERRUPT)
2861 notify_ring(dev, &dev_priv->ring[RCS]);
2862 if (iir & I915_BSD_USER_INTERRUPT)
2863 notify_ring(dev, &dev_priv->ring[VCS]);
2865 for_each_pipe(pipe) {
2866 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2867 i915_handle_vblank(dev, pipe, pipe, iir))
2868 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2870 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2875 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2876 intel_opregion_asle_intr(dev);
2878 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2879 gmbus_irq_handler(dev);
2881 /* With MSI, interrupts are only generated when iir
2882 * transitions from zero to nonzero. If another bit got
2883 * set while we were handling the existing iir bits, then
2884 * we would never get another interrupt.
2886 * This is fine on non-MSI as well, as if we hit this path
2887 * we avoid exiting the interrupt handler only to generate
2890 * Note that for MSI this could cause a stray interrupt report
2891 * if an interrupt landed in the time between writing IIR and
2892 * the posting read. This should be rare enough to never
2893 * trigger the 99% of 100,000 interrupts test for disabling
2899 i915_update_dri1_breadcrumb(dev);
2904 static void i965_irq_uninstall(struct drm_device * dev)
2906 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2912 I915_WRITE(PORT_HOTPLUG_EN, 0);
2913 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2915 I915_WRITE(HWSTAM, 0xffffffff);
2917 I915_WRITE(PIPESTAT(pipe), 0);
2918 I915_WRITE(IMR, 0xffffffff);
2919 I915_WRITE(IER, 0x0);
2922 I915_WRITE(PIPESTAT(pipe),
2923 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2924 I915_WRITE(IIR, I915_READ(IIR));
2927 void intel_irq_init(struct drm_device *dev)
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2931 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2932 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2933 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2934 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2936 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2937 i915_hangcheck_elapsed,
2938 (unsigned long) dev);
2940 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2942 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2943 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2944 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2945 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2946 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2949 if (drm_core_check_feature(dev, DRIVER_MODESET))
2950 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2952 dev->driver->get_vblank_timestamp = NULL;
2953 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2955 if (IS_VALLEYVIEW(dev)) {
2956 dev->driver->irq_handler = valleyview_irq_handler;
2957 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2958 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2959 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2960 dev->driver->enable_vblank = valleyview_enable_vblank;
2961 dev->driver->disable_vblank = valleyview_disable_vblank;
2962 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
2963 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2964 /* Share pre & uninstall handlers with ILK/SNB */
2965 dev->driver->irq_handler = ivybridge_irq_handler;
2966 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2967 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2968 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2969 dev->driver->enable_vblank = ivybridge_enable_vblank;
2970 dev->driver->disable_vblank = ivybridge_disable_vblank;
2971 } else if (HAS_PCH_SPLIT(dev)) {
2972 dev->driver->irq_handler = ironlake_irq_handler;
2973 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2974 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2975 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2976 dev->driver->enable_vblank = ironlake_enable_vblank;
2977 dev->driver->disable_vblank = ironlake_disable_vblank;
2979 if (INTEL_INFO(dev)->gen == 2) {
2980 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2981 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2982 dev->driver->irq_handler = i8xx_irq_handler;
2983 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2984 } else if (INTEL_INFO(dev)->gen == 3) {
2985 dev->driver->irq_preinstall = i915_irq_preinstall;
2986 dev->driver->irq_postinstall = i915_irq_postinstall;
2987 dev->driver->irq_uninstall = i915_irq_uninstall;
2988 dev->driver->irq_handler = i915_irq_handler;
2989 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2991 dev->driver->irq_preinstall = i965_irq_preinstall;
2992 dev->driver->irq_postinstall = i965_irq_postinstall;
2993 dev->driver->irq_uninstall = i965_irq_uninstall;
2994 dev->driver->irq_handler = i965_irq_handler;
2995 dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
2997 dev->driver->enable_vblank = i915_enable_vblank;
2998 dev->driver->disable_vblank = i915_disable_vblank;
3002 void intel_hpd_init(struct drm_device *dev)
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3006 if (dev_priv->display.hpd_irq_setup)
3007 dev_priv->display.hpd_irq_setup(dev);