drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* IIR can theoretically queue up two events. Be paranoid. */
  84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
  85         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
  86         POSTING_READ(GEN8_##type##_IMR(which)); \
  87         I915_WRITE(GEN8_##type##_IER(which), 0); \
  88         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  89         POSTING_READ(GEN8_##type##_IIR(which)); \
  90         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  91         POSTING_READ(GEN8_##type##_IIR(which)); \
  92 } while (0)
  93
  94 #define GEN5_IRQ_RESET(type) do { \
  95         I915_WRITE(type##IMR, 0xffffffff); \
  96         POSTING_READ(type##IMR); \
  97         I915_WRITE(type##IER, 0); \
  98         I915_WRITE(type##IIR, 0xffffffff); \
  99         POSTING_READ(type##IIR); \
 100         I915_WRITE(type##IIR, 0xffffffff); \
 101         POSTING_READ(type##IIR); \
 102 } while (0)
 103
 104 /*
 105  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 106  */
 107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
 108         u32 val = I915_READ(reg); \
 109         if (val) { \
 110                 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
 111                      (reg), val); \
 112                 I915_WRITE((reg), 0xffffffff); \
 113                 POSTING_READ(reg); \
 114                 I915_WRITE((reg), 0xffffffff); \
 115                 POSTING_READ(reg); \
 116         } \
 117 } while (0)
 118
 119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 120         GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
 121         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 122         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 123         POSTING_READ(GEN8_##type##_IER(which)); \
 124 } while (0)
 125
 126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 127         GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
 128         I915_WRITE(type##IMR, (imr_val)); \
 129         I915_WRITE(type##IER, (ier_val)); \
 130         POSTING_READ(type##IER); \
 131 } while (0)
 132
 133 /* For display hotplug interrupt */
 134 static void
 135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 136 {
 137         assert_spin_locked(&dev_priv->irq_lock);
 138
 139         if (WARN_ON(dev_priv->pm.irqs_disabled))
 140                 return;
 141
 142         if ((dev_priv->irq_mask & mask) != 0) {
 143                 dev_priv->irq_mask &= ~mask;
 144                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 145                 POSTING_READ(DEIMR);
 146         }
 147 }
 148
 149 static void
 150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 151 {
 152         assert_spin_locked(&dev_priv->irq_lock);
 153
 154         if (WARN_ON(dev_priv->pm.irqs_disabled))
 155                 return;
 156
 157         if ((dev_priv->irq_mask & mask) != mask) {
 158                 dev_priv->irq_mask |= mask;
 159                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 160                 POSTING_READ(DEIMR);
 161         }
 162 }
 163
 164 /**
 165  * ilk_update_gt_irq - update GTIMR
 166  * @dev_priv: driver private
 167  * @interrupt_mask: mask of interrupt bits to update
 168  * @enabled_irq_mask: mask of interrupt bits to enable
 169  */
 170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 171                               uint32_t interrupt_mask,
 172                               uint32_t enabled_irq_mask)
 173 {
 174         assert_spin_locked(&dev_priv->irq_lock);
 175
 176         if (WARN_ON(dev_priv->pm.irqs_disabled))
 177                 return;
 178
 179         dev_priv->gt_irq_mask &= ~interrupt_mask;
 180         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 181         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 182         POSTING_READ(GTIMR);
 183 }
 184
 185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 186 {
 187         ilk_update_gt_irq(dev_priv, mask, mask);
 188 }
 189
 190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 191 {
 192         ilk_update_gt_irq(dev_priv, mask, 0);
 193 }
 194
 195 /**
 196   * snb_update_pm_irq - update GEN6_PMIMR
 197   * @dev_priv: driver private
 198   * @interrupt_mask: mask of interrupt bits to update
 199   * @enabled_irq_mask: mask of interrupt bits to enable
 200   */
 201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 202                               uint32_t interrupt_mask,
 203                               uint32_t enabled_irq_mask)
 204 {
 205         uint32_t new_val;
 206
 207         assert_spin_locked(&dev_priv->irq_lock);
 208
 209         if (WARN_ON(dev_priv->pm.irqs_disabled))
 210                 return;
 211
 212         new_val = dev_priv->pm_irq_mask;
 213         new_val &= ~interrupt_mask;
 214         new_val |= (~enabled_irq_mask & interrupt_mask);
 215
 216         if (new_val != dev_priv->pm_irq_mask) {
 217                 dev_priv->pm_irq_mask = new_val;
 218                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 219                 POSTING_READ(GEN6_PMIMR);
 220         }
 221 }
 222
 223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 224 {
 225         snb_update_pm_irq(dev_priv, mask, mask);
 226 }
 227
 228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 229 {
 230         snb_update_pm_irq(dev_priv, mask, 0);
 231 }
 232
 233 static bool ivb_can_enable_err_int(struct drm_device *dev)
 234 {
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         struct intel_crtc *crtc;
 237         enum pipe pipe;
 238
 239         assert_spin_locked(&dev_priv->irq_lock);
 240
 241         for_each_pipe(pipe) {
 242                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 243
 244                 if (crtc->cpu_fifo_underrun_disabled)
 245                         return false;
 246         }
 247
 248         return true;
 249 }
 250
 251 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         enum pipe pipe;
 255         struct intel_crtc *crtc;
 256
 257         assert_spin_locked(&dev_priv->irq_lock);
 258
 259         for_each_pipe(pipe) {
 260                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 261
 262                 if (crtc->pch_fifo_underrun_disabled)
 263                         return false;
 264         }
 265
 266         return true;
 267 }
 268
 269 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         u32 reg = PIPESTAT(pipe);
 273         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 274
 275         assert_spin_locked(&dev_priv->irq_lock);
 276
 277         I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 278         POSTING_READ(reg);
 279 }
 280
 281 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 282                                                  enum pipe pipe, bool enable)
 283 {
 284         struct drm_i915_private *dev_priv = dev->dev_private;
 285         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 286                                           DE_PIPEB_FIFO_UNDERRUN;
 287
 288         if (enable)
 289                 ironlake_enable_display_irq(dev_priv, bit);
 290         else
 291                 ironlake_disable_display_irq(dev_priv, bit);
 292 }
 293
 294 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 295                                                   enum pipe pipe, bool enable)
 296 {
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         if (enable) {
 299                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 300
 301                 if (!ivb_can_enable_err_int(dev))
 302                         return;
 303
 304                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 305         } else {
 306                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 307
 308                 /* Change the state _after_ we've read out the current one. */
 309                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 310
 311                 if (!was_enabled &&
 312                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 313                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 314                                       pipe_name(pipe));
 315                 }
 316         }
 317 }
 318
 319 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 320                                                   enum pipe pipe, bool enable)
 321 {
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         assert_spin_locked(&dev_priv->irq_lock);
 325
 326         if (enable)
 327                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 328         else
 329                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 330         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 331         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 332 }
 333
 334 /**
 335  * ibx_display_interrupt_update - update SDEIMR
 336  * @dev_priv: driver private
 337  * @interrupt_mask: mask of interrupt bits to update
 338  * @enabled_irq_mask: mask of interrupt bits to enable
 339  */
 340 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 341                                          uint32_t interrupt_mask,
 342                                          uint32_t enabled_irq_mask)
 343 {
 344         uint32_t sdeimr = I915_READ(SDEIMR);
 345         sdeimr &= ~interrupt_mask;
 346         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 347
 348         assert_spin_locked(&dev_priv->irq_lock);
 349
 350         if (WARN_ON(dev_priv->pm.irqs_disabled))
 351                 return;
 352
 353         I915_WRITE(SDEIMR, sdeimr);
 354         POSTING_READ(SDEIMR);
 355 }
 356 #define ibx_enable_display_interrupt(dev_priv, bits) \
 357         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 358 #define ibx_disable_display_interrupt(dev_priv, bits) \
 359         ibx_display_interrupt_update((dev_priv), (bits), 0)
 360
 361 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 362                                             enum transcoder pch_transcoder,
 363                                             bool enable)
 364 {
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 367                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 368
 369         if (enable)
 370                 ibx_enable_display_interrupt(dev_priv, bit);
 371         else
 372                 ibx_disable_display_interrupt(dev_priv, bit);
 373 }
 374
 375 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 376                                             enum transcoder pch_transcoder,
 377                                             bool enable)
 378 {
 379         struct drm_i915_private *dev_priv = dev->dev_private;
 380
 381         if (enable) {
 382                 I915_WRITE(SERR_INT,
 383                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 384
 385                 if (!cpt_can_enable_serr_int(dev))
 386                         return;
 387
 388                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 389         } else {
 390                 uint32_t tmp = I915_READ(SERR_INT);
 391                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 392
 393                 /* Change the state _after_ we've read out the current one. */
 394                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 395
 396                 if (!was_enabled &&
 397                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 398                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 399                                       transcoder_name(pch_transcoder));
 400                 }
 401         }
 402 }
 403
 404 /**
 405  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 406  * @dev: drm device
 407  * @pipe: pipe
 408  * @enable: true if we want to report FIFO underrun errors, false otherwise
 409  *
 410  * This function makes us disable or enable CPU fifo underruns for a specific
 411  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 412  * reporting for one pipe may also disable all the other CPU error interruts for
 413  * the other pipes, due to the fact that there's just one interrupt mask/enable
 414  * bit for all the pipes.
 415  *
 416  * Returns the previous state of underrun reporting.
 417  */
 418 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 419                                              enum pipe pipe, bool enable)
 420 {
 421         struct drm_i915_private *dev_priv = dev->dev_private;
 422         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 424         bool ret;
 425
 426         assert_spin_locked(&dev_priv->irq_lock);
 427
 428         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 429
 430         if (enable == ret)
 431                 goto done;
 432
 433         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 434
 435         if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
 436                 i9xx_clear_fifo_underrun(dev, pipe);
 437         else if (IS_GEN5(dev) || IS_GEN6(dev))
 438                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 439         else if (IS_GEN7(dev))
 440                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 441         else if (IS_GEN8(dev))
 442                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 443
 444 done:
 445         return ret;
 446 }
 447
 448 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 449                                            enum pipe pipe, bool enable)
 450 {
 451         struct drm_i915_private *dev_priv = dev->dev_private;
 452         unsigned long flags;
 453         bool ret;
 454
 455         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 456         ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
 457         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 458
 459         return ret;
 460 }
 461
 462 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
 463                                                   enum pipe pipe)
 464 {
 465         struct drm_i915_private *dev_priv = dev->dev_private;
 466         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 468
 469         return !intel_crtc->cpu_fifo_underrun_disabled;
 470 }
 471
 472 /**
 473  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 474  * @dev: drm device
 475  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 476  * @enable: true if we want to report FIFO underrun errors, false otherwise
 477  *
 478  * This function makes us disable or enable PCH fifo underruns for a specific
 479  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 480  * underrun reporting for one transcoder may also disable all the other PCH
 481  * error interruts for the other transcoders, due to the fact that there's just
 482  * one interrupt mask/enable bit for all the transcoders.
 483  *
 484  * Returns the previous state of underrun reporting.
 485  */
 486 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 487                                            enum transcoder pch_transcoder,
 488                                            bool enable)
 489 {
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 493         unsigned long flags;
 494         bool ret;
 495
 496         /*
 497          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 498          * has only one pch transcoder A that all pipes can use. To avoid racy
 499          * pch transcoder -> pipe lookups from interrupt code simply store the
 500          * underrun statistics in crtc A. Since we never expose this anywhere
 501          * nor use it outside of the fifo underrun code here using the "wrong"
 502          * crtc on LPT won't cause issues.
 503          */
 504
 505         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 506
 507         ret = !intel_crtc->pch_fifo_underrun_disabled;
 508
 509         if (enable == ret)
 510                 goto done;
 511
 512         intel_crtc->pch_fifo_underrun_disabled = !enable;
 513
 514         if (HAS_PCH_IBX(dev))
 515                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 516         else
 517                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 518
 519 done:
 520         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 521         return ret;
 522 }
 523
 524
 525 static void
 526 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 527                        u32 enable_mask, u32 status_mask)
 528 {
 529         u32 reg = PIPESTAT(pipe);
 530         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 531
 532         assert_spin_locked(&dev_priv->irq_lock);
 533
 534         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 535                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 536                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 537                       pipe_name(pipe), enable_mask, status_mask))
 538                 return;
 539
 540         if ((pipestat & enable_mask) == enable_mask)
 541                 return;
 542
 543         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 544
 545         /* Enable the interrupt, clear any pending status */
 546         pipestat |= enable_mask | status_mask;
 547         I915_WRITE(reg, pipestat);
 548         POSTING_READ(reg);
 549 }
 550
 551 static void
 552 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 553                         u32 enable_mask, u32 status_mask)
 554 {
 555         u32 reg = PIPESTAT(pipe);
 556         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 557
 558         assert_spin_locked(&dev_priv->irq_lock);
 559
 560         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 561                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 562                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 563                       pipe_name(pipe), enable_mask, status_mask))
 564                 return;
 565
 566         if ((pipestat & enable_mask) == 0)
 567                 return;
 568
 569         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 570
 571         pipestat &= ~enable_mask;
 572         I915_WRITE(reg, pipestat);
 573         POSTING_READ(reg);
 574 }
 575
 576 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 577 {
 578         u32 enable_mask = status_mask << 16;
 579
 580         /*
 581          * On pipe A we don't support the PSR interrupt yet, on pipe B the
 582          * same bit MBZ.
 583          */
 584         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 585                 return 0;
 586
 587         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 588                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 589                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 590         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 591                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 592         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 593                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 594
 595         return enable_mask;
 596 }
 597
 598 void
 599 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 600                      u32 status_mask)
 601 {
 602         u32 enable_mask;
 603
 604         if (IS_VALLEYVIEW(dev_priv->dev))
 605                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 606                                                            status_mask);
 607         else
 608                 enable_mask = status_mask << 16;
 609         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 610 }
 611
 612 void
 613 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 614                       u32 status_mask)
 615 {
 616         u32 enable_mask;
 617
 618         if (IS_VALLEYVIEW(dev_priv->dev))
 619                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 620                                                            status_mask);
 621         else
 622                 enable_mask = status_mask << 16;
 623         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 624 }
 625
 626 /**
 627  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 628  */
 629 static void i915_enable_asle_pipestat(struct drm_device *dev)
 630 {
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         unsigned long irqflags;
 633
 634         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 635                 return;
 636
 637         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 638
 639         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 640         if (INTEL_INFO(dev)->gen >= 4)
 641                 i915_enable_pipestat(dev_priv, PIPE_A,
 642                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 643
 644         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 645 }
 646
 647 /**
 648  * i915_pipe_enabled - check if a pipe is enabled
 649  * @dev: DRM device
 650  * @pipe: pipe to check
 651  *
 652  * Reading certain registers when the pipe is disabled can hang the chip.
 653  * Use this routine to make sure the PLL is running and the pipe is active
 654  * before reading such registers if unsure.
 655  */
 656 static int
 657 i915_pipe_enabled(struct drm_device *dev, int pipe)
 658 {
 659         struct drm_i915_private *dev_priv = dev->dev_private;
 660
 661         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 662                 /* Locking is horribly broken here, but whatever. */
 663                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 664                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 665
 666                 return intel_crtc->active;
 667         } else {
 668                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 669         }
 670 }
 671
 672 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 673 {
 674         /* Gen2 doesn't have a hardware frame counter */
 675         return 0;
 676 }
 677
 678 /* Called from drm generic code, passed a 'crtc', which
 679  * we use as a pipe index
 680  */
 681 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 682 {
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         unsigned long high_frame;
 685         unsigned long low_frame;
 686         u32 high1, high2, low, pixel, vbl_start;
 687
 688         if (!i915_pipe_enabled(dev, pipe)) {
 689                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 690                                 "pipe %c\n", pipe_name(pipe));
 691                 return 0;
 692         }
 693
 694         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 695                 struct intel_crtc *intel_crtc =
 696                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 697                 const struct drm_display_mode *mode =
 698                         &intel_crtc->config.adjusted_mode;
 699
 700                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 701         } else {
 702                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 703                 u32 htotal;
 704
 705                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 706                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 707
 708                 vbl_start *= htotal;
 709         }
 710
 711         high_frame = PIPEFRAME(pipe);
 712         low_frame = PIPEFRAMEPIXEL(pipe);
 713
 714         /*
 715          * High & low register fields aren't synchronized, so make sure
 716          * we get a low value that's stable across two reads of the high
 717          * register.
 718          */
 719         do {
 720                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 721                 low   = I915_READ(low_frame);
 722                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 723         } while (high1 != high2);
 724
 725         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 726         pixel = low & PIPE_PIXEL_MASK;
 727         low >>= PIPE_FRAME_LOW_SHIFT;
 728
 729         /*
 730          * The frame counter increments at beginning of active.
 731          * Cook up a vblank counter by also checking the pixel
 732          * counter against vblank start.
 733          */
 734         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 735 }
 736
 737 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 738 {
 739         struct drm_i915_private *dev_priv = dev->dev_private;
 740         int reg = PIPE_FRMCOUNT_GM45(pipe);
 741
 742         if (!i915_pipe_enabled(dev, pipe)) {
 743                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 744                                  "pipe %c\n", pipe_name(pipe));
 745                 return 0;
 746         }
 747
 748         return I915_READ(reg);
 749 }
 750
 751 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 752 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 753
 754 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 755 {
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         uint32_t status;
 758         int reg;
 759
 760         if (INTEL_INFO(dev)->gen >= 8) {
 761                 status = GEN8_PIPE_VBLANK;
 762                 reg = GEN8_DE_PIPE_ISR(pipe);
 763         } else if (INTEL_INFO(dev)->gen >= 7) {
 764                 status = DE_PIPE_VBLANK_IVB(pipe);
 765                 reg = DEISR;
 766         } else {
 767                 status = DE_PIPE_VBLANK(pipe);
 768                 reg = DEISR;
 769         }
 770
 771         return __raw_i915_read32(dev_priv, reg) & status;
 772 }
 773
 774 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 775                                     unsigned int flags, int *vpos, int *hpos,
 776                                     ktime_t *stime, ktime_t *etime)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 781         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 782         int position;
 783         int vbl_start, vbl_end, htotal, vtotal;
 784         bool in_vbl = true;
 785         int ret = 0;
 786         unsigned long irqflags;
 787
 788         if (!intel_crtc->active) {
 789                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 790                                  "pipe %c\n", pipe_name(pipe));
 791                 return 0;
 792         }
 793
 794         htotal = mode->crtc_htotal;
 795         vtotal = mode->crtc_vtotal;
 796         vbl_start = mode->crtc_vblank_start;
 797         vbl_end = mode->crtc_vblank_end;
 798
 799         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 800                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 801                 vbl_end /= 2;
 802                 vtotal /= 2;
 803         }
 804
 805         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 806
 807         /*
 808          * Lock uncore.lock, as we will do multiple timing critical raw
 809          * register reads, potentially with preemption disabled, so the
 810          * following code must not block on uncore.lock.
 811          */
 812         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 813
 814         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 815
 816         /* Get optional system timestamp before query. */
 817         if (stime)
 818                 *stime = ktime_get();
 819
 820         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 821                 /* No obvious pixelcount register. Only query vertical
 822                  * scanout position from Display scan line register.
 823                  */
 824                 if (IS_GEN2(dev))
 825                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 826                 else
 827                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 828
 829                 if (HAS_DDI(dev)) {
 830                         /*
 831                          * On HSW HDMI outputs there seems to be a 2 line
 832                          * difference, whereas eDP has the normal 1 line
 833                          * difference that earlier platforms have. External
 834                          * DP is unknown. For now just check for the 2 line
 835                          * difference case on all output types on HSW+.
 836                          *
 837                          * This might misinterpret the scanline counter being
 838                          * one line too far along on eDP, but that's less
 839                          * dangerous than the alternative since that would lead
 840                          * the vblank timestamp code astray when it sees a
 841                          * scanline count before vblank_start during a vblank
 842                          * interrupt.
 843                          */
 844                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 845                         if ((in_vbl && (position == vbl_start - 2 ||
 846                                         position == vbl_start - 1)) ||
 847                             (!in_vbl && (position == vbl_end - 2 ||
 848                                          position == vbl_end - 1)))
 849                                 position = (position + 2) % vtotal;
 850                 } else if (HAS_PCH_SPLIT(dev)) {
 851                         /*
 852                          * The scanline counter increments at the leading edge
 853                          * of hsync, ie. it completely misses the active portion
 854                          * of the line. Fix up the counter at both edges of vblank
 855                          * to get a more accurate picture whether we're in vblank
 856                          * or not.
 857                          */
 858                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 859                         if ((in_vbl && position == vbl_start - 1) ||
 860                             (!in_vbl && position == vbl_end - 1))
 861                                 position = (position + 1) % vtotal;
 862                 } else {
 863                         /*
 864                          * ISR vblank status bits don't work the way we'd want
 865                          * them to work on non-PCH platforms (for
 866                          * ilk_pipe_in_vblank_locked()), and there doesn't
 867                          * appear any other way to determine if we're currently
 868                          * in vblank.
 869                          *
 870                          * Instead let's assume that we're already in vblank if
 871                          * we got called from the vblank interrupt and the
 872                          * scanline counter value indicates that we're on the
 873                          * line just prior to vblank start. This should result
 874                          * in the correct answer, unless the vblank interrupt
 875                          * delivery really got delayed for almost exactly one
 876                          * full frame/field.
 877                          */
 878                         if (flags & DRM_CALLED_FROM_VBLIRQ &&
 879                             position == vbl_start - 1) {
 880                                 position = (position + 1) % vtotal;
 881
 882                                 /* Signal this correction as "applied". */
 883                                 ret |= 0x8;
 884                         }
 885                 }
 886         } else {
 887                 /* Have access to pixelcount since start of frame.
 888                  * We can split this into vertical and horizontal
 889                  * scanout position.
 890                  */
 891                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 892
 893                 /* convert to pixel counts */
 894                 vbl_start *= htotal;
 895                 vbl_end *= htotal;
 896                 vtotal *= htotal;
 897         }
 898
 899         /* Get optional system timestamp after query. */
 900         if (etime)
 901                 *etime = ktime_get();
 902
 903         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 904
 905         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 906
 907         in_vbl = position >= vbl_start && position < vbl_end;
 908
 909         /*
 910          * While in vblank, position will be negative
 911          * counting up towards 0 at vbl_end. And outside
 912          * vblank, position will be positive counting
 913          * up since vbl_end.
 914          */
 915         if (position >= vbl_start)
 916                 position -= vbl_end;
 917         else
 918                 position += vtotal - vbl_end;
 919
 920         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 921                 *vpos = position;
 922                 *hpos = 0;
 923         } else {
 924                 *vpos = position / htotal;
 925                 *hpos = position - (*vpos * htotal);
 926         }
 927
 928         /* In vblank? */
 929         if (in_vbl)
 930                 ret |= DRM_SCANOUTPOS_INVBL;
 931
 932         return ret;
 933 }
 934
 935 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 936                               int *max_error,
 937                               struct timeval *vblank_time,
 938                               unsigned flags)
 939 {
 940         struct drm_crtc *crtc;
 941
 942         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 943                 DRM_ERROR("Invalid crtc %d\n", pipe);
 944                 return -EINVAL;
 945         }
 946
 947         /* Get drm_crtc to timestamp: */
 948         crtc = intel_get_crtc_for_pipe(dev, pipe);
 949         if (crtc == NULL) {
 950                 DRM_ERROR("Invalid crtc %d\n", pipe);
 951                 return -EINVAL;
 952         }
 953
 954         if (!crtc->enabled) {
 955                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 956                 return -EBUSY;
 957         }
 958
 959         /* Helper routine in DRM core does all the work: */
 960         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 961                                                      vblank_time, flags,
 962                                                      crtc,
 963                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 964 }
 965
 966 static bool intel_hpd_irq_event(struct drm_device *dev,
 967                                 struct drm_connector *connector)
 968 {
 969         enum drm_connector_status old_status;
 970
 971         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 972         old_status = connector->status;
 973
 974         connector->status = connector->funcs->detect(connector, false);
 975         if (old_status == connector->status)
 976                 return false;
 977
 978         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 979                       connector->base.id,
 980                       drm_get_connector_name(connector),
 981                       drm_get_connector_status_name(old_status),
 982                       drm_get_connector_status_name(connector->status));
 983
 984         return true;
 985 }
 986
 987 /*
 988  * Handle hotplug events outside the interrupt handler proper.
 989  */
 990 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 991
 992 static void i915_hotplug_work_func(struct work_struct *work)
 993 {
 994         struct drm_i915_private *dev_priv =
 995                 container_of(work, struct drm_i915_private, hotplug_work);
 996         struct drm_device *dev = dev_priv->dev;
 997         struct drm_mode_config *mode_config = &dev->mode_config;
 998         struct intel_connector *intel_connector;
 999         struct intel_encoder *intel_encoder;
1000         struct drm_connector *connector;
1001         unsigned long irqflags;
1002         bool hpd_disabled = false;
1003         bool changed = false;
1004         u32 hpd_event_bits;
1005
1006         /* HPD irq before everything is fully set up. */
1007         if (!dev_priv->enable_hotplug_processing)
1008                 return;
1009
1010         mutex_lock(&mode_config->mutex);
1011         DRM_DEBUG_KMS("running encoder hotplug functions\n");
1012
1013         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1014
1015         hpd_event_bits = dev_priv->hpd_event_bits;
1016         dev_priv->hpd_event_bits = 0;
1017         list_for_each_entry(connector, &mode_config->connector_list, head) {
1018                 intel_connector = to_intel_connector(connector);
1019                 intel_encoder = intel_connector->encoder;
1020                 if (intel_encoder->hpd_pin > HPD_NONE &&
1021                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1022                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
1023                         DRM_INFO("HPD interrupt storm detected on connector %s: "
1024                                  "switching from hotplug detection to polling\n",
1025                                 drm_get_connector_name(connector));
1026                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1027                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
1028                                 | DRM_CONNECTOR_POLL_DISCONNECT;
1029                         hpd_disabled = true;
1030                 }
1031                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1032                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1033                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
1034                 }
1035         }
1036          /* if there were no outputs to poll, poll was disabled,
1037           * therefore make sure it's enabled when disabling HPD on
1038           * some connectors */
1039         if (hpd_disabled) {
1040                 drm_kms_helper_poll_enable(dev);
1041                 mod_timer(&dev_priv->hotplug_reenable_timer,
1042                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1043         }
1044
1045         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1046
1047         list_for_each_entry(connector, &mode_config->connector_list, head) {
1048                 intel_connector = to_intel_connector(connector);
1049                 intel_encoder = intel_connector->encoder;
1050                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1051                         if (intel_encoder->hot_plug)
1052                                 intel_encoder->hot_plug(intel_encoder);
1053                         if (intel_hpd_irq_event(dev, connector))
1054                                 changed = true;
1055                 }
1056         }
1057         mutex_unlock(&mode_config->mutex);
1058
1059         if (changed)
1060                 drm_kms_helper_hotplug_event(dev);
1061 }
1062
1063 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1064 {
1065         del_timer_sync(&dev_priv->hotplug_reenable_timer);
1066 }
1067
1068 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1069 {
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         u32 busy_up, busy_down, max_avg, min_avg;
1072         u8 new_delay;
1073
1074         spin_lock(&mchdev_lock);
1075
1076         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1077
1078         new_delay = dev_priv->ips.cur_delay;
1079
1080         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1081         busy_up = I915_READ(RCPREVBSYTUPAVG);
1082         busy_down = I915_READ(RCPREVBSYTDNAVG);
1083         max_avg = I915_READ(RCBMAXAVG);
1084         min_avg = I915_READ(RCBMINAVG);
1085
1086         /* Handle RCS change request from hw */
1087         if (busy_up > max_avg) {
1088                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1089                         new_delay = dev_priv->ips.cur_delay - 1;
1090                 if (new_delay < dev_priv->ips.max_delay)
1091                         new_delay = dev_priv->ips.max_delay;
1092         } else if (busy_down < min_avg) {
1093                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1094                         new_delay = dev_priv->ips.cur_delay + 1;
1095                 if (new_delay > dev_priv->ips.min_delay)
1096                         new_delay = dev_priv->ips.min_delay;
1097         }
1098
1099         if (ironlake_set_drps(dev, new_delay))
1100                 dev_priv->ips.cur_delay = new_delay;
1101
1102         spin_unlock(&mchdev_lock);
1103
1104         return;
1105 }
1106
1107 static void notify_ring(struct drm_device *dev,
1108                         struct intel_ring_buffer *ring)
1109 {
1110         if (ring->obj == NULL)
1111                 return;
1112
1113         trace_i915_gem_request_complete(ring);
1114
1115         wake_up_all(&ring->irq_queue);
1116         i915_queue_hangcheck(dev);
1117 }
1118
1119 static void gen6_pm_rps_work(struct work_struct *work)
1120 {
1121         struct drm_i915_private *dev_priv =
1122                 container_of(work, struct drm_i915_private, rps.work);
1123         u32 pm_iir;
1124         int new_delay, adj;
1125
1126         spin_lock_irq(&dev_priv->irq_lock);
1127         pm_iir = dev_priv->rps.pm_iir;
1128         dev_priv->rps.pm_iir = 0;
1129         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1130         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1131         spin_unlock_irq(&dev_priv->irq_lock);
1132
1133         /* Make sure we didn't queue anything we're not going to process. */
1134         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1135
1136         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1137                 return;
1138
1139         mutex_lock(&dev_priv->rps.hw_lock);
1140
1141         adj = dev_priv->rps.last_adj;
1142         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1143                 if (adj > 0)
1144                         adj *= 2;
1145                 else
1146                         adj = 1;
1147                 new_delay = dev_priv->rps.cur_freq + adj;
1148
1149                 /*
1150                  * For better performance, jump directly
1151                  * to RPe if we're below it.
1152                  */
1153                 if (new_delay < dev_priv->rps.efficient_freq)
1154                         new_delay = dev_priv->rps.efficient_freq;
1155         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1156                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1157                         new_delay = dev_priv->rps.efficient_freq;
1158                 else
1159                         new_delay = dev_priv->rps.min_freq_softlimit;
1160                 adj = 0;
1161         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1162                 if (adj < 0)
1163                         adj *= 2;
1164                 else
1165                         adj = -1;
1166                 new_delay = dev_priv->rps.cur_freq + adj;
1167         } else { /* unknown event */
1168                 new_delay = dev_priv->rps.cur_freq;
1169         }
1170
1171         /* sysfs frequency interfaces may have snuck in while servicing the
1172          * interrupt
1173          */
1174         new_delay = clamp_t(int, new_delay,
1175                             dev_priv->rps.min_freq_softlimit,
1176                             dev_priv->rps.max_freq_softlimit);
1177
1178         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1179
1180         if (IS_VALLEYVIEW(dev_priv->dev))
1181                 valleyview_set_rps(dev_priv->dev, new_delay);
1182         else
1183                 gen6_set_rps(dev_priv->dev, new_delay);
1184
1185         mutex_unlock(&dev_priv->rps.hw_lock);
1186 }
1187
1188
1189 /**
1190  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1191  * occurred.
1192  * @work: workqueue struct
1193  *
1194  * Doesn't actually do anything except notify userspace. As a consequence of
1195  * this event, userspace should try to remap the bad rows since statistically
1196  * it is likely the same row is more likely to go bad again.
1197  */
1198 static void ivybridge_parity_work(struct work_struct *work)
1199 {
1200         struct drm_i915_private *dev_priv =
1201                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1202         u32 error_status, row, bank, subbank;
1203         char *parity_event[6];
1204         uint32_t misccpctl;
1205         unsigned long flags;
1206         uint8_t slice = 0;
1207
1208         /* We must turn off DOP level clock gating to access the L3 registers.
1209          * In order to prevent a get/put style interface, acquire struct mutex
1210          * any time we access those registers.
1211          */
1212         mutex_lock(&dev_priv->dev->struct_mutex);
1213
1214         /* If we've screwed up tracking, just let the interrupt fire again */
1215         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1216                 goto out;
1217
1218         misccpctl = I915_READ(GEN7_MISCCPCTL);
1219         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1220         POSTING_READ(GEN7_MISCCPCTL);
1221
1222         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1223                 u32 reg;
1224
1225                 slice--;
1226                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1227                         break;
1228
1229                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1230
1231                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1232
1233                 error_status = I915_READ(reg);
1234                 row = GEN7_PARITY_ERROR_ROW(error_status);
1235                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1236                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1237
1238                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1239                 POSTING_READ(reg);
1240
1241                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1242                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1243                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1244                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1245                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1246                 parity_event[5] = NULL;
1247
1248                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1249                                    KOBJ_CHANGE, parity_event);
1250
1251                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1252                           slice, row, bank, subbank);
1253
1254                 kfree(parity_event[4]);
1255                 kfree(parity_event[3]);
1256                 kfree(parity_event[2]);
1257                 kfree(parity_event[1]);
1258         }
1259
1260         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1261
1262 out:
1263         WARN_ON(dev_priv->l3_parity.which_slice);
1264         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1265         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1266         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1267
1268         mutex_unlock(&dev_priv->dev->struct_mutex);
1269 }
1270
1271 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1272 {
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274
1275         if (!HAS_L3_DPF(dev))
1276                 return;
1277
1278         spin_lock(&dev_priv->irq_lock);
1279         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1280         spin_unlock(&dev_priv->irq_lock);
1281
1282         iir &= GT_PARITY_ERROR(dev);
1283         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1284                 dev_priv->l3_parity.which_slice |= 1 << 1;
1285
1286         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1287                 dev_priv->l3_parity.which_slice |= 1 << 0;
1288
1289         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1290 }
1291
1292 static void ilk_gt_irq_handler(struct drm_device *dev,
1293                                struct drm_i915_private *dev_priv,
1294                                u32 gt_iir)
1295 {
1296         if (gt_iir &
1297             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1298                 notify_ring(dev, &dev_priv->ring[RCS]);
1299         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1300                 notify_ring(dev, &dev_priv->ring[VCS]);
1301 }
1302
1303 static void snb_gt_irq_handler(struct drm_device *dev,
1304                                struct drm_i915_private *dev_priv,
1305                                u32 gt_iir)
1306 {
1307
1308         if (gt_iir &
1309             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1310                 notify_ring(dev, &dev_priv->ring[RCS]);
1311         if (gt_iir & GT_BSD_USER_INTERRUPT)
1312                 notify_ring(dev, &dev_priv->ring[VCS]);
1313         if (gt_iir & GT_BLT_USER_INTERRUPT)
1314                 notify_ring(dev, &dev_priv->ring[BCS]);
1315
1316         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1317                       GT_BSD_CS_ERROR_INTERRUPT |
1318                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1319                 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1320                                   gt_iir);
1321         }
1322
1323         if (gt_iir & GT_PARITY_ERROR(dev))
1324                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1325 }
1326
1327 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1328                                        struct drm_i915_private *dev_priv,
1329                                        u32 master_ctl)
1330 {
1331         u32 rcs, bcs, vcs;
1332         uint32_t tmp = 0;
1333         irqreturn_t ret = IRQ_NONE;
1334
1335         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1336                 tmp = I915_READ(GEN8_GT_IIR(0));
1337                 if (tmp) {
1338                         ret = IRQ_HANDLED;
1339                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1340                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1341                         if (rcs & GT_RENDER_USER_INTERRUPT)
1342                                 notify_ring(dev, &dev_priv->ring[RCS]);
1343                         if (bcs & GT_RENDER_USER_INTERRUPT)
1344                                 notify_ring(dev, &dev_priv->ring[BCS]);
1345                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1346                 } else
1347                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1348         }
1349
1350         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1351                 tmp = I915_READ(GEN8_GT_IIR(1));
1352                 if (tmp) {
1353                         ret = IRQ_HANDLED;
1354                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1355                         if (vcs & GT_RENDER_USER_INTERRUPT)
1356                                 notify_ring(dev, &dev_priv->ring[VCS]);
1357                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1358                 } else
1359                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1360         }
1361
1362         if (master_ctl & GEN8_GT_VECS_IRQ) {
1363                 tmp = I915_READ(GEN8_GT_IIR(3));
1364                 if (tmp) {
1365                         ret = IRQ_HANDLED;
1366                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1367                         if (vcs & GT_RENDER_USER_INTERRUPT)
1368                                 notify_ring(dev, &dev_priv->ring[VECS]);
1369                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1370                 } else
1371                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1372         }
1373
1374         return ret;
1375 }
1376
1377 #define HPD_STORM_DETECT_PERIOD 1000
1378 #define HPD_STORM_THRESHOLD 5
1379
1380 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1381                                          u32 hotplug_trigger,
1382                                          const u32 *hpd)
1383 {
1384         struct drm_i915_private *dev_priv = dev->dev_private;
1385         int i;
1386         bool storm_detected = false;
1387
1388         if (!hotplug_trigger)
1389                 return;
1390
1391         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1392                           hotplug_trigger);
1393
1394         spin_lock(&dev_priv->irq_lock);
1395         for (i = 1; i < HPD_NUM_PINS; i++) {
1396
1397                 if (hpd[i] & hotplug_trigger &&
1398                     dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1399                         /*
1400                          * On GMCH platforms the interrupt mask bits only
1401                          * prevent irq generation, not the setting of the
1402                          * hotplug bits itself. So only WARN about unexpected
1403                          * interrupts on saner platforms.
1404                          */
1405                         WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1406                                   "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1407                                   hotplug_trigger, i, hpd[i]);
1408
1409                         continue;
1410                 }
1411
1412                 if (!(hpd[i] & hotplug_trigger) ||
1413                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1414                         continue;
1415
1416                 dev_priv->hpd_event_bits |= (1 << i);
1417                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1418                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1419                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1420                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1421                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1422                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1423                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1424                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1425                         dev_priv->hpd_event_bits &= ~(1 << i);
1426                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1427                         storm_detected = true;
1428                 } else {
1429                         dev_priv->hpd_stats[i].hpd_cnt++;
1430                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1431                                       dev_priv->hpd_stats[i].hpd_cnt);
1432                 }
1433         }
1434
1435         if (storm_detected)
1436                 dev_priv->display.hpd_irq_setup(dev);
1437         spin_unlock(&dev_priv->irq_lock);
1438
1439         /*
1440          * Our hotplug handler can grab modeset locks (by calling down into the
1441          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1442          * queue for otherwise the flush_work in the pageflip code will
1443          * deadlock.
1444          */
1445         schedule_work(&dev_priv->hotplug_work);
1446 }
1447
1448 static void gmbus_irq_handler(struct drm_device *dev)
1449 {
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451
1452         wake_up_all(&dev_priv->gmbus_wait_queue);
1453 }
1454
1455 static void dp_aux_irq_handler(struct drm_device *dev)
1456 {
1457         struct drm_i915_private *dev_priv = dev->dev_private;
1458
1459         wake_up_all(&dev_priv->gmbus_wait_queue);
1460 }
1461
1462 #if defined(CONFIG_DEBUG_FS)
1463 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1464                                          uint32_t crc0, uint32_t crc1,
1465                                          uint32_t crc2, uint32_t crc3,
1466                                          uint32_t crc4)
1467 {
1468         struct drm_i915_private *dev_priv = dev->dev_private;
1469         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1470         struct intel_pipe_crc_entry *entry;
1471         int head, tail;
1472
1473         spin_lock(&pipe_crc->lock);
1474
1475         if (!pipe_crc->entries) {
1476                 spin_unlock(&pipe_crc->lock);
1477                 DRM_ERROR("spurious interrupt\n");
1478                 return;
1479         }
1480
1481         head = pipe_crc->head;
1482         tail = pipe_crc->tail;
1483
1484         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1485                 spin_unlock(&pipe_crc->lock);
1486                 DRM_ERROR("CRC buffer overflowing\n");
1487                 return;
1488         }
1489
1490         entry = &pipe_crc->entries[head];
1491
1492         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1493         entry->crc[0] = crc0;
1494         entry->crc[1] = crc1;
1495         entry->crc[2] = crc2;
1496         entry->crc[3] = crc3;
1497         entry->crc[4] = crc4;
1498
1499         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1500         pipe_crc->head = head;
1501
1502         spin_unlock(&pipe_crc->lock);
1503
1504         wake_up_interruptible(&pipe_crc->wq);
1505 }
1506 #else
1507 static inline void
1508 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1509                              uint32_t crc0, uint32_t crc1,
1510                              uint32_t crc2, uint32_t crc3,
1511                              uint32_t crc4) {}
1512 #endif
1513
1514
1515 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1516 {
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518
1519         display_pipe_crc_irq_handler(dev, pipe,
1520                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1521                                      0, 0, 0, 0);
1522 }
1523
1524 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1525 {
1526         struct drm_i915_private *dev_priv = dev->dev_private;
1527
1528         display_pipe_crc_irq_handler(dev, pipe,
1529                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1530                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1531                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1532                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1533                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1534 }
1535
1536 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1537 {
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         uint32_t res1, res2;
1540
1541         if (INTEL_INFO(dev)->gen >= 3)
1542                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1543         else
1544                 res1 = 0;
1545
1546         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1547                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1548         else
1549                 res2 = 0;
1550
1551         display_pipe_crc_irq_handler(dev, pipe,
1552                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1553                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1554                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1555                                      res1, res2);
1556 }
1557
1558 /* The RPS events need forcewake, so we add them to a work queue and mask their
1559  * IMR bits until the work is done. Other interrupts can be processed without
1560  * the work queue. */
1561 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1562 {
1563         if (pm_iir & dev_priv->pm_rps_events) {
1564                 spin_lock(&dev_priv->irq_lock);
1565                 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1566                 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1567                 spin_unlock(&dev_priv->irq_lock);
1568
1569                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1570         }
1571
1572         if (HAS_VEBOX(dev_priv->dev)) {
1573                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1574                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1575
1576                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1577                         i915_handle_error(dev_priv->dev, false,
1578                                           "VEBOX CS error interrupt 0x%08x",
1579                                           pm_iir);
1580                 }
1581         }
1582 }
1583
1584 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1585 {
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         u32 pipe_stats[I915_MAX_PIPES] = { };
1588         int pipe;
1589
1590         spin_lock(&dev_priv->irq_lock);
1591         for_each_pipe(pipe) {
1592                 int reg;
1593                 u32 mask, iir_bit = 0;
1594
1595                 /*
1596                  * PIPESTAT bits get signalled even when the interrupt is
1597                  * disabled with the mask bits, and some of the status bits do
1598                  * not generate interrupts at all (like the underrun bit). Hence
1599                  * we need to be careful that we only handle what we want to
1600                  * handle.
1601                  */
1602                 mask = 0;
1603                 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1604                         mask |= PIPE_FIFO_UNDERRUN_STATUS;
1605
1606                 switch (pipe) {
1607                 case PIPE_A:
1608                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1609                         break;
1610                 case PIPE_B:
1611                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1612                         break;
1613                 }
1614                 if (iir & iir_bit)
1615                         mask |= dev_priv->pipestat_irq_mask[pipe];
1616
1617                 if (!mask)
1618                         continue;
1619
1620                 reg = PIPESTAT(pipe);
1621                 mask |= PIPESTAT_INT_ENABLE_MASK;
1622                 pipe_stats[pipe] = I915_READ(reg) & mask;
1623
1624                 /*
1625                  * Clear the PIPE*STAT regs before the IIR
1626                  */
1627                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1628                                         PIPESTAT_INT_STATUS_MASK))
1629                         I915_WRITE(reg, pipe_stats[pipe]);
1630         }
1631         spin_unlock(&dev_priv->irq_lock);
1632
1633         for_each_pipe(pipe) {
1634                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1635                         drm_handle_vblank(dev, pipe);
1636
1637                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1638                         intel_prepare_page_flip(dev, pipe);
1639                         intel_finish_page_flip(dev, pipe);
1640                 }
1641
1642                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1643                         i9xx_pipe_crc_irq_handler(dev, pipe);
1644
1645                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1646                     intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1647                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1648         }
1649
1650         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1651                 gmbus_irq_handler(dev);
1652 }
1653
1654 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1655 {
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1658
1659         if (IS_G4X(dev)) {
1660                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1661
1662                 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1663         } else {
1664                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1665
1666                 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1667         }
1668
1669         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1670             hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1671                 dp_aux_irq_handler(dev);
1672
1673         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1674         /*
1675          * Make sure hotplug status is cleared before we clear IIR, or else we
1676          * may miss hotplug events.
1677          */
1678         POSTING_READ(PORT_HOTPLUG_STAT);
1679 }
1680
1681 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1682 {
1683         struct drm_device *dev = (struct drm_device *) arg;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         u32 iir, gt_iir, pm_iir;
1686         irqreturn_t ret = IRQ_NONE;
1687
1688         while (true) {
1689                 iir = I915_READ(VLV_IIR);
1690                 gt_iir = I915_READ(GTIIR);
1691                 pm_iir = I915_READ(GEN6_PMIIR);
1692
1693                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1694                         goto out;
1695
1696                 ret = IRQ_HANDLED;
1697
1698                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1699
1700                 valleyview_pipestat_irq_handler(dev, iir);
1701
1702                 /* Consume port.  Then clear IIR or we'll miss events */
1703                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1704                         i9xx_hpd_irq_handler(dev);
1705
1706                 if (pm_iir)
1707                         gen6_rps_irq_handler(dev_priv, pm_iir);
1708
1709                 I915_WRITE(GTIIR, gt_iir);
1710                 I915_WRITE(GEN6_PMIIR, pm_iir);
1711                 I915_WRITE(VLV_IIR, iir);
1712         }
1713
1714 out:
1715         return ret;
1716 }
1717
1718 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1719 {
1720         struct drm_i915_private *dev_priv = dev->dev_private;
1721         int pipe;
1722         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1723
1724         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1725
1726         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1727                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1728                                SDE_AUDIO_POWER_SHIFT);
1729                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1730                                  port_name(port));
1731         }
1732
1733         if (pch_iir & SDE_AUX_MASK)
1734                 dp_aux_irq_handler(dev);
1735
1736         if (pch_iir & SDE_GMBUS)
1737                 gmbus_irq_handler(dev);
1738
1739         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1740                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1741
1742         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1743                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1744
1745         if (pch_iir & SDE_POISON)
1746                 DRM_ERROR("PCH poison interrupt\n");
1747
1748         if (pch_iir & SDE_FDI_MASK)
1749                 for_each_pipe(pipe)
1750                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1751                                          pipe_name(pipe),
1752                                          I915_READ(FDI_RX_IIR(pipe)));
1753
1754         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1755                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1756
1757         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1758                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1759
1760         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1761                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1762                                                           false))
1763                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1764
1765         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1766                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1767                                                           false))
1768                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1769 }
1770
1771 static void ivb_err_int_handler(struct drm_device *dev)
1772 {
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         u32 err_int = I915_READ(GEN7_ERR_INT);
1775         enum pipe pipe;
1776
1777         if (err_int & ERR_INT_POISON)
1778                 DRM_ERROR("Poison interrupt\n");
1779
1780         for_each_pipe(pipe) {
1781                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1782                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1783                                                                   false))
1784                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1785                                           pipe_name(pipe));
1786                 }
1787
1788                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1789                         if (IS_IVYBRIDGE(dev))
1790                                 ivb_pipe_crc_irq_handler(dev, pipe);
1791                         else
1792                                 hsw_pipe_crc_irq_handler(dev, pipe);
1793                 }
1794         }
1795
1796         I915_WRITE(GEN7_ERR_INT, err_int);
1797 }
1798
1799 static void cpt_serr_int_handler(struct drm_device *dev)
1800 {
1801         struct drm_i915_private *dev_priv = dev->dev_private;
1802         u32 serr_int = I915_READ(SERR_INT);
1803
1804         if (serr_int & SERR_INT_POISON)
1805                 DRM_ERROR("PCH poison interrupt\n");
1806
1807         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1808                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1809                                                           false))
1810                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1811
1812         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1813                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1814                                                           false))
1815                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1816
1817         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1818                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1819                                                           false))
1820                         DRM_ERROR("PCH transcoder C FIFO underrun\n");
1821
1822         I915_WRITE(SERR_INT, serr_int);
1823 }
1824
1825 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1826 {
1827         struct drm_i915_private *dev_priv = dev->dev_private;
1828         int pipe;
1829         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1830
1831         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1832
1833         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1834                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1835                                SDE_AUDIO_POWER_SHIFT_CPT);
1836                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1837                                  port_name(port));
1838         }
1839
1840         if (pch_iir & SDE_AUX_MASK_CPT)
1841                 dp_aux_irq_handler(dev);
1842
1843         if (pch_iir & SDE_GMBUS_CPT)
1844                 gmbus_irq_handler(dev);
1845
1846         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1847                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1848
1849         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1850                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1851
1852         if (pch_iir & SDE_FDI_MASK_CPT)
1853                 for_each_pipe(pipe)
1854                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1855                                          pipe_name(pipe),
1856                                          I915_READ(FDI_RX_IIR(pipe)));
1857
1858         if (pch_iir & SDE_ERROR_CPT)
1859                 cpt_serr_int_handler(dev);
1860 }
1861
1862 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1863 {
1864         struct drm_i915_private *dev_priv = dev->dev_private;
1865         enum pipe pipe;
1866
1867         if (de_iir & DE_AUX_CHANNEL_A)
1868                 dp_aux_irq_handler(dev);
1869
1870         if (de_iir & DE_GSE)
1871                 intel_opregion_asle_intr(dev);
1872
1873         if (de_iir & DE_POISON)
1874                 DRM_ERROR("Poison interrupt\n");
1875
1876         for_each_pipe(pipe) {
1877                 if (de_iir & DE_PIPE_VBLANK(pipe))
1878                         drm_handle_vblank(dev, pipe);
1879
1880                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1881                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1882                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1883                                           pipe_name(pipe));
1884
1885                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1886                         i9xx_pipe_crc_irq_handler(dev, pipe);
1887
1888                 /* plane/pipes map 1:1 on ilk+ */
1889                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1890                         intel_prepare_page_flip(dev, pipe);
1891                         intel_finish_page_flip_plane(dev, pipe);
1892                 }
1893         }
1894
1895         /* check event from PCH */
1896         if (de_iir & DE_PCH_EVENT) {
1897                 u32 pch_iir = I915_READ(SDEIIR);
1898
1899                 if (HAS_PCH_CPT(dev))
1900                         cpt_irq_handler(dev, pch_iir);
1901                 else
1902                         ibx_irq_handler(dev, pch_iir);
1903
1904                 /* should clear PCH hotplug event before clear CPU irq */
1905                 I915_WRITE(SDEIIR, pch_iir);
1906         }
1907
1908         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1909                 ironlake_rps_change_irq_handler(dev);
1910 }
1911
1912 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1913 {
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915         enum pipe pipe;
1916
1917         if (de_iir & DE_ERR_INT_IVB)
1918                 ivb_err_int_handler(dev);
1919
1920         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1921                 dp_aux_irq_handler(dev);
1922
1923         if (de_iir & DE_GSE_IVB)
1924                 intel_opregion_asle_intr(dev);
1925
1926         for_each_pipe(pipe) {
1927                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1928                         drm_handle_vblank(dev, pipe);
1929
1930                 /* plane/pipes map 1:1 on ilk+ */
1931                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1932                         intel_prepare_page_flip(dev, pipe);
1933                         intel_finish_page_flip_plane(dev, pipe);
1934                 }
1935         }
1936
1937         /* check event from PCH */
1938         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1939                 u32 pch_iir = I915_READ(SDEIIR);
1940
1941                 cpt_irq_handler(dev, pch_iir);
1942
1943                 /* clear PCH hotplug event before clear CPU irq */
1944                 I915_WRITE(SDEIIR, pch_iir);
1945         }
1946 }
1947
1948 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1949 {
1950         struct drm_device *dev = (struct drm_device *) arg;
1951         struct drm_i915_private *dev_priv = dev->dev_private;
1952         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1953         irqreturn_t ret = IRQ_NONE;
1954
1955         /* We get interrupts on unclaimed registers, so check for this before we
1956          * do any I915_{READ,WRITE}. */
1957         intel_uncore_check_errors(dev);
1958
1959         /* disable master interrupt before clearing iir  */
1960         de_ier = I915_READ(DEIER);
1961         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1962         POSTING_READ(DEIER);
1963
1964         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1965          * interrupts will will be stored on its back queue, and then we'll be
1966          * able to process them after we restore SDEIER (as soon as we restore
1967          * it, we'll get an interrupt if SDEIIR still has something to process
1968          * due to its back queue). */
1969         if (!HAS_PCH_NOP(dev)) {
1970                 sde_ier = I915_READ(SDEIER);
1971                 I915_WRITE(SDEIER, 0);
1972                 POSTING_READ(SDEIER);
1973         }
1974
1975         gt_iir = I915_READ(GTIIR);
1976         if (gt_iir) {
1977                 if (INTEL_INFO(dev)->gen >= 6)
1978                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1979                 else
1980                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1981                 I915_WRITE(GTIIR, gt_iir);
1982                 ret = IRQ_HANDLED;
1983         }
1984
1985         de_iir = I915_READ(DEIIR);
1986         if (de_iir) {
1987                 if (INTEL_INFO(dev)->gen >= 7)
1988                         ivb_display_irq_handler(dev, de_iir);
1989                 else
1990                         ilk_display_irq_handler(dev, de_iir);
1991                 I915_WRITE(DEIIR, de_iir);
1992                 ret = IRQ_HANDLED;
1993         }
1994
1995         if (INTEL_INFO(dev)->gen >= 6) {
1996                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1997                 if (pm_iir) {
1998                         gen6_rps_irq_handler(dev_priv, pm_iir);
1999                         I915_WRITE(GEN6_PMIIR, pm_iir);
2000                         ret = IRQ_HANDLED;
2001                 }
2002         }
2003
2004         I915_WRITE(DEIER, de_ier);
2005         POSTING_READ(DEIER);
2006         if (!HAS_PCH_NOP(dev)) {
2007                 I915_WRITE(SDEIER, sde_ier);
2008                 POSTING_READ(SDEIER);
2009         }
2010
2011         return ret;
2012 }
2013
2014 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2015 {
2016         struct drm_device *dev = arg;
2017         struct drm_i915_private *dev_priv = dev->dev_private;
2018         u32 master_ctl;
2019         irqreturn_t ret = IRQ_NONE;
2020         uint32_t tmp = 0;
2021         enum pipe pipe;
2022
2023         master_ctl = I915_READ(GEN8_MASTER_IRQ);
2024         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2025         if (!master_ctl)
2026                 return IRQ_NONE;
2027
2028         I915_WRITE(GEN8_MASTER_IRQ, 0);
2029         POSTING_READ(GEN8_MASTER_IRQ);
2030
2031         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2032
2033         if (master_ctl & GEN8_DE_MISC_IRQ) {
2034                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2035                 if (tmp & GEN8_DE_MISC_GSE)
2036                         intel_opregion_asle_intr(dev);
2037                 else if (tmp)
2038                         DRM_ERROR("Unexpected DE Misc interrupt\n");
2039                 else
2040                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2041
2042                 if (tmp) {
2043                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2044                         ret = IRQ_HANDLED;
2045                 }
2046         }
2047
2048         if (master_ctl & GEN8_DE_PORT_IRQ) {
2049                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2050                 if (tmp & GEN8_AUX_CHANNEL_A)
2051                         dp_aux_irq_handler(dev);
2052                 else if (tmp)
2053                         DRM_ERROR("Unexpected DE Port interrupt\n");
2054                 else
2055                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2056
2057                 if (tmp) {
2058                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2059                         ret = IRQ_HANDLED;
2060                 }
2061         }
2062
2063         for_each_pipe(pipe) {
2064                 uint32_t pipe_iir;
2065
2066                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2067                         continue;
2068
2069                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2070                 if (pipe_iir & GEN8_PIPE_VBLANK)
2071                         drm_handle_vblank(dev, pipe);
2072
2073                 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2074                         intel_prepare_page_flip(dev, pipe);
2075                         intel_finish_page_flip_plane(dev, pipe);
2076                 }
2077
2078                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2079                         hsw_pipe_crc_irq_handler(dev, pipe);
2080
2081                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2082                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2083                                                                   false))
2084                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2085                                           pipe_name(pipe));
2086                 }
2087
2088                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2089                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2090                                   pipe_name(pipe),
2091                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2092                 }
2093
2094                 if (pipe_iir) {
2095                         ret = IRQ_HANDLED;
2096                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2097                 } else
2098                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2099         }
2100
2101         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2102                 /*
2103                  * FIXME(BDW): Assume for now that the new interrupt handling
2104                  * scheme also closed the SDE interrupt handling race we've seen
2105                  * on older pch-split platforms. But this needs testing.
2106                  */
2107                 u32 pch_iir = I915_READ(SDEIIR);
2108
2109                 cpt_irq_handler(dev, pch_iir);
2110
2111                 if (pch_iir) {
2112                         I915_WRITE(SDEIIR, pch_iir);
2113                         ret = IRQ_HANDLED;
2114                 }
2115         }
2116
2117         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2118         POSTING_READ(GEN8_MASTER_IRQ);
2119
2120         return ret;
2121 }
2122
2123 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2124                                bool reset_completed)
2125 {
2126         struct intel_ring_buffer *ring;
2127         int i;
2128
2129         /*
2130          * Notify all waiters for GPU completion events that reset state has
2131          * been changed, and that they need to restart their wait after
2132          * checking for potential errors (and bail out to drop locks if there is
2133          * a gpu reset pending so that i915_error_work_func can acquire them).
2134          */
2135
2136         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2137         for_each_ring(ring, dev_priv, i)
2138                 wake_up_all(&ring->irq_queue);
2139
2140         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2141         wake_up_all(&dev_priv->pending_flip_queue);
2142
2143         /*
2144          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2145          * reset state is cleared.
2146          */
2147         if (reset_completed)
2148                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2149 }
2150
2151 /**
2152  * i915_error_work_func - do process context error handling work
2153  * @work: work struct
2154  *
2155  * Fire an error uevent so userspace can see that a hang or error
2156  * was detected.
2157  */
2158 static void i915_error_work_func(struct work_struct *work)
2159 {
2160         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2161                                                     work);
2162         struct drm_i915_private *dev_priv =
2163                 container_of(error, struct drm_i915_private, gpu_error);
2164         struct drm_device *dev = dev_priv->dev;
2165         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2166         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2167         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2168         int ret;
2169
2170         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2171
2172         /*
2173          * Note that there's only one work item which does gpu resets, so we
2174          * need not worry about concurrent gpu resets potentially incrementing
2175          * error->reset_counter twice. We only need to take care of another
2176          * racing irq/hangcheck declaring the gpu dead for a second time. A
2177          * quick check for that is good enough: schedule_work ensures the
2178          * correct ordering between hang detection and this work item, and since
2179          * the reset in-progress bit is only ever set by code outside of this
2180          * work we don't need to worry about any other races.
2181          */
2182         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2183                 DRM_DEBUG_DRIVER("resetting chip\n");
2184                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2185                                    reset_event);
2186
2187                 /*
2188                  * All state reset _must_ be completed before we update the
2189                  * reset counter, for otherwise waiters might miss the reset
2190                  * pending state and not properly drop locks, resulting in
2191                  * deadlocks with the reset work.
2192                  */
2193                 ret = i915_reset(dev);
2194
2195                 intel_display_handle_reset(dev);
2196
2197                 if (ret == 0) {
2198                         /*
2199                          * After all the gem state is reset, increment the reset
2200                          * counter and wake up everyone waiting for the reset to
2201                          * complete.
2202                          *
2203                          * Since unlock operations are a one-sided barrier only,
2204                          * we need to insert a barrier here to order any seqno
2205                          * updates before
2206                          * the counter increment.
2207                          */
2208                         smp_mb__before_atomic_inc();
2209                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2210
2211                         kobject_uevent_env(&dev->primary->kdev->kobj,
2212                                            KOBJ_CHANGE, reset_done_event);
2213                 } else {
2214                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2215                 }
2216
2217                 /*
2218                  * Note: The wake_up also serves as a memory barrier so that
2219                  * waiters see the update value of the reset counter atomic_t.
2220                  */
2221                 i915_error_wake_up(dev_priv, true);
2222         }
2223 }
2224
2225 static void i915_report_and_clear_eir(struct drm_device *dev)
2226 {
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228         uint32_t instdone[I915_NUM_INSTDONE_REG];
2229         u32 eir = I915_READ(EIR);
2230         int pipe, i;
2231
2232         if (!eir)
2233                 return;
2234
2235         pr_err("render error detected, EIR: 0x%08x\n", eir);
2236
2237         i915_get_extra_instdone(dev, instdone);
2238
2239         if (IS_G4X(dev)) {
2240                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2241                         u32 ipeir = I915_READ(IPEIR_I965);
2242
2243                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2244                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2245                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2246                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2247                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2248                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2249                         I915_WRITE(IPEIR_I965, ipeir);
2250                         POSTING_READ(IPEIR_I965);
2251                 }
2252                 if (eir & GM45_ERROR_PAGE_TABLE) {
2253                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2254                         pr_err("page table error\n");
2255                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2256                         I915_WRITE(PGTBL_ER, pgtbl_err);
2257                         POSTING_READ(PGTBL_ER);
2258                 }
2259         }
2260
2261         if (!IS_GEN2(dev)) {
2262                 if (eir & I915_ERROR_PAGE_TABLE) {
2263                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2264                         pr_err("page table error\n");
2265                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2266                         I915_WRITE(PGTBL_ER, pgtbl_err);
2267                         POSTING_READ(PGTBL_ER);
2268                 }
2269         }
2270
2271         if (eir & I915_ERROR_MEMORY_REFRESH) {
2272                 pr_err("memory refresh error:\n");
2273                 for_each_pipe(pipe)
2274                         pr_err("pipe %c stat: 0x%08x\n",
2275                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2276                 /* pipestat has already been acked */
2277         }
2278         if (eir & I915_ERROR_INSTRUCTION) {
2279                 pr_err("instruction error\n");
2280                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2281                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2282                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2283                 if (INTEL_INFO(dev)->gen < 4) {
2284                         u32 ipeir = I915_READ(IPEIR);
2285
2286                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2287                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2288                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2289                         I915_WRITE(IPEIR, ipeir);
2290                         POSTING_READ(IPEIR);
2291                 } else {
2292                         u32 ipeir = I915_READ(IPEIR_I965);
2293
2294                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2295                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2296                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2297                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2298                         I915_WRITE(IPEIR_I965, ipeir);
2299                         POSTING_READ(IPEIR_I965);
2300                 }
2301         }
2302
2303         I915_WRITE(EIR, eir);
2304         POSTING_READ(EIR);
2305         eir = I915_READ(EIR);
2306         if (eir) {
2307                 /*
2308                  * some errors might have become stuck,
2309                  * mask them.
2310                  */
2311                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2312                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2313                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2314         }
2315 }
2316
2317 /**
2318  * i915_handle_error - handle an error interrupt
2319  * @dev: drm device
2320  *
2321  * Do some basic checking of regsiter state at error interrupt time and
2322  * dump it to the syslog.  Also call i915_capture_error_state() to make
2323  * sure we get a record and make it available in debugfs.  Fire a uevent
2324  * so userspace knows something bad happened (should trigger collection
2325  * of a ring dump etc.).
2326  */
2327 void i915_handle_error(struct drm_device *dev, bool wedged,
2328                        const char *fmt, ...)
2329 {
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         va_list args;
2332         char error_msg[80];
2333
2334         va_start(args, fmt);
2335         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2336         va_end(args);
2337
2338         i915_capture_error_state(dev, wedged, error_msg);
2339         i915_report_and_clear_eir(dev);
2340
2341         if (wedged) {
2342                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2343                                 &dev_priv->gpu_error.reset_counter);
2344
2345                 /*
2346                  * Wakeup waiting processes so that the reset work function
2347                  * i915_error_work_func doesn't deadlock trying to grab various
2348                  * locks. By bumping the reset counter first, the woken
2349                  * processes will see a reset in progress and back off,
2350                  * releasing their locks and then wait for the reset completion.
2351                  * We must do this for _all_ gpu waiters that might hold locks
2352                  * that the reset work needs to acquire.
2353                  *
2354                  * Note: The wake_up serves as the required memory barrier to
2355                  * ensure that the waiters see the updated value of the reset
2356                  * counter atomic_t.
2357                  */
2358                 i915_error_wake_up(dev_priv, false);
2359         }
2360
2361         /*
2362          * Our reset work can grab modeset locks (since it needs to reset the
2363          * state of outstanding pagelips). Hence it must not be run on our own
2364          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2365          * code will deadlock.
2366          */
2367         schedule_work(&dev_priv->gpu_error.work);
2368 }
2369
2370 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2371 {
2372         struct drm_i915_private *dev_priv = dev->dev_private;
2373         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375         struct drm_i915_gem_object *obj;
2376         struct intel_unpin_work *work;
2377         unsigned long flags;
2378         bool stall_detected;
2379
2380         /* Ignore early vblank irqs */
2381         if (intel_crtc == NULL)
2382                 return;
2383
2384         spin_lock_irqsave(&dev->event_lock, flags);
2385         work = intel_crtc->unpin_work;
2386
2387         if (work == NULL ||
2388             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2389             !work->enable_stall_check) {
2390                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2391                 spin_unlock_irqrestore(&dev->event_lock, flags);
2392                 return;
2393         }
2394
2395         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2396         obj = work->pending_flip_obj;
2397         if (INTEL_INFO(dev)->gen >= 4) {
2398                 int dspsurf = DSPSURF(intel_crtc->plane);
2399                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2400                                         i915_gem_obj_ggtt_offset(obj);
2401         } else {
2402                 int dspaddr = DSPADDR(intel_crtc->plane);
2403                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2404                                                         crtc->y * crtc->primary->fb->pitches[0] +
2405                                                         crtc->x * crtc->primary->fb->bits_per_pixel/8);
2406         }
2407
2408         spin_unlock_irqrestore(&dev->event_lock, flags);
2409
2410         if (stall_detected) {
2411                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2412                 intel_prepare_page_flip(dev, intel_crtc->plane);
2413         }
2414 }
2415
2416 /* Called from drm generic code, passed 'crtc' which
2417  * we use as a pipe index
2418  */
2419 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2420 {
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         unsigned long irqflags;
2423
2424         if (!i915_pipe_enabled(dev, pipe))
2425                 return -EINVAL;
2426
2427         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2428         if (INTEL_INFO(dev)->gen >= 4)
2429                 i915_enable_pipestat(dev_priv, pipe,
2430                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2431         else
2432                 i915_enable_pipestat(dev_priv, pipe,
2433                                      PIPE_VBLANK_INTERRUPT_STATUS);
2434
2435         /* maintain vblank delivery even in deep C-states */
2436         if (INTEL_INFO(dev)->gen == 3)
2437                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2438         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2439
2440         return 0;
2441 }
2442
2443 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2444 {
2445         struct drm_i915_private *dev_priv = dev->dev_private;
2446         unsigned long irqflags;
2447         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2448                                                      DE_PIPE_VBLANK(pipe);
2449
2450         if (!i915_pipe_enabled(dev, pipe))
2451                 return -EINVAL;
2452
2453         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2454         ironlake_enable_display_irq(dev_priv, bit);
2455         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2456
2457         return 0;
2458 }
2459
2460 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2461 {
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         unsigned long irqflags;
2464
2465         if (!i915_pipe_enabled(dev, pipe))
2466                 return -EINVAL;
2467
2468         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2469         i915_enable_pipestat(dev_priv, pipe,
2470                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2471         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2472
2473         return 0;
2474 }
2475
2476 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2477 {
2478         struct drm_i915_private *dev_priv = dev->dev_private;
2479         unsigned long irqflags;
2480
2481         if (!i915_pipe_enabled(dev, pipe))
2482                 return -EINVAL;
2483
2484         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2485         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2486         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2487         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2488         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2489         return 0;
2490 }
2491
2492 /* Called from drm generic code, passed 'crtc' which
2493  * we use as a pipe index
2494  */
2495 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2496 {
2497         struct drm_i915_private *dev_priv = dev->dev_private;
2498         unsigned long irqflags;
2499
2500         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2501         if (INTEL_INFO(dev)->gen == 3)
2502                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2503
2504         i915_disable_pipestat(dev_priv, pipe,
2505                               PIPE_VBLANK_INTERRUPT_STATUS |
2506                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2507         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2508 }
2509
2510 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2511 {
2512         struct drm_i915_private *dev_priv = dev->dev_private;
2513         unsigned long irqflags;
2514         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2515                                                      DE_PIPE_VBLANK(pipe);
2516
2517         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2518         ironlake_disable_display_irq(dev_priv, bit);
2519         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2520 }
2521
2522 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         unsigned long irqflags;
2526
2527         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2528         i915_disable_pipestat(dev_priv, pipe,
2529                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2530         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2531 }
2532
2533 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2534 {
2535         struct drm_i915_private *dev_priv = dev->dev_private;
2536         unsigned long irqflags;
2537
2538         if (!i915_pipe_enabled(dev, pipe))
2539                 return;
2540
2541         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2542         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2543         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2544         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2545         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2546 }
2547
2548 static u32
2549 ring_last_seqno(struct intel_ring_buffer *ring)
2550 {
2551         return list_entry(ring->request_list.prev,
2552                           struct drm_i915_gem_request, list)->seqno;
2553 }
2554
2555 static bool
2556 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2557 {
2558         return (list_empty(&ring->request_list) ||
2559                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2560 }
2561
2562 static bool
2563 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2564 {
2565         if (INTEL_INFO(dev)->gen >= 8) {
2566                 /*
2567                  * FIXME: gen8 semaphore support - currently we don't emit
2568                  * semaphores on bdw anyway, but this needs to be addressed when
2569                  * we merge that code.
2570                  */
2571                 return false;
2572         } else {
2573                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2574                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2575                                  MI_SEMAPHORE_REGISTER);
2576         }
2577 }
2578
2579 static struct intel_ring_buffer *
2580 semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
2581 {
2582         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2583         struct intel_ring_buffer *signaller;
2584         int i;
2585
2586         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2587                 /*
2588                  * FIXME: gen8 semaphore support - currently we don't emit
2589                  * semaphores on bdw anyway, but this needs to be addressed when
2590                  * we merge that code.
2591                  */
2592                 return NULL;
2593         } else {
2594                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2595
2596                 for_each_ring(signaller, dev_priv, i) {
2597                         if(ring == signaller)
2598                                 continue;
2599
2600                         if (sync_bits ==
2601                             signaller->semaphore_register[ring->id])
2602                                 return signaller;
2603                 }
2604         }
2605
2606         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2607                   ring->id, ipehr);
2608
2609         return NULL;
2610 }
2611
2612 static struct intel_ring_buffer *
2613 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2614 {
2615         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2616         u32 cmd, ipehr, head;
2617         int i;
2618
2619         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2620         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2621                 return NULL;
2622
2623         /*
2624          * HEAD is likely pointing to the dword after the actual command,
2625          * so scan backwards until we find the MBOX. But limit it to just 3
2626          * dwords. Note that we don't care about ACTHD here since that might
2627          * point at at batch, and semaphores are always emitted into the
2628          * ringbuffer itself.
2629          */
2630         head = I915_READ_HEAD(ring) & HEAD_ADDR;
2631
2632         for (i = 4; i; --i) {
2633                 /*
2634                  * Be paranoid and presume the hw has gone off into the wild -
2635                  * our ring is smaller than what the hardware (and hence
2636                  * HEAD_ADDR) allows. Also handles wrap-around.
2637                  */
2638                 head &= ring->size - 1;
2639
2640                 /* This here seems to blow up */
2641                 cmd = ioread32(ring->virtual_start + head);
2642                 if (cmd == ipehr)
2643                         break;
2644
2645                 head -= 4;
2646         }
2647
2648         if (!i)
2649                 return NULL;
2650
2651         *seqno = ioread32(ring->virtual_start + head + 4) + 1;
2652         return semaphore_wait_to_signaller_ring(ring, ipehr);
2653 }
2654
2655 static int semaphore_passed(struct intel_ring_buffer *ring)
2656 {
2657         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2658         struct intel_ring_buffer *signaller;
2659         u32 seqno, ctl;
2660
2661         ring->hangcheck.deadlock = true;
2662
2663         signaller = semaphore_waits_for(ring, &seqno);
2664         if (signaller == NULL || signaller->hangcheck.deadlock)
2665                 return -1;
2666
2667         /* cursory check for an unkickable deadlock */
2668         ctl = I915_READ_CTL(signaller);
2669         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2670                 return -1;
2671
2672         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2673 }
2674
2675 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2676 {
2677         struct intel_ring_buffer *ring;
2678         int i;
2679
2680         for_each_ring(ring, dev_priv, i)
2681                 ring->hangcheck.deadlock = false;
2682 }
2683
2684 static enum intel_ring_hangcheck_action
2685 ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
2686 {
2687         struct drm_device *dev = ring->dev;
2688         struct drm_i915_private *dev_priv = dev->dev_private;
2689         u32 tmp;
2690
2691         if (ring->hangcheck.acthd != acthd)
2692                 return HANGCHECK_ACTIVE;
2693
2694         if (IS_GEN2(dev))
2695                 return HANGCHECK_HUNG;
2696
2697         /* Is the chip hanging on a WAIT_FOR_EVENT?
2698          * If so we can simply poke the RB_WAIT bit
2699          * and break the hang. This should work on
2700          * all but the second generation chipsets.
2701          */
2702         tmp = I915_READ_CTL(ring);
2703         if (tmp & RING_WAIT) {
2704                 i915_handle_error(dev, false,
2705                                   "Kicking stuck wait on %s",
2706                                   ring->name);
2707                 I915_WRITE_CTL(ring, tmp);
2708                 return HANGCHECK_KICK;
2709         }
2710
2711         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2712                 switch (semaphore_passed(ring)) {
2713                 default:
2714                         return HANGCHECK_HUNG;
2715                 case 1:
2716                         i915_handle_error(dev, false,
2717                                           "Kicking stuck semaphore on %s",
2718                                           ring->name);
2719                         I915_WRITE_CTL(ring, tmp);
2720                         return HANGCHECK_KICK;
2721                 case 0:
2722                         return HANGCHECK_WAIT;
2723                 }
2724         }
2725
2726         return HANGCHECK_HUNG;
2727 }
2728
2729 /**
2730  * This is called when the chip hasn't reported back with completed
2731  * batchbuffers in a long time. We keep track per ring seqno progress and
2732  * if there are no progress, hangcheck score for that ring is increased.
2733  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2734  * we kick the ring. If we see no progress on three subsequent calls
2735  * we assume chip is wedged and try to fix it by resetting the chip.
2736  */
2737 static void i915_hangcheck_elapsed(unsigned long data)
2738 {
2739         struct drm_device *dev = (struct drm_device *)data;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct intel_ring_buffer *ring;
2742         int i;
2743         int busy_count = 0, rings_hung = 0;
2744         bool stuck[I915_NUM_RINGS] = { 0 };
2745 #define BUSY 1
2746 #define KICK 5
2747 #define HUNG 20
2748
2749         if (!i915.enable_hangcheck)
2750                 return;
2751
2752         for_each_ring(ring, dev_priv, i) {
2753                 u64 acthd;
2754                 u32 seqno;
2755                 bool busy = true;
2756
2757                 semaphore_clear_deadlocks(dev_priv);
2758
2759                 seqno = ring->get_seqno(ring, false);
2760                 acthd = intel_ring_get_active_head(ring);
2761
2762                 if (ring->hangcheck.seqno == seqno) {
2763                         if (ring_idle(ring, seqno)) {
2764                                 ring->hangcheck.action = HANGCHECK_IDLE;
2765
2766                                 if (waitqueue_active(&ring->irq_queue)) {
2767                                         /* Issue a wake-up to catch stuck h/w. */
2768                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2769                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2770                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2771                                                                   ring->name);
2772                                                 else
2773                                                         DRM_INFO("Fake missed irq on %s\n",
2774                                                                  ring->name);
2775                                                 wake_up_all(&ring->irq_queue);
2776                                         }
2777                                         /* Safeguard against driver failure */
2778                                         ring->hangcheck.score += BUSY;
2779                                 } else
2780                                         busy = false;
2781                         } else {
2782                                 /* We always increment the hangcheck score
2783                                  * if the ring is busy and still processing
2784                                  * the same request, so that no single request
2785                                  * can run indefinitely (such as a chain of
2786                                  * batches). The only time we do not increment
2787                                  * the hangcheck score on this ring, if this
2788                                  * ring is in a legitimate wait for another
2789                                  * ring. In that case the waiting ring is a
2790                                  * victim and we want to be sure we catch the
2791                                  * right culprit. Then every time we do kick
2792                                  * the ring, add a small increment to the
2793                                  * score so that we can catch a batch that is
2794                                  * being repeatedly kicked and so responsible
2795                                  * for stalling the machine.
2796                                  */
2797                                 ring->hangcheck.action = ring_stuck(ring,
2798                                                                     acthd);
2799
2800                                 switch (ring->hangcheck.action) {
2801                                 case HANGCHECK_IDLE:
2802                                 case HANGCHECK_WAIT:
2803                                         break;
2804                                 case HANGCHECK_ACTIVE:
2805                                         ring->hangcheck.score += BUSY;
2806                                         break;
2807                                 case HANGCHECK_KICK:
2808                                         ring->hangcheck.score += KICK;
2809                                         break;
2810                                 case HANGCHECK_HUNG:
2811                                         ring->hangcheck.score += HUNG;
2812                                         stuck[i] = true;
2813                                         break;
2814                                 }
2815                         }
2816                 } else {
2817                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2818
2819                         /* Gradually reduce the count so that we catch DoS
2820                          * attempts across multiple batches.
2821                          */
2822                         if (ring->hangcheck.score > 0)
2823                                 ring->hangcheck.score--;
2824                 }
2825
2826                 ring->hangcheck.seqno = seqno;
2827                 ring->hangcheck.acthd = acthd;
2828                 busy_count += busy;
2829         }
2830
2831         for_each_ring(ring, dev_priv, i) {
2832                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2833                         DRM_INFO("%s on %s\n",
2834                                  stuck[i] ? "stuck" : "no progress",
2835                                  ring->name);
2836                         rings_hung++;
2837                 }
2838         }
2839
2840         if (rings_hung)
2841                 return i915_handle_error(dev, true, "Ring hung");
2842
2843         if (busy_count)
2844                 /* Reset timer case chip hangs without another request
2845                  * being added */
2846                 i915_queue_hangcheck(dev);
2847 }
2848
2849 void i915_queue_hangcheck(struct drm_device *dev)
2850 {
2851         struct drm_i915_private *dev_priv = dev->dev_private;
2852         if (!i915.enable_hangcheck)
2853                 return;
2854
2855         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2856                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2857 }
2858
2859 static void ibx_irq_reset(struct drm_device *dev)
2860 {
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862
2863         if (HAS_PCH_NOP(dev))
2864                 return;
2865
2866         GEN5_IRQ_RESET(SDE);
2867
2868         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2869                 I915_WRITE(SERR_INT, 0xffffffff);
2870 }
2871
2872 /*
2873  * SDEIER is also touched by the interrupt handler to work around missed PCH
2874  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2875  * instead we unconditionally enable all PCH interrupt sources here, but then
2876  * only unmask them as needed with SDEIMR.
2877  *
2878  * This function needs to be called before interrupts are enabled.
2879  */
2880 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2881 {
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883
2884         if (HAS_PCH_NOP(dev))
2885                 return;
2886
2887         WARN_ON(I915_READ(SDEIER) != 0);
2888         I915_WRITE(SDEIER, 0xffffffff);
2889         POSTING_READ(SDEIER);
2890 }
2891
2892 static void gen5_gt_irq_reset(struct drm_device *dev)
2893 {
2894         struct drm_i915_private *dev_priv = dev->dev_private;
2895
2896         GEN5_IRQ_RESET(GT);
2897         if (INTEL_INFO(dev)->gen >= 6)
2898                 GEN5_IRQ_RESET(GEN6_PM);
2899 }
2900
2901 /* drm_dma.h hooks
2902 */
2903 static void ironlake_irq_reset(struct drm_device *dev)
2904 {
2905         struct drm_i915_private *dev_priv = dev->dev_private;
2906
2907         I915_WRITE(HWSTAM, 0xffffffff);
2908
2909         GEN5_IRQ_RESET(DE);
2910         if (IS_GEN7(dev))
2911                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2912
2913         gen5_gt_irq_reset(dev);
2914
2915         ibx_irq_reset(dev);
2916 }
2917
2918 static void ironlake_irq_preinstall(struct drm_device *dev)
2919 {
2920         ironlake_irq_reset(dev);
2921 }
2922
2923 static void valleyview_irq_preinstall(struct drm_device *dev)
2924 {
2925         struct drm_i915_private *dev_priv = dev->dev_private;
2926         int pipe;
2927
2928         /* VLV magic */
2929         I915_WRITE(VLV_IMR, 0);
2930         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2931         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2932         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2933
2934         /* and GT */
2935         I915_WRITE(GTIIR, I915_READ(GTIIR));
2936         I915_WRITE(GTIIR, I915_READ(GTIIR));
2937
2938         gen5_gt_irq_reset(dev);
2939
2940         I915_WRITE(DPINVGTT, 0xff);
2941
2942         I915_WRITE(PORT_HOTPLUG_EN, 0);
2943         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2944         for_each_pipe(pipe)
2945                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2946         I915_WRITE(VLV_IIR, 0xffffffff);
2947         I915_WRITE(VLV_IMR, 0xffffffff);
2948         I915_WRITE(VLV_IER, 0x0);
2949         POSTING_READ(VLV_IER);
2950 }
2951
2952 static void gen8_irq_reset(struct drm_device *dev)
2953 {
2954         struct drm_i915_private *dev_priv = dev->dev_private;
2955         int pipe;
2956
2957         I915_WRITE(GEN8_MASTER_IRQ, 0);
2958         POSTING_READ(GEN8_MASTER_IRQ);
2959
2960         GEN8_IRQ_RESET_NDX(GT, 0);
2961         GEN8_IRQ_RESET_NDX(GT, 1);
2962         GEN8_IRQ_RESET_NDX(GT, 2);
2963         GEN8_IRQ_RESET_NDX(GT, 3);
2964
2965         for_each_pipe(pipe)
2966                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
2967
2968         GEN5_IRQ_RESET(GEN8_DE_PORT_);
2969         GEN5_IRQ_RESET(GEN8_DE_MISC_);
2970         GEN5_IRQ_RESET(GEN8_PCU_);
2971
2972         ibx_irq_reset(dev);
2973 }
2974
2975 static void gen8_irq_preinstall(struct drm_device *dev)
2976 {
2977         gen8_irq_reset(dev);
2978 }
2979
2980 static void ibx_hpd_irq_setup(struct drm_device *dev)
2981 {
2982         struct drm_i915_private *dev_priv = dev->dev_private;
2983         struct drm_mode_config *mode_config = &dev->mode_config;
2984         struct intel_encoder *intel_encoder;
2985         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2986
2987         if (HAS_PCH_IBX(dev)) {
2988                 hotplug_irqs = SDE_HOTPLUG_MASK;
2989                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2990                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2991                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2992         } else {
2993                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2994                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2995                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2996                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2997         }
2998
2999         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3000
3001         /*
3002          * Enable digital hotplug on the PCH, and configure the DP short pulse
3003          * duration to 2ms (which is the minimum in the Display Port spec)
3004          *
3005          * This register is the same on all known PCH chips.
3006          */
3007         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3008         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3009         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3010         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3011         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3012         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3013 }
3014
3015 static void ibx_irq_postinstall(struct drm_device *dev)
3016 {
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         u32 mask;
3019
3020         if (HAS_PCH_NOP(dev))
3021                 return;
3022
3023         if (HAS_PCH_IBX(dev))
3024                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3025         else
3026                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3027
3028         GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3029         I915_WRITE(SDEIMR, ~mask);
3030 }
3031
3032 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3033 {
3034         struct drm_i915_private *dev_priv = dev->dev_private;
3035         u32 pm_irqs, gt_irqs;
3036
3037         pm_irqs = gt_irqs = 0;
3038
3039         dev_priv->gt_irq_mask = ~0;
3040         if (HAS_L3_DPF(dev)) {
3041                 /* L3 parity interrupt is always unmasked. */
3042                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3043                 gt_irqs |= GT_PARITY_ERROR(dev);
3044         }
3045
3046         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3047         if (IS_GEN5(dev)) {
3048                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3049                            ILK_BSD_USER_INTERRUPT;
3050         } else {
3051                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3052         }
3053
3054         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3055
3056         if (INTEL_INFO(dev)->gen >= 6) {
3057                 pm_irqs |= dev_priv->pm_rps_events;
3058
3059                 if (HAS_VEBOX(dev))
3060                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3061
3062                 dev_priv->pm_irq_mask = 0xffffffff;
3063                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3064         }
3065 }
3066
3067 static int ironlake_irq_postinstall(struct drm_device *dev)
3068 {
3069         unsigned long irqflags;
3070         struct drm_i915_private *dev_priv = dev->dev_private;
3071         u32 display_mask, extra_mask;
3072
3073         if (INTEL_INFO(dev)->gen >= 7) {
3074                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3075                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3076                                 DE_PLANEB_FLIP_DONE_IVB |
3077                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3078                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3079                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3080         } else {
3081                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3082                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3083                                 DE_AUX_CHANNEL_A |
3084                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3085                                 DE_POISON);
3086                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3087                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3088         }
3089
3090         dev_priv->irq_mask = ~display_mask;
3091
3092         I915_WRITE(HWSTAM, 0xeffe);
3093
3094         ibx_irq_pre_postinstall(dev);
3095
3096         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3097
3098         gen5_gt_irq_postinstall(dev);
3099
3100         ibx_irq_postinstall(dev);
3101
3102         if (IS_IRONLAKE_M(dev)) {
3103                 /* Enable PCU event interrupts
3104                  *
3105                  * spinlocking not required here for correctness since interrupt
3106                  * setup is guaranteed to run in single-threaded context. But we
3107                  * need it to make the assert_spin_locked happy. */
3108                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3109                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3110                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3111         }
3112
3113         return 0;
3114 }
3115
3116 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3117 {
3118         u32 pipestat_mask;
3119         u32 iir_mask;
3120
3121         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3122                         PIPE_FIFO_UNDERRUN_STATUS;
3123
3124         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3125         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3126         POSTING_READ(PIPESTAT(PIPE_A));
3127
3128         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3129                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3130
3131         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3132                                                PIPE_GMBUS_INTERRUPT_STATUS);
3133         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3134
3135         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3136                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3137                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3138         dev_priv->irq_mask &= ~iir_mask;
3139
3140         I915_WRITE(VLV_IIR, iir_mask);
3141         I915_WRITE(VLV_IIR, iir_mask);
3142         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3143         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3144         POSTING_READ(VLV_IER);
3145 }
3146
3147 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3148 {
3149         u32 pipestat_mask;
3150         u32 iir_mask;
3151
3152         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3153                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3154                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3155
3156         dev_priv->irq_mask |= iir_mask;
3157         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3158         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3159         I915_WRITE(VLV_IIR, iir_mask);
3160         I915_WRITE(VLV_IIR, iir_mask);
3161         POSTING_READ(VLV_IIR);
3162
3163         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3164                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3165
3166         i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3167                                                 PIPE_GMBUS_INTERRUPT_STATUS);
3168         i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3169
3170         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3171                         PIPE_FIFO_UNDERRUN_STATUS;
3172         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3173         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3174         POSTING_READ(PIPESTAT(PIPE_A));
3175 }
3176
3177 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3178 {
3179         assert_spin_locked(&dev_priv->irq_lock);
3180
3181         if (dev_priv->display_irqs_enabled)
3182                 return;
3183
3184         dev_priv->display_irqs_enabled = true;
3185
3186         if (dev_priv->dev->irq_enabled)
3187                 valleyview_display_irqs_install(dev_priv);
3188 }
3189
3190 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3191 {
3192         assert_spin_locked(&dev_priv->irq_lock);
3193
3194         if (!dev_priv->display_irqs_enabled)
3195                 return;
3196
3197         dev_priv->display_irqs_enabled = false;
3198
3199         if (dev_priv->dev->irq_enabled)
3200                 valleyview_display_irqs_uninstall(dev_priv);
3201 }
3202
3203 static int valleyview_irq_postinstall(struct drm_device *dev)
3204 {
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         unsigned long irqflags;
3207
3208         dev_priv->irq_mask = ~0;
3209
3210         I915_WRITE(PORT_HOTPLUG_EN, 0);
3211         POSTING_READ(PORT_HOTPLUG_EN);
3212
3213         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3214         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3215         I915_WRITE(VLV_IIR, 0xffffffff);
3216         POSTING_READ(VLV_IER);
3217
3218         /* Interrupt setup is already guaranteed to be single-threaded, this is
3219          * just to make the assert_spin_locked check happy. */
3220         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3221         if (dev_priv->display_irqs_enabled)
3222                 valleyview_display_irqs_install(dev_priv);
3223         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3224
3225         I915_WRITE(VLV_IIR, 0xffffffff);
3226         I915_WRITE(VLV_IIR, 0xffffffff);
3227
3228         gen5_gt_irq_postinstall(dev);
3229
3230         /* ack & enable invalid PTE error interrupts */
3231 #if 0 /* FIXME: add support to irq handler for checking these bits */
3232         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3233         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3234 #endif
3235
3236         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3237
3238         return 0;
3239 }
3240
3241 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3242 {
3243         int i;
3244
3245         /* These are interrupts we'll toggle with the ring mask register */
3246         uint32_t gt_interrupts[] = {
3247                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3248                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3249                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3250                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3251                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3252                 0,
3253                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3254                 };
3255
3256         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3257                 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3258 }
3259
3260 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3261 {
3262         struct drm_device *dev = dev_priv->dev;
3263         uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3264                 GEN8_PIPE_CDCLK_CRC_DONE |
3265                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3266         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3267                 GEN8_PIPE_FIFO_UNDERRUN;
3268         int pipe;
3269         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3270         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3271         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3272
3273         for_each_pipe(pipe)
3274                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3275                                   de_pipe_enables);
3276
3277         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3278 }
3279
3280 static int gen8_irq_postinstall(struct drm_device *dev)
3281 {
3282         struct drm_i915_private *dev_priv = dev->dev_private;
3283
3284         ibx_irq_pre_postinstall(dev);
3285
3286         gen8_gt_irq_postinstall(dev_priv);
3287         gen8_de_irq_postinstall(dev_priv);
3288
3289         ibx_irq_postinstall(dev);
3290
3291         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3292         POSTING_READ(GEN8_MASTER_IRQ);
3293
3294         return 0;
3295 }
3296
3297 static void gen8_irq_uninstall(struct drm_device *dev)
3298 {
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300
3301         if (!dev_priv)
3302                 return;
3303
3304         intel_hpd_irq_uninstall(dev_priv);
3305
3306         gen8_irq_reset(dev);
3307 }
3308
3309 static void valleyview_irq_uninstall(struct drm_device *dev)
3310 {
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         unsigned long irqflags;
3313         int pipe;
3314
3315         if (!dev_priv)
3316                 return;
3317
3318         intel_hpd_irq_uninstall(dev_priv);
3319
3320         for_each_pipe(pipe)
3321                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3322
3323         I915_WRITE(HWSTAM, 0xffffffff);
3324         I915_WRITE(PORT_HOTPLUG_EN, 0);
3325         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3326
3327         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3328         if (dev_priv->display_irqs_enabled)
3329                 valleyview_display_irqs_uninstall(dev_priv);
3330         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3331
3332         dev_priv->irq_mask = 0;
3333
3334         I915_WRITE(VLV_IIR, 0xffffffff);
3335         I915_WRITE(VLV_IMR, 0xffffffff);
3336         I915_WRITE(VLV_IER, 0x0);
3337         POSTING_READ(VLV_IER);
3338 }
3339
3340 static void ironlake_irq_uninstall(struct drm_device *dev)
3341 {
3342         struct drm_i915_private *dev_priv = dev->dev_private;
3343
3344         if (!dev_priv)
3345                 return;
3346
3347         intel_hpd_irq_uninstall(dev_priv);
3348
3349         ironlake_irq_reset(dev);
3350 }
3351
3352 static void i8xx_irq_preinstall(struct drm_device * dev)
3353 {
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355         int pipe;
3356
3357         for_each_pipe(pipe)
3358                 I915_WRITE(PIPESTAT(pipe), 0);
3359         I915_WRITE16(IMR, 0xffff);
3360         I915_WRITE16(IER, 0x0);
3361         POSTING_READ16(IER);
3362 }
3363
3364 static int i8xx_irq_postinstall(struct drm_device *dev)
3365 {
3366         struct drm_i915_private *dev_priv = dev->dev_private;
3367         unsigned long irqflags;
3368
3369         I915_WRITE16(EMR,
3370                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3371
3372         /* Unmask the interrupts that we always want on. */
3373         dev_priv->irq_mask =
3374                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3375                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3376                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3377                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3378                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3379         I915_WRITE16(IMR, dev_priv->irq_mask);
3380
3381         I915_WRITE16(IER,
3382                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3383                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3384                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3385                      I915_USER_INTERRUPT);
3386         POSTING_READ16(IER);
3387
3388         /* Interrupt setup is already guaranteed to be single-threaded, this is
3389          * just to make the assert_spin_locked check happy. */
3390         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3391         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3392         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3393         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3394
3395         return 0;
3396 }
3397
3398 /*
3399  * Returns true when a page flip has completed.
3400  */
3401 static bool i8xx_handle_vblank(struct drm_device *dev,
3402                                int plane, int pipe, u32 iir)
3403 {
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3406
3407         if (!drm_handle_vblank(dev, pipe))
3408                 return false;
3409
3410         if ((iir & flip_pending) == 0)
3411                 return false;
3412
3413         intel_prepare_page_flip(dev, plane);
3414
3415         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3416          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3417          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3418          * the flip is completed (no longer pending). Since this doesn't raise
3419          * an interrupt per se, we watch for the change at vblank.
3420          */
3421         if (I915_READ16(ISR) & flip_pending)
3422                 return false;
3423
3424         intel_finish_page_flip(dev, pipe);
3425
3426         return true;
3427 }
3428
3429 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3430 {
3431         struct drm_device *dev = (struct drm_device *) arg;
3432         struct drm_i915_private *dev_priv = dev->dev_private;
3433         u16 iir, new_iir;
3434         u32 pipe_stats[2];
3435         unsigned long irqflags;
3436         int pipe;
3437         u16 flip_mask =
3438                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3439                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3440
3441         iir = I915_READ16(IIR);
3442         if (iir == 0)
3443                 return IRQ_NONE;
3444
3445         while (iir & ~flip_mask) {
3446                 /* Can't rely on pipestat interrupt bit in iir as it might
3447                  * have been cleared after the pipestat interrupt was received.
3448                  * It doesn't set the bit in iir again, but it still produces
3449                  * interrupts (for non-MSI).
3450                  */
3451                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3452                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3453                         i915_handle_error(dev, false,
3454                                           "Command parser error, iir 0x%08x",
3455                                           iir);
3456
3457                 for_each_pipe(pipe) {
3458                         int reg = PIPESTAT(pipe);
3459                         pipe_stats[pipe] = I915_READ(reg);
3460
3461                         /*
3462                          * Clear the PIPE*STAT regs before the IIR
3463                          */
3464                         if (pipe_stats[pipe] & 0x8000ffff)
3465                                 I915_WRITE(reg, pipe_stats[pipe]);
3466                 }
3467                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3468
3469                 I915_WRITE16(IIR, iir & ~flip_mask);
3470                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3471
3472                 i915_update_dri1_breadcrumb(dev);
3473
3474                 if (iir & I915_USER_INTERRUPT)
3475                         notify_ring(dev, &dev_priv->ring[RCS]);
3476
3477                 for_each_pipe(pipe) {
3478                         int plane = pipe;
3479                         if (HAS_FBC(dev))
3480                                 plane = !plane;
3481
3482                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3483                             i8xx_handle_vblank(dev, plane, pipe, iir))
3484                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3485
3486                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3487                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3488
3489                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3490                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3491                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3492                 }
3493
3494                 iir = new_iir;
3495         }
3496
3497         return IRQ_HANDLED;
3498 }
3499
3500 static void i8xx_irq_uninstall(struct drm_device * dev)
3501 {
3502         struct drm_i915_private *dev_priv = dev->dev_private;
3503         int pipe;
3504
3505         for_each_pipe(pipe) {
3506                 /* Clear enable bits; then clear status bits */
3507                 I915_WRITE(PIPESTAT(pipe), 0);
3508                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3509         }
3510         I915_WRITE16(IMR, 0xffff);
3511         I915_WRITE16(IER, 0x0);
3512         I915_WRITE16(IIR, I915_READ16(IIR));
3513 }
3514
3515 static void i915_irq_preinstall(struct drm_device * dev)
3516 {
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518         int pipe;
3519
3520         if (I915_HAS_HOTPLUG(dev)) {
3521                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3522                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3523         }
3524
3525         I915_WRITE16(HWSTAM, 0xeffe);
3526         for_each_pipe(pipe)
3527                 I915_WRITE(PIPESTAT(pipe), 0);
3528         I915_WRITE(IMR, 0xffffffff);
3529         I915_WRITE(IER, 0x0);
3530         POSTING_READ(IER);
3531 }
3532
3533 static int i915_irq_postinstall(struct drm_device *dev)
3534 {
3535         struct drm_i915_private *dev_priv = dev->dev_private;
3536         u32 enable_mask;
3537         unsigned long irqflags;
3538
3539         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3540
3541         /* Unmask the interrupts that we always want on. */
3542         dev_priv->irq_mask =
3543                 ~(I915_ASLE_INTERRUPT |
3544                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3545                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3546                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3547                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3548                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3549
3550         enable_mask =
3551                 I915_ASLE_INTERRUPT |
3552                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3553                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3554                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3555                 I915_USER_INTERRUPT;
3556
3557         if (I915_HAS_HOTPLUG(dev)) {
3558                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3559                 POSTING_READ(PORT_HOTPLUG_EN);
3560
3561                 /* Enable in IER... */
3562                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3563                 /* and unmask in IMR */
3564                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3565         }
3566
3567         I915_WRITE(IMR, dev_priv->irq_mask);
3568         I915_WRITE(IER, enable_mask);
3569         POSTING_READ(IER);
3570
3571         i915_enable_asle_pipestat(dev);
3572
3573         /* Interrupt setup is already guaranteed to be single-threaded, this is
3574          * just to make the assert_spin_locked check happy. */
3575         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3576         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3577         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3578         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3579
3580         return 0;
3581 }
3582
3583 /*
3584  * Returns true when a page flip has completed.
3585  */
3586 static bool i915_handle_vblank(struct drm_device *dev,
3587                                int plane, int pipe, u32 iir)
3588 {
3589         struct drm_i915_private *dev_priv = dev->dev_private;
3590         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3591
3592         if (!drm_handle_vblank(dev, pipe))
3593                 return false;
3594
3595         if ((iir & flip_pending) == 0)
3596                 return false;
3597
3598         intel_prepare_page_flip(dev, plane);
3599
3600         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3601          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3602          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3603          * the flip is completed (no longer pending). Since this doesn't raise
3604          * an interrupt per se, we watch for the change at vblank.
3605          */
3606         if (I915_READ(ISR) & flip_pending)
3607                 return false;
3608
3609         intel_finish_page_flip(dev, pipe);
3610
3611         return true;
3612 }
3613
3614 static irqreturn_t i915_irq_handler(int irq, void *arg)
3615 {
3616         struct drm_device *dev = (struct drm_device *) arg;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3619         unsigned long irqflags;
3620         u32 flip_mask =
3621                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3622                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3623         int pipe, ret = IRQ_NONE;
3624
3625         iir = I915_READ(IIR);
3626         do {
3627                 bool irq_received = (iir & ~flip_mask) != 0;
3628                 bool blc_event = false;
3629
3630                 /* Can't rely on pipestat interrupt bit in iir as it might
3631                  * have been cleared after the pipestat interrupt was received.
3632                  * It doesn't set the bit in iir again, but it still produces
3633                  * interrupts (for non-MSI).
3634                  */
3635                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3636                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3637                         i915_handle_error(dev, false,
3638                                           "Command parser error, iir 0x%08x",
3639                                           iir);
3640
3641                 for_each_pipe(pipe) {
3642                         int reg = PIPESTAT(pipe);
3643                         pipe_stats[pipe] = I915_READ(reg);
3644
3645                         /* Clear the PIPE*STAT regs before the IIR */
3646                         if (pipe_stats[pipe] & 0x8000ffff) {
3647                                 I915_WRITE(reg, pipe_stats[pipe]);
3648                                 irq_received = true;
3649                         }
3650                 }
3651                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3652
3653                 if (!irq_received)
3654                         break;
3655
3656                 /* Consume port.  Then clear IIR or we'll miss events */
3657                 if (I915_HAS_HOTPLUG(dev) &&
3658                     iir & I915_DISPLAY_PORT_INTERRUPT)
3659                         i9xx_hpd_irq_handler(dev);
3660
3661                 I915_WRITE(IIR, iir & ~flip_mask);
3662                 new_iir = I915_READ(IIR); /* Flush posted writes */
3663
3664                 if (iir & I915_USER_INTERRUPT)
3665                         notify_ring(dev, &dev_priv->ring[RCS]);
3666
3667                 for_each_pipe(pipe) {
3668                         int plane = pipe;
3669                         if (HAS_FBC(dev))
3670                                 plane = !plane;
3671
3672                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3673                             i915_handle_vblank(dev, plane, pipe, iir))
3674                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3675
3676                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3677                                 blc_event = true;
3678
3679                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3680                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3681
3682                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3683                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3684                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3685                 }
3686
3687                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3688                         intel_opregion_asle_intr(dev);
3689
3690                 /* With MSI, interrupts are only generated when iir
3691                  * transitions from zero to nonzero.  If another bit got
3692                  * set while we were handling the existing iir bits, then
3693                  * we would never get another interrupt.
3694                  *
3695                  * This is fine on non-MSI as well, as if we hit this path
3696                  * we avoid exiting the interrupt handler only to generate
3697                  * another one.
3698                  *
3699                  * Note that for MSI this could cause a stray interrupt report
3700                  * if an interrupt landed in the time between writing IIR and
3701                  * the posting read.  This should be rare enough to never
3702                  * trigger the 99% of 100,000 interrupts test for disabling
3703                  * stray interrupts.
3704                  */
3705                 ret = IRQ_HANDLED;
3706                 iir = new_iir;
3707         } while (iir & ~flip_mask);
3708
3709         i915_update_dri1_breadcrumb(dev);
3710
3711         return ret;
3712 }
3713
3714 static void i915_irq_uninstall(struct drm_device * dev)
3715 {
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717         int pipe;
3718
3719         intel_hpd_irq_uninstall(dev_priv);
3720
3721         if (I915_HAS_HOTPLUG(dev)) {
3722                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3723                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3724         }
3725
3726         I915_WRITE16(HWSTAM, 0xffff);
3727         for_each_pipe(pipe) {
3728                 /* Clear enable bits; then clear status bits */
3729                 I915_WRITE(PIPESTAT(pipe), 0);
3730                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3731         }
3732         I915_WRITE(IMR, 0xffffffff);
3733         I915_WRITE(IER, 0x0);
3734
3735         I915_WRITE(IIR, I915_READ(IIR));
3736 }
3737
3738 static void i965_irq_preinstall(struct drm_device * dev)
3739 {
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         int pipe;
3742
3743         I915_WRITE(PORT_HOTPLUG_EN, 0);
3744         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3745
3746         I915_WRITE(HWSTAM, 0xeffe);
3747         for_each_pipe(pipe)
3748                 I915_WRITE(PIPESTAT(pipe), 0);
3749         I915_WRITE(IMR, 0xffffffff);
3750         I915_WRITE(IER, 0x0);
3751         POSTING_READ(IER);
3752 }
3753
3754 static int i965_irq_postinstall(struct drm_device *dev)
3755 {
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757         u32 enable_mask;
3758         u32 error_mask;
3759         unsigned long irqflags;
3760
3761         /* Unmask the interrupts that we always want on. */
3762         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3763                                I915_DISPLAY_PORT_INTERRUPT |
3764                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3765                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3766                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3767                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3768                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3769
3770         enable_mask = ~dev_priv->irq_mask;
3771         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3772                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3773         enable_mask |= I915_USER_INTERRUPT;
3774
3775         if (IS_G4X(dev))
3776                 enable_mask |= I915_BSD_USER_INTERRUPT;
3777
3778         /* Interrupt setup is already guaranteed to be single-threaded, this is
3779          * just to make the assert_spin_locked check happy. */
3780         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3781         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3782         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3783         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3784         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3785
3786         /*
3787          * Enable some error detection, note the instruction error mask
3788          * bit is reserved, so we leave it masked.
3789          */
3790         if (IS_G4X(dev)) {
3791                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3792                                GM45_ERROR_MEM_PRIV |
3793                                GM45_ERROR_CP_PRIV |
3794                                I915_ERROR_MEMORY_REFRESH);
3795         } else {
3796                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3797                                I915_ERROR_MEMORY_REFRESH);
3798         }
3799         I915_WRITE(EMR, error_mask);
3800
3801         I915_WRITE(IMR, dev_priv->irq_mask);
3802         I915_WRITE(IER, enable_mask);
3803         POSTING_READ(IER);
3804
3805         I915_WRITE(PORT_HOTPLUG_EN, 0);
3806         POSTING_READ(PORT_HOTPLUG_EN);
3807
3808         i915_enable_asle_pipestat(dev);
3809
3810         return 0;
3811 }
3812
3813 static void i915_hpd_irq_setup(struct drm_device *dev)
3814 {
3815         struct drm_i915_private *dev_priv = dev->dev_private;
3816         struct drm_mode_config *mode_config = &dev->mode_config;
3817         struct intel_encoder *intel_encoder;
3818         u32 hotplug_en;
3819
3820         assert_spin_locked(&dev_priv->irq_lock);
3821
3822         if (I915_HAS_HOTPLUG(dev)) {
3823                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3824                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3825                 /* Note HDMI and DP share hotplug bits */
3826                 /* enable bits are the same for all generations */
3827                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3828                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3829                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3830                 /* Programming the CRT detection parameters tends
3831                    to generate a spurious hotplug event about three
3832                    seconds later.  So just do it once.
3833                 */
3834                 if (IS_G4X(dev))
3835                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3836                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3837                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3838
3839                 /* Ignore TV since it's buggy */
3840                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3841         }
3842 }
3843
3844 static irqreturn_t i965_irq_handler(int irq, void *arg)
3845 {
3846         struct drm_device *dev = (struct drm_device *) arg;
3847         struct drm_i915_private *dev_priv = dev->dev_private;
3848         u32 iir, new_iir;
3849         u32 pipe_stats[I915_MAX_PIPES];
3850         unsigned long irqflags;
3851         int ret = IRQ_NONE, pipe;
3852         u32 flip_mask =
3853                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3854                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3855
3856         iir = I915_READ(IIR);
3857
3858         for (;;) {
3859                 bool irq_received = (iir & ~flip_mask) != 0;
3860                 bool blc_event = false;
3861
3862                 /* Can't rely on pipestat interrupt bit in iir as it might
3863                  * have been cleared after the pipestat interrupt was received.
3864                  * It doesn't set the bit in iir again, but it still produces
3865                  * interrupts (for non-MSI).
3866                  */
3867                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3868                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3869                         i915_handle_error(dev, false,
3870                                           "Command parser error, iir 0x%08x",
3871                                           iir);
3872
3873                 for_each_pipe(pipe) {
3874                         int reg = PIPESTAT(pipe);
3875                         pipe_stats[pipe] = I915_READ(reg);
3876
3877                         /*
3878                          * Clear the PIPE*STAT regs before the IIR
3879                          */
3880                         if (pipe_stats[pipe] & 0x8000ffff) {
3881                                 I915_WRITE(reg, pipe_stats[pipe]);
3882                                 irq_received = true;
3883                         }
3884                 }
3885                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3886
3887                 if (!irq_received)
3888                         break;
3889
3890                 ret = IRQ_HANDLED;
3891
3892                 /* Consume port.  Then clear IIR or we'll miss events */
3893                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3894                         i9xx_hpd_irq_handler(dev);
3895
3896                 I915_WRITE(IIR, iir & ~flip_mask);
3897                 new_iir = I915_READ(IIR); /* Flush posted writes */
3898
3899                 if (iir & I915_USER_INTERRUPT)
3900                         notify_ring(dev, &dev_priv->ring[RCS]);
3901                 if (iir & I915_BSD_USER_INTERRUPT)
3902                         notify_ring(dev, &dev_priv->ring[VCS]);
3903
3904                 for_each_pipe(pipe) {
3905                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3906                             i915_handle_vblank(dev, pipe, pipe, iir))
3907                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3908
3909                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3910                                 blc_event = true;
3911
3912                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3913                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3914
3915                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3916                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3917                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3918                 }
3919
3920                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3921                         intel_opregion_asle_intr(dev);
3922
3923                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3924                         gmbus_irq_handler(dev);
3925
3926                 /* With MSI, interrupts are only generated when iir
3927                  * transitions from zero to nonzero.  If another bit got
3928                  * set while we were handling the existing iir bits, then
3929                  * we would never get another interrupt.
3930                  *
3931                  * This is fine on non-MSI as well, as if we hit this path
3932                  * we avoid exiting the interrupt handler only to generate
3933                  * another one.
3934                  *
3935                  * Note that for MSI this could cause a stray interrupt report
3936                  * if an interrupt landed in the time between writing IIR and
3937                  * the posting read.  This should be rare enough to never
3938                  * trigger the 99% of 100,000 interrupts test for disabling
3939                  * stray interrupts.
3940                  */
3941                 iir = new_iir;
3942         }
3943
3944         i915_update_dri1_breadcrumb(dev);
3945
3946         return ret;
3947 }
3948
3949 static void i965_irq_uninstall(struct drm_device * dev)
3950 {
3951         struct drm_i915_private *dev_priv = dev->dev_private;
3952         int pipe;
3953
3954         if (!dev_priv)
3955                 return;
3956
3957         intel_hpd_irq_uninstall(dev_priv);
3958
3959         I915_WRITE(PORT_HOTPLUG_EN, 0);
3960         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3961
3962         I915_WRITE(HWSTAM, 0xffffffff);
3963         for_each_pipe(pipe)
3964                 I915_WRITE(PIPESTAT(pipe), 0);
3965         I915_WRITE(IMR, 0xffffffff);
3966         I915_WRITE(IER, 0x0);
3967
3968         for_each_pipe(pipe)
3969                 I915_WRITE(PIPESTAT(pipe),
3970                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3971         I915_WRITE(IIR, I915_READ(IIR));
3972 }
3973
3974 static void intel_hpd_irq_reenable(unsigned long data)
3975 {
3976         struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
3977         struct drm_device *dev = dev_priv->dev;
3978         struct drm_mode_config *mode_config = &dev->mode_config;
3979         unsigned long irqflags;
3980         int i;
3981
3982         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3983         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3984                 struct drm_connector *connector;
3985
3986                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3987                         continue;
3988
3989                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3990
3991                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3992                         struct intel_connector *intel_connector = to_intel_connector(connector);
3993
3994                         if (intel_connector->encoder->hpd_pin == i) {
3995                                 if (connector->polled != intel_connector->polled)
3996                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3997                                                          drm_get_connector_name(connector));
3998                                 connector->polled = intel_connector->polled;
3999                                 if (!connector->polled)
4000                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4001                         }
4002                 }
4003         }
4004         if (dev_priv->display.hpd_irq_setup)
4005                 dev_priv->display.hpd_irq_setup(dev);
4006         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4007 }
4008
4009 void intel_irq_init(struct drm_device *dev)
4010 {
4011         struct drm_i915_private *dev_priv = dev->dev_private;
4012
4013         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4014         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4015         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4016         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4017
4018         /* Let's track the enabled rps events */
4019         dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4020
4021         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4022                     i915_hangcheck_elapsed,
4023                     (unsigned long) dev);
4024         setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4025                     (unsigned long) dev_priv);
4026
4027         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4028
4029         if (IS_GEN2(dev)) {
4030                 dev->max_vblank_count = 0;
4031                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4032         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4033                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4034                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4035         } else {
4036                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4037                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4038         }
4039
4040         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4041                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4042                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4043         }
4044
4045         if (IS_VALLEYVIEW(dev)) {
4046                 dev->driver->irq_handler = valleyview_irq_handler;
4047                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4048                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4049                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4050                 dev->driver->enable_vblank = valleyview_enable_vblank;
4051                 dev->driver->disable_vblank = valleyview_disable_vblank;
4052                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4053         } else if (IS_GEN8(dev)) {
4054                 dev->driver->irq_handler = gen8_irq_handler;
4055                 dev->driver->irq_preinstall = gen8_irq_preinstall;
4056                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4057                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4058                 dev->driver->enable_vblank = gen8_enable_vblank;
4059                 dev->driver->disable_vblank = gen8_disable_vblank;
4060                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4061         } else if (HAS_PCH_SPLIT(dev)) {
4062                 dev->driver->irq_handler = ironlake_irq_handler;
4063                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4064                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4065                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4066                 dev->driver->enable_vblank = ironlake_enable_vblank;
4067                 dev->driver->disable_vblank = ironlake_disable_vblank;
4068                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4069         } else {
4070                 if (INTEL_INFO(dev)->gen == 2) {
4071                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4072                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4073                         dev->driver->irq_handler = i8xx_irq_handler;
4074                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4075                 } else if (INTEL_INFO(dev)->gen == 3) {
4076                         dev->driver->irq_preinstall = i915_irq_preinstall;
4077                         dev->driver->irq_postinstall = i915_irq_postinstall;
4078                         dev->driver->irq_uninstall = i915_irq_uninstall;
4079                         dev->driver->irq_handler = i915_irq_handler;
4080                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4081                 } else {
4082                         dev->driver->irq_preinstall = i965_irq_preinstall;
4083                         dev->driver->irq_postinstall = i965_irq_postinstall;
4084                         dev->driver->irq_uninstall = i965_irq_uninstall;
4085                         dev->driver->irq_handler = i965_irq_handler;
4086                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4087                 }
4088                 dev->driver->enable_vblank = i915_enable_vblank;
4089                 dev->driver->disable_vblank = i915_disable_vblank;
4090         }
4091 }
4092
4093 void intel_hpd_init(struct drm_device *dev)
4094 {
4095         struct drm_i915_private *dev_priv = dev->dev_private;
4096         struct drm_mode_config *mode_config = &dev->mode_config;
4097         struct drm_connector *connector;
4098         unsigned long irqflags;
4099         int i;
4100
4101         for (i = 1; i < HPD_NUM_PINS; i++) {
4102                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4103                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4104         }
4105         list_for_each_entry(connector, &mode_config->connector_list, head) {
4106                 struct intel_connector *intel_connector = to_intel_connector(connector);
4107                 connector->polled = intel_connector->polled;
4108                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4109                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4110         }
4111
4112         /* Interrupt setup is already guaranteed to be single-threaded, this is
4113          * just to make the assert_spin_locked checks happy. */
4114         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4115         if (dev_priv->display.hpd_irq_setup)
4116                 dev_priv->display.hpd_irq_setup(dev);
4117         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4118 }
4119
4120 /* Disable interrupts so we can allow runtime PM. */
4121 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4122 {
4123         struct drm_i915_private *dev_priv = dev->dev_private;
4124
4125         dev->driver->irq_uninstall(dev);
4126         dev_priv->pm.irqs_disabled = true;
4127 }
4128
4129 /* Restore interrupts so we can recover from runtime PM. */
4130 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4131 {
4132         struct drm_i915_private *dev_priv = dev->dev_private;
4133
4134         dev_priv->pm.irqs_disabled = false;
4135         dev->driver->irq_preinstall(dev);
4136         dev->driver->irq_postinstall(dev);
4137 }