drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30
  31 #define GEN_DEFAULT_PIPEOFFSETS \
  32         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  33                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  34         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  35                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  36         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  37
  38 #define GEN_CHV_PIPEOFFSETS \
  39         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  40                           CHV_PIPE_C_OFFSET }, \
  41         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  42                            CHV_TRANSCODER_C_OFFSET, }, \
  43         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  44                              CHV_PALETTE_C_OFFSET }
  45
  46 #define CURSOR_OFFSETS \
  47         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  48
  49 #define IVB_CURSOR_OFFSETS \
  50         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  51
  52 #define BDW_COLORS \
  53         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  54 #define CHV_COLORS \
  55         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  56
  57 static const struct intel_device_info intel_i830_info = {
  58         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  59         .has_overlay = 1, .overlay_needs_physical = 1,
  60         .ring_mask = RENDER_RING,
  61         GEN_DEFAULT_PIPEOFFSETS,
  62         CURSOR_OFFSETS,
  63 };
  64
  65 static const struct intel_device_info intel_845g_info = {
  66         .gen = 2, .num_pipes = 1,
  67         .has_overlay = 1, .overlay_needs_physical = 1,
  68         .ring_mask = RENDER_RING,
  69         GEN_DEFAULT_PIPEOFFSETS,
  70         CURSOR_OFFSETS,
  71 };
  72
  73 static const struct intel_device_info intel_i85x_info = {
  74         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  75         .cursor_needs_physical = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .has_fbc = 1,
  78         .ring_mask = RENDER_RING,
  79         GEN_DEFAULT_PIPEOFFSETS,
  80         CURSOR_OFFSETS,
  81 };
  82
  83 static const struct intel_device_info intel_i865g_info = {
  84         .gen = 2, .num_pipes = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .ring_mask = RENDER_RING,
  87         GEN_DEFAULT_PIPEOFFSETS,
  88         CURSOR_OFFSETS,
  89 };
  90
  91 static const struct intel_device_info intel_i915g_info = {
  92         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  93         .has_overlay = 1, .overlay_needs_physical = 1,
  94         .ring_mask = RENDER_RING,
  95         GEN_DEFAULT_PIPEOFFSETS,
  96         CURSOR_OFFSETS,
  97 };
  98 static const struct intel_device_info intel_i915gm_info = {
  99         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 100         .cursor_needs_physical = 1,
 101         .has_overlay = 1, .overlay_needs_physical = 1,
 102         .supports_tv = 1,
 103         .has_fbc = 1,
 104         .ring_mask = RENDER_RING,
 105         GEN_DEFAULT_PIPEOFFSETS,
 106         CURSOR_OFFSETS,
 107 };
 108 static const struct intel_device_info intel_i945g_info = {
 109         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .ring_mask = RENDER_RING,
 112         GEN_DEFAULT_PIPEOFFSETS,
 113         CURSOR_OFFSETS,
 114 };
 115 static const struct intel_device_info intel_i945gm_info = {
 116         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 117         .has_hotplug = 1, .cursor_needs_physical = 1,
 118         .has_overlay = 1, .overlay_needs_physical = 1,
 119         .supports_tv = 1,
 120         .has_fbc = 1,
 121         .ring_mask = RENDER_RING,
 122         GEN_DEFAULT_PIPEOFFSETS,
 123         CURSOR_OFFSETS,
 124 };
 125
 126 static const struct intel_device_info intel_i965g_info = {
 127         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 128         .has_hotplug = 1,
 129         .has_overlay = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965gm_info = {
 136         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 137         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .supports_tv = 1,
 140         .ring_mask = RENDER_RING,
 141         GEN_DEFAULT_PIPEOFFSETS,
 142         CURSOR_OFFSETS,
 143 };
 144
 145 static const struct intel_device_info intel_g33_info = {
 146         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 147         .need_gfx_hws = 1, .has_hotplug = 1,
 148         .has_overlay = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g45_info = {
 155         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 156         .has_pipe_cxsr = 1, .has_hotplug = 1,
 157         .ring_mask = RENDER_RING | BSD_RING,
 158         GEN_DEFAULT_PIPEOFFSETS,
 159         CURSOR_OFFSETS,
 160 };
 161
 162 static const struct intel_device_info intel_gm45_info = {
 163         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 164         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .supports_tv = 1,
 167         .ring_mask = RENDER_RING | BSD_RING,
 168         GEN_DEFAULT_PIPEOFFSETS,
 169         CURSOR_OFFSETS,
 170 };
 171
 172 static const struct intel_device_info intel_pineview_info = {
 173         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 174         .need_gfx_hws = 1, .has_hotplug = 1,
 175         .has_overlay = 1,
 176         .ring_mask = RENDER_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_ironlake_d_info = {
 182         .gen = 5, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .ring_mask = RENDER_RING | BSD_RING,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_m_info = {
 190         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .has_fbc = 1,
 193         .ring_mask = RENDER_RING | BSD_RING,
 194         GEN_DEFAULT_PIPEOFFSETS,
 195         CURSOR_OFFSETS,
 196 };
 197
 198 static const struct intel_device_info intel_sandybridge_d_info = {
 199         .gen = 6, .num_pipes = 2,
 200         .need_gfx_hws = 1, .has_hotplug = 1,
 201         .has_fbc = 1,
 202         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 203         .has_llc = 1,
 204         GEN_DEFAULT_PIPEOFFSETS,
 205         CURSOR_OFFSETS,
 206 };
 207
 208 static const struct intel_device_info intel_sandybridge_m_info = {
 209         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_fbc = 1,
 212         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 213         .has_llc = 1,
 214         GEN_DEFAULT_PIPEOFFSETS,
 215         CURSOR_OFFSETS,
 216 };
 217
 218 #define GEN7_FEATURES  \
 219         .gen = 7, .num_pipes = 3, \
 220         .need_gfx_hws = 1, .has_hotplug = 1, \
 221         .has_fbc = 1, \
 222         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 223         .has_llc = 1, \
 224         GEN_DEFAULT_PIPEOFFSETS, \
 225         IVB_CURSOR_OFFSETS
 226
 227 static const struct intel_device_info intel_ivybridge_d_info = {
 228         GEN7_FEATURES,
 229         .is_ivybridge = 1,
 230 };
 231
 232 static const struct intel_device_info intel_ivybridge_m_info = {
 233         GEN7_FEATURES,
 234         .is_ivybridge = 1,
 235         .is_mobile = 1,
 236 };
 237
 238 static const struct intel_device_info intel_ivybridge_q_info = {
 239         GEN7_FEATURES,
 240         .is_ivybridge = 1,
 241         .num_pipes = 0, /* legal, last one wins */
 242 };
 243
 244 #define VLV_FEATURES  \
 245         .gen = 7, .num_pipes = 2, \
 246         .need_gfx_hws = 1, .has_hotplug = 1, \
 247         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 248         .display_mmio_offset = VLV_DISPLAY_BASE, \
 249         GEN_DEFAULT_PIPEOFFSETS, \
 250         CURSOR_OFFSETS
 251
 252 static const struct intel_device_info intel_valleyview_m_info = {
 253         VLV_FEATURES,
 254         .is_valleyview = 1,
 255         .is_mobile = 1,
 256 };
 257
 258 static const struct intel_device_info intel_valleyview_d_info = {
 259         VLV_FEATURES,
 260         .is_valleyview = 1,
 261 };
 262
 263 #define HSW_FEATURES  \
 264         GEN7_FEATURES, \
 265         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 266         .has_ddi = 1, \
 267         .has_fpga_dbg = 1
 268
 269 static const struct intel_device_info intel_haswell_d_info = {
 270         HSW_FEATURES,
 271         .is_haswell = 1,
 272 };
 273
 274 static const struct intel_device_info intel_haswell_m_info = {
 275         HSW_FEATURES,
 276         .is_haswell = 1,
 277         .is_mobile = 1,
 278 };
 279
 280 #define BDW_FEATURES \
 281         HSW_FEATURES, \
 282         BDW_COLORS
 283
 284 static const struct intel_device_info intel_broadwell_d_info = {
 285         BDW_FEATURES,
 286         .gen = 8,
 287         .is_broadwell = 1,
 288 };
 289
 290 static const struct intel_device_info intel_broadwell_m_info = {
 291         BDW_FEATURES,
 292         .gen = 8, .is_mobile = 1,
 293         .is_broadwell = 1,
 294 };
 295
 296 static const struct intel_device_info intel_broadwell_gt3d_info = {
 297         BDW_FEATURES,
 298         .gen = 8,
 299         .is_broadwell = 1,
 300         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 301 };
 302
 303 static const struct intel_device_info intel_broadwell_gt3m_info = {
 304         BDW_FEATURES,
 305         .gen = 8, .is_mobile = 1,
 306         .is_broadwell = 1,
 307         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 308 };
 309
 310 static const struct intel_device_info intel_cherryview_info = {
 311         .gen = 8, .num_pipes = 3,
 312         .need_gfx_hws = 1, .has_hotplug = 1,
 313         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 314         .is_cherryview = 1,
 315         .display_mmio_offset = VLV_DISPLAY_BASE,
 316         GEN_CHV_PIPEOFFSETS,
 317         CURSOR_OFFSETS,
 318         CHV_COLORS,
 319 };
 320
 321 static const struct intel_device_info intel_skylake_info = {
 322         BDW_FEATURES,
 323         .is_skylake = 1,
 324         .gen = 9,
 325 };
 326
 327 static const struct intel_device_info intel_skylake_gt3_info = {
 328         BDW_FEATURES,
 329         .is_skylake = 1,
 330         .gen = 9,
 331         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 332 };
 333
 334 static const struct intel_device_info intel_broxton_info = {
 335         .is_broxton = 1,
 336         .gen = 9,
 337         .need_gfx_hws = 1, .has_hotplug = 1,
 338         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 339         .num_pipes = 3,
 340         .has_ddi = 1,
 341         .has_fpga_dbg = 1,
 342         .has_fbc = 1,
 343         .has_pooled_eu = 0,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346         BDW_COLORS,
 347 };
 348
 349 static const struct intel_device_info intel_kabylake_info = {
 350         BDW_FEATURES,
 351         .is_kabylake = 1,
 352         .gen = 9,
 353 };
 354
 355 static const struct intel_device_info intel_kabylake_gt3_info = {
 356         BDW_FEATURES,
 357         .is_kabylake = 1,
 358         .gen = 9,
 359         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 360 };
 361
 362 /*
 363  * Make sure any device matches here are from most specific to most
 364  * general.  For example, since the Quanta match is based on the subsystem
 365  * and subvendor IDs, we need it to come before the more general IVB
 366  * PCI ID matches, otherwise we'll use the wrong info struct above.
 367  */
 368 static const struct pci_device_id pciidlist[] = {
 369         INTEL_I830_IDS(&intel_i830_info),
 370         INTEL_I845G_IDS(&intel_845g_info),
 371         INTEL_I85X_IDS(&intel_i85x_info),
 372         INTEL_I865G_IDS(&intel_i865g_info),
 373         INTEL_I915G_IDS(&intel_i915g_info),
 374         INTEL_I915GM_IDS(&intel_i915gm_info),
 375         INTEL_I945G_IDS(&intel_i945g_info),
 376         INTEL_I945GM_IDS(&intel_i945gm_info),
 377         INTEL_I965G_IDS(&intel_i965g_info),
 378         INTEL_G33_IDS(&intel_g33_info),
 379         INTEL_I965GM_IDS(&intel_i965gm_info),
 380         INTEL_GM45_IDS(&intel_gm45_info),
 381         INTEL_G45_IDS(&intel_g45_info),
 382         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 383         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 384         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 385         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 386         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 387         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 388         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 389         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 390         INTEL_HSW_D_IDS(&intel_haswell_d_info),
 391         INTEL_HSW_M_IDS(&intel_haswell_m_info),
 392         INTEL_VLV_M_IDS(&intel_valleyview_m_info),
 393         INTEL_VLV_D_IDS(&intel_valleyview_d_info),
 394         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
 395         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
 396         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
 397         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
 398         INTEL_CHV_IDS(&intel_cherryview_info),
 399         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 400         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 401         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 402         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 403         INTEL_BXT_IDS(&intel_broxton_info),
 404         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 405         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 406         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 407         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 408         {0, 0, 0}
 409 };
 410 MODULE_DEVICE_TABLE(pci, pciidlist);
 411
 412 extern int i915_driver_load(struct pci_dev *pdev,
 413                             const struct pci_device_id *ent);
 414
 415 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 416 {
 417         struct intel_device_info *intel_info =
 418                 (struct intel_device_info *) ent->driver_data;
 419
 420         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 421                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 422                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 423                 return -ENODEV;
 424         }
 425
 426         /* Only bind to function 0 of the device. Early generations
 427          * used function 1 as a placeholder for multi-head. This causes
 428          * us confusion instead, especially on the systems where both
 429          * functions have the same PCI-ID!
 430          */
 431         if (PCI_FUNC(pdev->devfn))
 432                 return -ENODEV;
 433
 434         /*
 435          * apple-gmux is needed on dual GPU MacBook Pro
 436          * to probe the panel if we're the inactive GPU.
 437          */
 438         if (vga_switcheroo_client_probe_defer(pdev))
 439                 return -EPROBE_DEFER;
 440
 441         return i915_driver_load(pdev, ent);
 442 }
 443
 444 extern void i915_driver_unload(struct drm_device *dev);
 445
 446 static void i915_pci_remove(struct pci_dev *pdev)
 447 {
 448         struct drm_device *dev = pci_get_drvdata(pdev);
 449
 450         i915_driver_unload(dev);
 451         drm_dev_unref(dev);
 452 }
 453
 454 extern const struct dev_pm_ops i915_pm_ops;
 455
 456 static struct pci_driver i915_pci_driver = {
 457         .name = DRIVER_NAME,
 458         .id_table = pciidlist,
 459         .probe = i915_pci_probe,
 460         .remove = i915_pci_remove,
 461         .driver.pm = &i915_pm_ops,
 462 };
 463
 464 static int __init i915_init(void)
 465 {
 466         bool use_kms = true;
 467
 468         /*
 469          * Enable KMS by default, unless explicitly overriden by
 470          * either the i915.modeset prarameter or by the
 471          * vga_text_mode_force boot option.
 472          */
 473
 474         if (i915.modeset == 0)
 475                 use_kms = false;
 476
 477         if (vgacon_text_force() && i915.modeset == -1)
 478                 use_kms = false;
 479
 480         if (!use_kms) {
 481                 /* Silently fail loading to not upset userspace. */
 482                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 483                 return 0;
 484         }
 485
 486         return pci_register_driver(&i915_pci_driver);
 487 }
 488
 489 static void __exit i915_exit(void)
 490 {
 491         if (!i915_pci_driver.driver.owner)
 492                 return;
 493
 494         pci_unregister_driver(&i915_pci_driver);
 495 }
 496
 497 module_init(i915_init);
 498 module_exit(i915_exit);
 499
 500 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 501 MODULE_AUTHOR("Intel Corporation");
 502
 503 MODULE_DESCRIPTION(DRIVER_DESC);
 504 MODULE_LICENSE("GPL and additional rights");