drivers/gpu/drm/i915/i915_suspend.c

   1 /*
   2  *
   3  * Copyright 2008 (c) Intel Corporation
   4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "drmP.h"
  28 #include "i915_drm.h"
  29 #include "intel_drv.h"
  30 #include "i915_reg.h"
  31
  32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  33 {
  34         struct drm_i915_private *dev_priv = dev->dev_private;
  35         u32     dpll_reg;
  36
  37         /* On IVB, 3rd pipe shares PLL with another one */
  38         if (pipe > 1)
  39                 return false;
  40
  41         if (HAS_PCH_SPLIT(dev))
  42                 dpll_reg = _PCH_DPLL(pipe);
  43         else
  44                 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
  45
  46         return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
  47 }
  48
  49 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  50 {
  51         struct drm_i915_private *dev_priv = dev->dev_private;
  52         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  53         u32 *array;
  54         int i;
  55
  56         if (!i915_pipe_enabled(dev, pipe))
  57                 return;
  58
  59         if (HAS_PCH_SPLIT(dev))
  60                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  61
  62         if (pipe == PIPE_A)
  63                 array = dev_priv->save_palette_a;
  64         else
  65                 array = dev_priv->save_palette_b;
  66
  67         for (i = 0; i < 256; i++)
  68                 array[i] = I915_READ(reg + (i << 2));
  69 }
  70
  71 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
  72 {
  73         struct drm_i915_private *dev_priv = dev->dev_private;
  74         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  75         u32 *array;
  76         int i;
  77
  78         if (!i915_pipe_enabled(dev, pipe))
  79                 return;
  80
  81         if (HAS_PCH_SPLIT(dev))
  82                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  83
  84         if (pipe == PIPE_A)
  85                 array = dev_priv->save_palette_a;
  86         else
  87                 array = dev_priv->save_palette_b;
  88
  89         for (i = 0; i < 256; i++)
  90                 I915_WRITE(reg + (i << 2), array[i]);
  91 }
  92
  93 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
  94 {
  95         struct drm_i915_private *dev_priv = dev->dev_private;
  96
  97         I915_WRITE8(index_port, reg);
  98         return I915_READ8(data_port);
  99 }
 100
 101 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
 102 {
 103         struct drm_i915_private *dev_priv = dev->dev_private;
 104
 105         I915_READ8(st01);
 106         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 107         return I915_READ8(VGA_AR_DATA_READ);
 108 }
 109
 110 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
 111 {
 112         struct drm_i915_private *dev_priv = dev->dev_private;
 113
 114         I915_READ8(st01);
 115         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 116         I915_WRITE8(VGA_AR_DATA_WRITE, val);
 117 }
 118
 119 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
 120 {
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122
 123         I915_WRITE8(index_port, reg);
 124         I915_WRITE8(data_port, val);
 125 }
 126
 127 static void i915_save_vga(struct drm_device *dev)
 128 {
 129         struct drm_i915_private *dev_priv = dev->dev_private;
 130         int i;
 131         u16 cr_index, cr_data, st01;
 132
 133         /* VGA color palette registers */
 134         dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
 135
 136         /* MSR bits */
 137         dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
 138         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 139                 cr_index = VGA_CR_INDEX_CGA;
 140                 cr_data = VGA_CR_DATA_CGA;
 141                 st01 = VGA_ST01_CGA;
 142         } else {
 143                 cr_index = VGA_CR_INDEX_MDA;
 144                 cr_data = VGA_CR_DATA_MDA;
 145                 st01 = VGA_ST01_MDA;
 146         }
 147
 148         /* CRT controller regs */
 149         i915_write_indexed(dev, cr_index, cr_data, 0x11,
 150                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
 151                            (~0x80));
 152         for (i = 0; i <= 0x24; i++)
 153                 dev_priv->saveCR[i] =
 154                         i915_read_indexed(dev, cr_index, cr_data, i);
 155         /* Make sure we don't turn off CR group 0 writes */
 156         dev_priv->saveCR[0x11] &= ~0x80;
 157
 158         /* Attribute controller registers */
 159         I915_READ8(st01);
 160         dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
 161         for (i = 0; i <= 0x14; i++)
 162                 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
 163         I915_READ8(st01);
 164         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
 165         I915_READ8(st01);
 166
 167         /* Graphics controller registers */
 168         for (i = 0; i < 9; i++)
 169                 dev_priv->saveGR[i] =
 170                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
 171
 172         dev_priv->saveGR[0x10] =
 173                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 174         dev_priv->saveGR[0x11] =
 175                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 176         dev_priv->saveGR[0x18] =
 177                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 178
 179         /* Sequencer registers */
 180         for (i = 0; i < 8; i++)
 181                 dev_priv->saveSR[i] =
 182                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
 183 }
 184
 185 static void i915_restore_vga(struct drm_device *dev)
 186 {
 187         struct drm_i915_private *dev_priv = dev->dev_private;
 188         int i;
 189         u16 cr_index, cr_data, st01;
 190
 191         /* MSR bits */
 192         I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
 193         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 194                 cr_index = VGA_CR_INDEX_CGA;
 195                 cr_data = VGA_CR_DATA_CGA;
 196                 st01 = VGA_ST01_CGA;
 197         } else {
 198                 cr_index = VGA_CR_INDEX_MDA;
 199                 cr_data = VGA_CR_DATA_MDA;
 200                 st01 = VGA_ST01_MDA;
 201         }
 202
 203         /* Sequencer registers, don't write SR07 */
 204         for (i = 0; i < 7; i++)
 205                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
 206                                    dev_priv->saveSR[i]);
 207
 208         /* CRT controller regs */
 209         /* Enable CR group 0 writes */
 210         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 211         for (i = 0; i <= 0x24; i++)
 212                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
 213
 214         /* Graphics controller regs */
 215         for (i = 0; i < 9; i++)
 216                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
 217                                    dev_priv->saveGR[i]);
 218
 219         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 220                            dev_priv->saveGR[0x10]);
 221         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 222                            dev_priv->saveGR[0x11]);
 223         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 224                            dev_priv->saveGR[0x18]);
 225
 226         /* Attribute controller registers */
 227         I915_READ8(st01); /* switch back to index mode */
 228         for (i = 0; i <= 0x14; i++)
 229                 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
 230         I915_READ8(st01); /* switch back to index mode */
 231         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
 232         I915_READ8(st01);
 233
 234         /* VGA color palette registers */
 235         I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
 236 }
 237
 238 static void i915_save_modeset_reg(struct drm_device *dev)
 239 {
 240         struct drm_i915_private *dev_priv = dev->dev_private;
 241         int i;
 242
 243         if (drm_core_check_feature(dev, DRIVER_MODESET))
 244                 return;
 245
 246         /* Cursor state */
 247         dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
 248         dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
 249         dev_priv->saveCURABASE = I915_READ(_CURABASE);
 250         dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
 251         dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
 252         dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
 253         if (IS_GEN2(dev))
 254                 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
 255
 256         if (HAS_PCH_SPLIT(dev)) {
 257                 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
 258                 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
 259         }
 260
 261         /* Pipe & plane A info */
 262         dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
 263         dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
 264         if (HAS_PCH_SPLIT(dev)) {
 265                 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
 266                 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
 267                 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
 268         } else {
 269                 dev_priv->saveFPA0 = I915_READ(_FPA0);
 270                 dev_priv->saveFPA1 = I915_READ(_FPA1);
 271                 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
 272         }
 273         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 274                 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
 275         dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
 276         dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
 277         dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
 278         dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
 279         dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
 280         dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
 281         if (!HAS_PCH_SPLIT(dev))
 282                 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
 283
 284         if (HAS_PCH_SPLIT(dev)) {
 285                 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
 286                 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
 287                 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
 288                 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
 289
 290                 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
 291                 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
 292
 293                 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
 294                 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
 295                 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
 296
 297                 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
 298                 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
 299                 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
 300                 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
 301                 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
 302                 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
 303                 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
 304         }
 305
 306         dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
 307         dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
 308         dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
 309         dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
 310         dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
 311         if (INTEL_INFO(dev)->gen >= 4) {
 312                 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
 313                 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
 314         }
 315         i915_save_palette(dev, PIPE_A);
 316         dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
 317
 318         /* Pipe & plane B info */
 319         dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
 320         dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
 321         if (HAS_PCH_SPLIT(dev)) {
 322                 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
 323                 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
 324                 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
 325         } else {
 326                 dev_priv->saveFPB0 = I915_READ(_FPB0);
 327                 dev_priv->saveFPB1 = I915_READ(_FPB1);
 328                 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
 329         }
 330         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 331                 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
 332         dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
 333         dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
 334         dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
 335         dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
 336         dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
 337         dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
 338         if (!HAS_PCH_SPLIT(dev))
 339                 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
 340
 341         if (HAS_PCH_SPLIT(dev)) {
 342                 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
 343                 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
 344                 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
 345                 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
 346
 347                 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
 348                 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
 349
 350                 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
 351                 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
 352                 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
 353
 354                 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
 355                 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
 356                 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
 357                 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
 358                 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
 359                 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
 360                 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
 361         }
 362
 363         dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
 364         dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
 365         dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
 366         dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
 367         dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
 368         if (INTEL_INFO(dev)->gen >= 4) {
 369                 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
 370                 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
 371         }
 372         i915_save_palette(dev, PIPE_B);
 373         dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
 374
 375         /* Fences */
 376         switch (INTEL_INFO(dev)->gen) {
 377         case 7:
 378         case 6:
 379                 for (i = 0; i < 16; i++)
 380                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 381                 break;
 382         case 5:
 383         case 4:
 384                 for (i = 0; i < 16; i++)
 385                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 386                 break;
 387         case 3:
 388                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 389                         for (i = 0; i < 8; i++)
 390                                 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 391         case 2:
 392                 for (i = 0; i < 8; i++)
 393                         dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 394                 break;
 395         }
 396
 397         return;
 398 }
 399
 400 static void i915_restore_modeset_reg(struct drm_device *dev)
 401 {
 402         struct drm_i915_private *dev_priv = dev->dev_private;
 403         int dpll_a_reg, fpa0_reg, fpa1_reg;
 404         int dpll_b_reg, fpb0_reg, fpb1_reg;
 405         int i;
 406
 407         if (drm_core_check_feature(dev, DRIVER_MODESET))
 408                 return;
 409
 410         /* Fences */
 411         switch (INTEL_INFO(dev)->gen) {
 412         case 7:
 413         case 6:
 414                 for (i = 0; i < 16; i++)
 415                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
 416                 break;
 417         case 5:
 418         case 4:
 419                 for (i = 0; i < 16; i++)
 420                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
 421                 break;
 422         case 3:
 423         case 2:
 424                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 425                         for (i = 0; i < 8; i++)
 426                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
 427                 for (i = 0; i < 8; i++)
 428                         I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
 429                 break;
 430         }
 431
 432
 433         if (HAS_PCH_SPLIT(dev)) {
 434                 dpll_a_reg = _PCH_DPLL_A;
 435                 dpll_b_reg = _PCH_DPLL_B;
 436                 fpa0_reg = _PCH_FPA0;
 437                 fpb0_reg = _PCH_FPB0;
 438                 fpa1_reg = _PCH_FPA1;
 439                 fpb1_reg = _PCH_FPB1;
 440         } else {
 441                 dpll_a_reg = _DPLL_A;
 442                 dpll_b_reg = _DPLL_B;
 443                 fpa0_reg = _FPA0;
 444                 fpb0_reg = _FPB0;
 445                 fpa1_reg = _FPA1;
 446                 fpb1_reg = _FPB1;
 447         }
 448
 449         if (HAS_PCH_SPLIT(dev)) {
 450                 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
 451                 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
 452         }
 453
 454         /* Pipe & plane A info */
 455         /* Prime the clock */
 456         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 457                 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
 458                            ~DPLL_VCO_ENABLE);
 459                 POSTING_READ(dpll_a_reg);
 460                 udelay(150);
 461         }
 462         I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
 463         I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
 464         /* Actually enable it */
 465         I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
 466         POSTING_READ(dpll_a_reg);
 467         udelay(150);
 468         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 469                 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 470                 POSTING_READ(_DPLL_A_MD);
 471         }
 472         udelay(150);
 473
 474         /* Restore mode */
 475         I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
 476         I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
 477         I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
 478         I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
 479         I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
 480         I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
 481         if (!HAS_PCH_SPLIT(dev))
 482                 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 483
 484         if (HAS_PCH_SPLIT(dev)) {
 485                 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
 486                 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
 487                 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
 488                 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
 489
 490                 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
 491                 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
 492
 493                 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
 494                 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
 495                 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
 496
 497                 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
 498                 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
 499                 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
 500                 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
 501                 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
 502                 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
 503                 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
 504         }
 505
 506         /* Restore plane info */
 507         I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
 508         I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
 509         I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
 510         I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
 511         I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 512         if (INTEL_INFO(dev)->gen >= 4) {
 513                 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
 514                 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 515         }
 516
 517         I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
 518
 519         i915_restore_palette(dev, PIPE_A);
 520         /* Enable the plane */
 521         I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
 522         I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
 523
 524         /* Pipe & plane B info */
 525         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 526                 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
 527                            ~DPLL_VCO_ENABLE);
 528                 POSTING_READ(dpll_b_reg);
 529                 udelay(150);
 530         }
 531         I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
 532         I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
 533         /* Actually enable it */
 534         I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
 535         POSTING_READ(dpll_b_reg);
 536         udelay(150);
 537         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 538                 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 539                 POSTING_READ(_DPLL_B_MD);
 540         }
 541         udelay(150);
 542
 543         /* Restore mode */
 544         I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
 545         I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
 546         I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
 547         I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
 548         I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
 549         I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
 550         if (!HAS_PCH_SPLIT(dev))
 551                 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 552
 553         if (HAS_PCH_SPLIT(dev)) {
 554                 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
 555                 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
 556                 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
 557                 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
 558
 559                 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
 560                 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
 561
 562                 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
 563                 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
 564                 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
 565
 566                 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
 567                 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
 568                 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
 569                 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
 570                 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
 571                 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
 572                 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
 573         }
 574
 575         /* Restore plane info */
 576         I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
 577         I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
 578         I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
 579         I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
 580         I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 581         if (INTEL_INFO(dev)->gen >= 4) {
 582                 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
 583                 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 584         }
 585
 586         I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
 587
 588         i915_restore_palette(dev, PIPE_B);
 589         /* Enable the plane */
 590         I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
 591         I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
 592
 593         /* Cursor state */
 594         I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
 595         I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
 596         I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
 597         I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
 598         I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
 599         I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
 600         if (IS_GEN2(dev))
 601                 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
 602
 603         return;
 604 }
 605
 606 static void i915_save_display(struct drm_device *dev)
 607 {
 608         struct drm_i915_private *dev_priv = dev->dev_private;
 609
 610         /* Display arbitration control */
 611         dev_priv->saveDSPARB = I915_READ(DSPARB);
 612
 613         /* This is only meaningful in non-KMS mode */
 614         /* Don't save them in KMS mode */
 615         i915_save_modeset_reg(dev);
 616
 617         /* CRT state */
 618         if (HAS_PCH_SPLIT(dev)) {
 619                 dev_priv->saveADPA = I915_READ(PCH_ADPA);
 620         } else {
 621                 dev_priv->saveADPA = I915_READ(ADPA);
 622         }
 623
 624         /* LVDS state */
 625         if (HAS_PCH_SPLIT(dev)) {
 626                 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
 627                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
 628                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
 629                 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
 630                 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
 631                 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
 632         } else {
 633                 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 634                 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 635                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 636                 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
 637                 if (INTEL_INFO(dev)->gen >= 4)
 638                         dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 639                 if (IS_MOBILE(dev) && !IS_I830(dev))
 640                         dev_priv->saveLVDS = I915_READ(LVDS);
 641         }
 642
 643         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 644                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 645
 646         if (HAS_PCH_SPLIT(dev)) {
 647                 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 648                 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
 649                 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
 650         } else {
 651                 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 652                 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
 653                 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
 654         }
 655
 656         /* Display Port state */
 657         if (SUPPORTS_INTEGRATED_DP(dev)) {
 658                 dev_priv->saveDP_B = I915_READ(DP_B);
 659                 dev_priv->saveDP_C = I915_READ(DP_C);
 660                 dev_priv->saveDP_D = I915_READ(DP_D);
 661                 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
 662                 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
 663                 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
 664                 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
 665                 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
 666                 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
 667                 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
 668                 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
 669         }
 670         /* FIXME: save TV & SDVO state */
 671
 672         /* Only save FBC state on the platform that supports FBC */
 673         if (I915_HAS_FBC(dev)) {
 674                 if (HAS_PCH_SPLIT(dev)) {
 675                         dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
 676                 } else if (IS_GM45(dev)) {
 677                         dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
 678                 } else {
 679                         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 680                         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 681                         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 682                         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 683                 }
 684         }
 685
 686         /* VGA state */
 687         dev_priv->saveVGA0 = I915_READ(VGA0);
 688         dev_priv->saveVGA1 = I915_READ(VGA1);
 689         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
 690         if (HAS_PCH_SPLIT(dev))
 691                 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
 692         else
 693                 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 694
 695         i915_save_vga(dev);
 696 }
 697
 698 static void i915_restore_display(struct drm_device *dev)
 699 {
 700         struct drm_i915_private *dev_priv = dev->dev_private;
 701
 702         /* Display arbitration */
 703         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 704
 705         /* Display port ratios (must be done before clock is set) */
 706         if (SUPPORTS_INTEGRATED_DP(dev)) {
 707                 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
 708                 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
 709                 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
 710                 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
 711                 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
 712                 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
 713                 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
 714                 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
 715         }
 716
 717         /* This is only meaningful in non-KMS mode */
 718         /* Don't restore them in KMS mode */
 719         i915_restore_modeset_reg(dev);
 720
 721         /* CRT state */
 722         if (HAS_PCH_SPLIT(dev))
 723                 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
 724         else
 725                 I915_WRITE(ADPA, dev_priv->saveADPA);
 726
 727         /* LVDS state */
 728         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 729                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 730
 731         if (HAS_PCH_SPLIT(dev)) {
 732                 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
 733         } else if (IS_MOBILE(dev) && !IS_I830(dev))
 734                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 735
 736         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 737                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 738
 739         if (HAS_PCH_SPLIT(dev)) {
 740                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
 741                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
 742                 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
 743                  * otherwise we get blank eDP screen after S3 on some machines
 744                  */
 745                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
 746                 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
 747                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 748                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 749                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
 750                 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
 751                 I915_WRITE(RSTDBYCTL,
 752                            dev_priv->saveMCHBAR_RENDER_STANDBY);
 753         } else {
 754                 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 755                 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 756                 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
 757                 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 758                 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 759                 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
 760                 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 761         }
 762
 763         /* Display Port state */
 764         if (SUPPORTS_INTEGRATED_DP(dev)) {
 765                 I915_WRITE(DP_B, dev_priv->saveDP_B);
 766                 I915_WRITE(DP_C, dev_priv->saveDP_C);
 767                 I915_WRITE(DP_D, dev_priv->saveDP_D);
 768         }
 769         /* FIXME: restore TV & SDVO state */
 770
 771         /* only restore FBC info on the platform that supports FBC*/
 772         intel_disable_fbc(dev);
 773         if (I915_HAS_FBC(dev)) {
 774                 if (HAS_PCH_SPLIT(dev)) {
 775                         I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 776                 } else if (IS_GM45(dev)) {
 777                         I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 778                 } else {
 779                         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 780                         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 781                         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 782                         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 783                 }
 784         }
 785         /* VGA state */
 786         if (HAS_PCH_SPLIT(dev))
 787                 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
 788         else
 789                 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 790
 791         I915_WRITE(VGA0, dev_priv->saveVGA0);
 792         I915_WRITE(VGA1, dev_priv->saveVGA1);
 793         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
 794         POSTING_READ(VGA_PD);
 795         udelay(150);
 796
 797         i915_restore_vga(dev);
 798 }
 799
 800 int i915_save_state(struct drm_device *dev)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         int i;
 804
 805         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 806
 807         mutex_lock(&dev->struct_mutex);
 808
 809         /* Hardware status page */
 810         dev_priv->saveHWS = I915_READ(HWS_PGA);
 811
 812         i915_save_display(dev);
 813
 814         /* Interrupt state */
 815         if (HAS_PCH_SPLIT(dev)) {
 816                 dev_priv->saveDEIER = I915_READ(DEIER);
 817                 dev_priv->saveDEIMR = I915_READ(DEIMR);
 818                 dev_priv->saveGTIER = I915_READ(GTIER);
 819                 dev_priv->saveGTIMR = I915_READ(GTIMR);
 820                 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
 821                 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
 822                 dev_priv->saveMCHBAR_RENDER_STANDBY =
 823                         I915_READ(RSTDBYCTL);
 824                 dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
 825         } else {
 826                 dev_priv->saveIER = I915_READ(IER);
 827                 dev_priv->saveIMR = I915_READ(IMR);
 828         }
 829
 830         intel_disable_gt_powersave(dev);
 831
 832         /* Cache mode state */
 833         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 834
 835         /* Memory Arbitration state */
 836         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 837
 838         /* Scratch space */
 839         for (i = 0; i < 16; i++) {
 840                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
 841                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 842         }
 843         for (i = 0; i < 3; i++)
 844                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 845
 846         mutex_unlock(&dev->struct_mutex);
 847
 848         return 0;
 849 }
 850
 851 int i915_restore_state(struct drm_device *dev)
 852 {
 853         struct drm_i915_private *dev_priv = dev->dev_private;
 854         int i;
 855
 856         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 857
 858         mutex_lock(&dev->struct_mutex);
 859
 860         /* Hardware status page */
 861         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
 862
 863         i915_restore_display(dev);
 864
 865         /* Interrupt state */
 866         if (HAS_PCH_SPLIT(dev)) {
 867                 I915_WRITE(DEIER, dev_priv->saveDEIER);
 868                 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
 869                 I915_WRITE(GTIER, dev_priv->saveGTIER);
 870                 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
 871                 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
 872                 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
 873                 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
 874         } else {
 875                 I915_WRITE(IER, dev_priv->saveIER);
 876                 I915_WRITE(IMR, dev_priv->saveIMR);
 877         }
 878
 879         /* Cache mode state */
 880         I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 881
 882         /* Memory arbitration state */
 883         I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 884
 885         for (i = 0; i < 16; i++) {
 886                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
 887                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
 888         }
 889         for (i = 0; i < 3; i++)
 890                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 891
 892         mutex_unlock(&dev->struct_mutex);
 893
 894         intel_i2c_reset(dev);
 895
 896         return 0;
 897 }