2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
78 static const uint32_t intel_cursor_formats[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
115 if (!connector->mst_port)
116 return connector->encoder;
118 return &connector->mst_port->mst_encoders[pipe]->base;
127 int p2_slow, p2_fast;
130 typedef struct intel_limit intel_limit_t;
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
137 intel_pch_rawclk(struct drm_device *dev)
139 struct drm_i915_private *dev_priv = dev->dev_private;
141 WARN_ON(!HAS_PCH_SPLIT(dev));
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146 static inline u32 /* units of 100MHz */
147 intel_fdi_link_freq(struct drm_device *dev)
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
156 static const intel_limit_t intel_limits_i8xx_dac = {
157 .dot = { .min = 25000, .max = 350000 },
158 .vco = { .min = 908000, .max = 1512000 },
159 .n = { .min = 2, .max = 16 },
160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
169 static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
171 .vco = { .min = 908000, .max = 1512000 },
172 .n = { .min = 2, .max = 16 },
173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
182 static const intel_limit_t intel_limits_i8xx_lvds = {
183 .dot = { .min = 25000, .max = 350000 },
184 .vco = { .min = 908000, .max = 1512000 },
185 .n = { .min = 2, .max = 16 },
186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
195 static const intel_limit_t intel_limits_i9xx_sdvo = {
196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
208 static const intel_limit_t intel_limits_i9xx_lvds = {
209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
222 static const intel_limit_t intel_limits_g4x_sdvo = {
223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
237 static const intel_limit_t intel_limits_g4x_hdmi = {
238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
278 static const intel_limit_t intel_limits_pineview_sdvo = {
279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
281 /* Pineview's Ncounter is a ring counter */
282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
284 /* Pineview only has one combined m divider, which we treat as m2. */
285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
293 static const intel_limit_t intel_limits_pineview_lvds = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
306 /* Ironlake / Sandybridge
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
311 static const intel_limit_t intel_limits_ironlake_dac = {
312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
350 /* LVDS 100mhz refclk limits. */
351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
372 .p1 = { .min = 2, .max = 6 },
373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
377 static const intel_limit_t intel_limits_vlv = {
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
385 .vco = { .min = 4000000, .max = 6000000 },
386 .n = { .min = 1, .max = 7 },
387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
393 static const intel_limit_t intel_limits_chv = {
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
401 .vco = { .min = 4800000, .max = 6480000 },
402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409 static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6700000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422 needs_modeset(struct drm_crtc_state *state)
424 return state->mode_changed || state->active_changed;
428 * Returns whether any output on the specified pipe is of the specified type
430 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
432 struct drm_device *dev = crtc->base.dev;
433 struct intel_encoder *encoder;
435 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
436 if (encoder->type == type)
443 * Returns whether any output on the specified pipe will have the specified
444 * type after a staged modeset is complete, i.e., the same as
445 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
448 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
451 struct drm_atomic_state *state = crtc_state->base.state;
452 struct drm_connector *connector;
453 struct drm_connector_state *connector_state;
454 struct intel_encoder *encoder;
455 int i, num_connectors = 0;
457 for_each_connector_in_state(state, connector, connector_state, i) {
458 if (connector_state->crtc != crtc_state->base.crtc)
463 encoder = to_intel_encoder(connector_state->best_encoder);
464 if (encoder->type == type)
468 WARN_ON(num_connectors == 0);
473 static const intel_limit_t *
474 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
476 struct drm_device *dev = crtc_state->base.crtc->dev;
477 const intel_limit_t *limit;
479 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
480 if (intel_is_dual_link_lvds(dev)) {
481 if (refclk == 100000)
482 limit = &intel_limits_ironlake_dual_lvds_100m;
484 limit = &intel_limits_ironlake_dual_lvds;
486 if (refclk == 100000)
487 limit = &intel_limits_ironlake_single_lvds_100m;
489 limit = &intel_limits_ironlake_single_lvds;
492 limit = &intel_limits_ironlake_dac;
497 static const intel_limit_t *
498 intel_g4x_limit(struct intel_crtc_state *crtc_state)
500 struct drm_device *dev = crtc_state->base.crtc->dev;
501 const intel_limit_t *limit;
503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
504 if (intel_is_dual_link_lvds(dev))
505 limit = &intel_limits_g4x_dual_channel_lvds;
507 limit = &intel_limits_g4x_single_channel_lvds;
508 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
510 limit = &intel_limits_g4x_hdmi;
511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
512 limit = &intel_limits_g4x_sdvo;
513 } else /* The option is for other outputs */
514 limit = &intel_limits_i9xx_sdvo;
519 static const intel_limit_t *
520 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
522 struct drm_device *dev = crtc_state->base.crtc->dev;
523 const intel_limit_t *limit;
526 limit = &intel_limits_bxt;
527 else if (HAS_PCH_SPLIT(dev))
528 limit = intel_ironlake_limit(crtc_state, refclk);
529 else if (IS_G4X(dev)) {
530 limit = intel_g4x_limit(crtc_state);
531 } else if (IS_PINEVIEW(dev)) {
532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
533 limit = &intel_limits_pineview_lvds;
535 limit = &intel_limits_pineview_sdvo;
536 } else if (IS_CHERRYVIEW(dev)) {
537 limit = &intel_limits_chv;
538 } else if (IS_VALLEYVIEW(dev)) {
539 limit = &intel_limits_vlv;
540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
544 limit = &intel_limits_i9xx_sdvo;
546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
547 limit = &intel_limits_i8xx_lvds;
548 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
549 limit = &intel_limits_i8xx_dvo;
551 limit = &intel_limits_i8xx_dac;
557 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
558 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
559 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
560 * The helpers' return value is the rate of the clock that is fed to the
561 * display engine's pipe which can be the above fast dot clock rate or a
562 * divided-down version of it.
564 /* m1 is reserved as 0 in Pineview, n is a ring counter */
565 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
569 if (WARN_ON(clock->n == 0 || clock->p == 0))
571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
584 clock->m = i9xx_dpll_compute_m(clock);
585 clock->p = clock->p1 * clock->p2;
586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603 return clock->dot / 5;
606 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
608 clock->m = clock->m1 * clock->m2;
609 clock->p = clock->p1 * clock->p2;
610 if (WARN_ON(clock->n == 0 || clock->p == 0))
612 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
616 return clock->dot / 5;
619 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
621 * Returns whether the given set of divisors are valid for a given refclk with
622 * the given connectors.
625 static bool intel_PLL_is_valid(struct drm_device *dev,
626 const intel_limit_t *limit,
627 const intel_clock_t *clock)
629 if (clock->n < limit->n.min || limit->n.max < clock->n)
630 INTELPllInvalid("n out of range\n");
631 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
632 INTELPllInvalid("p1 out of range\n");
633 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
634 INTELPllInvalid("m2 out of range\n");
635 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
636 INTELPllInvalid("m1 out of range\n");
638 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
639 if (clock->m1 <= clock->m2)
640 INTELPllInvalid("m1 <= m2\n");
642 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
643 if (clock->p < limit->p.min || limit->p.max < clock->p)
644 INTELPllInvalid("p out of range\n");
645 if (clock->m < limit->m.min || limit->m.max < clock->m)
646 INTELPllInvalid("m out of range\n");
649 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
650 INTELPllInvalid("vco out of range\n");
651 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
652 * connector, etc., rather than just a single range.
654 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
655 INTELPllInvalid("dot out of range\n");
661 i9xx_select_p2_div(const intel_limit_t *limit,
662 const struct intel_crtc_state *crtc_state,
665 struct drm_device *dev = crtc_state->base.crtc->dev;
667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
669 * For LVDS just rely on its current settings for dual-channel.
670 * We haven't figured out how to reliably set up different
671 * single/dual channel state, if we even can.
673 if (intel_is_dual_link_lvds(dev))
674 return limit->p2.p2_fast;
676 return limit->p2.p2_slow;
678 if (target < limit->p2.dot_limit)
679 return limit->p2.p2_slow;
681 return limit->p2.p2_fast;
686 i9xx_find_best_dpll(const intel_limit_t *limit,
687 struct intel_crtc_state *crtc_state,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
691 struct drm_device *dev = crtc_state->base.crtc->dev;
695 memset(best_clock, 0, sizeof(*best_clock));
697 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
699 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
701 for (clock.m2 = limit->m2.min;
702 clock.m2 <= limit->m2.max; clock.m2++) {
703 if (clock.m2 >= clock.m1)
705 for (clock.n = limit->n.min;
706 clock.n <= limit->n.max; clock.n++) {
707 for (clock.p1 = limit->p1.min;
708 clock.p1 <= limit->p1.max; clock.p1++) {
711 i9xx_calc_dpll_params(refclk, &clock);
712 if (!intel_PLL_is_valid(dev, limit,
716 clock.p != match_clock->p)
719 this_err = abs(clock.dot - target);
720 if (this_err < err) {
729 return (err != target);
733 pnv_find_best_dpll(const intel_limit_t *limit,
734 struct intel_crtc_state *crtc_state,
735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
738 struct drm_device *dev = crtc_state->base.crtc->dev;
742 memset(best_clock, 0, sizeof(*best_clock));
744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748 for (clock.m2 = limit->m2.min;
749 clock.m2 <= limit->m2.max; clock.m2++) {
750 for (clock.n = limit->n.min;
751 clock.n <= limit->n.max; clock.n++) {
752 for (clock.p1 = limit->p1.min;
753 clock.p1 <= limit->p1.max; clock.p1++) {
756 pnv_calc_dpll_params(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
761 clock.p != match_clock->p)
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
774 return (err != target);
778 g4x_find_best_dpll(const intel_limit_t *limit,
779 struct intel_crtc_state *crtc_state,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
783 struct drm_device *dev = crtc_state->base.crtc->dev;
787 /* approximately equals target * 0.00585 */
788 int err_most = (target >> 8) + (target >> 9);
790 memset(best_clock, 0, sizeof(*best_clock));
792 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
794 max_n = limit->n.max;
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797 /* based on hardware requirement, prefere larger m1,m2 */
798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
806 i9xx_calc_dpll_params(refclk, &clock);
807 if (!intel_PLL_is_valid(dev, limit,
811 this_err = abs(clock.dot - target);
812 if (this_err < err_most) {
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
829 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
839 if (IS_CHERRYVIEW(dev)) {
842 return calculated_clock->p > best_clock->p;
845 if (WARN_ON_ONCE(!target_freq))
848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
862 return *error_ppm + 10 < best_error_ppm;
866 vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
872 struct drm_device *dev = crtc->base.dev;
874 unsigned int bestppm = 1000000;
875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
879 target *= 5; /* fast clock */
881 memset(best_clock, 0, sizeof(*best_clock));
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
888 clock.p = clock.p1 * clock.p2;
889 /* based on hardware requirement, prefer bigger m1,m2 values */
890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
896 vlv_calc_dpll_params(refclk, &clock);
898 if (!intel_PLL_is_valid(dev, limit,
902 if (!vlv_PLL_is_optimal(dev, target,
920 chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
926 struct drm_device *dev = crtc->base.dev;
927 unsigned int best_error_ppm;
932 memset(best_clock, 0, sizeof(*best_clock));
933 best_error_ppm = 1000000;
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 unsigned int error_ppm;
949 clock.p = clock.p1 * clock.p2;
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
954 if (m2 > INT_MAX/clock.m1)
959 chv_calc_dpll_params(refclk, &clock);
961 if (!intel_PLL_is_valid(dev, limit, &clock))
964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
969 best_error_ppm = error_ppm;
977 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
980 int refclk = i9xx_get_refclk(crtc_state, 0);
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
986 bool intel_crtc_active(struct drm_crtc *crtc)
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
993 * We can ditch the adjusted_mode.crtc_clock check as soon
994 * as Haswell has gained clock readout/fastboot support.
996 * We can ditch the crtc->primary->fb check as soon as we can
997 * properly reconstruct framebuffers.
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1003 return intel_crtc->active && crtc->primary->state->fb &&
1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
1007 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1013 return intel_crtc->config->cpu_transcoder;
1016 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1024 line_mask = DSL_LINEMASK_GEN2;
1026 line_mask = DSL_LINEMASK_GEN3;
1028 line1 = I915_READ(reg) & line_mask;
1030 line2 = I915_READ(reg) & line_mask;
1032 return line1 == line2;
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
1037 * @crtc: crtc whose pipe to wait for
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
1051 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1053 struct drm_device *dev = crtc->base.dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1056 enum pipe pipe = crtc->pipe;
1058 if (INTEL_INFO(dev)->gen >= 4) {
1059 int reg = PIPECONF(cpu_transcoder);
1061 /* Wait for the Pipe State to go off */
1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1064 WARN(1, "pipe_off wait timed out\n");
1066 /* Wait for the display line to settle */
1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1068 WARN(1, "pipe_off wait timed out\n");
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1077 * Returns true if @port is connected, false otherwise.
1079 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1084 if (HAS_PCH_IBX(dev_priv->dev)) {
1085 switch (port->port) {
1087 bit = SDE_PORTB_HOTPLUG;
1090 bit = SDE_PORTC_HOTPLUG;
1093 bit = SDE_PORTD_HOTPLUG;
1099 switch (port->port) {
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1114 return I915_READ(SDEISR) & bit;
1117 static const char *state_string(bool enabled)
1119 return enabled ? "on" : "off";
1122 /* Only for pre-ILK configs */
1123 void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
1133 I915_STATE_WARN(cur_state != state,
1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1138 /* XXX: the dsi pll is shared between MIPI DSI ports */
1139 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144 mutex_lock(&dev_priv->sb_lock);
1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1146 mutex_unlock(&dev_priv->sb_lock);
1148 cur_state = val & DSI_PLL_VCO_EN;
1149 I915_STATE_WARN(cur_state != state,
1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1153 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1156 struct intel_shared_dpll *
1157 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1161 if (crtc->config->shared_dpll < 0)
1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1168 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1173 struct intel_dpll_hw_state hw_state;
1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1180 I915_STATE_WARN(cur_state != state,
1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
1185 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1197 val = I915_READ(reg);
1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1204 I915_STATE_WARN(cur_state != state,
1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1208 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1211 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
1221 I915_STATE_WARN(cur_state != state,
1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1225 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1228 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1234 /* ILK FDI PLL is always enabled */
1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1239 if (HAS_DDI(dev_priv->dev))
1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1247 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
1262 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1265 struct drm_device *dev = dev_priv->dev;
1268 enum pipe panel_pipe = PIPE_A;
1271 if (WARN_ON(HAS_DDI(dev)))
1274 if (HAS_PCH_SPLIT(dev)) {
1277 pp_reg = PCH_PP_CONTROL;
1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1289 pp_reg = PP_CONTROL;
1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1299 I915_STATE_WARN(panel_pipe == pipe && locked,
1300 "panel assertion failure, pipe %c regs locked\n",
1304 static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1307 struct drm_device *dev = dev_priv->dev;
1310 if (IS_845G(dev) || IS_I865G(dev))
1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1315 I915_STATE_WARN(cur_state != state,
1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1319 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1322 void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1336 if (!intel_display_power_is_enabled(dev_priv,
1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1345 I915_STATE_WARN(cur_state != state,
1346 "pipe %c assertion failure (expected %s, current %s)\n",
1347 pipe_name(pipe), state_string(state), state_string(cur_state));
1350 static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1360 I915_STATE_WARN(cur_state != state,
1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
1365 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1368 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1371 struct drm_device *dev = dev_priv->dev;
1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381 "plane %c assertion failure, should be disabled but not\n",
1386 /* Need to check both planes against the pipe */
1387 for_each_pipe(dev_priv, i) {
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
1398 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1401 struct drm_device *dev = dev_priv->dev;
1405 if (INTEL_INFO(dev)->gen >= 9) {
1406 for_each_sprite(dev_priv, pipe, sprite) {
1407 val = I915_READ(PLANE_CTL(pipe, sprite));
1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1412 } else if (IS_VALLEYVIEW(dev)) {
1413 for_each_sprite(dev_priv, pipe, sprite) {
1414 reg = SPCNTR(pipe, sprite);
1415 val = I915_READ(reg);
1416 I915_STATE_WARN(val & SP_ENABLE,
1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418 sprite_name(pipe, sprite), pipe_name(pipe));
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1422 val = I915_READ(reg);
1423 I915_STATE_WARN(val & SPRITE_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
1428 val = I915_READ(reg);
1429 I915_STATE_WARN(val & DVS_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 plane_name(pipe), pipe_name(pipe));
1435 static void assert_vblank_disabled(struct drm_crtc *crtc)
1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1438 drm_crtc_vblank_put(crtc);
1441 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1454 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1461 reg = PCH_TRANSCONF(pipe);
1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
1464 I915_STATE_WARN(enabled,
1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1469 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
1472 if ((val & DP_PORT_EN) == 0)
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1490 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1493 if ((val & SDVO_ENABLE) == 0)
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1509 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1512 if ((val & LVDS_PORT_EN) == 0)
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1525 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1540 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1541 enum pipe pipe, int reg, u32 port_sel)
1543 u32 val = I915_READ(reg);
1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1546 reg, pipe_name(pipe));
1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1549 && (val & DP_PIPEB_SELECT),
1550 "IBX PCH dp port still using transcoder B\n");
1553 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1556 u32 val = I915_READ(reg);
1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1559 reg, pipe_name(pipe));
1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1562 && (val & SDVO_PIPE_B_SELECT),
1563 "IBX PCH hdmi port still using transcoder B\n");
1566 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1577 val = I915_READ(reg);
1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
1583 val = I915_READ(reg);
1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1593 static void intel_init_dpio(struct drm_device *dev)
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1597 if (!IS_VALLEYVIEW(dev))
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1613 static void vlv_enable_pll(struct intel_crtc *crtc,
1614 const struct intel_crtc_state *pipe_config)
1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
1621 assert_pipe_disabled(dev_priv, crtc->pipe);
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1626 /* PLL is protected by panel, make sure we can write it */
1627 if (IS_MOBILE(dev_priv->dev))
1628 assert_panel_unlocked(dev_priv, crtc->pipe);
1630 I915_WRITE(reg, dpll);
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1638 POSTING_READ(DPLL_MD(crtc->pipe));
1640 /* We do this three times for luck */
1641 I915_WRITE(reg, dpll);
1643 udelay(150); /* wait for warmup */
1644 I915_WRITE(reg, dpll);
1646 udelay(150); /* wait for warmup */
1647 I915_WRITE(reg, dpll);
1649 udelay(150); /* wait for warmup */
1652 static void chv_enable_pll(struct intel_crtc *crtc,
1653 const struct intel_crtc_state *pipe_config)
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1665 mutex_lock(&dev_priv->sb_lock);
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1672 mutex_unlock(&dev_priv->sb_lock);
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1682 /* Check PLL is locked */
1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1686 /* not sure when this should be written */
1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1688 POSTING_READ(DPLL_MD(pipe));
1691 static int intel_num_dvo_pipes(struct drm_device *dev)
1693 struct intel_crtc *crtc;
1696 for_each_intel_crtc(dev, crtc)
1697 count += crtc->base.state->active &&
1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703 static void i9xx_enable_pll(struct intel_crtc *crtc)
1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
1710 assert_pipe_disabled(dev_priv, crtc->pipe);
1712 /* No really, not for ILK+ */
1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1715 /* PLL is protected by panel, make sure we can write it */
1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1732 /* Wait for the clocks to stabilize. */
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
1738 crtc->config->dpll_hw_state.dpll_md);
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1743 * So write it again.
1745 I915_WRITE(reg, dpll);
1748 /* We do this three times for luck */
1749 I915_WRITE(reg, dpll);
1751 udelay(150); /* wait for warmup */
1752 I915_WRITE(reg, dpll);
1754 udelay(150); /* wait for warmup */
1755 I915_WRITE(reg, dpll);
1757 udelay(150); /* wait for warmup */
1761 * i9xx_disable_pll - disable a PLL
1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1767 * Note! This is for pre-ILK only.
1769 static void i9xx_disable_pll(struct intel_crtc *crtc)
1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1778 !intel_num_dvo_pipes(dev)) {
1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1793 I915_WRITE(DPLL(pipe), 0);
1794 POSTING_READ(DPLL(pipe));
1797 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1809 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1810 I915_WRITE(DPLL(pipe), val);
1811 POSTING_READ(DPLL(pipe));
1815 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1817 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1820 /* Make sure the pipe isn't still relying on us */
1821 assert_pipe_disabled(dev_priv, pipe);
1823 /* Set PLL en = 0 */
1824 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1826 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1827 I915_WRITE(DPLL(pipe), val);
1828 POSTING_READ(DPLL(pipe));
1830 mutex_lock(&dev_priv->sb_lock);
1832 /* Disable 10bit clock to display controller */
1833 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1834 val &= ~DPIO_DCLKP_EN;
1835 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1837 /* disable left/right clock distribution */
1838 if (pipe != PIPE_B) {
1839 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1840 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1844 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1848 mutex_unlock(&dev_priv->sb_lock);
1851 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1852 struct intel_digital_port *dport,
1853 unsigned int expected_mask)
1858 switch (dport->port) {
1860 port_mask = DPLL_PORTB_READY_MASK;
1864 port_mask = DPLL_PORTC_READY_MASK;
1866 expected_mask <<= 4;
1869 port_mask = DPLL_PORTD_READY_MASK;
1870 dpll_reg = DPIO_PHY_STATUS;
1876 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1877 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1878 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1881 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1883 struct drm_device *dev = crtc->base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1887 if (WARN_ON(pll == NULL))
1890 WARN_ON(!pll->config.crtc_mask);
1891 if (pll->active == 0) {
1892 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1894 assert_shared_dpll_disabled(dev_priv, pll);
1896 pll->mode_set(dev_priv, pll);
1901 * intel_enable_shared_dpll - enable PCH PLL
1902 * @dev_priv: i915 private structure
1903 * @pipe: pipe PLL to enable
1905 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1906 * drives the transcoder clock.
1908 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1914 if (WARN_ON(pll == NULL))
1917 if (WARN_ON(pll->config.crtc_mask == 0))
1920 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
1922 crtc->base.base.id);
1924 if (pll->active++) {
1926 assert_shared_dpll_enabled(dev_priv, pll);
1931 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1933 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1934 pll->enable(dev_priv, pll);
1938 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1940 struct drm_device *dev = crtc->base.dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1944 /* PCH only available on ILK+ */
1945 BUG_ON(INTEL_INFO(dev)->gen < 5);
1949 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1952 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1953 pll->name, pll->active, pll->on,
1954 crtc->base.base.id);
1956 if (WARN_ON(pll->active == 0)) {
1957 assert_shared_dpll_disabled(dev_priv, pll);
1961 assert_shared_dpll_enabled(dev_priv, pll);
1966 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1967 pll->disable(dev_priv, pll);
1970 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1973 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1976 struct drm_device *dev = dev_priv->dev;
1977 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1979 uint32_t reg, val, pipeconf_val;
1981 /* PCH only available on ILK+ */
1982 BUG_ON(!HAS_PCH_SPLIT(dev));
1984 /* Make sure PCH DPLL is enabled */
1985 assert_shared_dpll_enabled(dev_priv,
1986 intel_crtc_to_shared_dpll(intel_crtc));
1988 /* FDI must be feeding us bits for PCH ports */
1989 assert_fdi_tx_enabled(dev_priv, pipe);
1990 assert_fdi_rx_enabled(dev_priv, pipe);
1992 if (HAS_PCH_CPT(dev)) {
1993 /* Workaround: Set the timing override bit before enabling the
1994 * pch transcoder. */
1995 reg = TRANS_CHICKEN2(pipe);
1996 val = I915_READ(reg);
1997 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(reg, val);
2001 reg = PCH_TRANSCONF(pipe);
2002 val = I915_READ(reg);
2003 pipeconf_val = I915_READ(PIPECONF(pipe));
2005 if (HAS_PCH_IBX(dev_priv->dev)) {
2007 * Make the BPC in transcoder be consistent with
2008 * that in pipeconf reg. For HDMI we must use 8bpc
2009 * here for both 8bpc and 12bpc.
2011 val &= ~PIPECONF_BPC_MASK;
2012 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2013 val |= PIPECONF_8BPC;
2015 val |= pipeconf_val & PIPECONF_BPC_MASK;
2018 val &= ~TRANS_INTERLACE_MASK;
2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2020 if (HAS_PCH_IBX(dev_priv->dev) &&
2021 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2022 val |= TRANS_LEGACY_INTERLACED_ILK;
2024 val |= TRANS_INTERLACED;
2026 val |= TRANS_PROGRESSIVE;
2028 I915_WRITE(reg, val | TRANS_ENABLE);
2029 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2030 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2033 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2034 enum transcoder cpu_transcoder)
2036 u32 val, pipeconf_val;
2038 /* PCH only available on ILK+ */
2039 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2041 /* FDI must be feeding us bits for PCH ports */
2042 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2043 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2045 /* Workaround: set timing override bit. */
2046 val = I915_READ(_TRANSA_CHICKEN2);
2047 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2048 I915_WRITE(_TRANSA_CHICKEN2, val);
2051 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2053 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2054 PIPECONF_INTERLACED_ILK)
2055 val |= TRANS_INTERLACED;
2057 val |= TRANS_PROGRESSIVE;
2059 I915_WRITE(LPT_TRANSCONF, val);
2060 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2061 DRM_ERROR("Failed to enable PCH transcoder\n");
2064 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2067 struct drm_device *dev = dev_priv->dev;
2070 /* FDI relies on the transcoder */
2071 assert_fdi_tx_disabled(dev_priv, pipe);
2072 assert_fdi_rx_disabled(dev_priv, pipe);
2074 /* Ports must be off as well */
2075 assert_pch_ports_disabled(dev_priv, pipe);
2077 reg = PCH_TRANSCONF(pipe);
2078 val = I915_READ(reg);
2079 val &= ~TRANS_ENABLE;
2080 I915_WRITE(reg, val);
2081 /* wait for PCH transcoder off, transcoder state */
2082 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2083 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2085 if (!HAS_PCH_IBX(dev)) {
2086 /* Workaround: Clear the timing override chicken bit again. */
2087 reg = TRANS_CHICKEN2(pipe);
2088 val = I915_READ(reg);
2089 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090 I915_WRITE(reg, val);
2094 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2098 val = I915_READ(LPT_TRANSCONF);
2099 val &= ~TRANS_ENABLE;
2100 I915_WRITE(LPT_TRANSCONF, val);
2101 /* wait for PCH transcoder off, transcoder state */
2102 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2103 DRM_ERROR("Failed to disable PCH transcoder\n");
2105 /* Workaround: clear timing override bit. */
2106 val = I915_READ(_TRANSA_CHICKEN2);
2107 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2108 I915_WRITE(_TRANSA_CHICKEN2, val);
2112 * intel_enable_pipe - enable a pipe, asserting requirements
2113 * @crtc: crtc responsible for the pipe
2115 * Enable @crtc's pipe, making sure that various hardware specific requirements
2116 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2118 static void intel_enable_pipe(struct intel_crtc *crtc)
2120 struct drm_device *dev = crtc->base.dev;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 enum pipe pipe = crtc->pipe;
2123 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2125 enum pipe pch_transcoder;
2129 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2131 assert_planes_disabled(dev_priv, pipe);
2132 assert_cursor_disabled(dev_priv, pipe);
2133 assert_sprites_disabled(dev_priv, pipe);
2135 if (HAS_PCH_LPT(dev_priv->dev))
2136 pch_transcoder = TRANSCODER_A;
2138 pch_transcoder = pipe;
2141 * A pipe without a PLL won't actually be able to drive bits from
2142 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2146 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2147 assert_dsi_pll_enabled(dev_priv);
2149 assert_pll_enabled(dev_priv, pipe);
2151 if (crtc->config->has_pch_encoder) {
2152 /* if driving the PCH, we need FDI enabled */
2153 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2154 assert_fdi_tx_pll_enabled(dev_priv,
2155 (enum pipe) cpu_transcoder);
2157 /* FIXME: assert CPU port conditions for SNB+ */
2160 reg = PIPECONF(cpu_transcoder);
2161 val = I915_READ(reg);
2162 if (val & PIPECONF_ENABLE) {
2163 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2164 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2168 I915_WRITE(reg, val | PIPECONF_ENABLE);
2173 * intel_disable_pipe - disable a pipe, asserting requirements
2174 * @crtc: crtc whose pipes is to be disabled
2176 * Disable the pipe of @crtc, making sure that various hardware
2177 * specific requirements are met, if applicable, e.g. plane
2178 * disabled, panel fitter off, etc.
2180 * Will wait until the pipe has shut down before returning.
2182 static void intel_disable_pipe(struct intel_crtc *crtc)
2184 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2185 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2186 enum pipe pipe = crtc->pipe;
2190 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2196 assert_planes_disabled(dev_priv, pipe);
2197 assert_cursor_disabled(dev_priv, pipe);
2198 assert_sprites_disabled(dev_priv, pipe);
2200 reg = PIPECONF(cpu_transcoder);
2201 val = I915_READ(reg);
2202 if ((val & PIPECONF_ENABLE) == 0)
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2209 if (crtc->config->double_wide)
2210 val &= ~PIPECONF_DOUBLE_WIDE;
2212 /* Don't disable pipe or pipe PLLs if needed */
2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2215 val &= ~PIPECONF_ENABLE;
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
2222 static bool need_vtd_wa(struct drm_device *dev)
2224 #ifdef CONFIG_INTEL_IOMMU
2225 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2232 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2233 uint64_t fb_format_modifier)
2235 unsigned int tile_height;
2236 uint32_t pixel_bytes;
2238 switch (fb_format_modifier) {
2239 case DRM_FORMAT_MOD_NONE:
2242 case I915_FORMAT_MOD_X_TILED:
2243 tile_height = IS_GEN2(dev) ? 16 : 8;
2245 case I915_FORMAT_MOD_Y_TILED:
2248 case I915_FORMAT_MOD_Yf_TILED:
2249 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2250 switch (pixel_bytes) {
2264 "128-bit pixels are not supported for display!");
2270 MISSING_CASE(fb_format_modifier);
2279 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2280 uint32_t pixel_format, uint64_t fb_format_modifier)
2282 return ALIGN(height, intel_tile_height(dev, pixel_format,
2283 fb_format_modifier));
2287 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2288 const struct drm_plane_state *plane_state)
2290 struct intel_rotation_info *info = &view->rotation_info;
2291 unsigned int tile_height, tile_pitch;
2293 *view = i915_ggtt_view_normal;
2298 if (!intel_rotation_90_or_270(plane_state->rotation))
2301 *view = i915_ggtt_view_rotated;
2303 info->height = fb->height;
2304 info->pixel_format = fb->pixel_format;
2305 info->pitch = fb->pitches[0];
2306 info->fb_modifier = fb->modifier[0];
2308 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2310 tile_pitch = PAGE_SIZE / tile_height;
2311 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2312 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2313 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2318 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2320 if (INTEL_INFO(dev_priv)->gen >= 9)
2322 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2323 IS_VALLEYVIEW(dev_priv))
2325 else if (INTEL_INFO(dev_priv)->gen >= 4)
2332 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2333 struct drm_framebuffer *fb,
2334 const struct drm_plane_state *plane_state,
2335 struct intel_engine_cs *pipelined,
2336 struct drm_i915_gem_request **pipelined_request)
2338 struct drm_device *dev = fb->dev;
2339 struct drm_i915_private *dev_priv = dev->dev_private;
2340 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2341 struct i915_ggtt_view view;
2345 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347 switch (fb->modifier[0]) {
2348 case DRM_FORMAT_MOD_NONE:
2349 alignment = intel_linear_alignment(dev_priv);
2351 case I915_FORMAT_MOD_X_TILED:
2352 if (INTEL_INFO(dev)->gen >= 9)
2353 alignment = 256 * 1024;
2355 /* pin() will align the object as required by fence */
2359 case I915_FORMAT_MOD_Y_TILED:
2360 case I915_FORMAT_MOD_Yf_TILED:
2361 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2362 "Y tiling bo slipped through, driver bug!\n"))
2364 alignment = 1 * 1024 * 1024;
2367 MISSING_CASE(fb->modifier[0]);
2371 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2375 /* Note that the w/a also requires 64 PTE of padding following the
2376 * bo. We currently fill all unused PTE with the shadow page and so
2377 * we should always have valid PTE following the scanout preventing
2380 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2381 alignment = 256 * 1024;
2384 * Global gtt pte registers are special registers which actually forward
2385 * writes to a chunk of system memory. Which means that there is no risk
2386 * that the register values disappear as soon as we call
2387 * intel_runtime_pm_put(), so it is correct to wrap only the
2388 * pin/unpin/fence and not more.
2390 intel_runtime_pm_get(dev_priv);
2392 dev_priv->mm.interruptible = false;
2393 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2394 pipelined_request, &view);
2396 goto err_interruptible;
2398 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2399 * fence, whereas 965+ only requires a fence if using
2400 * framebuffer compression. For simplicity, we always install
2401 * a fence as the cost is not that onerous.
2403 ret = i915_gem_object_get_fence(obj);
2407 i915_gem_object_pin_fence(obj);
2409 dev_priv->mm.interruptible = true;
2410 intel_runtime_pm_put(dev_priv);
2414 i915_gem_object_unpin_from_display_plane(obj, &view);
2416 dev_priv->mm.interruptible = true;
2417 intel_runtime_pm_put(dev_priv);
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422 const struct drm_plane_state *plane_state)
2424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425 struct i915_ggtt_view view;
2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2430 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431 WARN_ONCE(ret, "Couldn't get view from plane state!");
2433 i915_gem_object_unpin_fence(obj);
2434 i915_gem_object_unpin_from_display_plane(obj, &view);
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438 * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2441 unsigned int tiling_mode,
2445 if (tiling_mode != I915_TILING_NONE) {
2446 unsigned int tile_rows, tiles;
2451 tiles = *x / (512/cpp);
2454 return tile_rows * pitch * 8 + tiles * 4096;
2456 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2457 unsigned int offset;
2459 offset = *y * pitch + *x * cpp;
2460 *y = (offset & alignment) / pitch;
2461 *x = ((offset & alignment) - *y * pitch) / cpp;
2462 return offset & ~alignment;
2466 static int i9xx_format_to_fourcc(int format)
2469 case DISPPLANE_8BPP:
2470 return DRM_FORMAT_C8;
2471 case DISPPLANE_BGRX555:
2472 return DRM_FORMAT_XRGB1555;
2473 case DISPPLANE_BGRX565:
2474 return DRM_FORMAT_RGB565;
2476 case DISPPLANE_BGRX888:
2477 return DRM_FORMAT_XRGB8888;
2478 case DISPPLANE_RGBX888:
2479 return DRM_FORMAT_XBGR8888;
2480 case DISPPLANE_BGRX101010:
2481 return DRM_FORMAT_XRGB2101010;
2482 case DISPPLANE_RGBX101010:
2483 return DRM_FORMAT_XBGR2101010;
2487 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490 case PLANE_CTL_FORMAT_RGB_565:
2491 return DRM_FORMAT_RGB565;
2493 case PLANE_CTL_FORMAT_XRGB_8888:
2496 return DRM_FORMAT_ABGR8888;
2498 return DRM_FORMAT_XBGR8888;
2501 return DRM_FORMAT_ARGB8888;
2503 return DRM_FORMAT_XRGB8888;
2505 case PLANE_CTL_FORMAT_XRGB_2101010:
2507 return DRM_FORMAT_XBGR2101010;
2509 return DRM_FORMAT_XRGB2101010;
2514 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515 struct intel_initial_plane_config *plane_config)
2517 struct drm_device *dev = crtc->base.dev;
2518 struct drm_i915_gem_object *obj = NULL;
2519 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2520 struct drm_framebuffer *fb = &plane_config->fb->base;
2521 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2522 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 size_aligned -= base_aligned;
2527 if (plane_config->size == 0)
2530 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537 obj->tiling_mode = plane_config->tiling;
2538 if (obj->tiling_mode == I915_TILING_X)
2539 obj->stride = fb->pitches[0];
2541 mode_cmd.pixel_format = fb->pixel_format;
2542 mode_cmd.width = fb->width;
2543 mode_cmd.height = fb->height;
2544 mode_cmd.pitches[0] = fb->pitches[0];
2545 mode_cmd.modifier[0] = fb->modifier[0];
2546 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2548 mutex_lock(&dev->struct_mutex);
2549 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2551 DRM_DEBUG_KMS("intel fb init failed\n");
2554 mutex_unlock(&dev->struct_mutex);
2556 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2560 drm_gem_object_unreference(&obj->base);
2561 mutex_unlock(&dev->struct_mutex);
2565 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2567 update_state_fb(struct drm_plane *plane)
2569 if (plane->fb == plane->state->fb)
2572 if (plane->state->fb)
2573 drm_framebuffer_unreference(plane->state->fb);
2574 plane->state->fb = plane->fb;
2575 if (plane->state->fb)
2576 drm_framebuffer_reference(plane->state->fb);
2580 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2581 struct intel_initial_plane_config *plane_config)
2583 struct drm_device *dev = intel_crtc->base.dev;
2584 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct intel_crtc *i;
2587 struct drm_i915_gem_object *obj;
2588 struct drm_plane *primary = intel_crtc->base.primary;
2589 struct drm_framebuffer *fb;
2591 if (!plane_config->fb)
2594 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2595 fb = &plane_config->fb->base;
2599 kfree(plane_config->fb);
2602 * Failed to alloc the obj, check to see if we should share
2603 * an fb with another CRTC instead
2605 for_each_crtc(dev, c) {
2606 i = to_intel_crtc(c);
2608 if (c == &intel_crtc->base)
2614 fb = c->primary->fb;
2618 obj = intel_fb_obj(fb);
2619 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2620 drm_framebuffer_reference(fb);
2628 obj = intel_fb_obj(fb);
2629 if (obj->tiling_mode != I915_TILING_NONE)
2630 dev_priv->preserve_bios_swizzle = true;
2633 primary->crtc = primary->state->crtc = &intel_crtc->base;
2634 update_state_fb(primary);
2635 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2636 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2639 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2640 struct drm_framebuffer *fb,
2643 struct drm_device *dev = crtc->dev;
2644 struct drm_i915_private *dev_priv = dev->dev_private;
2645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2646 struct drm_plane *primary = crtc->primary;
2647 bool visible = to_intel_plane_state(primary->state)->visible;
2648 struct drm_i915_gem_object *obj;
2649 int plane = intel_crtc->plane;
2650 unsigned long linear_offset;
2652 u32 reg = DSPCNTR(plane);
2655 if (!visible || !fb) {
2657 if (INTEL_INFO(dev)->gen >= 4)
2658 I915_WRITE(DSPSURF(plane), 0);
2660 I915_WRITE(DSPADDR(plane), 0);
2665 obj = intel_fb_obj(fb);
2666 if (WARN_ON(obj == NULL))
2669 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2671 dspcntr = DISPPLANE_GAMMA_ENABLE;
2673 dspcntr |= DISPLAY_PLANE_ENABLE;
2675 if (INTEL_INFO(dev)->gen < 4) {
2676 if (intel_crtc->pipe == PIPE_B)
2677 dspcntr |= DISPPLANE_SEL_PIPE_B;
2679 /* pipesrc and dspsize control the size that is scaled from,
2680 * which should always be the user's requested size.
2682 I915_WRITE(DSPSIZE(plane),
2683 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2684 (intel_crtc->config->pipe_src_w - 1));
2685 I915_WRITE(DSPPOS(plane), 0);
2686 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2687 I915_WRITE(PRIMSIZE(plane),
2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
2690 I915_WRITE(PRIMPOS(plane), 0);
2691 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2694 switch (fb->pixel_format) {
2696 dspcntr |= DISPPLANE_8BPP;
2698 case DRM_FORMAT_XRGB1555:
2699 dspcntr |= DISPPLANE_BGRX555;
2701 case DRM_FORMAT_RGB565:
2702 dspcntr |= DISPPLANE_BGRX565;
2704 case DRM_FORMAT_XRGB8888:
2705 dspcntr |= DISPPLANE_BGRX888;
2707 case DRM_FORMAT_XBGR8888:
2708 dspcntr |= DISPPLANE_RGBX888;
2710 case DRM_FORMAT_XRGB2101010:
2711 dspcntr |= DISPPLANE_BGRX101010;
2713 case DRM_FORMAT_XBGR2101010:
2714 dspcntr |= DISPPLANE_RGBX101010;
2720 if (INTEL_INFO(dev)->gen >= 4 &&
2721 obj->tiling_mode != I915_TILING_NONE)
2722 dspcntr |= DISPPLANE_TILED;
2725 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2727 linear_offset = y * fb->pitches[0] + x * pixel_size;
2729 if (INTEL_INFO(dev)->gen >= 4) {
2730 intel_crtc->dspaddr_offset =
2731 intel_gen4_compute_page_offset(dev_priv,
2732 &x, &y, obj->tiling_mode,
2735 linear_offset -= intel_crtc->dspaddr_offset;
2737 intel_crtc->dspaddr_offset = linear_offset;
2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741 dspcntr |= DISPPLANE_ROTATE_180;
2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2753 I915_WRITE(reg, dspcntr);
2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2766 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 struct drm_plane *primary = crtc->primary;
2774 bool visible = to_intel_plane_state(primary->state)->visible;
2775 struct drm_i915_gem_object *obj;
2776 int plane = intel_crtc->plane;
2777 unsigned long linear_offset;
2779 u32 reg = DSPCNTR(plane);
2782 if (!visible || !fb) {
2784 I915_WRITE(DSPSURF(plane), 0);
2789 obj = intel_fb_obj(fb);
2790 if (WARN_ON(obj == NULL))
2793 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2795 dspcntr = DISPPLANE_GAMMA_ENABLE;
2797 dspcntr |= DISPLAY_PLANE_ENABLE;
2799 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2802 switch (fb->pixel_format) {
2804 dspcntr |= DISPPLANE_8BPP;
2806 case DRM_FORMAT_RGB565:
2807 dspcntr |= DISPPLANE_BGRX565;
2809 case DRM_FORMAT_XRGB8888:
2810 dspcntr |= DISPPLANE_BGRX888;
2812 case DRM_FORMAT_XBGR8888:
2813 dspcntr |= DISPPLANE_RGBX888;
2815 case DRM_FORMAT_XRGB2101010:
2816 dspcntr |= DISPPLANE_BGRX101010;
2818 case DRM_FORMAT_XBGR2101010:
2819 dspcntr |= DISPPLANE_RGBX101010;
2825 if (obj->tiling_mode != I915_TILING_NONE)
2826 dspcntr |= DISPPLANE_TILED;
2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2829 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2831 linear_offset = y * fb->pitches[0] + x * pixel_size;
2832 intel_crtc->dspaddr_offset =
2833 intel_gen4_compute_page_offset(dev_priv,
2834 &x, &y, obj->tiling_mode,
2837 linear_offset -= intel_crtc->dspaddr_offset;
2838 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2839 dspcntr |= DISPPLANE_ROTATE_180;
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2842 x += (intel_crtc->config->pipe_src_w - 1);
2843 y += (intel_crtc->config->pipe_src_h - 1);
2845 /* Finding the last pixel of the last line of the display
2846 data and adding to linear_offset*/
2848 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2849 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2853 I915_WRITE(reg, dspcntr);
2855 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2856 I915_WRITE(DSPSURF(plane),
2857 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2858 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2859 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2861 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2862 I915_WRITE(DSPLINOFF(plane), linear_offset);
2867 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2868 uint32_t pixel_format)
2870 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2873 * The stride is either expressed as a multiple of 64 bytes
2874 * chunks for linear buffers or in number of tiles for tiled
2877 switch (fb_modifier) {
2878 case DRM_FORMAT_MOD_NONE:
2880 case I915_FORMAT_MOD_X_TILED:
2881 if (INTEL_INFO(dev)->gen == 2)
2884 case I915_FORMAT_MOD_Y_TILED:
2885 /* No need to check for old gens and Y tiling since this is
2886 * about the display engine and those will be blocked before
2890 case I915_FORMAT_MOD_Yf_TILED:
2891 if (bits_per_pixel == 8)
2896 MISSING_CASE(fb_modifier);
2901 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2902 struct drm_i915_gem_object *obj)
2904 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2906 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2907 view = &i915_ggtt_view_rotated;
2909 return i915_gem_obj_ggtt_offset_view(obj, view);
2913 * This function detaches (aka. unbinds) unused scalers in hardware
2915 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2917 struct drm_device *dev;
2918 struct drm_i915_private *dev_priv;
2919 struct intel_crtc_scaler_state *scaler_state;
2922 dev = intel_crtc->base.dev;
2923 dev_priv = dev->dev_private;
2924 scaler_state = &intel_crtc->config->scaler_state;
2926 /* loop through and disable scalers that aren't in use */
2927 for (i = 0; i < intel_crtc->num_scalers; i++) {
2928 if (!scaler_state->scalers[i].in_use) {
2929 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2930 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2931 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2932 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2933 intel_crtc->base.base.id, intel_crtc->pipe, i);
2938 u32 skl_plane_ctl_format(uint32_t pixel_format)
2940 switch (pixel_format) {
2942 return PLANE_CTL_FORMAT_INDEXED;
2943 case DRM_FORMAT_RGB565:
2944 return PLANE_CTL_FORMAT_RGB_565;
2945 case DRM_FORMAT_XBGR8888:
2946 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2947 case DRM_FORMAT_XRGB8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888;
2950 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2951 * to be already pre-multiplied. We need to add a knob (or a different
2952 * DRM_FORMAT) for user-space to configure that.
2954 case DRM_FORMAT_ABGR8888:
2955 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2957 case DRM_FORMAT_ARGB8888:
2958 return PLANE_CTL_FORMAT_XRGB_8888 |
2959 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2960 case DRM_FORMAT_XRGB2101010:
2961 return PLANE_CTL_FORMAT_XRGB_2101010;
2962 case DRM_FORMAT_XBGR2101010:
2963 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2964 case DRM_FORMAT_YUYV:
2965 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2966 case DRM_FORMAT_YVYU:
2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2968 case DRM_FORMAT_UYVY:
2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2970 case DRM_FORMAT_VYUY:
2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2973 MISSING_CASE(pixel_format);
2979 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2981 switch (fb_modifier) {
2982 case DRM_FORMAT_MOD_NONE:
2984 case I915_FORMAT_MOD_X_TILED:
2985 return PLANE_CTL_TILED_X;
2986 case I915_FORMAT_MOD_Y_TILED:
2987 return PLANE_CTL_TILED_Y;
2988 case I915_FORMAT_MOD_Yf_TILED:
2989 return PLANE_CTL_TILED_YF;
2991 MISSING_CASE(fb_modifier);
2997 u32 skl_plane_ctl_rotation(unsigned int rotation)
3000 case BIT(DRM_ROTATE_0):
3003 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3004 * while i915 HW rotation is clockwise, thats why this swapping.
3006 case BIT(DRM_ROTATE_90):
3007 return PLANE_CTL_ROTATE_270;
3008 case BIT(DRM_ROTATE_180):
3009 return PLANE_CTL_ROTATE_180;
3010 case BIT(DRM_ROTATE_270):
3011 return PLANE_CTL_ROTATE_90;
3013 MISSING_CASE(rotation);
3019 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3020 struct drm_framebuffer *fb,
3023 struct drm_device *dev = crtc->dev;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3026 struct drm_plane *plane = crtc->primary;
3027 bool visible = to_intel_plane_state(plane->state)->visible;
3028 struct drm_i915_gem_object *obj;
3029 int pipe = intel_crtc->pipe;
3030 u32 plane_ctl, stride_div, stride;
3031 u32 tile_height, plane_offset, plane_size;
3032 unsigned int rotation;
3033 int x_offset, y_offset;
3034 unsigned long surf_addr;
3035 struct intel_crtc_state *crtc_state = intel_crtc->config;
3036 struct intel_plane_state *plane_state;
3037 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3038 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3041 plane_state = to_intel_plane_state(plane->state);
3043 if (!visible || !fb) {
3044 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3045 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3046 POSTING_READ(PLANE_CTL(pipe, 0));
3050 plane_ctl = PLANE_CTL_ENABLE |
3051 PLANE_CTL_PIPE_GAMMA_ENABLE |
3052 PLANE_CTL_PIPE_CSC_ENABLE;
3054 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3055 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3056 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3058 rotation = plane->state->rotation;
3059 plane_ctl |= skl_plane_ctl_rotation(rotation);
3061 obj = intel_fb_obj(fb);
3062 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3064 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3067 * FIXME: intel_plane_state->src, dst aren't set when transitional
3068 * update_plane helpers are called from legacy paths.
3069 * Once full atomic crtc is available, below check can be avoided.
3071 if (drm_rect_width(&plane_state->src)) {
3072 scaler_id = plane_state->scaler_id;
3073 src_x = plane_state->src.x1 >> 16;
3074 src_y = plane_state->src.y1 >> 16;
3075 src_w = drm_rect_width(&plane_state->src) >> 16;
3076 src_h = drm_rect_height(&plane_state->src) >> 16;
3077 dst_x = plane_state->dst.x1;
3078 dst_y = plane_state->dst.y1;
3079 dst_w = drm_rect_width(&plane_state->dst);
3080 dst_h = drm_rect_height(&plane_state->dst);
3082 WARN_ON(x != src_x || y != src_y);
3084 src_w = intel_crtc->config->pipe_src_w;
3085 src_h = intel_crtc->config->pipe_src_h;
3088 if (intel_rotation_90_or_270(rotation)) {
3089 /* stride = Surface height in tiles */
3090 tile_height = intel_tile_height(dev, fb->pixel_format,
3092 stride = DIV_ROUND_UP(fb->height, tile_height);
3093 x_offset = stride * tile_height - y - src_h;
3095 plane_size = (src_w - 1) << 16 | (src_h - 1);
3097 stride = fb->pitches[0] / stride_div;
3100 plane_size = (src_h - 1) << 16 | (src_w - 1);
3102 plane_offset = y_offset << 16 | x_offset;
3104 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3105 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3106 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3107 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3109 if (scaler_id >= 0) {
3110 uint32_t ps_ctrl = 0;
3112 WARN_ON(!dst_w || !dst_h);
3113 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3114 crtc_state->scaler_state.scalers[scaler_id].mode;
3115 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3116 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3117 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3118 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3119 I915_WRITE(PLANE_POS(pipe, 0), 0);
3121 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3124 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3126 POSTING_READ(PLANE_SURF(pipe, 0));
3129 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3131 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3132 int x, int y, enum mode_set_atomic state)
3134 struct drm_device *dev = crtc->dev;
3135 struct drm_i915_private *dev_priv = dev->dev_private;
3137 if (dev_priv->display.disable_fbc)
3138 dev_priv->display.disable_fbc(dev);
3140 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3145 static void intel_complete_page_flips(struct drm_device *dev)
3147 struct drm_crtc *crtc;
3149 for_each_crtc(dev, crtc) {
3150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3151 enum plane plane = intel_crtc->plane;
3153 intel_prepare_page_flip(dev, plane);
3154 intel_finish_page_flip_plane(dev, plane);
3158 static void intel_update_primary_planes(struct drm_device *dev)
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 struct drm_crtc *crtc;
3163 for_each_crtc(dev, crtc) {
3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3166 drm_modeset_lock(&crtc->mutex, NULL);
3168 * FIXME: Once we have proper support for primary planes (and
3169 * disabling them without disabling the entire crtc) allow again
3170 * a NULL crtc->primary->fb.
3172 if (intel_crtc->active && crtc->primary->fb)
3173 dev_priv->display.update_primary_plane(crtc,
3177 drm_modeset_unlock(&crtc->mutex);
3181 void intel_prepare_reset(struct drm_device *dev)
3183 /* no reset support for gen2 */
3187 /* reset doesn't touch the display */
3188 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3191 drm_modeset_lock_all(dev);
3193 * Disabling the crtcs gracefully seems nicer. Also the
3194 * g33 docs say we should at least disable all the planes.
3196 intel_display_suspend(dev);
3199 void intel_finish_reset(struct drm_device *dev)
3201 struct drm_i915_private *dev_priv = to_i915(dev);
3204 * Flips in the rings will be nuked by the reset,
3205 * so complete all pending flips so that user space
3206 * will get its events and not get stuck.
3208 intel_complete_page_flips(dev);
3210 /* no reset support for gen2 */
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3217 * Flips in the rings have been nuked by the reset,
3218 * so update the base address of all primary
3219 * planes to the the last fb to make sure we're
3220 * showing the correct fb after a reset.
3222 intel_update_primary_planes(dev);
3227 * The display has been reset as well,
3228 * so need a full re-initialization.
3230 intel_runtime_pm_disable_interrupts(dev_priv);
3231 intel_runtime_pm_enable_interrupts(dev_priv);
3233 intel_modeset_init_hw(dev);
3235 spin_lock_irq(&dev_priv->irq_lock);
3236 if (dev_priv->display.hpd_irq_setup)
3237 dev_priv->display.hpd_irq_setup(dev);
3238 spin_unlock_irq(&dev_priv->irq_lock);
3240 intel_modeset_setup_hw_state(dev, true);
3242 intel_hpd_init(dev_priv);
3244 drm_modeset_unlock_all(dev);
3248 intel_finish_fb(struct drm_framebuffer *old_fb)
3250 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3251 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3252 bool was_interruptible = dev_priv->mm.interruptible;
3255 /* Big Hammer, we also need to ensure that any pending
3256 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3257 * current scanout is retired before unpinning the old
3258 * framebuffer. Note that we rely on userspace rendering
3259 * into the buffer attached to the pipe they are waiting
3260 * on. If not, userspace generates a GPU hang with IPEHR
3261 * point to the MI_WAIT_FOR_EVENT.
3263 * This should only fail upon a hung GPU, in which case we
3264 * can safely continue.
3266 dev_priv->mm.interruptible = false;
3267 ret = i915_gem_object_wait_rendering(obj, true);
3268 dev_priv->mm.interruptible = was_interruptible;
3273 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3281 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3284 spin_lock_irq(&dev->event_lock);
3285 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3286 spin_unlock_irq(&dev->event_lock);
3291 static void intel_update_pipe_size(struct intel_crtc *crtc)
3293 struct drm_device *dev = crtc->base.dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 const struct drm_display_mode *adjusted_mode;
3301 * Update pipe size and adjust fitter if needed: the reason for this is
3302 * that in compute_mode_changes we check the native mode (not the pfit
3303 * mode) to see if we can flip rather than do a full mode set. In the
3304 * fastboot case, we'll flip, but if we don't update the pipesrc and
3305 * pfit state, we'll end up with a big fb scanned out into the wrong
3308 * To fix this properly, we need to hoist the checks up into
3309 * compute_mode_changes (or above), check the actual pfit state and
3310 * whether the platform allows pfit disable with pipe active, and only
3311 * then update the pipesrc and pfit state, even on the flip path.
3314 adjusted_mode = &crtc->config->base.adjusted_mode;
3316 I915_WRITE(PIPESRC(crtc->pipe),
3317 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3318 (adjusted_mode->crtc_vdisplay - 1));
3319 if (!crtc->config->pch_pfit.enabled &&
3320 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3321 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3322 I915_WRITE(PF_CTL(crtc->pipe), 0);
3323 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3324 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3326 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3327 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3330 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3332 struct drm_device *dev = crtc->dev;
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335 int pipe = intel_crtc->pipe;
3338 /* enable normal train */
3339 reg = FDI_TX_CTL(pipe);
3340 temp = I915_READ(reg);
3341 if (IS_IVYBRIDGE(dev)) {
3342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3348 I915_WRITE(reg, temp);
3350 reg = FDI_RX_CTL(pipe);
3351 temp = I915_READ(reg);
3352 if (HAS_PCH_CPT(dev)) {
3353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3356 temp &= ~FDI_LINK_TRAIN_NONE;
3357 temp |= FDI_LINK_TRAIN_NONE;
3359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3361 /* wait one idle pattern time */
3365 /* IVB wants error correction enabled */
3366 if (IS_IVYBRIDGE(dev))
3367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3368 FDI_FE_ERRC_ENABLE);
3371 /* The FDI link training functions for ILK/Ibexpeak. */
3372 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377 int pipe = intel_crtc->pipe;
3378 u32 reg, temp, tries;
3380 /* FDI needs bits from pipe first */
3381 assert_pipe_enabled(dev_priv, pipe);
3383 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3385 reg = FDI_RX_IMR(pipe);
3386 temp = I915_READ(reg);
3387 temp &= ~FDI_RX_SYMBOL_LOCK;
3388 temp &= ~FDI_RX_BIT_LOCK;
3389 I915_WRITE(reg, temp);
3393 /* enable CPU FDI TX and PCH FDI RX */
3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
3396 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3397 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3398 temp &= ~FDI_LINK_TRAIN_NONE;
3399 temp |= FDI_LINK_TRAIN_PATTERN_1;
3400 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3402 reg = FDI_RX_CTL(pipe);
3403 temp = I915_READ(reg);
3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
3406 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3411 /* Ironlake workaround, enable clock pointer after FDI enable*/
3412 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3413 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3414 FDI_RX_PHASE_SYNC_POINTER_EN);
3416 reg = FDI_RX_IIR(pipe);
3417 for (tries = 0; tries < 5; tries++) {
3418 temp = I915_READ(reg);
3419 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421 if ((temp & FDI_RX_BIT_LOCK)) {
3422 DRM_DEBUG_KMS("FDI train 1 done.\n");
3423 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3428 DRM_ERROR("FDI train 1 fail!\n");
3431 reg = FDI_TX_CTL(pipe);
3432 temp = I915_READ(reg);
3433 temp &= ~FDI_LINK_TRAIN_NONE;
3434 temp |= FDI_LINK_TRAIN_PATTERN_2;
3435 I915_WRITE(reg, temp);
3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
3441 I915_WRITE(reg, temp);
3446 reg = FDI_RX_IIR(pipe);
3447 for (tries = 0; tries < 5; tries++) {
3448 temp = I915_READ(reg);
3449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3451 if (temp & FDI_RX_SYMBOL_LOCK) {
3452 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3453 DRM_DEBUG_KMS("FDI train 2 done.\n");
3458 DRM_ERROR("FDI train 2 fail!\n");
3460 DRM_DEBUG_KMS("FDI train done\n");
3464 static const int snb_b_fdi_train_param[] = {
3465 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3466 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3467 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3468 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3471 /* The FDI link training functions for SNB/Cougarpoint. */
3472 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477 int pipe = intel_crtc->pipe;
3478 u32 reg, temp, i, retry;
3480 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3482 reg = FDI_RX_IMR(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~FDI_RX_SYMBOL_LOCK;
3485 temp &= ~FDI_RX_BIT_LOCK;
3486 I915_WRITE(reg, temp);
3491 /* enable CPU FDI TX and PCH FDI RX */
3492 reg = FDI_TX_CTL(pipe);
3493 temp = I915_READ(reg);
3494 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3495 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3496 temp &= ~FDI_LINK_TRAIN_NONE;
3497 temp |= FDI_LINK_TRAIN_PATTERN_1;
3498 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3500 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3501 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3503 I915_WRITE(FDI_RX_MISC(pipe),
3504 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3506 reg = FDI_RX_CTL(pipe);
3507 temp = I915_READ(reg);
3508 if (HAS_PCH_CPT(dev)) {
3509 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1;
3515 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3520 for (i = 0; i < 4; i++) {
3521 reg = FDI_TX_CTL(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3524 temp |= snb_b_fdi_train_param[i];
3525 I915_WRITE(reg, temp);
3530 for (retry = 0; retry < 5; retry++) {
3531 reg = FDI_RX_IIR(pipe);
3532 temp = I915_READ(reg);
3533 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3534 if (temp & FDI_RX_BIT_LOCK) {
3535 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3536 DRM_DEBUG_KMS("FDI train 1 done.\n");
3545 DRM_ERROR("FDI train 1 fail!\n");
3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
3550 temp &= ~FDI_LINK_TRAIN_NONE;
3551 temp |= FDI_LINK_TRAIN_PATTERN_2;
3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3557 I915_WRITE(reg, temp);
3559 reg = FDI_RX_CTL(pipe);
3560 temp = I915_READ(reg);
3561 if (HAS_PCH_CPT(dev)) {
3562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_2;
3568 I915_WRITE(reg, temp);
3573 for (i = 0; i < 4; i++) {
3574 reg = FDI_TX_CTL(pipe);
3575 temp = I915_READ(reg);
3576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577 temp |= snb_b_fdi_train_param[i];
3578 I915_WRITE(reg, temp);
3583 for (retry = 0; retry < 5; retry++) {
3584 reg = FDI_RX_IIR(pipe);
3585 temp = I915_READ(reg);
3586 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3587 if (temp & FDI_RX_SYMBOL_LOCK) {
3588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3589 DRM_DEBUG_KMS("FDI train 2 done.\n");
3598 DRM_ERROR("FDI train 2 fail!\n");
3600 DRM_DEBUG_KMS("FDI train done.\n");
3603 /* Manual link training for Ivy Bridge A0 parts */
3604 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609 int pipe = intel_crtc->pipe;
3610 u32 reg, temp, i, j;
3612 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3614 reg = FDI_RX_IMR(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~FDI_RX_SYMBOL_LOCK;
3617 temp &= ~FDI_RX_BIT_LOCK;
3618 I915_WRITE(reg, temp);
3623 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3624 I915_READ(FDI_RX_IIR(pipe)));
3626 /* Try each vswing and preemphasis setting twice before moving on */
3627 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3628 /* disable first in case we need to retry */
3629 reg = FDI_TX_CTL(pipe);
3630 temp = I915_READ(reg);
3631 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3632 temp &= ~FDI_TX_ENABLE;
3633 I915_WRITE(reg, temp);
3635 reg = FDI_RX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_LINK_TRAIN_AUTO;
3638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3639 temp &= ~FDI_RX_ENABLE;
3640 I915_WRITE(reg, temp);
3642 /* enable CPU FDI TX and PCH FDI RX */
3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3646 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3647 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3649 temp |= snb_b_fdi_train_param[j/2];
3650 temp |= FDI_COMPOSITE_SYNC;
3651 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3653 I915_WRITE(FDI_RX_MISC(pipe),
3654 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3656 reg = FDI_RX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3659 temp |= FDI_COMPOSITE_SYNC;
3660 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3663 udelay(1); /* should be 0.5us */
3665 for (i = 0; i < 4; i++) {
3666 reg = FDI_RX_IIR(pipe);
3667 temp = I915_READ(reg);
3668 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3670 if (temp & FDI_RX_BIT_LOCK ||
3671 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3672 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3673 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3677 udelay(1); /* should be 0.5us */
3680 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3685 reg = FDI_TX_CTL(pipe);
3686 temp = I915_READ(reg);
3687 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3688 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3689 I915_WRITE(reg, temp);
3691 reg = FDI_RX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3695 I915_WRITE(reg, temp);
3698 udelay(2); /* should be 1.5us */
3700 for (i = 0; i < 4; i++) {
3701 reg = FDI_RX_IIR(pipe);
3702 temp = I915_READ(reg);
3703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3705 if (temp & FDI_RX_SYMBOL_LOCK ||
3706 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3708 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3712 udelay(2); /* should be 1.5us */
3715 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3719 DRM_DEBUG_KMS("FDI train done.\n");
3722 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3724 struct drm_device *dev = intel_crtc->base.dev;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 int pipe = intel_crtc->pipe;
3730 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3731 reg = FDI_RX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3734 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3735 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3736 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3741 /* Switch from Rawclk to PCDclk */
3742 temp = I915_READ(reg);
3743 I915_WRITE(reg, temp | FDI_PCDCLK);
3748 /* Enable CPU FDI TX PLL, always on for Ironlake */
3749 reg = FDI_TX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3752 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3759 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3761 struct drm_device *dev = intel_crtc->base.dev;
3762 struct drm_i915_private *dev_priv = dev->dev_private;
3763 int pipe = intel_crtc->pipe;
3766 /* Switch from PCDclk to Rawclk */
3767 reg = FDI_RX_CTL(pipe);
3768 temp = I915_READ(reg);
3769 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3771 /* Disable CPU FDI TX PLL */
3772 reg = FDI_TX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3779 reg = FDI_RX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3783 /* Wait for the clocks to turn off. */
3788 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3793 int pipe = intel_crtc->pipe;
3796 /* disable CPU FDI tx and PCH FDI rx */
3797 reg = FDI_TX_CTL(pipe);
3798 temp = I915_READ(reg);
3799 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 temp &= ~(0x7 << 16);
3805 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3806 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3811 /* Ironlake workaround, disable clock pointer after downing FDI */
3812 if (HAS_PCH_IBX(dev))
3813 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3815 /* still set train pattern 1 */
3816 reg = FDI_TX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 temp &= ~FDI_LINK_TRAIN_NONE;
3819 temp |= FDI_LINK_TRAIN_PATTERN_1;
3820 I915_WRITE(reg, temp);
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 if (HAS_PCH_CPT(dev)) {
3825 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3826 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3828 temp &= ~FDI_LINK_TRAIN_NONE;
3829 temp |= FDI_LINK_TRAIN_PATTERN_1;
3831 /* BPC in FDI rx is consistent with that in PIPECONF */
3832 temp &= ~(0x07 << 16);
3833 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3834 I915_WRITE(reg, temp);
3840 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3842 struct intel_crtc *crtc;
3844 /* Note that we don't need to be called with mode_config.lock here
3845 * as our list of CRTC objects is static for the lifetime of the
3846 * device and so cannot disappear as we iterate. Similarly, we can
3847 * happily treat the predicates as racy, atomic checks as userspace
3848 * cannot claim and pin a new fb without at least acquring the
3849 * struct_mutex and so serialising with us.
3851 for_each_intel_crtc(dev, crtc) {
3852 if (atomic_read(&crtc->unpin_work_count) == 0)
3855 if (crtc->unpin_work)
3856 intel_wait_for_vblank(dev, crtc->pipe);
3864 static void page_flip_completed(struct intel_crtc *intel_crtc)
3866 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3867 struct intel_unpin_work *work = intel_crtc->unpin_work;
3869 /* ensure that the unpin work is consistent wrt ->pending. */
3871 intel_crtc->unpin_work = NULL;
3874 drm_send_vblank_event(intel_crtc->base.dev,
3878 drm_crtc_vblank_put(&intel_crtc->base);
3880 wake_up_all(&dev_priv->pending_flip_queue);
3881 queue_work(dev_priv->wq, &work->work);
3883 trace_i915_flip_complete(intel_crtc->plane,
3884 work->pending_flip_obj);
3887 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3889 struct drm_device *dev = crtc->dev;
3890 struct drm_i915_private *dev_priv = dev->dev_private;
3892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3893 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3894 !intel_crtc_has_pending_flip(crtc),
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3898 spin_lock_irq(&dev->event_lock);
3899 if (intel_crtc->unpin_work) {
3900 WARN_ONCE(1, "Removing stuck page flip\n");
3901 page_flip_completed(intel_crtc);
3903 spin_unlock_irq(&dev->event_lock);
3906 if (crtc->primary->fb) {
3907 mutex_lock(&dev->struct_mutex);
3908 intel_finish_fb(crtc->primary->fb);
3909 mutex_unlock(&dev->struct_mutex);
3913 /* Program iCLKIP clock to the desired frequency */
3914 static void lpt_program_iclkip(struct drm_crtc *crtc)
3916 struct drm_device *dev = crtc->dev;
3917 struct drm_i915_private *dev_priv = dev->dev_private;
3918 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3919 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3922 mutex_lock(&dev_priv->sb_lock);
3924 /* It is necessary to ungate the pixclk gate prior to programming
3925 * the divisors, and gate it back when it is done.
3927 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3929 /* Disable SSCCTL */
3930 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3931 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3935 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3936 if (clock == 20000) {
3941 /* The iCLK virtual clock root frequency is in MHz,
3942 * but the adjusted_mode->crtc_clock in in KHz. To get the
3943 * divisors, it is necessary to divide one by another, so we
3944 * convert the virtual clock precision to KHz here for higher
3947 u32 iclk_virtual_root_freq = 172800 * 1000;
3948 u32 iclk_pi_range = 64;
3949 u32 desired_divisor, msb_divisor_value, pi_value;
3951 desired_divisor = (iclk_virtual_root_freq / clock);
3952 msb_divisor_value = desired_divisor / iclk_pi_range;
3953 pi_value = desired_divisor % iclk_pi_range;
3956 divsel = msb_divisor_value - 2;
3957 phaseinc = pi_value;
3960 /* This should not happen with any sane values */
3961 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3962 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3963 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3964 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3966 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3973 /* Program SSCDIVINTPHASE6 */
3974 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3975 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3976 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3977 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3978 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3979 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3980 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3981 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3983 /* Program SSCAUXDIV */
3984 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3985 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3986 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3987 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3989 /* Enable modulator and associated divider */
3990 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3991 temp &= ~SBI_SSCCTL_DISABLE;
3992 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3994 /* Wait for initialization time */
3997 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3999 mutex_unlock(&dev_priv->sb_lock);
4002 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4003 enum pipe pch_transcoder)
4005 struct drm_device *dev = crtc->base.dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
4007 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4009 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4010 I915_READ(HTOTAL(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4012 I915_READ(HBLANK(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4014 I915_READ(HSYNC(cpu_transcoder)));
4016 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4017 I915_READ(VTOTAL(cpu_transcoder)));
4018 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4019 I915_READ(VBLANK(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4021 I915_READ(VSYNC(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4023 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4026 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4031 temp = I915_READ(SOUTH_CHICKEN1);
4032 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4035 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4036 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4038 temp &= ~FDI_BC_BIFURCATION_SELECT;
4040 temp |= FDI_BC_BIFURCATION_SELECT;
4042 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4043 I915_WRITE(SOUTH_CHICKEN1, temp);
4044 POSTING_READ(SOUTH_CHICKEN1);
4047 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4049 struct drm_device *dev = intel_crtc->base.dev;
4051 switch (intel_crtc->pipe) {
4055 if (intel_crtc->config->fdi_lanes > 2)
4056 cpt_set_fdi_bc_bifurcation(dev, false);
4058 cpt_set_fdi_bc_bifurcation(dev, true);
4062 cpt_set_fdi_bc_bifurcation(dev, true);
4071 * Enable PCH resources required for PCH ports:
4073 * - FDI training & RX/TX
4074 * - update transcoder timings
4075 * - DP transcoding bits
4078 static void ironlake_pch_enable(struct drm_crtc *crtc)
4080 struct drm_device *dev = crtc->dev;
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4083 int pipe = intel_crtc->pipe;
4086 assert_pch_transcoder_disabled(dev_priv, pipe);
4088 if (IS_IVYBRIDGE(dev))
4089 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4091 /* Write the TU size bits before fdi link training, so that error
4092 * detection works. */
4093 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4094 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4096 /* For PCH output, training FDI link */
4097 dev_priv->display.fdi_link_train(crtc);
4099 /* We need to program the right clock selection before writing the pixel
4100 * mutliplier into the DPLL. */
4101 if (HAS_PCH_CPT(dev)) {
4104 temp = I915_READ(PCH_DPLL_SEL);
4105 temp |= TRANS_DPLL_ENABLE(pipe);
4106 sel = TRANS_DPLLB_SEL(pipe);
4107 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4111 I915_WRITE(PCH_DPLL_SEL, temp);
4114 /* XXX: pch pll's can be enabled any time before we enable the PCH
4115 * transcoder, and we actually should do this to not upset any PCH
4116 * transcoder that already use the clock when we share it.
4118 * Note that enable_shared_dpll tries to do the right thing, but
4119 * get_shared_dpll unconditionally resets the pll - we need that to have
4120 * the right LVDS enable sequence. */
4121 intel_enable_shared_dpll(intel_crtc);
4123 /* set transcoder timing, panel must allow it */
4124 assert_panel_unlocked(dev_priv, pipe);
4125 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4127 intel_fdi_normal_train(crtc);
4129 /* For PCH DP, enable TRANS_DP_CTL */
4130 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4131 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4132 reg = TRANS_DP_CTL(pipe);
4133 temp = I915_READ(reg);
4134 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4135 TRANS_DP_SYNC_MASK |
4137 temp |= TRANS_DP_OUTPUT_ENABLE;
4138 temp |= bpc << 9; /* same format but at 11:9 */
4140 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4141 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4142 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4143 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4145 switch (intel_trans_dp_port_sel(crtc)) {
4147 temp |= TRANS_DP_PORT_SEL_B;
4150 temp |= TRANS_DP_PORT_SEL_C;
4153 temp |= TRANS_DP_PORT_SEL_D;
4159 I915_WRITE(reg, temp);
4162 ironlake_enable_pch_transcoder(dev_priv, pipe);
4165 static void lpt_pch_enable(struct drm_crtc *crtc)
4167 struct drm_device *dev = crtc->dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4170 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4172 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4174 lpt_program_iclkip(crtc);
4176 /* Set transcoder timing. */
4177 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4179 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4182 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4183 struct intel_crtc_state *crtc_state)
4185 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4186 struct intel_shared_dpll *pll;
4187 struct intel_shared_dpll_config *shared_dpll;
4188 enum intel_dpll_id i;
4190 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4192 if (HAS_PCH_IBX(dev_priv->dev)) {
4193 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4194 i = (enum intel_dpll_id) crtc->pipe;
4195 pll = &dev_priv->shared_dplls[i];
4197 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4198 crtc->base.base.id, pll->name);
4200 WARN_ON(shared_dpll[i].crtc_mask);
4205 if (IS_BROXTON(dev_priv->dev)) {
4206 /* PLL is attached to port in bxt */
4207 struct intel_encoder *encoder;
4208 struct intel_digital_port *intel_dig_port;
4210 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4211 if (WARN_ON(!encoder))
4214 intel_dig_port = enc_to_dig_port(&encoder->base);
4215 /* 1:1 mapping between ports and PLLs */
4216 i = (enum intel_dpll_id)intel_dig_port->port;
4217 pll = &dev_priv->shared_dplls[i];
4218 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4219 crtc->base.base.id, pll->name);
4220 WARN_ON(shared_dpll[i].crtc_mask);
4225 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4226 pll = &dev_priv->shared_dplls[i];
4228 /* Only want to check enabled timings first */
4229 if (shared_dpll[i].crtc_mask == 0)
4232 if (memcmp(&crtc_state->dpll_hw_state,
4233 &shared_dpll[i].hw_state,
4234 sizeof(crtc_state->dpll_hw_state)) == 0) {
4235 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4236 crtc->base.base.id, pll->name,
4237 shared_dpll[i].crtc_mask,
4243 /* Ok no matching timings, maybe there's a free one? */
4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
4246 if (shared_dpll[i].crtc_mask == 0) {
4247 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4248 crtc->base.base.id, pll->name);
4256 if (shared_dpll[i].crtc_mask == 0)
4257 shared_dpll[i].hw_state =
4258 crtc_state->dpll_hw_state;
4260 crtc_state->shared_dpll = i;
4261 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4262 pipe_name(crtc->pipe));
4264 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4269 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4271 struct drm_i915_private *dev_priv = to_i915(state->dev);
4272 struct intel_shared_dpll_config *shared_dpll;
4273 struct intel_shared_dpll *pll;
4274 enum intel_dpll_id i;
4276 if (!to_intel_atomic_state(state)->dpll_set)
4279 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4280 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4281 pll = &dev_priv->shared_dplls[i];
4282 pll->config = shared_dpll[i];
4286 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4288 struct drm_i915_private *dev_priv = dev->dev_private;
4289 int dslreg = PIPEDSL(pipe);
4292 temp = I915_READ(dslreg);
4294 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4295 if (wait_for(I915_READ(dslreg) != temp, 5))
4296 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4301 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4302 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4303 int src_w, int src_h, int dst_w, int dst_h)
4305 struct intel_crtc_scaler_state *scaler_state =
4306 &crtc_state->scaler_state;
4307 struct intel_crtc *intel_crtc =
4308 to_intel_crtc(crtc_state->base.crtc);
4311 need_scaling = intel_rotation_90_or_270(rotation) ?
4312 (src_h != dst_w || src_w != dst_h):
4313 (src_w != dst_w || src_h != dst_h);
4316 * if plane is being disabled or scaler is no more required or force detach
4317 * - free scaler binded to this plane/crtc
4318 * - in order to do this, update crtc->scaler_usage
4320 * Here scaler state in crtc_state is set free so that
4321 * scaler can be assigned to other user. Actual register
4322 * update to free the scaler is done in plane/panel-fit programming.
4323 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4325 if (force_detach || !need_scaling) {
4326 if (*scaler_id >= 0) {
4327 scaler_state->scaler_users &= ~(1 << scaler_user);
4328 scaler_state->scalers[*scaler_id].in_use = 0;
4330 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4331 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4332 intel_crtc->pipe, scaler_user, *scaler_id,
4333 scaler_state->scaler_users);
4340 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4341 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4343 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4344 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4345 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4346 "size is out of scaler range\n",
4347 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4351 /* mark this plane as a scaler user in crtc_state */
4352 scaler_state->scaler_users |= (1 << scaler_user);
4353 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4354 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4355 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4356 scaler_state->scaler_users);
4362 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4364 * @state: crtc's scaler state
4365 * @force_detach: whether to forcibly disable scaler
4368 * 0 - scaler_usage updated successfully
4369 * error - requested scaling cannot be supported or other error condition
4371 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4373 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4374 struct drm_display_mode *adjusted_mode =
4375 &state->base.adjusted_mode;
4377 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4378 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4380 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4381 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4382 state->pipe_src_w, state->pipe_src_h,
4383 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4387 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4389 * @state: crtc's scaler state
4390 * @plane_state: atomic plane state to update
4393 * 0 - scaler_usage updated successfully
4394 * error - requested scaling cannot be supported or other error condition
4396 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4397 struct intel_plane_state *plane_state)
4400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4401 struct intel_plane *intel_plane =
4402 to_intel_plane(plane_state->base.plane);
4403 struct drm_framebuffer *fb = plane_state->base.fb;
4406 bool force_detach = !fb || !plane_state->visible;
4408 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4409 intel_plane->base.base.id, intel_crtc->pipe,
4410 drm_plane_index(&intel_plane->base));
4412 ret = skl_update_scaler(crtc_state, force_detach,
4413 drm_plane_index(&intel_plane->base),
4414 &plane_state->scaler_id,
4415 plane_state->base.rotation,
4416 drm_rect_width(&plane_state->src) >> 16,
4417 drm_rect_height(&plane_state->src) >> 16,
4418 drm_rect_width(&plane_state->dst),
4419 drm_rect_height(&plane_state->dst));
4421 if (ret || plane_state->scaler_id < 0)
4424 /* check colorkey */
4425 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4426 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4427 intel_plane->base.base.id);
4431 /* Check src format */
4432 switch (fb->pixel_format) {
4433 case DRM_FORMAT_RGB565:
4434 case DRM_FORMAT_XBGR8888:
4435 case DRM_FORMAT_XRGB8888:
4436 case DRM_FORMAT_ABGR8888:
4437 case DRM_FORMAT_ARGB8888:
4438 case DRM_FORMAT_XRGB2101010:
4439 case DRM_FORMAT_XBGR2101010:
4440 case DRM_FORMAT_YUYV:
4441 case DRM_FORMAT_YVYU:
4442 case DRM_FORMAT_UYVY:
4443 case DRM_FORMAT_VYUY:
4446 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4447 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4454 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 int pipe = crtc->pipe;
4459 struct intel_crtc_scaler_state *scaler_state =
4460 &crtc->config->scaler_state;
4462 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4464 /* To update pfit, first update scaler state */
4465 skl_update_scaler_crtc(crtc->config, !enable);
4466 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4467 skl_detach_scalers(crtc);
4471 if (crtc->config->pch_pfit.enabled) {
4474 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4475 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4479 id = scaler_state->scaler_id;
4480 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4481 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4482 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4483 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4485 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4489 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4491 struct drm_device *dev = crtc->base.dev;
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4493 int pipe = crtc->pipe;
4495 if (crtc->config->pch_pfit.enabled) {
4496 /* Force use of hard-coded filter coefficients
4497 * as some pre-programmed values are broken,
4500 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4501 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4502 PF_PIPE_SEL_IVB(pipe));
4504 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4505 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4506 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4510 void hsw_enable_ips(struct intel_crtc *crtc)
4512 struct drm_device *dev = crtc->base.dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4515 if (!crtc->config->ips_enabled)
4518 /* We can only enable IPS after we enable a plane and wait for a vblank */
4519 intel_wait_for_vblank(dev, crtc->pipe);
4521 assert_plane_enabled(dev_priv, crtc->plane);
4522 if (IS_BROADWELL(dev)) {
4523 mutex_lock(&dev_priv->rps.hw_lock);
4524 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4525 mutex_unlock(&dev_priv->rps.hw_lock);
4526 /* Quoting Art Runyan: "its not safe to expect any particular
4527 * value in IPS_CTL bit 31 after enabling IPS through the
4528 * mailbox." Moreover, the mailbox may return a bogus state,
4529 * so we need to just enable it and continue on.
4532 I915_WRITE(IPS_CTL, IPS_ENABLE);
4533 /* The bit only becomes 1 in the next vblank, so this wait here
4534 * is essentially intel_wait_for_vblank. If we don't have this
4535 * and don't wait for vblanks until the end of crtc_enable, then
4536 * the HW state readout code will complain that the expected
4537 * IPS_CTL value is not the one we read. */
4538 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4539 DRM_ERROR("Timed out waiting for IPS enable\n");
4543 void hsw_disable_ips(struct intel_crtc *crtc)
4545 struct drm_device *dev = crtc->base.dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4548 if (!crtc->config->ips_enabled)
4551 assert_plane_enabled(dev_priv, crtc->plane);
4552 if (IS_BROADWELL(dev)) {
4553 mutex_lock(&dev_priv->rps.hw_lock);
4554 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4555 mutex_unlock(&dev_priv->rps.hw_lock);
4556 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4557 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4558 DRM_ERROR("Timed out waiting for IPS disable\n");
4560 I915_WRITE(IPS_CTL, 0);
4561 POSTING_READ(IPS_CTL);
4564 /* We need to wait for a vblank before we can disable the plane. */
4565 intel_wait_for_vblank(dev, crtc->pipe);
4568 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4569 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4571 struct drm_device *dev = crtc->dev;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4574 enum pipe pipe = intel_crtc->pipe;
4575 int palreg = PALETTE(pipe);
4577 bool reenable_ips = false;
4579 /* The clocks have to be on to load the palette. */
4580 if (!crtc->state->active)
4583 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4584 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4585 assert_dsi_pll_enabled(dev_priv);
4587 assert_pll_enabled(dev_priv, pipe);
4590 /* use legacy palette for Ironlake */
4591 if (!HAS_GMCH_DISPLAY(dev))
4592 palreg = LGC_PALETTE(pipe);
4594 /* Workaround : Do not read or write the pipe palette/gamma data while
4595 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4597 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4598 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4599 GAMMA_MODE_MODE_SPLIT)) {
4600 hsw_disable_ips(intel_crtc);
4601 reenable_ips = true;
4604 for (i = 0; i < 256; i++) {
4605 I915_WRITE(palreg + 4 * i,
4606 (intel_crtc->lut_r[i] << 16) |
4607 (intel_crtc->lut_g[i] << 8) |
4608 intel_crtc->lut_b[i]);
4612 hsw_enable_ips(intel_crtc);
4615 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4617 if (intel_crtc->overlay) {
4618 struct drm_device *dev = intel_crtc->base.dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4621 mutex_lock(&dev->struct_mutex);
4622 dev_priv->mm.interruptible = false;
4623 (void) intel_overlay_switch_off(intel_crtc->overlay);
4624 dev_priv->mm.interruptible = true;
4625 mutex_unlock(&dev->struct_mutex);
4628 /* Let userspace switch the overlay on again. In most cases userspace
4629 * has to recompute where to put it anyway.
4634 * intel_post_enable_primary - Perform operations after enabling primary plane
4635 * @crtc: the CRTC whose primary plane was just enabled
4637 * Performs potentially sleeping operations that must be done after the primary
4638 * plane is enabled, such as updating FBC and IPS. Note that this may be
4639 * called due to an explicit primary plane update, or due to an implicit
4640 * re-enable that is caused when a sprite plane is updated to no longer
4641 * completely hide the primary plane.
4644 intel_post_enable_primary(struct drm_crtc *crtc)
4646 struct drm_device *dev = crtc->dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 int pipe = intel_crtc->pipe;
4652 * BDW signals flip done immediately if the plane
4653 * is disabled, even if the plane enable is already
4654 * armed to occur at the next vblank :(
4656 if (IS_BROADWELL(dev))
4657 intel_wait_for_vblank(dev, pipe);
4660 * FIXME IPS should be fine as long as one plane is
4661 * enabled, but in practice it seems to have problems
4662 * when going from primary only to sprite only and vice
4665 hsw_enable_ips(intel_crtc);
4668 * Gen2 reports pipe underruns whenever all planes are disabled.
4669 * So don't enable underrun reporting before at least some planes
4671 * FIXME: Need to fix the logic to work when we turn off all planes
4672 * but leave the pipe running.
4675 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4677 /* Underruns don't raise interrupts, so check manually. */
4678 if (HAS_GMCH_DISPLAY(dev))
4679 i9xx_check_fifo_underruns(dev_priv);
4683 * intel_pre_disable_primary - Perform operations before disabling primary plane
4684 * @crtc: the CRTC whose primary plane is to be disabled
4686 * Performs potentially sleeping operations that must be done before the
4687 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4688 * be called due to an explicit primary plane update, or due to an implicit
4689 * disable that is caused when a sprite plane completely hides the primary
4693 intel_pre_disable_primary(struct drm_crtc *crtc)
4695 struct drm_device *dev = crtc->dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
4701 * Gen2 reports pipe underruns whenever all planes are disabled.
4702 * So diasble underrun reporting before all the planes get disabled.
4703 * FIXME: Need to fix the logic to work when we turn off all planes
4704 * but leave the pipe running.
4707 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4710 * Vblank time updates from the shadow to live plane control register
4711 * are blocked if the memory self-refresh mode is active at that
4712 * moment. So to make sure the plane gets truly disabled, disable
4713 * first the self-refresh mode. The self-refresh enable bit in turn
4714 * will be checked/applied by the HW only at the next frame start
4715 * event which is after the vblank start event, so we need to have a
4716 * wait-for-vblank between disabling the plane and the pipe.
4718 if (HAS_GMCH_DISPLAY(dev)) {
4719 intel_set_memory_cxsr(dev_priv, false);
4720 dev_priv->wm.vlv.cxsr = false;
4721 intel_wait_for_vblank(dev, pipe);
4725 * FIXME IPS should be fine as long as one plane is
4726 * enabled, but in practice it seems to have problems
4727 * when going from primary only to sprite only and vice
4730 hsw_disable_ips(intel_crtc);
4733 static void intel_post_plane_update(struct intel_crtc *crtc)
4735 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4736 struct drm_device *dev = crtc->base.dev;
4737 struct drm_plane *plane;
4739 if (atomic->wait_vblank)
4740 intel_wait_for_vblank(dev, crtc->pipe);
4742 intel_frontbuffer_flip(dev, atomic->fb_bits);
4744 if (atomic->disable_cxsr)
4745 crtc->wm.cxsr_allowed = true;
4747 if (crtc->atomic.update_wm_post)
4748 intel_update_watermarks(&crtc->base);
4750 if (atomic->update_fbc)
4751 intel_fbc_update(dev);
4753 if (atomic->post_enable_primary)
4754 intel_post_enable_primary(&crtc->base);
4756 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4757 intel_update_sprite_watermarks(plane, &crtc->base,
4758 0, 0, 0, false, false);
4760 memset(atomic, 0, sizeof(*atomic));
4763 static void intel_pre_plane_update(struct intel_crtc *crtc)
4765 struct drm_device *dev = crtc->base.dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4768 struct drm_plane *p;
4770 /* Track fb's for any planes being disabled */
4771 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4772 struct intel_plane *plane = to_intel_plane(p);
4774 mutex_lock(&dev->struct_mutex);
4775 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4776 plane->frontbuffer_bit);
4777 mutex_unlock(&dev->struct_mutex);
4780 if (atomic->wait_for_flips)
4781 intel_crtc_wait_for_pending_flips(&crtc->base);
4783 if (atomic->disable_fbc)
4784 intel_fbc_disable_crtc(crtc);
4786 if (crtc->atomic.disable_ips)
4787 hsw_disable_ips(crtc);
4789 if (atomic->pre_disable_primary)
4790 intel_pre_disable_primary(&crtc->base);
4792 if (atomic->disable_cxsr) {
4793 crtc->wm.cxsr_allowed = false;
4794 intel_set_memory_cxsr(dev_priv, false);
4798 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4800 struct drm_device *dev = crtc->dev;
4801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4802 struct drm_plane *p;
4803 int pipe = intel_crtc->pipe;
4805 intel_crtc_dpms_overlay_disable(intel_crtc);
4807 drm_for_each_plane_mask(p, dev, plane_mask)
4808 to_intel_plane(p)->disable_plane(p, crtc);
4811 * FIXME: Once we grow proper nuclear flip support out of this we need
4812 * to compute the mask of flip planes precisely. For the time being
4813 * consider this a flip to a NULL plane.
4815 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4818 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4820 struct drm_device *dev = crtc->dev;
4821 struct drm_i915_private *dev_priv = dev->dev_private;
4822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4823 struct intel_encoder *encoder;
4824 int pipe = intel_crtc->pipe;
4826 if (WARN_ON(intel_crtc->active))
4829 if (intel_crtc->config->has_pch_encoder)
4830 intel_prepare_shared_dpll(intel_crtc);
4832 if (intel_crtc->config->has_dp_encoder)
4833 intel_dp_set_m_n(intel_crtc, M1_N1);
4835 intel_set_pipe_timings(intel_crtc);
4837 if (intel_crtc->config->has_pch_encoder) {
4838 intel_cpu_transcoder_set_m_n(intel_crtc,
4839 &intel_crtc->config->fdi_m_n, NULL);
4842 ironlake_set_pipeconf(crtc);
4844 intel_crtc->active = true;
4846 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4847 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4849 for_each_encoder_on_crtc(dev, crtc, encoder)
4850 if (encoder->pre_enable)
4851 encoder->pre_enable(encoder);
4853 if (intel_crtc->config->has_pch_encoder) {
4854 /* Note: FDI PLL enabling _must_ be done before we enable the
4855 * cpu pipes, hence this is separate from all the other fdi/pch
4857 ironlake_fdi_pll_enable(intel_crtc);
4859 assert_fdi_tx_disabled(dev_priv, pipe);
4860 assert_fdi_rx_disabled(dev_priv, pipe);
4863 ironlake_pfit_enable(intel_crtc);
4866 * On ILK+ LUT must be loaded before the pipe is running but with
4869 intel_crtc_load_lut(crtc);
4871 intel_update_watermarks(crtc);
4872 intel_enable_pipe(intel_crtc);
4874 if (intel_crtc->config->has_pch_encoder)
4875 ironlake_pch_enable(crtc);
4877 assert_vblank_disabled(crtc);
4878 drm_crtc_vblank_on(crtc);
4880 for_each_encoder_on_crtc(dev, crtc, encoder)
4881 encoder->enable(encoder);
4883 if (HAS_PCH_CPT(dev))
4884 cpt_verify_modeset(dev, intel_crtc->pipe);
4887 /* IPS only exists on ULT machines and is tied to pipe A. */
4888 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4890 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4893 static void haswell_crtc_enable(struct drm_crtc *crtc)
4895 struct drm_device *dev = crtc->dev;
4896 struct drm_i915_private *dev_priv = dev->dev_private;
4897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4898 struct intel_encoder *encoder;
4899 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4900 struct intel_crtc_state *pipe_config =
4901 to_intel_crtc_state(crtc->state);
4903 if (WARN_ON(intel_crtc->active))
4906 if (intel_crtc_to_shared_dpll(intel_crtc))
4907 intel_enable_shared_dpll(intel_crtc);
4909 if (intel_crtc->config->has_dp_encoder)
4910 intel_dp_set_m_n(intel_crtc, M1_N1);
4912 intel_set_pipe_timings(intel_crtc);
4914 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4915 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4916 intel_crtc->config->pixel_multiplier - 1);
4919 if (intel_crtc->config->has_pch_encoder) {
4920 intel_cpu_transcoder_set_m_n(intel_crtc,
4921 &intel_crtc->config->fdi_m_n, NULL);
4924 haswell_set_pipeconf(crtc);
4926 intel_set_pipe_csc(crtc);
4928 intel_crtc->active = true;
4930 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4931 for_each_encoder_on_crtc(dev, crtc, encoder)
4932 if (encoder->pre_enable)
4933 encoder->pre_enable(encoder);
4935 if (intel_crtc->config->has_pch_encoder) {
4936 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4938 dev_priv->display.fdi_link_train(crtc);
4941 intel_ddi_enable_pipe_clock(intel_crtc);
4943 if (INTEL_INFO(dev)->gen == 9)
4944 skylake_pfit_update(intel_crtc, 1);
4945 else if (INTEL_INFO(dev)->gen < 9)
4946 ironlake_pfit_enable(intel_crtc);
4948 MISSING_CASE(INTEL_INFO(dev)->gen);
4951 * On ILK+ LUT must be loaded before the pipe is running but with
4954 intel_crtc_load_lut(crtc);
4956 intel_ddi_set_pipe_settings(crtc);
4957 intel_ddi_enable_transcoder_func(crtc);
4959 intel_update_watermarks(crtc);
4960 intel_enable_pipe(intel_crtc);
4962 if (intel_crtc->config->has_pch_encoder)
4963 lpt_pch_enable(crtc);
4965 if (intel_crtc->config->dp_encoder_is_mst)
4966 intel_ddi_set_vc_payload_alloc(crtc, true);
4968 assert_vblank_disabled(crtc);
4969 drm_crtc_vblank_on(crtc);
4971 for_each_encoder_on_crtc(dev, crtc, encoder) {
4972 encoder->enable(encoder);
4973 intel_opregion_notify_encoder(encoder, true);
4976 /* If we change the relative order between pipe/planes enabling, we need
4977 * to change the workaround. */
4978 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4979 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4980 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4981 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4985 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4987 struct drm_device *dev = crtc->base.dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 int pipe = crtc->pipe;
4991 /* To avoid upsetting the power well on haswell only disable the pfit if
4992 * it's in use. The hw state code will make sure we get this right. */
4993 if (crtc->config->pch_pfit.enabled) {
4994 I915_WRITE(PF_CTL(pipe), 0);
4995 I915_WRITE(PF_WIN_POS(pipe), 0);
4996 I915_WRITE(PF_WIN_SZ(pipe), 0);
5000 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5002 struct drm_device *dev = crtc->dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005 struct intel_encoder *encoder;
5006 int pipe = intel_crtc->pipe;
5009 for_each_encoder_on_crtc(dev, crtc, encoder)
5010 encoder->disable(encoder);
5012 drm_crtc_vblank_off(crtc);
5013 assert_vblank_disabled(crtc);
5015 if (intel_crtc->config->has_pch_encoder)
5016 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5018 intel_disable_pipe(intel_crtc);
5020 ironlake_pfit_disable(intel_crtc);
5022 if (intel_crtc->config->has_pch_encoder)
5023 ironlake_fdi_disable(crtc);
5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 if (encoder->post_disable)
5027 encoder->post_disable(encoder);
5029 if (intel_crtc->config->has_pch_encoder) {
5030 ironlake_disable_pch_transcoder(dev_priv, pipe);
5032 if (HAS_PCH_CPT(dev)) {
5033 /* disable TRANS_DP_CTL */
5034 reg = TRANS_DP_CTL(pipe);
5035 temp = I915_READ(reg);
5036 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5037 TRANS_DP_PORT_SEL_MASK);
5038 temp |= TRANS_DP_PORT_SEL_NONE;
5039 I915_WRITE(reg, temp);
5041 /* disable DPLL_SEL */
5042 temp = I915_READ(PCH_DPLL_SEL);
5043 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5044 I915_WRITE(PCH_DPLL_SEL, temp);
5047 ironlake_fdi_pll_disable(intel_crtc);
5051 static void haswell_crtc_disable(struct drm_crtc *crtc)
5053 struct drm_device *dev = crtc->dev;
5054 struct drm_i915_private *dev_priv = dev->dev_private;
5055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5056 struct intel_encoder *encoder;
5057 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5059 for_each_encoder_on_crtc(dev, crtc, encoder) {
5060 intel_opregion_notify_encoder(encoder, false);
5061 encoder->disable(encoder);
5064 drm_crtc_vblank_off(crtc);
5065 assert_vblank_disabled(crtc);
5067 if (intel_crtc->config->has_pch_encoder)
5068 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5070 intel_disable_pipe(intel_crtc);
5072 if (intel_crtc->config->dp_encoder_is_mst)
5073 intel_ddi_set_vc_payload_alloc(crtc, false);
5075 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5077 if (INTEL_INFO(dev)->gen == 9)
5078 skylake_pfit_update(intel_crtc, 0);
5079 else if (INTEL_INFO(dev)->gen < 9)
5080 ironlake_pfit_disable(intel_crtc);
5082 MISSING_CASE(INTEL_INFO(dev)->gen);
5084 intel_ddi_disable_pipe_clock(intel_crtc);
5086 if (intel_crtc->config->has_pch_encoder) {
5087 lpt_disable_pch_transcoder(dev_priv);
5088 intel_ddi_fdi_disable(crtc);
5091 for_each_encoder_on_crtc(dev, crtc, encoder)
5092 if (encoder->post_disable)
5093 encoder->post_disable(encoder);
5096 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5098 struct drm_device *dev = crtc->base.dev;
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 struct intel_crtc_state *pipe_config = crtc->config;
5102 if (!pipe_config->gmch_pfit.control)
5106 * The panel fitter should only be adjusted whilst the pipe is disabled,
5107 * according to register description and PRM.
5109 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5110 assert_pipe_disabled(dev_priv, crtc->pipe);
5112 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5113 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5115 /* Border color in case we don't scale up to the full screen. Black by
5116 * default, change to something else for debugging. */
5117 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5120 static enum intel_display_power_domain port_to_power_domain(enum port port)
5124 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5126 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5128 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5130 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5133 return POWER_DOMAIN_PORT_OTHER;
5137 #define for_each_power_domain(domain, mask) \
5138 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5139 if ((1 << (domain)) & (mask))
5141 enum intel_display_power_domain
5142 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5144 struct drm_device *dev = intel_encoder->base.dev;
5145 struct intel_digital_port *intel_dig_port;
5147 switch (intel_encoder->type) {
5148 case INTEL_OUTPUT_UNKNOWN:
5149 /* Only DDI platforms should ever use this output type */
5150 WARN_ON_ONCE(!HAS_DDI(dev));
5151 case INTEL_OUTPUT_DISPLAYPORT:
5152 case INTEL_OUTPUT_HDMI:
5153 case INTEL_OUTPUT_EDP:
5154 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5155 return port_to_power_domain(intel_dig_port->port);
5156 case INTEL_OUTPUT_DP_MST:
5157 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5158 return port_to_power_domain(intel_dig_port->port);
5159 case INTEL_OUTPUT_ANALOG:
5160 return POWER_DOMAIN_PORT_CRT;
5161 case INTEL_OUTPUT_DSI:
5162 return POWER_DOMAIN_PORT_DSI;
5164 return POWER_DOMAIN_PORT_OTHER;
5168 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5170 struct drm_device *dev = crtc->dev;
5171 struct intel_encoder *intel_encoder;
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 enum pipe pipe = intel_crtc->pipe;
5175 enum transcoder transcoder;
5177 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5179 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5180 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5181 if (intel_crtc->config->pch_pfit.enabled ||
5182 intel_crtc->config->pch_pfit.force_thru)
5183 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5185 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5186 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5191 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5193 struct drm_device *dev = state->dev;
5194 struct drm_i915_private *dev_priv = dev->dev_private;
5195 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5196 struct intel_crtc *crtc;
5199 * First get all needed power domains, then put all unneeded, to avoid
5200 * any unnecessary toggling of the power wells.
5202 for_each_intel_crtc(dev, crtc) {
5203 enum intel_display_power_domain domain;
5205 if (!crtc->base.state->enable)
5208 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5210 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5211 intel_display_power_get(dev_priv, domain);
5214 if (dev_priv->display.modeset_commit_cdclk) {
5215 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5217 if (cdclk != dev_priv->cdclk_freq &&
5218 !WARN_ON(!state->allow_modeset))
5219 dev_priv->display.modeset_commit_cdclk(state);
5222 for_each_intel_crtc(dev, crtc) {
5223 enum intel_display_power_domain domain;
5225 for_each_power_domain(domain, crtc->enabled_power_domains)
5226 intel_display_power_put(dev_priv, domain);
5228 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5231 intel_display_set_init_power(dev_priv, false);
5234 static void intel_update_max_cdclk(struct drm_device *dev)
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5238 if (IS_SKYLAKE(dev)) {
5239 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5241 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5242 dev_priv->max_cdclk_freq = 675000;
5243 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5244 dev_priv->max_cdclk_freq = 540000;
5245 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5246 dev_priv->max_cdclk_freq = 450000;
5248 dev_priv->max_cdclk_freq = 337500;
5249 } else if (IS_BROADWELL(dev)) {
5251 * FIXME with extra cooling we can allow
5252 * 540 MHz for ULX and 675 Mhz for ULT.
5253 * How can we know if extra cooling is
5254 * available? PCI ID, VTB, something else?
5256 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5257 dev_priv->max_cdclk_freq = 450000;
5258 else if (IS_BDW_ULX(dev))
5259 dev_priv->max_cdclk_freq = 450000;
5260 else if (IS_BDW_ULT(dev))
5261 dev_priv->max_cdclk_freq = 540000;
5263 dev_priv->max_cdclk_freq = 675000;
5264 } else if (IS_CHERRYVIEW(dev)) {
5265 dev_priv->max_cdclk_freq = 320000;
5266 } else if (IS_VALLEYVIEW(dev)) {
5267 dev_priv->max_cdclk_freq = 400000;
5269 /* otherwise assume cdclk is fixed */
5270 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5273 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5274 dev_priv->max_cdclk_freq);
5277 static void intel_update_cdclk(struct drm_device *dev)
5279 struct drm_i915_private *dev_priv = dev->dev_private;
5281 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5282 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5283 dev_priv->cdclk_freq);
5286 * Program the gmbus_freq based on the cdclk frequency.
5287 * BSpec erroneously claims we should aim for 4MHz, but
5288 * in fact 1MHz is the correct frequency.
5290 if (IS_VALLEYVIEW(dev)) {
5292 * Program the gmbus_freq based on the cdclk frequency.
5293 * BSpec erroneously claims we should aim for 4MHz, but
5294 * in fact 1MHz is the correct frequency.
5296 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5299 if (dev_priv->max_cdclk_freq == 0)
5300 intel_update_max_cdclk(dev);
5303 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5308 uint32_t current_freq;
5311 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5312 switch (frequency) {
5314 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5315 ratio = BXT_DE_PLL_RATIO(60);
5318 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5319 ratio = BXT_DE_PLL_RATIO(60);
5322 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5323 ratio = BXT_DE_PLL_RATIO(60);
5326 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5327 ratio = BXT_DE_PLL_RATIO(60);
5330 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5331 ratio = BXT_DE_PLL_RATIO(65);
5335 * Bypass frequency with DE PLL disabled. Init ratio, divider
5336 * to suppress GCC warning.
5342 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5347 mutex_lock(&dev_priv->rps.hw_lock);
5348 /* Inform power controller of upcoming frequency change */
5349 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5351 mutex_unlock(&dev_priv->rps.hw_lock);
5354 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5359 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5360 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5361 current_freq = current_freq * 500 + 1000;
5364 * DE PLL has to be disabled when
5365 * - setting to 19.2MHz (bypass, PLL isn't used)
5366 * - before setting to 624MHz (PLL needs toggling)
5367 * - before setting to any frequency from 624MHz (PLL needs toggling)
5369 if (frequency == 19200 || frequency == 624000 ||
5370 current_freq == 624000) {
5371 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5373 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5375 DRM_ERROR("timout waiting for DE PLL unlock\n");
5378 if (frequency != 19200) {
5381 val = I915_READ(BXT_DE_PLL_CTL);
5382 val &= ~BXT_DE_PLL_RATIO_MASK;
5384 I915_WRITE(BXT_DE_PLL_CTL, val);
5386 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5388 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5389 DRM_ERROR("timeout waiting for DE PLL lock\n");
5391 val = I915_READ(CDCLK_CTL);
5392 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5395 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5398 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5399 if (frequency >= 500000)
5400 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5402 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5403 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5404 val |= (frequency - 1000) / 500;
5405 I915_WRITE(CDCLK_CTL, val);
5408 mutex_lock(&dev_priv->rps.hw_lock);
5409 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5410 DIV_ROUND_UP(frequency, 25000));
5411 mutex_unlock(&dev_priv->rps.hw_lock);
5414 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5419 intel_update_cdclk(dev);
5422 void broxton_init_cdclk(struct drm_device *dev)
5424 struct drm_i915_private *dev_priv = dev->dev_private;
5428 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5429 * or else the reset will hang because there is no PCH to respond.
5430 * Move the handshake programming to initialization sequence.
5431 * Previously was left up to BIOS.
5433 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5434 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5435 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5437 /* Enable PG1 for cdclk */
5438 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5440 /* check if cd clock is enabled */
5441 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5442 DRM_DEBUG_KMS("Display already initialized\n");
5448 * - The initial CDCLK needs to be read from VBT.
5449 * Need to make this change after VBT has changes for BXT.
5450 * - check if setting the max (or any) cdclk freq is really necessary
5451 * here, it belongs to modeset time
5453 broxton_set_cdclk(dev, 624000);
5455 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5456 POSTING_READ(DBUF_CTL);
5460 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5461 DRM_ERROR("DBuf power enable timeout!\n");
5464 void broxton_uninit_cdclk(struct drm_device *dev)
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5468 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5469 POSTING_READ(DBUF_CTL);
5473 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5474 DRM_ERROR("DBuf power disable timeout!\n");
5476 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5477 broxton_set_cdclk(dev, 19200);
5479 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5482 static const struct skl_cdclk_entry {
5485 } skl_cdclk_frequencies[] = {
5486 { .freq = 308570, .vco = 8640 },
5487 { .freq = 337500, .vco = 8100 },
5488 { .freq = 432000, .vco = 8640 },
5489 { .freq = 450000, .vco = 8100 },
5490 { .freq = 540000, .vco = 8100 },
5491 { .freq = 617140, .vco = 8640 },
5492 { .freq = 675000, .vco = 8100 },
5495 static unsigned int skl_cdclk_decimal(unsigned int freq)
5497 return (freq - 1000) / 500;
5500 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5504 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5505 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5507 if (e->freq == freq)
5515 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5517 unsigned int min_freq;
5520 /* select the minimum CDCLK before enabling DPLL 0 */
5521 val = I915_READ(CDCLK_CTL);
5522 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5523 val |= CDCLK_FREQ_337_308;
5525 if (required_vco == 8640)
5530 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5532 I915_WRITE(CDCLK_CTL, val);
5533 POSTING_READ(CDCLK_CTL);
5536 * We always enable DPLL0 with the lowest link rate possible, but still
5537 * taking into account the VCO required to operate the eDP panel at the
5538 * desired frequency. The usual DP link rates operate with a VCO of
5539 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5540 * The modeset code is responsible for the selection of the exact link
5541 * rate later on, with the constraint of choosing a frequency that
5542 * works with required_vco.
5544 val = I915_READ(DPLL_CTRL1);
5546 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5547 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5548 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5549 if (required_vco == 8640)
5550 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5553 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5556 I915_WRITE(DPLL_CTRL1, val);
5557 POSTING_READ(DPLL_CTRL1);
5559 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5561 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5562 DRM_ERROR("DPLL0 not locked\n");
5565 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5570 /* inform PCU we want to change CDCLK */
5571 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5572 mutex_lock(&dev_priv->rps.hw_lock);
5573 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5574 mutex_unlock(&dev_priv->rps.hw_lock);
5576 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5579 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5583 for (i = 0; i < 15; i++) {
5584 if (skl_cdclk_pcu_ready(dev_priv))
5592 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5594 struct drm_device *dev = dev_priv->dev;
5595 u32 freq_select, pcu_ack;
5597 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5599 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5600 DRM_ERROR("failed to inform PCU about cdclk change\n");
5608 freq_select = CDCLK_FREQ_450_432;
5612 freq_select = CDCLK_FREQ_540;
5618 freq_select = CDCLK_FREQ_337_308;
5623 freq_select = CDCLK_FREQ_675_617;
5628 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5629 POSTING_READ(CDCLK_CTL);
5631 /* inform PCU of the change */
5632 mutex_lock(&dev_priv->rps.hw_lock);
5633 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5634 mutex_unlock(&dev_priv->rps.hw_lock);
5636 intel_update_cdclk(dev);
5639 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5641 /* disable DBUF power */
5642 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5643 POSTING_READ(DBUF_CTL);
5647 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5648 DRM_ERROR("DBuf power disable timeout\n");
5651 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5652 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5653 DRM_ERROR("Couldn't disable DPLL0\n");
5655 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5658 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5661 unsigned int required_vco;
5663 /* enable PCH reset handshake */
5664 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5665 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5667 /* enable PG1 and Misc I/O */
5668 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5670 /* DPLL0 already enabed !? */
5671 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5672 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5677 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5678 skl_dpll0_enable(dev_priv, required_vco);
5680 /* set CDCLK to the frequency the BIOS chose */
5681 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5683 /* enable DBUF power */
5684 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5685 POSTING_READ(DBUF_CTL);
5689 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5690 DRM_ERROR("DBuf power enable timeout\n");
5693 /* returns HPLL frequency in kHz */
5694 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5696 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5698 /* Obtain SKU information */
5699 mutex_lock(&dev_priv->sb_lock);
5700 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5701 CCK_FUSE_HPLL_FREQ_MASK;
5702 mutex_unlock(&dev_priv->sb_lock);
5704 return vco_freq[hpll_freq] * 1000;
5707 /* Adjust CDclk dividers to allow high res or save power if possible */
5708 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5713 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5714 != dev_priv->cdclk_freq);
5716 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5718 else if (cdclk == 266667)
5723 mutex_lock(&dev_priv->rps.hw_lock);
5724 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5725 val &= ~DSPFREQGUAR_MASK;
5726 val |= (cmd << DSPFREQGUAR_SHIFT);
5727 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5728 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5729 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5731 DRM_ERROR("timed out waiting for CDclk change\n");
5733 mutex_unlock(&dev_priv->rps.hw_lock);
5735 mutex_lock(&dev_priv->sb_lock);
5737 if (cdclk == 400000) {
5740 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5742 /* adjust cdclk divider */
5743 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5744 val &= ~DISPLAY_FREQUENCY_VALUES;
5746 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5748 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5749 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5751 DRM_ERROR("timed out waiting for CDclk change\n");
5754 /* adjust self-refresh exit latency value */
5755 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5759 * For high bandwidth configs, we set a higher latency in the bunit
5760 * so that the core display fetch happens in time to avoid underruns.
5762 if (cdclk == 400000)
5763 val |= 4500 / 250; /* 4.5 usec */
5765 val |= 3000 / 250; /* 3.0 usec */
5766 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5768 mutex_unlock(&dev_priv->sb_lock);
5770 intel_update_cdclk(dev);
5773 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5775 struct drm_i915_private *dev_priv = dev->dev_private;
5778 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5779 != dev_priv->cdclk_freq);
5788 MISSING_CASE(cdclk);
5793 * Specs are full of misinformation, but testing on actual
5794 * hardware has shown that we just need to write the desired
5795 * CCK divider into the Punit register.
5797 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5799 mutex_lock(&dev_priv->rps.hw_lock);
5800 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5801 val &= ~DSPFREQGUAR_MASK_CHV;
5802 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5803 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5804 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5805 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5807 DRM_ERROR("timed out waiting for CDclk change\n");
5809 mutex_unlock(&dev_priv->rps.hw_lock);
5811 intel_update_cdclk(dev);
5814 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5817 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5818 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5821 * Really only a few cases to deal with, as only 4 CDclks are supported:
5824 * 320/333MHz (depends on HPLL freq)
5826 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5827 * of the lower bin and adjust if needed.
5829 * We seem to get an unstable or solid color picture at 200MHz.
5830 * Not sure what's wrong. For now use 200MHz only when all pipes
5833 if (!IS_CHERRYVIEW(dev_priv) &&
5834 max_pixclk > freq_320*limit/100)
5836 else if (max_pixclk > 266667*limit/100)
5838 else if (max_pixclk > 0)
5844 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5849 * - remove the guardband, it's not needed on BXT
5850 * - set 19.2MHz bypass frequency if there are no active pipes
5852 if (max_pixclk > 576000*9/10)
5854 else if (max_pixclk > 384000*9/10)
5856 else if (max_pixclk > 288000*9/10)
5858 else if (max_pixclk > 144000*9/10)
5864 /* Compute the max pixel clock for new configuration. Uses atomic state if
5865 * that's non-NULL, look at current state otherwise. */
5866 static int intel_mode_max_pixclk(struct drm_device *dev,
5867 struct drm_atomic_state *state)
5869 struct intel_crtc *intel_crtc;
5870 struct intel_crtc_state *crtc_state;
5873 for_each_intel_crtc(dev, intel_crtc) {
5874 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5875 if (IS_ERR(crtc_state))
5876 return PTR_ERR(crtc_state);
5878 if (!crtc_state->base.enable)
5881 max_pixclk = max(max_pixclk,
5882 crtc_state->base.adjusted_mode.crtc_clock);
5888 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5890 struct drm_device *dev = state->dev;
5891 struct drm_i915_private *dev_priv = dev->dev_private;
5892 int max_pixclk = intel_mode_max_pixclk(dev, state);
5897 to_intel_atomic_state(state)->cdclk =
5898 valleyview_calc_cdclk(dev_priv, max_pixclk);
5903 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5905 struct drm_device *dev = state->dev;
5906 struct drm_i915_private *dev_priv = dev->dev_private;
5907 int max_pixclk = intel_mode_max_pixclk(dev, state);
5912 to_intel_atomic_state(state)->cdclk =
5913 broxton_calc_cdclk(dev_priv, max_pixclk);
5918 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5920 unsigned int credits, default_credits;
5922 if (IS_CHERRYVIEW(dev_priv))
5923 default_credits = PFI_CREDIT(12);
5925 default_credits = PFI_CREDIT(8);
5927 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5928 /* CHV suggested value is 31 or 63 */
5929 if (IS_CHERRYVIEW(dev_priv))
5930 credits = PFI_CREDIT_63;
5932 credits = PFI_CREDIT(15);
5934 credits = default_credits;
5938 * WA - write default credits before re-programming
5939 * FIXME: should we also set the resend bit here?
5941 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5944 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5945 credits | PFI_CREDIT_RESEND);
5948 * FIXME is this guaranteed to clear
5949 * immediately or should we poll for it?
5951 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5954 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5956 struct drm_device *dev = old_state->dev;
5957 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5958 struct drm_i915_private *dev_priv = dev->dev_private;
5961 * FIXME: We can end up here with all power domains off, yet
5962 * with a CDCLK frequency other than the minimum. To account
5963 * for this take the PIPE-A power domain, which covers the HW
5964 * blocks needed for the following programming. This can be
5965 * removed once it's guaranteed that we get here either with
5966 * the minimum CDCLK set, or the required power domains
5969 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5971 if (IS_CHERRYVIEW(dev))
5972 cherryview_set_cdclk(dev, req_cdclk);
5974 valleyview_set_cdclk(dev, req_cdclk);
5976 vlv_program_pfi_credits(dev_priv);
5978 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5981 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5983 struct drm_device *dev = crtc->dev;
5984 struct drm_i915_private *dev_priv = to_i915(dev);
5985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5986 struct intel_encoder *encoder;
5987 int pipe = intel_crtc->pipe;
5990 if (WARN_ON(intel_crtc->active))
5993 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5996 if (IS_CHERRYVIEW(dev))
5997 chv_prepare_pll(intel_crtc, intel_crtc->config);
5999 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6002 if (intel_crtc->config->has_dp_encoder)
6003 intel_dp_set_m_n(intel_crtc, M1_N1);
6005 intel_set_pipe_timings(intel_crtc);
6007 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6008 struct drm_i915_private *dev_priv = dev->dev_private;
6010 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6011 I915_WRITE(CHV_CANVAS(pipe), 0);
6014 i9xx_set_pipeconf(intel_crtc);
6016 intel_crtc->active = true;
6018 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6020 for_each_encoder_on_crtc(dev, crtc, encoder)
6021 if (encoder->pre_pll_enable)
6022 encoder->pre_pll_enable(encoder);
6025 if (IS_CHERRYVIEW(dev))
6026 chv_enable_pll(intel_crtc, intel_crtc->config);
6028 vlv_enable_pll(intel_crtc, intel_crtc->config);
6031 for_each_encoder_on_crtc(dev, crtc, encoder)
6032 if (encoder->pre_enable)
6033 encoder->pre_enable(encoder);
6035 i9xx_pfit_enable(intel_crtc);
6037 intel_crtc_load_lut(crtc);
6039 intel_enable_pipe(intel_crtc);
6041 assert_vblank_disabled(crtc);
6042 drm_crtc_vblank_on(crtc);
6044 for_each_encoder_on_crtc(dev, crtc, encoder)
6045 encoder->enable(encoder);
6048 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6050 struct drm_device *dev = crtc->base.dev;
6051 struct drm_i915_private *dev_priv = dev->dev_private;
6053 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6054 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6057 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6059 struct drm_device *dev = crtc->dev;
6060 struct drm_i915_private *dev_priv = to_i915(dev);
6061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6062 struct intel_encoder *encoder;
6063 int pipe = intel_crtc->pipe;
6065 if (WARN_ON(intel_crtc->active))
6068 i9xx_set_pll_dividers(intel_crtc);
6070 if (intel_crtc->config->has_dp_encoder)
6071 intel_dp_set_m_n(intel_crtc, M1_N1);
6073 intel_set_pipe_timings(intel_crtc);
6075 i9xx_set_pipeconf(intel_crtc);
6077 intel_crtc->active = true;
6080 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6082 for_each_encoder_on_crtc(dev, crtc, encoder)
6083 if (encoder->pre_enable)
6084 encoder->pre_enable(encoder);
6086 i9xx_enable_pll(intel_crtc);
6088 i9xx_pfit_enable(intel_crtc);
6090 intel_crtc_load_lut(crtc);
6092 intel_update_watermarks(crtc);
6093 intel_enable_pipe(intel_crtc);
6095 assert_vblank_disabled(crtc);
6096 drm_crtc_vblank_on(crtc);
6098 for_each_encoder_on_crtc(dev, crtc, encoder)
6099 encoder->enable(encoder);
6102 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6104 struct drm_device *dev = crtc->base.dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6107 if (!crtc->config->gmch_pfit.control)
6110 assert_pipe_disabled(dev_priv, crtc->pipe);
6112 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6113 I915_READ(PFIT_CONTROL));
6114 I915_WRITE(PFIT_CONTROL, 0);
6117 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6119 struct drm_device *dev = crtc->dev;
6120 struct drm_i915_private *dev_priv = dev->dev_private;
6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122 struct intel_encoder *encoder;
6123 int pipe = intel_crtc->pipe;
6126 * On gen2 planes are double buffered but the pipe isn't, so we must
6127 * wait for planes to fully turn off before disabling the pipe.
6128 * We also need to wait on all gmch platforms because of the
6129 * self-refresh mode constraint explained above.
6131 intel_wait_for_vblank(dev, pipe);
6133 for_each_encoder_on_crtc(dev, crtc, encoder)
6134 encoder->disable(encoder);
6136 drm_crtc_vblank_off(crtc);
6137 assert_vblank_disabled(crtc);
6139 intel_disable_pipe(intel_crtc);
6141 i9xx_pfit_disable(intel_crtc);
6143 for_each_encoder_on_crtc(dev, crtc, encoder)
6144 if (encoder->post_disable)
6145 encoder->post_disable(encoder);
6147 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6148 if (IS_CHERRYVIEW(dev))
6149 chv_disable_pll(dev_priv, pipe);
6150 else if (IS_VALLEYVIEW(dev))
6151 vlv_disable_pll(dev_priv, pipe);
6153 i9xx_disable_pll(intel_crtc);
6157 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6160 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6164 enum intel_display_power_domain domain;
6165 unsigned long domains;
6167 if (!intel_crtc->active)
6170 if (to_intel_plane_state(crtc->primary->state)->visible) {
6171 intel_crtc_wait_for_pending_flips(crtc);
6172 intel_pre_disable_primary(crtc);
6175 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6176 dev_priv->display.crtc_disable(crtc);
6178 domains = intel_crtc->enabled_power_domains;
6179 for_each_power_domain(domain, domains)
6180 intel_display_power_put(dev_priv, domain);
6181 intel_crtc->enabled_power_domains = 0;
6185 * turn all crtc's off, but do not adjust state
6186 * This has to be paired with a call to intel_modeset_setup_hw_state.
6188 void intel_display_suspend(struct drm_device *dev)
6190 struct drm_crtc *crtc;
6192 for_each_crtc(dev, crtc)
6193 intel_crtc_disable_noatomic(crtc);
6196 /* Master function to enable/disable CRTC and corresponding power wells */
6197 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6199 struct drm_device *dev = crtc->dev;
6200 struct drm_mode_config *config = &dev->mode_config;
6201 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203 struct intel_crtc_state *pipe_config;
6204 struct drm_atomic_state *state;
6207 if (enable == intel_crtc->active)
6210 if (enable && !crtc->state->enable)
6213 /* this function should be called with drm_modeset_lock_all for now */
6216 lockdep_assert_held(&ctx->ww_ctx);
6218 state = drm_atomic_state_alloc(dev);
6219 if (WARN_ON(!state))
6222 state->acquire_ctx = ctx;
6223 state->allow_modeset = true;
6225 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6226 if (IS_ERR(pipe_config)) {
6227 ret = PTR_ERR(pipe_config);
6230 pipe_config->base.active = enable;
6232 ret = intel_set_mode(state);
6237 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6238 drm_atomic_state_free(state);
6243 * Sets the power management mode of the pipe and plane.
6245 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6247 struct drm_device *dev = crtc->dev;
6248 struct intel_encoder *intel_encoder;
6249 bool enable = false;
6251 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6252 enable |= intel_encoder->connectors_active;
6254 intel_crtc_control(crtc, enable);
6257 void intel_encoder_destroy(struct drm_encoder *encoder)
6259 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6261 drm_encoder_cleanup(encoder);
6262 kfree(intel_encoder);
6265 /* Simple dpms helper for encoders with just one connector, no cloning and only
6266 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6267 * state of the entire output pipe. */
6268 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6270 if (mode == DRM_MODE_DPMS_ON) {
6271 encoder->connectors_active = true;
6273 intel_crtc_update_dpms(encoder->base.crtc);
6275 encoder->connectors_active = false;
6277 intel_crtc_update_dpms(encoder->base.crtc);
6281 /* Cross check the actual hw state with our own modeset state tracking (and it's
6282 * internal consistency). */
6283 static void intel_connector_check_state(struct intel_connector *connector)
6285 if (connector->get_hw_state(connector)) {
6286 struct intel_encoder *encoder = connector->encoder;
6287 struct drm_crtc *crtc;
6288 bool encoder_enabled;
6291 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6292 connector->base.base.id,
6293 connector->base.name);
6295 /* there is no real hw state for MST connectors */
6296 if (connector->mst_port)
6299 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6300 "wrong connector dpms state\n");
6301 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6302 "active connector not linked to encoder\n");
6305 I915_STATE_WARN(!encoder->connectors_active,
6306 "encoder->connectors_active not set\n");
6308 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6309 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6310 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6313 crtc = encoder->base.crtc;
6315 I915_STATE_WARN(!crtc->state->enable,
6316 "crtc not enabled\n");
6317 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6318 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6319 "encoder active on the wrong pipe\n");
6324 int intel_connector_init(struct intel_connector *connector)
6326 struct drm_connector_state *connector_state;
6328 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6329 if (!connector_state)
6332 connector->base.state = connector_state;
6336 struct intel_connector *intel_connector_alloc(void)
6338 struct intel_connector *connector;
6340 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6344 if (intel_connector_init(connector) < 0) {
6352 /* Even simpler default implementation, if there's really no special case to
6354 void intel_connector_dpms(struct drm_connector *connector, int mode)
6356 /* All the simple cases only support two dpms states. */
6357 if (mode != DRM_MODE_DPMS_ON)
6358 mode = DRM_MODE_DPMS_OFF;
6360 if (mode == connector->dpms)
6363 connector->dpms = mode;
6365 /* Only need to change hw state when actually enabled */
6366 if (connector->encoder)
6367 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6369 intel_modeset_check_state(connector->dev);
6372 /* Simple connector->get_hw_state implementation for encoders that support only
6373 * one connector and no cloning and hence the encoder state determines the state
6374 * of the connector. */
6375 bool intel_connector_get_hw_state(struct intel_connector *connector)
6378 struct intel_encoder *encoder = connector->encoder;
6380 return encoder->get_hw_state(encoder, &pipe);
6383 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6385 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6386 return crtc_state->fdi_lanes;
6391 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6392 struct intel_crtc_state *pipe_config)
6394 struct drm_atomic_state *state = pipe_config->base.state;
6395 struct intel_crtc *other_crtc;
6396 struct intel_crtc_state *other_crtc_state;
6398 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6399 pipe_name(pipe), pipe_config->fdi_lanes);
6400 if (pipe_config->fdi_lanes > 4) {
6401 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6402 pipe_name(pipe), pipe_config->fdi_lanes);
6406 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6407 if (pipe_config->fdi_lanes > 2) {
6408 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6409 pipe_config->fdi_lanes);
6416 if (INTEL_INFO(dev)->num_pipes == 2)
6419 /* Ivybridge 3 pipe is really complicated */
6424 if (pipe_config->fdi_lanes <= 2)
6427 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6429 intel_atomic_get_crtc_state(state, other_crtc);
6430 if (IS_ERR(other_crtc_state))
6431 return PTR_ERR(other_crtc_state);
6433 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6434 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6435 pipe_name(pipe), pipe_config->fdi_lanes);
6440 if (pipe_config->fdi_lanes > 2) {
6441 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6442 pipe_name(pipe), pipe_config->fdi_lanes);
6446 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6448 intel_atomic_get_crtc_state(state, other_crtc);
6449 if (IS_ERR(other_crtc_state))
6450 return PTR_ERR(other_crtc_state);
6452 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6453 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6463 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6464 struct intel_crtc_state *pipe_config)
6466 struct drm_device *dev = intel_crtc->base.dev;
6467 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6468 int lane, link_bw, fdi_dotclock, ret;
6469 bool needs_recompute = false;
6472 /* FDI is a binary signal running at ~2.7GHz, encoding
6473 * each output octet as 10 bits. The actual frequency
6474 * is stored as a divider into a 100MHz clock, and the
6475 * mode pixel clock is stored in units of 1KHz.
6476 * Hence the bw of each lane in terms of the mode signal
6479 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6481 fdi_dotclock = adjusted_mode->crtc_clock;
6483 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6484 pipe_config->pipe_bpp);
6486 pipe_config->fdi_lanes = lane;
6488 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6489 link_bw, &pipe_config->fdi_m_n);
6491 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6492 intel_crtc->pipe, pipe_config);
6493 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6494 pipe_config->pipe_bpp -= 2*3;
6495 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6496 pipe_config->pipe_bpp);
6497 needs_recompute = true;
6498 pipe_config->bw_constrained = true;
6503 if (needs_recompute)
6509 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6510 struct intel_crtc_state *pipe_config)
6512 if (pipe_config->pipe_bpp > 24)
6515 /* HSW can handle pixel rate up to cdclk? */
6516 if (IS_HASWELL(dev_priv->dev))
6520 * We compare against max which means we must take
6521 * the increased cdclk requirement into account when
6522 * calculating the new cdclk.
6524 * Should measure whether using a lower cdclk w/o IPS
6526 return ilk_pipe_pixel_rate(pipe_config) <=
6527 dev_priv->max_cdclk_freq * 95 / 100;
6530 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6531 struct intel_crtc_state *pipe_config)
6533 struct drm_device *dev = crtc->base.dev;
6534 struct drm_i915_private *dev_priv = dev->dev_private;
6536 pipe_config->ips_enabled = i915.enable_ips &&
6537 hsw_crtc_supports_ips(crtc) &&
6538 pipe_config_supports_ips(dev_priv, pipe_config);
6541 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6542 struct intel_crtc_state *pipe_config)
6544 struct drm_device *dev = crtc->base.dev;
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6548 /* FIXME should check pixel clock limits on all platforms */
6549 if (INTEL_INFO(dev)->gen < 4) {
6550 int clock_limit = dev_priv->max_cdclk_freq;
6553 * Enable pixel doubling when the dot clock
6554 * is > 90% of the (display) core speed.
6556 * GDG double wide on either pipe,
6557 * otherwise pipe A only.
6559 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6560 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6562 pipe_config->double_wide = true;
6565 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6570 * Pipe horizontal size must be even in:
6572 * - LVDS dual channel mode
6573 * - Double wide pipe
6575 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6576 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6577 pipe_config->pipe_src_w &= ~1;
6579 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6580 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6582 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6583 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6587 hsw_compute_ips_config(crtc, pipe_config);
6589 if (pipe_config->has_pch_encoder)
6590 return ironlake_fdi_compute_config(crtc, pipe_config);
6595 static int skylake_get_display_clock_speed(struct drm_device *dev)
6597 struct drm_i915_private *dev_priv = to_i915(dev);
6598 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6599 uint32_t cdctl = I915_READ(CDCLK_CTL);
6602 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6603 return 24000; /* 24MHz is the cd freq with NSSC ref */
6605 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6608 linkrate = (I915_READ(DPLL_CTRL1) &
6609 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6611 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6612 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6614 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6615 case CDCLK_FREQ_450_432:
6617 case CDCLK_FREQ_337_308:
6619 case CDCLK_FREQ_675_617:
6622 WARN(1, "Unknown cd freq selection\n");
6626 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6627 case CDCLK_FREQ_450_432:
6629 case CDCLK_FREQ_337_308:
6631 case CDCLK_FREQ_675_617:
6634 WARN(1, "Unknown cd freq selection\n");
6638 /* error case, do as if DPLL0 isn't enabled */
6642 static int broxton_get_display_clock_speed(struct drm_device *dev)
6644 struct drm_i915_private *dev_priv = to_i915(dev);
6645 uint32_t cdctl = I915_READ(CDCLK_CTL);
6646 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6647 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6650 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6653 cdclk = 19200 * pll_ratio / 2;
6655 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6656 case BXT_CDCLK_CD2X_DIV_SEL_1:
6657 return cdclk; /* 576MHz or 624MHz */
6658 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6659 return cdclk * 2 / 3; /* 384MHz */
6660 case BXT_CDCLK_CD2X_DIV_SEL_2:
6661 return cdclk / 2; /* 288MHz */
6662 case BXT_CDCLK_CD2X_DIV_SEL_4:
6663 return cdclk / 4; /* 144MHz */
6666 /* error case, do as if DE PLL isn't enabled */
6670 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673 uint32_t lcpll = I915_READ(LCPLL_CTL);
6674 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6676 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6678 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6680 else if (freq == LCPLL_CLK_FREQ_450)
6682 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6684 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6690 static int haswell_get_display_clock_speed(struct drm_device *dev)
6692 struct drm_i915_private *dev_priv = dev->dev_private;
6693 uint32_t lcpll = I915_READ(LCPLL_CTL);
6694 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6696 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6698 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6700 else if (freq == LCPLL_CLK_FREQ_450)
6702 else if (IS_HSW_ULT(dev))
6708 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6714 if (dev_priv->hpll_freq == 0)
6715 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6717 mutex_lock(&dev_priv->sb_lock);
6718 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6719 mutex_unlock(&dev_priv->sb_lock);
6721 divider = val & DISPLAY_FREQUENCY_VALUES;
6723 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6724 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6725 "cdclk change in progress\n");
6727 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6730 static int ilk_get_display_clock_speed(struct drm_device *dev)
6735 static int i945_get_display_clock_speed(struct drm_device *dev)
6740 static int i915_get_display_clock_speed(struct drm_device *dev)
6745 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6750 static int pnv_get_display_clock_speed(struct drm_device *dev)
6754 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6756 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6757 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6759 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6761 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6763 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6766 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6767 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6769 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6774 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6778 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6780 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6783 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6784 case GC_DISPLAY_CLOCK_333_MHZ:
6787 case GC_DISPLAY_CLOCK_190_200_MHZ:
6793 static int i865_get_display_clock_speed(struct drm_device *dev)
6798 static int i85x_get_display_clock_speed(struct drm_device *dev)
6803 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6804 * encoding is different :(
6805 * FIXME is this the right way to detect 852GM/852GMV?
6807 if (dev->pdev->revision == 0x1)
6810 pci_bus_read_config_word(dev->pdev->bus,
6811 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6813 /* Assume that the hardware is in the high speed state. This
6814 * should be the default.
6816 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6817 case GC_CLOCK_133_200:
6818 case GC_CLOCK_133_200_2:
6819 case GC_CLOCK_100_200:
6821 case GC_CLOCK_166_250:
6823 case GC_CLOCK_100_133:
6825 case GC_CLOCK_133_266:
6826 case GC_CLOCK_133_266_2:
6827 case GC_CLOCK_166_266:
6831 /* Shouldn't happen */
6835 static int i830_get_display_clock_speed(struct drm_device *dev)
6840 static unsigned int intel_hpll_vco(struct drm_device *dev)
6842 struct drm_i915_private *dev_priv = dev->dev_private;
6843 static const unsigned int blb_vco[8] = {
6850 static const unsigned int pnv_vco[8] = {
6857 static const unsigned int cl_vco[8] = {
6866 static const unsigned int elk_vco[8] = {
6872 static const unsigned int ctg_vco[8] = {
6880 const unsigned int *vco_table;
6884 /* FIXME other chipsets? */
6886 vco_table = ctg_vco;
6887 else if (IS_G4X(dev))
6888 vco_table = elk_vco;
6889 else if (IS_CRESTLINE(dev))
6891 else if (IS_PINEVIEW(dev))
6892 vco_table = pnv_vco;
6893 else if (IS_G33(dev))
6894 vco_table = blb_vco;
6898 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6900 vco = vco_table[tmp & 0x7];
6902 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6904 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6909 static int gm45_get_display_clock_speed(struct drm_device *dev)
6911 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6914 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6916 cdclk_sel = (tmp >> 12) & 0x1;
6922 return cdclk_sel ? 333333 : 222222;
6924 return cdclk_sel ? 320000 : 228571;
6926 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6931 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6933 static const uint8_t div_3200[] = { 16, 10, 8 };
6934 static const uint8_t div_4000[] = { 20, 12, 10 };
6935 static const uint8_t div_5333[] = { 24, 16, 14 };
6936 const uint8_t *div_table;
6937 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6940 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6942 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6944 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6949 div_table = div_3200;
6952 div_table = div_4000;
6955 div_table = div_5333;
6961 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6964 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6968 static int g33_get_display_clock_speed(struct drm_device *dev)
6970 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6971 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6972 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6973 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6974 const uint8_t *div_table;
6975 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6978 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6980 cdclk_sel = (tmp >> 4) & 0x7;
6982 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6987 div_table = div_3200;
6990 div_table = div_4000;
6993 div_table = div_4800;
6996 div_table = div_5333;
7002 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7005 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7010 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7012 while (*num > DATA_LINK_M_N_MASK ||
7013 *den > DATA_LINK_M_N_MASK) {
7019 static void compute_m_n(unsigned int m, unsigned int n,
7020 uint32_t *ret_m, uint32_t *ret_n)
7022 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7023 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7024 intel_reduce_m_n_ratio(ret_m, ret_n);
7028 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7029 int pixel_clock, int link_clock,
7030 struct intel_link_m_n *m_n)
7034 compute_m_n(bits_per_pixel * pixel_clock,
7035 link_clock * nlanes * 8,
7036 &m_n->gmch_m, &m_n->gmch_n);
7038 compute_m_n(pixel_clock, link_clock,
7039 &m_n->link_m, &m_n->link_n);
7042 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7044 if (i915.panel_use_ssc >= 0)
7045 return i915.panel_use_ssc != 0;
7046 return dev_priv->vbt.lvds_use_ssc
7047 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7050 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7053 struct drm_device *dev = crtc_state->base.crtc->dev;
7054 struct drm_i915_private *dev_priv = dev->dev_private;
7057 WARN_ON(!crtc_state->base.state);
7059 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7061 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7062 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7063 refclk = dev_priv->vbt.lvds_ssc_freq;
7064 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7065 } else if (!IS_GEN2(dev)) {
7074 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7076 return (1 << dpll->n) << 16 | dpll->m2;
7079 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7081 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7084 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7085 struct intel_crtc_state *crtc_state,
7086 intel_clock_t *reduced_clock)
7088 struct drm_device *dev = crtc->base.dev;
7091 if (IS_PINEVIEW(dev)) {
7092 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7094 fp2 = pnv_dpll_compute_fp(reduced_clock);
7096 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7098 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7101 crtc_state->dpll_hw_state.fp0 = fp;
7103 crtc->lowfreq_avail = false;
7104 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7106 crtc_state->dpll_hw_state.fp1 = fp2;
7107 crtc->lowfreq_avail = true;
7109 crtc_state->dpll_hw_state.fp1 = fp;
7113 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7119 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7120 * and set it to a reasonable value instead.
7122 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7123 reg_val &= 0xffffff00;
7124 reg_val |= 0x00000030;
7125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7127 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7128 reg_val &= 0x8cffffff;
7129 reg_val = 0x8c000000;
7130 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7132 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7133 reg_val &= 0xffffff00;
7134 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7136 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7137 reg_val &= 0x00ffffff;
7138 reg_val |= 0xb0000000;
7139 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7142 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7143 struct intel_link_m_n *m_n)
7145 struct drm_device *dev = crtc->base.dev;
7146 struct drm_i915_private *dev_priv = dev->dev_private;
7147 int pipe = crtc->pipe;
7149 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7150 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7151 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7152 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7155 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7156 struct intel_link_m_n *m_n,
7157 struct intel_link_m_n *m2_n2)
7159 struct drm_device *dev = crtc->base.dev;
7160 struct drm_i915_private *dev_priv = dev->dev_private;
7161 int pipe = crtc->pipe;
7162 enum transcoder transcoder = crtc->config->cpu_transcoder;
7164 if (INTEL_INFO(dev)->gen >= 5) {
7165 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7166 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7167 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7168 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7169 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7170 * for gen < 8) and if DRRS is supported (to make sure the
7171 * registers are not unnecessarily accessed).
7173 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7174 crtc->config->has_drrs) {
7175 I915_WRITE(PIPE_DATA_M2(transcoder),
7176 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7177 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7178 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7179 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7182 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7183 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7184 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7185 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7189 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7191 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7194 dp_m_n = &crtc->config->dp_m_n;
7195 dp_m2_n2 = &crtc->config->dp_m2_n2;
7196 } else if (m_n == M2_N2) {
7199 * M2_N2 registers are not supported. Hence m2_n2 divider value
7200 * needs to be programmed into M1_N1.
7202 dp_m_n = &crtc->config->dp_m2_n2;
7204 DRM_ERROR("Unsupported divider value\n");
7208 if (crtc->config->has_pch_encoder)
7209 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7211 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7214 static void vlv_compute_dpll(struct intel_crtc *crtc,
7215 struct intel_crtc_state *pipe_config)
7220 * Enable DPIO clock input. We should never disable the reference
7221 * clock for pipe B, since VGA hotplug / manual detection depends
7224 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7225 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7226 /* We should never disable this, set it here for state tracking */
7227 if (crtc->pipe == PIPE_B)
7228 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7229 dpll |= DPLL_VCO_ENABLE;
7230 pipe_config->dpll_hw_state.dpll = dpll;
7232 dpll_md = (pipe_config->pixel_multiplier - 1)
7233 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7234 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7237 static void vlv_prepare_pll(struct intel_crtc *crtc,
7238 const struct intel_crtc_state *pipe_config)
7240 struct drm_device *dev = crtc->base.dev;
7241 struct drm_i915_private *dev_priv = dev->dev_private;
7242 int pipe = crtc->pipe;
7244 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7245 u32 coreclk, reg_val;
7247 mutex_lock(&dev_priv->sb_lock);
7249 bestn = pipe_config->dpll.n;
7250 bestm1 = pipe_config->dpll.m1;
7251 bestm2 = pipe_config->dpll.m2;
7252 bestp1 = pipe_config->dpll.p1;
7253 bestp2 = pipe_config->dpll.p2;
7255 /* See eDP HDMI DPIO driver vbios notes doc */
7257 /* PLL B needs special handling */
7259 vlv_pllb_recal_opamp(dev_priv, pipe);
7261 /* Set up Tx target for periodic Rcomp update */
7262 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7264 /* Disable target IRef on PLL */
7265 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7266 reg_val &= 0x00ffffff;
7267 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7269 /* Disable fast lock */
7270 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7272 /* Set idtafcrecal before PLL is enabled */
7273 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7274 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7275 mdiv |= ((bestn << DPIO_N_SHIFT));
7276 mdiv |= (1 << DPIO_K_SHIFT);
7279 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7280 * but we don't support that).
7281 * Note: don't use the DAC post divider as it seems unstable.
7283 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7286 mdiv |= DPIO_ENABLE_CALIBRATION;
7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7289 /* Set HBR and RBR LPF coefficients */
7290 if (pipe_config->port_clock == 162000 ||
7291 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7292 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7293 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7299 if (pipe_config->has_dp_encoder) {
7300 /* Use SSC source */
7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7307 } else { /* HDMI or VGA */
7308 /* Use bend source */
7310 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7317 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7318 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7319 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7320 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7321 coreclk |= 0x01000000;
7322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7324 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7325 mutex_unlock(&dev_priv->sb_lock);
7328 static void chv_compute_dpll(struct intel_crtc *crtc,
7329 struct intel_crtc_state *pipe_config)
7331 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7332 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7334 if (crtc->pipe != PIPE_A)
7335 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7337 pipe_config->dpll_hw_state.dpll_md =
7338 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7341 static void chv_prepare_pll(struct intel_crtc *crtc,
7342 const struct intel_crtc_state *pipe_config)
7344 struct drm_device *dev = crtc->base.dev;
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 int pipe = crtc->pipe;
7347 int dpll_reg = DPLL(crtc->pipe);
7348 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7349 u32 loopfilter, tribuf_calcntr;
7350 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7354 bestn = pipe_config->dpll.n;
7355 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7356 bestm1 = pipe_config->dpll.m1;
7357 bestm2 = pipe_config->dpll.m2 >> 22;
7358 bestp1 = pipe_config->dpll.p1;
7359 bestp2 = pipe_config->dpll.p2;
7360 vco = pipe_config->dpll.vco;
7365 * Enable Refclk and SSC
7367 I915_WRITE(dpll_reg,
7368 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7370 mutex_lock(&dev_priv->sb_lock);
7372 /* p1 and p2 divider */
7373 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7374 5 << DPIO_CHV_S1_DIV_SHIFT |
7375 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7376 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7377 1 << DPIO_CHV_K_DIV_SHIFT);
7379 /* Feedback post-divider - m2 */
7380 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7382 /* Feedback refclk divider - n and m1 */
7383 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7384 DPIO_CHV_M1_DIV_BY_2 |
7385 1 << DPIO_CHV_N_DIV_SHIFT);
7387 /* M2 fraction division */
7389 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7391 /* M2 fraction division enable */
7392 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7393 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7394 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7396 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7397 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7399 /* Program digital lock detect threshold */
7400 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7401 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7402 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7403 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7405 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7406 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7409 if (vco == 5400000) {
7410 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7411 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7412 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7413 tribuf_calcntr = 0x9;
7414 } else if (vco <= 6200000) {
7415 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7416 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7417 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7418 tribuf_calcntr = 0x9;
7419 } else if (vco <= 6480000) {
7420 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7421 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7422 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7423 tribuf_calcntr = 0x8;
7425 /* Not supported. Apply the same limits as in the max case */
7426 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7427 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7428 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7431 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7433 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7434 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7435 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7436 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7439 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7440 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7443 mutex_unlock(&dev_priv->sb_lock);
7447 * vlv_force_pll_on - forcibly enable just the PLL
7448 * @dev_priv: i915 private structure
7449 * @pipe: pipe PLL to enable
7450 * @dpll: PLL configuration
7452 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7453 * in cases where we need the PLL enabled even when @pipe is not going to
7456 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7457 const struct dpll *dpll)
7459 struct intel_crtc *crtc =
7460 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7461 struct intel_crtc_state pipe_config = {
7462 .base.crtc = &crtc->base,
7463 .pixel_multiplier = 1,
7467 if (IS_CHERRYVIEW(dev)) {
7468 chv_compute_dpll(crtc, &pipe_config);
7469 chv_prepare_pll(crtc, &pipe_config);
7470 chv_enable_pll(crtc, &pipe_config);
7472 vlv_compute_dpll(crtc, &pipe_config);
7473 vlv_prepare_pll(crtc, &pipe_config);
7474 vlv_enable_pll(crtc, &pipe_config);
7479 * vlv_force_pll_off - forcibly disable just the PLL
7480 * @dev_priv: i915 private structure
7481 * @pipe: pipe PLL to disable
7483 * Disable the PLL for @pipe. To be used in cases where we need
7484 * the PLL enabled even when @pipe is not going to be enabled.
7486 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7488 if (IS_CHERRYVIEW(dev))
7489 chv_disable_pll(to_i915(dev), pipe);
7491 vlv_disable_pll(to_i915(dev), pipe);
7494 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7495 struct intel_crtc_state *crtc_state,
7496 intel_clock_t *reduced_clock,
7499 struct drm_device *dev = crtc->base.dev;
7500 struct drm_i915_private *dev_priv = dev->dev_private;
7503 struct dpll *clock = &crtc_state->dpll;
7505 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7507 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7508 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7510 dpll = DPLL_VGA_MODE_DIS;
7512 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7513 dpll |= DPLLB_MODE_LVDS;
7515 dpll |= DPLLB_MODE_DAC_SERIAL;
7517 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7518 dpll |= (crtc_state->pixel_multiplier - 1)
7519 << SDVO_MULTIPLIER_SHIFT_HIRES;
7523 dpll |= DPLL_SDVO_HIGH_SPEED;
7525 if (crtc_state->has_dp_encoder)
7526 dpll |= DPLL_SDVO_HIGH_SPEED;
7528 /* compute bitmask from p1 value */
7529 if (IS_PINEVIEW(dev))
7530 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7532 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7533 if (IS_G4X(dev) && reduced_clock)
7534 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7536 switch (clock->p2) {
7538 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7541 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7544 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7547 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7550 if (INTEL_INFO(dev)->gen >= 4)
7551 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7553 if (crtc_state->sdvo_tv_clock)
7554 dpll |= PLL_REF_INPUT_TVCLKINBC;
7555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7556 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7557 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7559 dpll |= PLL_REF_INPUT_DREFCLK;
7561 dpll |= DPLL_VCO_ENABLE;
7562 crtc_state->dpll_hw_state.dpll = dpll;
7564 if (INTEL_INFO(dev)->gen >= 4) {
7565 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7566 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7567 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7571 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7572 struct intel_crtc_state *crtc_state,
7573 intel_clock_t *reduced_clock,
7576 struct drm_device *dev = crtc->base.dev;
7577 struct drm_i915_private *dev_priv = dev->dev_private;
7579 struct dpll *clock = &crtc_state->dpll;
7581 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7583 dpll = DPLL_VGA_MODE_DIS;
7585 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7586 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7589 dpll |= PLL_P1_DIVIDE_BY_TWO;
7591 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7593 dpll |= PLL_P2_DIVIDE_BY_4;
7596 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7597 dpll |= DPLL_DVO_2X_MODE;
7599 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7600 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7603 dpll |= PLL_REF_INPUT_DREFCLK;
7605 dpll |= DPLL_VCO_ENABLE;
7606 crtc_state->dpll_hw_state.dpll = dpll;
7609 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7611 struct drm_device *dev = intel_crtc->base.dev;
7612 struct drm_i915_private *dev_priv = dev->dev_private;
7613 enum pipe pipe = intel_crtc->pipe;
7614 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7615 struct drm_display_mode *adjusted_mode =
7616 &intel_crtc->config->base.adjusted_mode;
7617 uint32_t crtc_vtotal, crtc_vblank_end;
7620 /* We need to be careful not to changed the adjusted mode, for otherwise
7621 * the hw state checker will get angry at the mismatch. */
7622 crtc_vtotal = adjusted_mode->crtc_vtotal;
7623 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7625 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7626 /* the chip adds 2 halflines automatically */
7628 crtc_vblank_end -= 1;
7630 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7631 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7633 vsyncshift = adjusted_mode->crtc_hsync_start -
7634 adjusted_mode->crtc_htotal / 2;
7636 vsyncshift += adjusted_mode->crtc_htotal;
7639 if (INTEL_INFO(dev)->gen > 3)
7640 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7642 I915_WRITE(HTOTAL(cpu_transcoder),
7643 (adjusted_mode->crtc_hdisplay - 1) |
7644 ((adjusted_mode->crtc_htotal - 1) << 16));
7645 I915_WRITE(HBLANK(cpu_transcoder),
7646 (adjusted_mode->crtc_hblank_start - 1) |
7647 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7648 I915_WRITE(HSYNC(cpu_transcoder),
7649 (adjusted_mode->crtc_hsync_start - 1) |
7650 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7652 I915_WRITE(VTOTAL(cpu_transcoder),
7653 (adjusted_mode->crtc_vdisplay - 1) |
7654 ((crtc_vtotal - 1) << 16));
7655 I915_WRITE(VBLANK(cpu_transcoder),
7656 (adjusted_mode->crtc_vblank_start - 1) |
7657 ((crtc_vblank_end - 1) << 16));
7658 I915_WRITE(VSYNC(cpu_transcoder),
7659 (adjusted_mode->crtc_vsync_start - 1) |
7660 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7662 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7663 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7664 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7666 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7667 (pipe == PIPE_B || pipe == PIPE_C))
7668 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7670 /* pipesrc controls the size that is scaled from, which should
7671 * always be the user's requested size.
7673 I915_WRITE(PIPESRC(pipe),
7674 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7675 (intel_crtc->config->pipe_src_h - 1));
7678 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7679 struct intel_crtc_state *pipe_config)
7681 struct drm_device *dev = crtc->base.dev;
7682 struct drm_i915_private *dev_priv = dev->dev_private;
7683 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7686 tmp = I915_READ(HTOTAL(cpu_transcoder));
7687 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7688 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7689 tmp = I915_READ(HBLANK(cpu_transcoder));
7690 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7691 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7692 tmp = I915_READ(HSYNC(cpu_transcoder));
7693 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7694 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7696 tmp = I915_READ(VTOTAL(cpu_transcoder));
7697 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7698 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7699 tmp = I915_READ(VBLANK(cpu_transcoder));
7700 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7701 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7702 tmp = I915_READ(VSYNC(cpu_transcoder));
7703 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7704 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7706 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7707 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7708 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7709 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7712 tmp = I915_READ(PIPESRC(crtc->pipe));
7713 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7714 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7716 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7717 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7720 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7721 struct intel_crtc_state *pipe_config)
7723 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7724 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7725 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7726 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7728 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7729 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7730 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7731 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7733 mode->flags = pipe_config->base.adjusted_mode.flags;
7735 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7736 mode->flags |= pipe_config->base.adjusted_mode.flags;
7739 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7741 struct drm_device *dev = intel_crtc->base.dev;
7742 struct drm_i915_private *dev_priv = dev->dev_private;
7747 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7748 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7749 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7751 if (intel_crtc->config->double_wide)
7752 pipeconf |= PIPECONF_DOUBLE_WIDE;
7754 /* only g4x and later have fancy bpc/dither controls */
7755 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7756 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7757 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7758 pipeconf |= PIPECONF_DITHER_EN |
7759 PIPECONF_DITHER_TYPE_SP;
7761 switch (intel_crtc->config->pipe_bpp) {
7763 pipeconf |= PIPECONF_6BPC;
7766 pipeconf |= PIPECONF_8BPC;
7769 pipeconf |= PIPECONF_10BPC;
7772 /* Case prevented by intel_choose_pipe_bpp_dither. */
7777 if (HAS_PIPE_CXSR(dev)) {
7778 if (intel_crtc->lowfreq_avail) {
7779 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7780 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7782 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7786 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7787 if (INTEL_INFO(dev)->gen < 4 ||
7788 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7789 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7791 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7793 pipeconf |= PIPECONF_PROGRESSIVE;
7795 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7796 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7798 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7799 POSTING_READ(PIPECONF(intel_crtc->pipe));
7802 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7803 struct intel_crtc_state *crtc_state)
7805 struct drm_device *dev = crtc->base.dev;
7806 struct drm_i915_private *dev_priv = dev->dev_private;
7807 int refclk, num_connectors = 0;
7808 intel_clock_t clock;
7810 bool is_dsi = false;
7811 struct intel_encoder *encoder;
7812 const intel_limit_t *limit;
7813 struct drm_atomic_state *state = crtc_state->base.state;
7814 struct drm_connector *connector;
7815 struct drm_connector_state *connector_state;
7818 memset(&crtc_state->dpll_hw_state, 0,
7819 sizeof(crtc_state->dpll_hw_state));
7821 for_each_connector_in_state(state, connector, connector_state, i) {
7822 if (connector_state->crtc != &crtc->base)
7825 encoder = to_intel_encoder(connector_state->best_encoder);
7827 switch (encoder->type) {
7828 case INTEL_OUTPUT_DSI:
7841 if (!crtc_state->clock_set) {
7842 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7845 * Returns a set of divisors for the desired target clock with
7846 * the given refclk, or FALSE. The returned values represent
7847 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7850 limit = intel_limit(crtc_state, refclk);
7851 ok = dev_priv->display.find_dpll(limit, crtc_state,
7852 crtc_state->port_clock,
7853 refclk, NULL, &clock);
7855 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7859 /* Compat-code for transition, will disappear. */
7860 crtc_state->dpll.n = clock.n;
7861 crtc_state->dpll.m1 = clock.m1;
7862 crtc_state->dpll.m2 = clock.m2;
7863 crtc_state->dpll.p1 = clock.p1;
7864 crtc_state->dpll.p2 = clock.p2;
7868 i8xx_compute_dpll(crtc, crtc_state, NULL,
7870 } else if (IS_CHERRYVIEW(dev)) {
7871 chv_compute_dpll(crtc, crtc_state);
7872 } else if (IS_VALLEYVIEW(dev)) {
7873 vlv_compute_dpll(crtc, crtc_state);
7875 i9xx_compute_dpll(crtc, crtc_state, NULL,
7882 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7883 struct intel_crtc_state *pipe_config)
7885 struct drm_device *dev = crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7889 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7892 tmp = I915_READ(PFIT_CONTROL);
7893 if (!(tmp & PFIT_ENABLE))
7896 /* Check whether the pfit is attached to our pipe. */
7897 if (INTEL_INFO(dev)->gen < 4) {
7898 if (crtc->pipe != PIPE_B)
7901 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7905 pipe_config->gmch_pfit.control = tmp;
7906 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7907 if (INTEL_INFO(dev)->gen < 5)
7908 pipe_config->gmch_pfit.lvds_border_bits =
7909 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7912 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7913 struct intel_crtc_state *pipe_config)
7915 struct drm_device *dev = crtc->base.dev;
7916 struct drm_i915_private *dev_priv = dev->dev_private;
7917 int pipe = pipe_config->cpu_transcoder;
7918 intel_clock_t clock;
7920 int refclk = 100000;
7922 /* In case of MIPI DPLL will not even be used */
7923 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7926 mutex_lock(&dev_priv->sb_lock);
7927 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7928 mutex_unlock(&dev_priv->sb_lock);
7930 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7931 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7932 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7933 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7934 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7936 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7940 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7941 struct intel_initial_plane_config *plane_config)
7943 struct drm_device *dev = crtc->base.dev;
7944 struct drm_i915_private *dev_priv = dev->dev_private;
7945 u32 val, base, offset;
7946 int pipe = crtc->pipe, plane = crtc->plane;
7947 int fourcc, pixel_format;
7948 unsigned int aligned_height;
7949 struct drm_framebuffer *fb;
7950 struct intel_framebuffer *intel_fb;
7952 val = I915_READ(DSPCNTR(plane));
7953 if (!(val & DISPLAY_PLANE_ENABLE))
7956 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7958 DRM_DEBUG_KMS("failed to alloc fb\n");
7962 fb = &intel_fb->base;
7964 if (INTEL_INFO(dev)->gen >= 4) {
7965 if (val & DISPPLANE_TILED) {
7966 plane_config->tiling = I915_TILING_X;
7967 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7971 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7972 fourcc = i9xx_format_to_fourcc(pixel_format);
7973 fb->pixel_format = fourcc;
7974 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7976 if (INTEL_INFO(dev)->gen >= 4) {
7977 if (plane_config->tiling)
7978 offset = I915_READ(DSPTILEOFF(plane));
7980 offset = I915_READ(DSPLINOFF(plane));
7981 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7983 base = I915_READ(DSPADDR(plane));
7985 plane_config->base = base;
7987 val = I915_READ(PIPESRC(pipe));
7988 fb->width = ((val >> 16) & 0xfff) + 1;
7989 fb->height = ((val >> 0) & 0xfff) + 1;
7991 val = I915_READ(DSPSTRIDE(pipe));
7992 fb->pitches[0] = val & 0xffffffc0;
7994 aligned_height = intel_fb_align_height(dev, fb->height,
7998 plane_config->size = fb->pitches[0] * aligned_height;
8000 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8001 pipe_name(pipe), plane, fb->width, fb->height,
8002 fb->bits_per_pixel, base, fb->pitches[0],
8003 plane_config->size);
8005 plane_config->fb = intel_fb;
8008 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8009 struct intel_crtc_state *pipe_config)
8011 struct drm_device *dev = crtc->base.dev;
8012 struct drm_i915_private *dev_priv = dev->dev_private;
8013 int pipe = pipe_config->cpu_transcoder;
8014 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8015 intel_clock_t clock;
8016 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8017 int refclk = 100000;
8019 mutex_lock(&dev_priv->sb_lock);
8020 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8021 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8022 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8023 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8024 mutex_unlock(&dev_priv->sb_lock);
8026 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8027 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8028 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8029 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8030 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8032 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8035 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8036 struct intel_crtc_state *pipe_config)
8038 struct drm_device *dev = crtc->base.dev;
8039 struct drm_i915_private *dev_priv = dev->dev_private;
8042 if (!intel_display_power_is_enabled(dev_priv,
8043 POWER_DOMAIN_PIPE(crtc->pipe)))
8046 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8047 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8049 tmp = I915_READ(PIPECONF(crtc->pipe));
8050 if (!(tmp & PIPECONF_ENABLE))
8053 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8054 switch (tmp & PIPECONF_BPC_MASK) {
8056 pipe_config->pipe_bpp = 18;
8059 pipe_config->pipe_bpp = 24;
8061 case PIPECONF_10BPC:
8062 pipe_config->pipe_bpp = 30;
8069 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8070 pipe_config->limited_color_range = true;
8072 if (INTEL_INFO(dev)->gen < 4)
8073 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8075 intel_get_pipe_timings(crtc, pipe_config);
8077 i9xx_get_pfit_config(crtc, pipe_config);
8079 if (INTEL_INFO(dev)->gen >= 4) {
8080 tmp = I915_READ(DPLL_MD(crtc->pipe));
8081 pipe_config->pixel_multiplier =
8082 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8083 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8084 pipe_config->dpll_hw_state.dpll_md = tmp;
8085 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8086 tmp = I915_READ(DPLL(crtc->pipe));
8087 pipe_config->pixel_multiplier =
8088 ((tmp & SDVO_MULTIPLIER_MASK)
8089 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8091 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8092 * port and will be fixed up in the encoder->get_config
8094 pipe_config->pixel_multiplier = 1;
8096 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8097 if (!IS_VALLEYVIEW(dev)) {
8099 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8100 * on 830. Filter it out here so that we don't
8101 * report errors due to that.
8104 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8106 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8107 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8109 /* Mask out read-only status bits. */
8110 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8111 DPLL_PORTC_READY_MASK |
8112 DPLL_PORTB_READY_MASK);
8115 if (IS_CHERRYVIEW(dev))
8116 chv_crtc_clock_get(crtc, pipe_config);
8117 else if (IS_VALLEYVIEW(dev))
8118 vlv_crtc_clock_get(crtc, pipe_config);
8120 i9xx_crtc_clock_get(crtc, pipe_config);
8125 static void ironlake_init_pch_refclk(struct drm_device *dev)
8127 struct drm_i915_private *dev_priv = dev->dev_private;
8128 struct intel_encoder *encoder;
8130 bool has_lvds = false;
8131 bool has_cpu_edp = false;
8132 bool has_panel = false;
8133 bool has_ck505 = false;
8134 bool can_ssc = false;
8136 /* We need to take the global config into account */
8137 for_each_intel_encoder(dev, encoder) {
8138 switch (encoder->type) {
8139 case INTEL_OUTPUT_LVDS:
8143 case INTEL_OUTPUT_EDP:
8145 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8153 if (HAS_PCH_IBX(dev)) {
8154 has_ck505 = dev_priv->vbt.display_clock_mode;
8155 can_ssc = has_ck505;
8161 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8162 has_panel, has_lvds, has_ck505);
8164 /* Ironlake: try to setup display ref clock before DPLL
8165 * enabling. This is only under driver's control after
8166 * PCH B stepping, previous chipset stepping should be
8167 * ignoring this setting.
8169 val = I915_READ(PCH_DREF_CONTROL);
8171 /* As we must carefully and slowly disable/enable each source in turn,
8172 * compute the final state we want first and check if we need to
8173 * make any changes at all.
8176 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8178 final |= DREF_NONSPREAD_CK505_ENABLE;
8180 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8182 final &= ~DREF_SSC_SOURCE_MASK;
8183 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8184 final &= ~DREF_SSC1_ENABLE;
8187 final |= DREF_SSC_SOURCE_ENABLE;
8189 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8190 final |= DREF_SSC1_ENABLE;
8193 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8194 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8196 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8198 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8200 final |= DREF_SSC_SOURCE_DISABLE;
8201 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8207 /* Always enable nonspread source */
8208 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8211 val |= DREF_NONSPREAD_CK505_ENABLE;
8213 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8216 val &= ~DREF_SSC_SOURCE_MASK;
8217 val |= DREF_SSC_SOURCE_ENABLE;
8219 /* SSC must be turned on before enabling the CPU output */
8220 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8221 DRM_DEBUG_KMS("Using SSC on panel\n");
8222 val |= DREF_SSC1_ENABLE;
8224 val &= ~DREF_SSC1_ENABLE;
8226 /* Get SSC going before enabling the outputs */
8227 I915_WRITE(PCH_DREF_CONTROL, val);
8228 POSTING_READ(PCH_DREF_CONTROL);
8231 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8233 /* Enable CPU source on CPU attached eDP */
8235 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8236 DRM_DEBUG_KMS("Using SSC on eDP\n");
8237 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8239 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8241 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8243 I915_WRITE(PCH_DREF_CONTROL, val);
8244 POSTING_READ(PCH_DREF_CONTROL);
8247 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8249 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8251 /* Turn off CPU output */
8252 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8254 I915_WRITE(PCH_DREF_CONTROL, val);
8255 POSTING_READ(PCH_DREF_CONTROL);
8258 /* Turn off the SSC source */
8259 val &= ~DREF_SSC_SOURCE_MASK;
8260 val |= DREF_SSC_SOURCE_DISABLE;
8263 val &= ~DREF_SSC1_ENABLE;
8265 I915_WRITE(PCH_DREF_CONTROL, val);
8266 POSTING_READ(PCH_DREF_CONTROL);
8270 BUG_ON(val != final);
8273 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8277 tmp = I915_READ(SOUTH_CHICKEN2);
8278 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8279 I915_WRITE(SOUTH_CHICKEN2, tmp);
8281 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8282 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8283 DRM_ERROR("FDI mPHY reset assert timeout\n");
8285 tmp = I915_READ(SOUTH_CHICKEN2);
8286 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8287 I915_WRITE(SOUTH_CHICKEN2, tmp);
8289 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8290 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8291 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8294 /* WaMPhyProgramming:hsw */
8295 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8299 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8300 tmp &= ~(0xFF << 24);
8301 tmp |= (0x12 << 24);
8302 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8304 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8306 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8308 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8310 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8312 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8313 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8314 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8316 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8317 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8318 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8320 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8323 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8325 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8328 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8330 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8333 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8335 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8338 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8340 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8341 tmp &= ~(0xFF << 16);
8342 tmp |= (0x1C << 16);
8343 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8345 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8346 tmp &= ~(0xFF << 16);
8347 tmp |= (0x1C << 16);
8348 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8350 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8352 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8354 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8356 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8358 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8359 tmp &= ~(0xF << 28);
8361 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8363 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8364 tmp &= ~(0xF << 28);
8366 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8369 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8370 * Programming" based on the parameters passed:
8371 * - Sequence to enable CLKOUT_DP
8372 * - Sequence to enable CLKOUT_DP without spread
8373 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8375 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8378 struct drm_i915_private *dev_priv = dev->dev_private;
8381 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8383 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8384 with_fdi, "LP PCH doesn't have FDI\n"))
8387 mutex_lock(&dev_priv->sb_lock);
8389 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8390 tmp &= ~SBI_SSCCTL_DISABLE;
8391 tmp |= SBI_SSCCTL_PATHALT;
8392 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8397 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8398 tmp &= ~SBI_SSCCTL_PATHALT;
8399 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8402 lpt_reset_fdi_mphy(dev_priv);
8403 lpt_program_fdi_mphy(dev_priv);
8407 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8408 SBI_GEN0 : SBI_DBUFF0;
8409 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8410 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8411 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8413 mutex_unlock(&dev_priv->sb_lock);
8416 /* Sequence to disable CLKOUT_DP */
8417 static void lpt_disable_clkout_dp(struct drm_device *dev)
8419 struct drm_i915_private *dev_priv = dev->dev_private;
8422 mutex_lock(&dev_priv->sb_lock);
8424 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8425 SBI_GEN0 : SBI_DBUFF0;
8426 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8427 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8428 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8430 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8431 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8432 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8433 tmp |= SBI_SSCCTL_PATHALT;
8434 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8437 tmp |= SBI_SSCCTL_DISABLE;
8438 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8441 mutex_unlock(&dev_priv->sb_lock);
8444 static void lpt_init_pch_refclk(struct drm_device *dev)
8446 struct intel_encoder *encoder;
8447 bool has_vga = false;
8449 for_each_intel_encoder(dev, encoder) {
8450 switch (encoder->type) {
8451 case INTEL_OUTPUT_ANALOG:
8460 lpt_enable_clkout_dp(dev, true, true);
8462 lpt_disable_clkout_dp(dev);
8466 * Initialize reference clocks when the driver loads
8468 void intel_init_pch_refclk(struct drm_device *dev)
8470 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8471 ironlake_init_pch_refclk(dev);
8472 else if (HAS_PCH_LPT(dev))
8473 lpt_init_pch_refclk(dev);
8476 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8478 struct drm_device *dev = crtc_state->base.crtc->dev;
8479 struct drm_i915_private *dev_priv = dev->dev_private;
8480 struct drm_atomic_state *state = crtc_state->base.state;
8481 struct drm_connector *connector;
8482 struct drm_connector_state *connector_state;
8483 struct intel_encoder *encoder;
8484 int num_connectors = 0, i;
8485 bool is_lvds = false;
8487 for_each_connector_in_state(state, connector, connector_state, i) {
8488 if (connector_state->crtc != crtc_state->base.crtc)
8491 encoder = to_intel_encoder(connector_state->best_encoder);
8493 switch (encoder->type) {
8494 case INTEL_OUTPUT_LVDS:
8503 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8504 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8505 dev_priv->vbt.lvds_ssc_freq);
8506 return dev_priv->vbt.lvds_ssc_freq;
8512 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8514 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8516 int pipe = intel_crtc->pipe;
8521 switch (intel_crtc->config->pipe_bpp) {
8523 val |= PIPECONF_6BPC;
8526 val |= PIPECONF_8BPC;
8529 val |= PIPECONF_10BPC;
8532 val |= PIPECONF_12BPC;
8535 /* Case prevented by intel_choose_pipe_bpp_dither. */
8539 if (intel_crtc->config->dither)
8540 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8542 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8543 val |= PIPECONF_INTERLACED_ILK;
8545 val |= PIPECONF_PROGRESSIVE;
8547 if (intel_crtc->config->limited_color_range)
8548 val |= PIPECONF_COLOR_RANGE_SELECT;
8550 I915_WRITE(PIPECONF(pipe), val);
8551 POSTING_READ(PIPECONF(pipe));
8555 * Set up the pipe CSC unit.
8557 * Currently only full range RGB to limited range RGB conversion
8558 * is supported, but eventually this should handle various
8559 * RGB<->YCbCr scenarios as well.
8561 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8563 struct drm_device *dev = crtc->dev;
8564 struct drm_i915_private *dev_priv = dev->dev_private;
8565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8566 int pipe = intel_crtc->pipe;
8567 uint16_t coeff = 0x7800; /* 1.0 */
8570 * TODO: Check what kind of values actually come out of the pipe
8571 * with these coeff/postoff values and adjust to get the best
8572 * accuracy. Perhaps we even need to take the bpc value into
8576 if (intel_crtc->config->limited_color_range)
8577 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8580 * GY/GU and RY/RU should be the other way around according
8581 * to BSpec, but reality doesn't agree. Just set them up in
8582 * a way that results in the correct picture.
8584 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8585 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8587 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8588 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8590 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8591 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8593 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8594 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8595 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8597 if (INTEL_INFO(dev)->gen > 6) {
8598 uint16_t postoff = 0;
8600 if (intel_crtc->config->limited_color_range)
8601 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8603 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8604 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8605 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8607 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8609 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8611 if (intel_crtc->config->limited_color_range)
8612 mode |= CSC_BLACK_SCREEN_OFFSET;
8614 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8618 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8620 struct drm_device *dev = crtc->dev;
8621 struct drm_i915_private *dev_priv = dev->dev_private;
8622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623 enum pipe pipe = intel_crtc->pipe;
8624 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8629 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8630 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8632 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8633 val |= PIPECONF_INTERLACED_ILK;
8635 val |= PIPECONF_PROGRESSIVE;
8637 I915_WRITE(PIPECONF(cpu_transcoder), val);
8638 POSTING_READ(PIPECONF(cpu_transcoder));
8640 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8641 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8643 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8646 switch (intel_crtc->config->pipe_bpp) {
8648 val |= PIPEMISC_DITHER_6_BPC;
8651 val |= PIPEMISC_DITHER_8_BPC;
8654 val |= PIPEMISC_DITHER_10_BPC;
8657 val |= PIPEMISC_DITHER_12_BPC;
8660 /* Case prevented by pipe_config_set_bpp. */
8664 if (intel_crtc->config->dither)
8665 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8667 I915_WRITE(PIPEMISC(pipe), val);
8671 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8672 struct intel_crtc_state *crtc_state,
8673 intel_clock_t *clock,
8674 bool *has_reduced_clock,
8675 intel_clock_t *reduced_clock)
8677 struct drm_device *dev = crtc->dev;
8678 struct drm_i915_private *dev_priv = dev->dev_private;
8680 const intel_limit_t *limit;
8683 refclk = ironlake_get_refclk(crtc_state);
8686 * Returns a set of divisors for the desired target clock with the given
8687 * refclk, or FALSE. The returned values represent the clock equation:
8688 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8690 limit = intel_limit(crtc_state, refclk);
8691 ret = dev_priv->display.find_dpll(limit, crtc_state,
8692 crtc_state->port_clock,
8693 refclk, NULL, clock);
8700 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8703 * Account for spread spectrum to avoid
8704 * oversubscribing the link. Max center spread
8705 * is 2.5%; use 5% for safety's sake.
8707 u32 bps = target_clock * bpp * 21 / 20;
8708 return DIV_ROUND_UP(bps, link_bw * 8);
8711 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8713 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8716 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8717 struct intel_crtc_state *crtc_state,
8719 intel_clock_t *reduced_clock, u32 *fp2)
8721 struct drm_crtc *crtc = &intel_crtc->base;
8722 struct drm_device *dev = crtc->dev;
8723 struct drm_i915_private *dev_priv = dev->dev_private;
8724 struct drm_atomic_state *state = crtc_state->base.state;
8725 struct drm_connector *connector;
8726 struct drm_connector_state *connector_state;
8727 struct intel_encoder *encoder;
8729 int factor, num_connectors = 0, i;
8730 bool is_lvds = false, is_sdvo = false;
8732 for_each_connector_in_state(state, connector, connector_state, i) {
8733 if (connector_state->crtc != crtc_state->base.crtc)
8736 encoder = to_intel_encoder(connector_state->best_encoder);
8738 switch (encoder->type) {
8739 case INTEL_OUTPUT_LVDS:
8742 case INTEL_OUTPUT_SDVO:
8743 case INTEL_OUTPUT_HDMI:
8753 /* Enable autotuning of the PLL clock (if permissible) */
8756 if ((intel_panel_use_ssc(dev_priv) &&
8757 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8758 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8760 } else if (crtc_state->sdvo_tv_clock)
8763 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8766 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8772 dpll |= DPLLB_MODE_LVDS;
8774 dpll |= DPLLB_MODE_DAC_SERIAL;
8776 dpll |= (crtc_state->pixel_multiplier - 1)
8777 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8780 dpll |= DPLL_SDVO_HIGH_SPEED;
8781 if (crtc_state->has_dp_encoder)
8782 dpll |= DPLL_SDVO_HIGH_SPEED;
8784 /* compute bitmask from p1 value */
8785 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8787 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8789 switch (crtc_state->dpll.p2) {
8791 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8794 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8797 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8800 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8804 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8805 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8807 dpll |= PLL_REF_INPUT_DREFCLK;
8809 return dpll | DPLL_VCO_ENABLE;
8812 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8813 struct intel_crtc_state *crtc_state)
8815 struct drm_device *dev = crtc->base.dev;
8816 intel_clock_t clock, reduced_clock;
8817 u32 dpll = 0, fp = 0, fp2 = 0;
8818 bool ok, has_reduced_clock = false;
8819 bool is_lvds = false;
8820 struct intel_shared_dpll *pll;
8822 memset(&crtc_state->dpll_hw_state, 0,
8823 sizeof(crtc_state->dpll_hw_state));
8825 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8827 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8828 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8830 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8831 &has_reduced_clock, &reduced_clock);
8832 if (!ok && !crtc_state->clock_set) {
8833 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8836 /* Compat-code for transition, will disappear. */
8837 if (!crtc_state->clock_set) {
8838 crtc_state->dpll.n = clock.n;
8839 crtc_state->dpll.m1 = clock.m1;
8840 crtc_state->dpll.m2 = clock.m2;
8841 crtc_state->dpll.p1 = clock.p1;
8842 crtc_state->dpll.p2 = clock.p2;
8845 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8846 if (crtc_state->has_pch_encoder) {
8847 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8848 if (has_reduced_clock)
8849 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8851 dpll = ironlake_compute_dpll(crtc, crtc_state,
8852 &fp, &reduced_clock,
8853 has_reduced_clock ? &fp2 : NULL);
8855 crtc_state->dpll_hw_state.dpll = dpll;
8856 crtc_state->dpll_hw_state.fp0 = fp;
8857 if (has_reduced_clock)
8858 crtc_state->dpll_hw_state.fp1 = fp2;
8860 crtc_state->dpll_hw_state.fp1 = fp;
8862 pll = intel_get_shared_dpll(crtc, crtc_state);
8864 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8865 pipe_name(crtc->pipe));
8870 if (is_lvds && has_reduced_clock)
8871 crtc->lowfreq_avail = true;
8873 crtc->lowfreq_avail = false;
8878 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8879 struct intel_link_m_n *m_n)
8881 struct drm_device *dev = crtc->base.dev;
8882 struct drm_i915_private *dev_priv = dev->dev_private;
8883 enum pipe pipe = crtc->pipe;
8885 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8886 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8887 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8889 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8890 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8891 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8894 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8895 enum transcoder transcoder,
8896 struct intel_link_m_n *m_n,
8897 struct intel_link_m_n *m2_n2)
8899 struct drm_device *dev = crtc->base.dev;
8900 struct drm_i915_private *dev_priv = dev->dev_private;
8901 enum pipe pipe = crtc->pipe;
8903 if (INTEL_INFO(dev)->gen >= 5) {
8904 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8905 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8906 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8908 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8909 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8910 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8911 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8912 * gen < 8) and if DRRS is supported (to make sure the
8913 * registers are not unnecessarily read).
8915 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8916 crtc->config->has_drrs) {
8917 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8918 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8919 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8921 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8922 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8923 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8926 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8927 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8928 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8930 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8931 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8932 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8936 void intel_dp_get_m_n(struct intel_crtc *crtc,
8937 struct intel_crtc_state *pipe_config)
8939 if (pipe_config->has_pch_encoder)
8940 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8942 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8943 &pipe_config->dp_m_n,
8944 &pipe_config->dp_m2_n2);
8947 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8948 struct intel_crtc_state *pipe_config)
8950 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8951 &pipe_config->fdi_m_n, NULL);
8954 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8955 struct intel_crtc_state *pipe_config)
8957 struct drm_device *dev = crtc->base.dev;
8958 struct drm_i915_private *dev_priv = dev->dev_private;
8959 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8960 uint32_t ps_ctrl = 0;
8964 /* find scaler attached to this pipe */
8965 for (i = 0; i < crtc->num_scalers; i++) {
8966 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8967 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8969 pipe_config->pch_pfit.enabled = true;
8970 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8971 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8976 scaler_state->scaler_id = id;
8978 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8980 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8985 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8986 struct intel_initial_plane_config *plane_config)
8988 struct drm_device *dev = crtc->base.dev;
8989 struct drm_i915_private *dev_priv = dev->dev_private;
8990 u32 val, base, offset, stride_mult, tiling;
8991 int pipe = crtc->pipe;
8992 int fourcc, pixel_format;
8993 unsigned int aligned_height;
8994 struct drm_framebuffer *fb;
8995 struct intel_framebuffer *intel_fb;
8997 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8999 DRM_DEBUG_KMS("failed to alloc fb\n");
9003 fb = &intel_fb->base;
9005 val = I915_READ(PLANE_CTL(pipe, 0));
9006 if (!(val & PLANE_CTL_ENABLE))
9009 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9010 fourcc = skl_format_to_fourcc(pixel_format,
9011 val & PLANE_CTL_ORDER_RGBX,
9012 val & PLANE_CTL_ALPHA_MASK);
9013 fb->pixel_format = fourcc;
9014 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9016 tiling = val & PLANE_CTL_TILED_MASK;
9018 case PLANE_CTL_TILED_LINEAR:
9019 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9021 case PLANE_CTL_TILED_X:
9022 plane_config->tiling = I915_TILING_X;
9023 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9025 case PLANE_CTL_TILED_Y:
9026 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9028 case PLANE_CTL_TILED_YF:
9029 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9032 MISSING_CASE(tiling);
9036 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9037 plane_config->base = base;
9039 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9041 val = I915_READ(PLANE_SIZE(pipe, 0));
9042 fb->height = ((val >> 16) & 0xfff) + 1;
9043 fb->width = ((val >> 0) & 0x1fff) + 1;
9045 val = I915_READ(PLANE_STRIDE(pipe, 0));
9046 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9048 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9050 aligned_height = intel_fb_align_height(dev, fb->height,
9054 plane_config->size = fb->pitches[0] * aligned_height;
9056 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9057 pipe_name(pipe), fb->width, fb->height,
9058 fb->bits_per_pixel, base, fb->pitches[0],
9059 plane_config->size);
9061 plane_config->fb = intel_fb;
9068 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9069 struct intel_crtc_state *pipe_config)
9071 struct drm_device *dev = crtc->base.dev;
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9075 tmp = I915_READ(PF_CTL(crtc->pipe));
9077 if (tmp & PF_ENABLE) {
9078 pipe_config->pch_pfit.enabled = true;
9079 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9080 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9082 /* We currently do not free assignements of panel fitters on
9083 * ivb/hsw (since we don't use the higher upscaling modes which
9084 * differentiates them) so just WARN about this case for now. */
9086 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9087 PF_PIPE_SEL_IVB(crtc->pipe));
9093 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9094 struct intel_initial_plane_config *plane_config)
9096 struct drm_device *dev = crtc->base.dev;
9097 struct drm_i915_private *dev_priv = dev->dev_private;
9098 u32 val, base, offset;
9099 int pipe = crtc->pipe;
9100 int fourcc, pixel_format;
9101 unsigned int aligned_height;
9102 struct drm_framebuffer *fb;
9103 struct intel_framebuffer *intel_fb;
9105 val = I915_READ(DSPCNTR(pipe));
9106 if (!(val & DISPLAY_PLANE_ENABLE))
9109 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9111 DRM_DEBUG_KMS("failed to alloc fb\n");
9115 fb = &intel_fb->base;
9117 if (INTEL_INFO(dev)->gen >= 4) {
9118 if (val & DISPPLANE_TILED) {
9119 plane_config->tiling = I915_TILING_X;
9120 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9124 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9125 fourcc = i9xx_format_to_fourcc(pixel_format);
9126 fb->pixel_format = fourcc;
9127 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9129 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9130 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9131 offset = I915_READ(DSPOFFSET(pipe));
9133 if (plane_config->tiling)
9134 offset = I915_READ(DSPTILEOFF(pipe));
9136 offset = I915_READ(DSPLINOFF(pipe));
9138 plane_config->base = base;
9140 val = I915_READ(PIPESRC(pipe));
9141 fb->width = ((val >> 16) & 0xfff) + 1;
9142 fb->height = ((val >> 0) & 0xfff) + 1;
9144 val = I915_READ(DSPSTRIDE(pipe));
9145 fb->pitches[0] = val & 0xffffffc0;
9147 aligned_height = intel_fb_align_height(dev, fb->height,
9151 plane_config->size = fb->pitches[0] * aligned_height;
9153 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9154 pipe_name(pipe), fb->width, fb->height,
9155 fb->bits_per_pixel, base, fb->pitches[0],
9156 plane_config->size);
9158 plane_config->fb = intel_fb;
9161 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9162 struct intel_crtc_state *pipe_config)
9164 struct drm_device *dev = crtc->base.dev;
9165 struct drm_i915_private *dev_priv = dev->dev_private;
9168 if (!intel_display_power_is_enabled(dev_priv,
9169 POWER_DOMAIN_PIPE(crtc->pipe)))
9172 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9173 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9175 tmp = I915_READ(PIPECONF(crtc->pipe));
9176 if (!(tmp & PIPECONF_ENABLE))
9179 switch (tmp & PIPECONF_BPC_MASK) {
9181 pipe_config->pipe_bpp = 18;
9184 pipe_config->pipe_bpp = 24;
9186 case PIPECONF_10BPC:
9187 pipe_config->pipe_bpp = 30;
9189 case PIPECONF_12BPC:
9190 pipe_config->pipe_bpp = 36;
9196 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9197 pipe_config->limited_color_range = true;
9199 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9200 struct intel_shared_dpll *pll;
9202 pipe_config->has_pch_encoder = true;
9204 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9205 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9206 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9208 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9210 if (HAS_PCH_IBX(dev_priv->dev)) {
9211 pipe_config->shared_dpll =
9212 (enum intel_dpll_id) crtc->pipe;
9214 tmp = I915_READ(PCH_DPLL_SEL);
9215 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9216 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9218 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9221 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9223 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9224 &pipe_config->dpll_hw_state));
9226 tmp = pipe_config->dpll_hw_state.dpll;
9227 pipe_config->pixel_multiplier =
9228 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9229 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9231 ironlake_pch_clock_get(crtc, pipe_config);
9233 pipe_config->pixel_multiplier = 1;
9236 intel_get_pipe_timings(crtc, pipe_config);
9238 ironlake_get_pfit_config(crtc, pipe_config);
9243 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9245 struct drm_device *dev = dev_priv->dev;
9246 struct intel_crtc *crtc;
9248 for_each_intel_crtc(dev, crtc)
9249 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9250 pipe_name(crtc->pipe));
9252 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9253 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9254 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9255 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9256 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9257 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9258 "CPU PWM1 enabled\n");
9259 if (IS_HASWELL(dev))
9260 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9261 "CPU PWM2 enabled\n");
9262 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9263 "PCH PWM1 enabled\n");
9264 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9265 "Utility pin enabled\n");
9266 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9269 * In theory we can still leave IRQs enabled, as long as only the HPD
9270 * interrupts remain enabled. We used to check for that, but since it's
9271 * gen-specific and since we only disable LCPLL after we fully disable
9272 * the interrupts, the check below should be enough.
9274 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9277 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9279 struct drm_device *dev = dev_priv->dev;
9281 if (IS_HASWELL(dev))
9282 return I915_READ(D_COMP_HSW);
9284 return I915_READ(D_COMP_BDW);
9287 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9289 struct drm_device *dev = dev_priv->dev;
9291 if (IS_HASWELL(dev)) {
9292 mutex_lock(&dev_priv->rps.hw_lock);
9293 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9295 DRM_ERROR("Failed to write to D_COMP\n");
9296 mutex_unlock(&dev_priv->rps.hw_lock);
9298 I915_WRITE(D_COMP_BDW, val);
9299 POSTING_READ(D_COMP_BDW);
9304 * This function implements pieces of two sequences from BSpec:
9305 * - Sequence for display software to disable LCPLL
9306 * - Sequence for display software to allow package C8+
9307 * The steps implemented here are just the steps that actually touch the LCPLL
9308 * register. Callers should take care of disabling all the display engine
9309 * functions, doing the mode unset, fixing interrupts, etc.
9311 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9312 bool switch_to_fclk, bool allow_power_down)
9316 assert_can_disable_lcpll(dev_priv);
9318 val = I915_READ(LCPLL_CTL);
9320 if (switch_to_fclk) {
9321 val |= LCPLL_CD_SOURCE_FCLK;
9322 I915_WRITE(LCPLL_CTL, val);
9324 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9325 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9326 DRM_ERROR("Switching to FCLK failed\n");
9328 val = I915_READ(LCPLL_CTL);
9331 val |= LCPLL_PLL_DISABLE;
9332 I915_WRITE(LCPLL_CTL, val);
9333 POSTING_READ(LCPLL_CTL);
9335 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9336 DRM_ERROR("LCPLL still locked\n");
9338 val = hsw_read_dcomp(dev_priv);
9339 val |= D_COMP_COMP_DISABLE;
9340 hsw_write_dcomp(dev_priv, val);
9343 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9345 DRM_ERROR("D_COMP RCOMP still in progress\n");
9347 if (allow_power_down) {
9348 val = I915_READ(LCPLL_CTL);
9349 val |= LCPLL_POWER_DOWN_ALLOW;
9350 I915_WRITE(LCPLL_CTL, val);
9351 POSTING_READ(LCPLL_CTL);
9356 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9359 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9363 val = I915_READ(LCPLL_CTL);
9365 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9366 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9370 * Make sure we're not on PC8 state before disabling PC8, otherwise
9371 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9373 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9375 if (val & LCPLL_POWER_DOWN_ALLOW) {
9376 val &= ~LCPLL_POWER_DOWN_ALLOW;
9377 I915_WRITE(LCPLL_CTL, val);
9378 POSTING_READ(LCPLL_CTL);
9381 val = hsw_read_dcomp(dev_priv);
9382 val |= D_COMP_COMP_FORCE;
9383 val &= ~D_COMP_COMP_DISABLE;
9384 hsw_write_dcomp(dev_priv, val);
9386 val = I915_READ(LCPLL_CTL);
9387 val &= ~LCPLL_PLL_DISABLE;
9388 I915_WRITE(LCPLL_CTL, val);
9390 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9391 DRM_ERROR("LCPLL not locked yet\n");
9393 if (val & LCPLL_CD_SOURCE_FCLK) {
9394 val = I915_READ(LCPLL_CTL);
9395 val &= ~LCPLL_CD_SOURCE_FCLK;
9396 I915_WRITE(LCPLL_CTL, val);
9398 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9399 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9400 DRM_ERROR("Switching back to LCPLL failed\n");
9403 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9404 intel_update_cdclk(dev_priv->dev);
9408 * Package states C8 and deeper are really deep PC states that can only be
9409 * reached when all the devices on the system allow it, so even if the graphics
9410 * device allows PC8+, it doesn't mean the system will actually get to these
9411 * states. Our driver only allows PC8+ when going into runtime PM.
9413 * The requirements for PC8+ are that all the outputs are disabled, the power
9414 * well is disabled and most interrupts are disabled, and these are also
9415 * requirements for runtime PM. When these conditions are met, we manually do
9416 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9417 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9420 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9421 * the state of some registers, so when we come back from PC8+ we need to
9422 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9423 * need to take care of the registers kept by RC6. Notice that this happens even
9424 * if we don't put the device in PCI D3 state (which is what currently happens
9425 * because of the runtime PM support).
9427 * For more, read "Display Sequences for Package C8" on the hardware
9430 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9432 struct drm_device *dev = dev_priv->dev;
9435 DRM_DEBUG_KMS("Enabling package C8+\n");
9437 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9438 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9439 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9440 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9443 lpt_disable_clkout_dp(dev);
9444 hsw_disable_lcpll(dev_priv, true, true);
9447 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9449 struct drm_device *dev = dev_priv->dev;
9452 DRM_DEBUG_KMS("Disabling package C8+\n");
9454 hsw_restore_lcpll(dev_priv);
9455 lpt_init_pch_refclk(dev);
9457 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9458 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9459 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9460 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9463 intel_prepare_ddi(dev);
9466 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9468 struct drm_device *dev = old_state->dev;
9469 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9471 broxton_set_cdclk(dev, req_cdclk);
9474 /* compute the max rate for new configuration */
9475 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9477 struct intel_crtc *intel_crtc;
9478 struct intel_crtc_state *crtc_state;
9479 int max_pixel_rate = 0;
9481 for_each_intel_crtc(state->dev, intel_crtc) {
9484 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9485 if (IS_ERR(crtc_state))
9486 return PTR_ERR(crtc_state);
9488 if (!crtc_state->base.enable)
9491 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9493 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9494 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9495 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9497 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9500 return max_pixel_rate;
9503 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9509 if (WARN((I915_READ(LCPLL_CTL) &
9510 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9511 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9512 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9513 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9514 "trying to change cdclk frequency with cdclk not enabled\n"))
9517 mutex_lock(&dev_priv->rps.hw_lock);
9518 ret = sandybridge_pcode_write(dev_priv,
9519 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9520 mutex_unlock(&dev_priv->rps.hw_lock);
9522 DRM_ERROR("failed to inform pcode about cdclk change\n");
9526 val = I915_READ(LCPLL_CTL);
9527 val |= LCPLL_CD_SOURCE_FCLK;
9528 I915_WRITE(LCPLL_CTL, val);
9530 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9531 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9532 DRM_ERROR("Switching to FCLK failed\n");
9534 val = I915_READ(LCPLL_CTL);
9535 val &= ~LCPLL_CLK_FREQ_MASK;
9539 val |= LCPLL_CLK_FREQ_450;
9543 val |= LCPLL_CLK_FREQ_54O_BDW;
9547 val |= LCPLL_CLK_FREQ_337_5_BDW;
9551 val |= LCPLL_CLK_FREQ_675_BDW;
9555 WARN(1, "invalid cdclk frequency\n");
9559 I915_WRITE(LCPLL_CTL, val);
9561 val = I915_READ(LCPLL_CTL);
9562 val &= ~LCPLL_CD_SOURCE_FCLK;
9563 I915_WRITE(LCPLL_CTL, val);
9565 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9566 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9567 DRM_ERROR("Switching back to LCPLL failed\n");
9569 mutex_lock(&dev_priv->rps.hw_lock);
9570 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9571 mutex_unlock(&dev_priv->rps.hw_lock);
9573 intel_update_cdclk(dev);
9575 WARN(cdclk != dev_priv->cdclk_freq,
9576 "cdclk requested %d kHz but got %d kHz\n",
9577 cdclk, dev_priv->cdclk_freq);
9580 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9582 struct drm_i915_private *dev_priv = to_i915(state->dev);
9583 int max_pixclk = ilk_max_pixel_rate(state);
9587 * FIXME should also account for plane ratio
9588 * once 64bpp pixel formats are supported.
9590 if (max_pixclk > 540000)
9592 else if (max_pixclk > 450000)
9594 else if (max_pixclk > 337500)
9600 * FIXME move the cdclk caclulation to
9601 * compute_config() so we can fail gracegully.
9603 if (cdclk > dev_priv->max_cdclk_freq) {
9604 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9605 cdclk, dev_priv->max_cdclk_freq);
9606 cdclk = dev_priv->max_cdclk_freq;
9609 to_intel_atomic_state(state)->cdclk = cdclk;
9614 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9616 struct drm_device *dev = old_state->dev;
9617 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9619 broadwell_set_cdclk(dev, req_cdclk);
9622 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9623 struct intel_crtc_state *crtc_state)
9625 if (!intel_ddi_pll_select(crtc, crtc_state))
9628 crtc->lowfreq_avail = false;
9633 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9635 struct intel_crtc_state *pipe_config)
9639 pipe_config->ddi_pll_sel = SKL_DPLL0;
9640 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9643 pipe_config->ddi_pll_sel = SKL_DPLL1;
9644 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9647 pipe_config->ddi_pll_sel = SKL_DPLL2;
9648 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9651 DRM_ERROR("Incorrect port type\n");
9655 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9657 struct intel_crtc_state *pipe_config)
9659 u32 temp, dpll_ctl1;
9661 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9662 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9664 switch (pipe_config->ddi_pll_sel) {
9667 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9668 * of the shared DPLL framework and thus needs to be read out
9671 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9672 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9675 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9678 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9681 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9686 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9688 struct intel_crtc_state *pipe_config)
9690 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9692 switch (pipe_config->ddi_pll_sel) {
9693 case PORT_CLK_SEL_WRPLL1:
9694 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9696 case PORT_CLK_SEL_WRPLL2:
9697 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9702 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9703 struct intel_crtc_state *pipe_config)
9705 struct drm_device *dev = crtc->base.dev;
9706 struct drm_i915_private *dev_priv = dev->dev_private;
9707 struct intel_shared_dpll *pll;
9711 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9713 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9715 if (IS_SKYLAKE(dev))
9716 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9717 else if (IS_BROXTON(dev))
9718 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9720 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9722 if (pipe_config->shared_dpll >= 0) {
9723 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9725 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9726 &pipe_config->dpll_hw_state));
9730 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9731 * DDI E. So just check whether this pipe is wired to DDI E and whether
9732 * the PCH transcoder is on.
9734 if (INTEL_INFO(dev)->gen < 9 &&
9735 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9736 pipe_config->has_pch_encoder = true;
9738 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9739 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9740 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9742 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9746 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9747 struct intel_crtc_state *pipe_config)
9749 struct drm_device *dev = crtc->base.dev;
9750 struct drm_i915_private *dev_priv = dev->dev_private;
9751 enum intel_display_power_domain pfit_domain;
9754 if (!intel_display_power_is_enabled(dev_priv,
9755 POWER_DOMAIN_PIPE(crtc->pipe)))
9758 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9759 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9761 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9762 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9763 enum pipe trans_edp_pipe;
9764 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9766 WARN(1, "unknown pipe linked to edp transcoder\n");
9767 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9768 case TRANS_DDI_EDP_INPUT_A_ON:
9769 trans_edp_pipe = PIPE_A;
9771 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9772 trans_edp_pipe = PIPE_B;
9774 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9775 trans_edp_pipe = PIPE_C;
9779 if (trans_edp_pipe == crtc->pipe)
9780 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9783 if (!intel_display_power_is_enabled(dev_priv,
9784 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9787 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9788 if (!(tmp & PIPECONF_ENABLE))
9791 haswell_get_ddi_port_state(crtc, pipe_config);
9793 intel_get_pipe_timings(crtc, pipe_config);
9795 if (INTEL_INFO(dev)->gen >= 9) {
9796 skl_init_scalers(dev, crtc, pipe_config);
9799 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9801 if (INTEL_INFO(dev)->gen >= 9) {
9802 pipe_config->scaler_state.scaler_id = -1;
9803 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9806 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9807 if (INTEL_INFO(dev)->gen == 9)
9808 skylake_get_pfit_config(crtc, pipe_config);
9809 else if (INTEL_INFO(dev)->gen < 9)
9810 ironlake_get_pfit_config(crtc, pipe_config);
9812 MISSING_CASE(INTEL_INFO(dev)->gen);
9815 if (IS_HASWELL(dev))
9816 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9817 (I915_READ(IPS_CTL) & IPS_ENABLE);
9819 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9820 pipe_config->pixel_multiplier =
9821 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9823 pipe_config->pixel_multiplier = 1;
9829 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9831 struct drm_device *dev = crtc->dev;
9832 struct drm_i915_private *dev_priv = dev->dev_private;
9833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9834 uint32_t cntl = 0, size = 0;
9837 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9838 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9839 unsigned int stride = roundup_pow_of_two(width) * 4;
9843 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9854 cntl |= CURSOR_ENABLE |
9855 CURSOR_GAMMA_ENABLE |
9856 CURSOR_FORMAT_ARGB |
9857 CURSOR_STRIDE(stride);
9859 size = (height << 12) | width;
9862 if (intel_crtc->cursor_cntl != 0 &&
9863 (intel_crtc->cursor_base != base ||
9864 intel_crtc->cursor_size != size ||
9865 intel_crtc->cursor_cntl != cntl)) {
9866 /* On these chipsets we can only modify the base/size/stride
9867 * whilst the cursor is disabled.
9869 I915_WRITE(_CURACNTR, 0);
9870 POSTING_READ(_CURACNTR);
9871 intel_crtc->cursor_cntl = 0;
9874 if (intel_crtc->cursor_base != base) {
9875 I915_WRITE(_CURABASE, base);
9876 intel_crtc->cursor_base = base;
9879 if (intel_crtc->cursor_size != size) {
9880 I915_WRITE(CURSIZE, size);
9881 intel_crtc->cursor_size = size;
9884 if (intel_crtc->cursor_cntl != cntl) {
9885 I915_WRITE(_CURACNTR, cntl);
9886 POSTING_READ(_CURACNTR);
9887 intel_crtc->cursor_cntl = cntl;
9891 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9893 struct drm_device *dev = crtc->dev;
9894 struct drm_i915_private *dev_priv = dev->dev_private;
9895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9896 int pipe = intel_crtc->pipe;
9901 cntl = MCURSOR_GAMMA_ENABLE;
9902 switch (intel_crtc->base.cursor->state->crtc_w) {
9904 cntl |= CURSOR_MODE_64_ARGB_AX;
9907 cntl |= CURSOR_MODE_128_ARGB_AX;
9910 cntl |= CURSOR_MODE_256_ARGB_AX;
9913 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9916 cntl |= pipe << 28; /* Connect to correct pipe */
9918 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9919 cntl |= CURSOR_PIPE_CSC_ENABLE;
9922 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9923 cntl |= CURSOR_ROTATE_180;
9925 if (intel_crtc->cursor_cntl != cntl) {
9926 I915_WRITE(CURCNTR(pipe), cntl);
9927 POSTING_READ(CURCNTR(pipe));
9928 intel_crtc->cursor_cntl = cntl;
9931 /* and commit changes on next vblank */
9932 I915_WRITE(CURBASE(pipe), base);
9933 POSTING_READ(CURBASE(pipe));
9935 intel_crtc->cursor_base = base;
9938 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9939 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9942 struct drm_device *dev = crtc->dev;
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9945 int pipe = intel_crtc->pipe;
9946 int x = crtc->cursor_x;
9947 int y = crtc->cursor_y;
9948 u32 base = 0, pos = 0;
9951 base = intel_crtc->cursor_addr;
9953 if (x >= intel_crtc->config->pipe_src_w)
9956 if (y >= intel_crtc->config->pipe_src_h)
9960 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9963 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9966 pos |= x << CURSOR_X_SHIFT;
9969 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9972 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9975 pos |= y << CURSOR_Y_SHIFT;
9977 if (base == 0 && intel_crtc->cursor_base == 0)
9980 I915_WRITE(CURPOS(pipe), pos);
9982 /* ILK+ do this automagically */
9983 if (HAS_GMCH_DISPLAY(dev) &&
9984 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9985 base += (intel_crtc->base.cursor->state->crtc_h *
9986 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9989 if (IS_845G(dev) || IS_I865G(dev))
9990 i845_update_cursor(crtc, base);
9992 i9xx_update_cursor(crtc, base);
9995 static bool cursor_size_ok(struct drm_device *dev,
9996 uint32_t width, uint32_t height)
9998 if (width == 0 || height == 0)
10002 * 845g/865g are special in that they are only limited by
10003 * the width of their cursors, the height is arbitrary up to
10004 * the precision of the register. Everything else requires
10005 * square cursors, limited to a few power-of-two sizes.
10007 if (IS_845G(dev) || IS_I865G(dev)) {
10008 if ((width & 63) != 0)
10011 if (width > (IS_845G(dev) ? 64 : 512))
10017 switch (width | height) {
10032 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10033 u16 *blue, uint32_t start, uint32_t size)
10035 int end = (start + size > 256) ? 256 : start + size, i;
10036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10038 for (i = start; i < end; i++) {
10039 intel_crtc->lut_r[i] = red[i] >> 8;
10040 intel_crtc->lut_g[i] = green[i] >> 8;
10041 intel_crtc->lut_b[i] = blue[i] >> 8;
10044 intel_crtc_load_lut(crtc);
10047 /* VESA 640x480x72Hz mode to set on the pipe */
10048 static struct drm_display_mode load_detect_mode = {
10049 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10050 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10053 struct drm_framebuffer *
10054 __intel_framebuffer_create(struct drm_device *dev,
10055 struct drm_mode_fb_cmd2 *mode_cmd,
10056 struct drm_i915_gem_object *obj)
10058 struct intel_framebuffer *intel_fb;
10061 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10063 drm_gem_object_unreference(&obj->base);
10064 return ERR_PTR(-ENOMEM);
10067 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10071 return &intel_fb->base;
10073 drm_gem_object_unreference(&obj->base);
10076 return ERR_PTR(ret);
10079 static struct drm_framebuffer *
10080 intel_framebuffer_create(struct drm_device *dev,
10081 struct drm_mode_fb_cmd2 *mode_cmd,
10082 struct drm_i915_gem_object *obj)
10084 struct drm_framebuffer *fb;
10087 ret = i915_mutex_lock_interruptible(dev);
10089 return ERR_PTR(ret);
10090 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10091 mutex_unlock(&dev->struct_mutex);
10097 intel_framebuffer_pitch_for_width(int width, int bpp)
10099 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10100 return ALIGN(pitch, 64);
10104 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10106 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10107 return PAGE_ALIGN(pitch * mode->vdisplay);
10110 static struct drm_framebuffer *
10111 intel_framebuffer_create_for_mode(struct drm_device *dev,
10112 struct drm_display_mode *mode,
10113 int depth, int bpp)
10115 struct drm_i915_gem_object *obj;
10116 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10118 obj = i915_gem_alloc_object(dev,
10119 intel_framebuffer_size_for_mode(mode, bpp));
10121 return ERR_PTR(-ENOMEM);
10123 mode_cmd.width = mode->hdisplay;
10124 mode_cmd.height = mode->vdisplay;
10125 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10127 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10129 return intel_framebuffer_create(dev, &mode_cmd, obj);
10132 static struct drm_framebuffer *
10133 mode_fits_in_fbdev(struct drm_device *dev,
10134 struct drm_display_mode *mode)
10136 #ifdef CONFIG_DRM_I915_FBDEV
10137 struct drm_i915_private *dev_priv = dev->dev_private;
10138 struct drm_i915_gem_object *obj;
10139 struct drm_framebuffer *fb;
10141 if (!dev_priv->fbdev)
10144 if (!dev_priv->fbdev->fb)
10147 obj = dev_priv->fbdev->fb->obj;
10150 fb = &dev_priv->fbdev->fb->base;
10151 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10152 fb->bits_per_pixel))
10155 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10164 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10165 struct drm_crtc *crtc,
10166 struct drm_display_mode *mode,
10167 struct drm_framebuffer *fb,
10170 struct drm_plane_state *plane_state;
10171 int hdisplay, vdisplay;
10174 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10175 if (IS_ERR(plane_state))
10176 return PTR_ERR(plane_state);
10179 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10181 hdisplay = vdisplay = 0;
10183 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10186 drm_atomic_set_fb_for_plane(plane_state, fb);
10187 plane_state->crtc_x = 0;
10188 plane_state->crtc_y = 0;
10189 plane_state->crtc_w = hdisplay;
10190 plane_state->crtc_h = vdisplay;
10191 plane_state->src_x = x << 16;
10192 plane_state->src_y = y << 16;
10193 plane_state->src_w = hdisplay << 16;
10194 plane_state->src_h = vdisplay << 16;
10199 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10200 struct drm_display_mode *mode,
10201 struct intel_load_detect_pipe *old,
10202 struct drm_modeset_acquire_ctx *ctx)
10204 struct intel_crtc *intel_crtc;
10205 struct intel_encoder *intel_encoder =
10206 intel_attached_encoder(connector);
10207 struct drm_crtc *possible_crtc;
10208 struct drm_encoder *encoder = &intel_encoder->base;
10209 struct drm_crtc *crtc = NULL;
10210 struct drm_device *dev = encoder->dev;
10211 struct drm_framebuffer *fb;
10212 struct drm_mode_config *config = &dev->mode_config;
10213 struct drm_atomic_state *state = NULL;
10214 struct drm_connector_state *connector_state;
10215 struct intel_crtc_state *crtc_state;
10218 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10219 connector->base.id, connector->name,
10220 encoder->base.id, encoder->name);
10223 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10228 * Algorithm gets a little messy:
10230 * - if the connector already has an assigned crtc, use it (but make
10231 * sure it's on first)
10233 * - try to find the first unused crtc that can drive this connector,
10234 * and use that if we find one
10237 /* See if we already have a CRTC for this connector */
10238 if (encoder->crtc) {
10239 crtc = encoder->crtc;
10241 ret = drm_modeset_lock(&crtc->mutex, ctx);
10244 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10248 old->dpms_mode = connector->dpms;
10249 old->load_detect_temp = false;
10251 /* Make sure the crtc and connector are running */
10252 if (connector->dpms != DRM_MODE_DPMS_ON)
10253 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10258 /* Find an unused one (if possible) */
10259 for_each_crtc(dev, possible_crtc) {
10261 if (!(encoder->possible_crtcs & (1 << i)))
10263 if (possible_crtc->state->enable)
10265 /* This can occur when applying the pipe A quirk on resume. */
10266 if (to_intel_crtc(possible_crtc)->new_enabled)
10269 crtc = possible_crtc;
10274 * If we didn't find an unused CRTC, don't use any.
10277 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10281 ret = drm_modeset_lock(&crtc->mutex, ctx);
10284 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10287 intel_encoder->new_crtc = to_intel_crtc(crtc);
10288 to_intel_connector(connector)->new_encoder = intel_encoder;
10290 intel_crtc = to_intel_crtc(crtc);
10291 intel_crtc->new_enabled = true;
10292 old->dpms_mode = connector->dpms;
10293 old->load_detect_temp = true;
10294 old->release_fb = NULL;
10296 state = drm_atomic_state_alloc(dev);
10300 state->acquire_ctx = ctx;
10302 connector_state = drm_atomic_get_connector_state(state, connector);
10303 if (IS_ERR(connector_state)) {
10304 ret = PTR_ERR(connector_state);
10308 connector_state->crtc = crtc;
10309 connector_state->best_encoder = &intel_encoder->base;
10311 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10312 if (IS_ERR(crtc_state)) {
10313 ret = PTR_ERR(crtc_state);
10317 crtc_state->base.active = crtc_state->base.enable = true;
10320 mode = &load_detect_mode;
10322 /* We need a framebuffer large enough to accommodate all accesses
10323 * that the plane may generate whilst we perform load detection.
10324 * We can not rely on the fbcon either being present (we get called
10325 * during its initialisation to detect all boot displays, or it may
10326 * not even exist) or that it is large enough to satisfy the
10329 fb = mode_fits_in_fbdev(dev, mode);
10331 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10332 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10333 old->release_fb = fb;
10335 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10337 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10341 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10345 drm_mode_copy(&crtc_state->base.mode, mode);
10347 if (intel_set_mode(state)) {
10348 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10349 if (old->release_fb)
10350 old->release_fb->funcs->destroy(old->release_fb);
10353 crtc->primary->crtc = crtc;
10355 /* let the connector get through one full cycle before testing */
10356 intel_wait_for_vblank(dev, intel_crtc->pipe);
10360 intel_crtc->new_enabled = crtc->state->enable;
10362 drm_atomic_state_free(state);
10365 if (ret == -EDEADLK) {
10366 drm_modeset_backoff(ctx);
10373 void intel_release_load_detect_pipe(struct drm_connector *connector,
10374 struct intel_load_detect_pipe *old,
10375 struct drm_modeset_acquire_ctx *ctx)
10377 struct drm_device *dev = connector->dev;
10378 struct intel_encoder *intel_encoder =
10379 intel_attached_encoder(connector);
10380 struct drm_encoder *encoder = &intel_encoder->base;
10381 struct drm_crtc *crtc = encoder->crtc;
10382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10383 struct drm_atomic_state *state;
10384 struct drm_connector_state *connector_state;
10385 struct intel_crtc_state *crtc_state;
10388 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10389 connector->base.id, connector->name,
10390 encoder->base.id, encoder->name);
10392 if (old->load_detect_temp) {
10393 state = drm_atomic_state_alloc(dev);
10397 state->acquire_ctx = ctx;
10399 connector_state = drm_atomic_get_connector_state(state, connector);
10400 if (IS_ERR(connector_state))
10403 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10404 if (IS_ERR(crtc_state))
10407 to_intel_connector(connector)->new_encoder = NULL;
10408 intel_encoder->new_crtc = NULL;
10409 intel_crtc->new_enabled = false;
10411 connector_state->best_encoder = NULL;
10412 connector_state->crtc = NULL;
10414 crtc_state->base.enable = crtc_state->base.active = false;
10416 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10421 ret = intel_set_mode(state);
10425 if (old->release_fb) {
10426 drm_framebuffer_unregister_private(old->release_fb);
10427 drm_framebuffer_unreference(old->release_fb);
10433 /* Switch crtc and encoder back off if necessary */
10434 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10435 connector->funcs->dpms(connector, old->dpms_mode);
10439 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10440 drm_atomic_state_free(state);
10443 static int i9xx_pll_refclk(struct drm_device *dev,
10444 const struct intel_crtc_state *pipe_config)
10446 struct drm_i915_private *dev_priv = dev->dev_private;
10447 u32 dpll = pipe_config->dpll_hw_state.dpll;
10449 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10450 return dev_priv->vbt.lvds_ssc_freq;
10451 else if (HAS_PCH_SPLIT(dev))
10453 else if (!IS_GEN2(dev))
10459 /* Returns the clock of the currently programmed mode of the given pipe. */
10460 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10461 struct intel_crtc_state *pipe_config)
10463 struct drm_device *dev = crtc->base.dev;
10464 struct drm_i915_private *dev_priv = dev->dev_private;
10465 int pipe = pipe_config->cpu_transcoder;
10466 u32 dpll = pipe_config->dpll_hw_state.dpll;
10468 intel_clock_t clock;
10470 int refclk = i9xx_pll_refclk(dev, pipe_config);
10472 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10473 fp = pipe_config->dpll_hw_state.fp0;
10475 fp = pipe_config->dpll_hw_state.fp1;
10477 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10478 if (IS_PINEVIEW(dev)) {
10479 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10480 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10482 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10483 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10486 if (!IS_GEN2(dev)) {
10487 if (IS_PINEVIEW(dev))
10488 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10489 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10491 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10492 DPLL_FPA01_P1_POST_DIV_SHIFT);
10494 switch (dpll & DPLL_MODE_MASK) {
10495 case DPLLB_MODE_DAC_SERIAL:
10496 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10499 case DPLLB_MODE_LVDS:
10500 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10504 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10505 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10509 if (IS_PINEVIEW(dev))
10510 port_clock = pnv_calc_dpll_params(refclk, &clock);
10512 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10514 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10515 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10518 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10519 DPLL_FPA01_P1_POST_DIV_SHIFT);
10521 if (lvds & LVDS_CLKB_POWER_UP)
10526 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10529 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10530 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10532 if (dpll & PLL_P2_DIVIDE_BY_4)
10538 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10542 * This value includes pixel_multiplier. We will use
10543 * port_clock to compute adjusted_mode.crtc_clock in the
10544 * encoder's get_config() function.
10546 pipe_config->port_clock = port_clock;
10549 int intel_dotclock_calculate(int link_freq,
10550 const struct intel_link_m_n *m_n)
10553 * The calculation for the data clock is:
10554 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10555 * But we want to avoid losing precison if possible, so:
10556 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10558 * and the link clock is simpler:
10559 * link_clock = (m * link_clock) / n
10565 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10568 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10569 struct intel_crtc_state *pipe_config)
10571 struct drm_device *dev = crtc->base.dev;
10573 /* read out port_clock from the DPLL */
10574 i9xx_crtc_clock_get(crtc, pipe_config);
10577 * This value does not include pixel_multiplier.
10578 * We will check that port_clock and adjusted_mode.crtc_clock
10579 * agree once we know their relationship in the encoder's
10580 * get_config() function.
10582 pipe_config->base.adjusted_mode.crtc_clock =
10583 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10584 &pipe_config->fdi_m_n);
10587 /** Returns the currently programmed mode of the given pipe. */
10588 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10589 struct drm_crtc *crtc)
10591 struct drm_i915_private *dev_priv = dev->dev_private;
10592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10593 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10594 struct drm_display_mode *mode;
10595 struct intel_crtc_state pipe_config;
10596 int htot = I915_READ(HTOTAL(cpu_transcoder));
10597 int hsync = I915_READ(HSYNC(cpu_transcoder));
10598 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10599 int vsync = I915_READ(VSYNC(cpu_transcoder));
10600 enum pipe pipe = intel_crtc->pipe;
10602 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10607 * Construct a pipe_config sufficient for getting the clock info
10608 * back out of crtc_clock_get.
10610 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10611 * to use a real value here instead.
10613 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10614 pipe_config.pixel_multiplier = 1;
10615 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10616 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10617 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10618 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10620 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10621 mode->hdisplay = (htot & 0xffff) + 1;
10622 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10623 mode->hsync_start = (hsync & 0xffff) + 1;
10624 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10625 mode->vdisplay = (vtot & 0xffff) + 1;
10626 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10627 mode->vsync_start = (vsync & 0xffff) + 1;
10628 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10630 drm_mode_set_name(mode);
10635 void intel_mark_busy(struct drm_device *dev)
10637 struct drm_i915_private *dev_priv = dev->dev_private;
10639 if (dev_priv->mm.busy)
10642 intel_runtime_pm_get(dev_priv);
10643 i915_update_gfx_val(dev_priv);
10644 if (INTEL_INFO(dev)->gen >= 6)
10645 gen6_rps_busy(dev_priv);
10646 dev_priv->mm.busy = true;
10649 void intel_mark_idle(struct drm_device *dev)
10651 struct drm_i915_private *dev_priv = dev->dev_private;
10653 if (!dev_priv->mm.busy)
10656 dev_priv->mm.busy = false;
10658 if (INTEL_INFO(dev)->gen >= 6)
10659 gen6_rps_idle(dev->dev_private);
10661 intel_runtime_pm_put(dev_priv);
10664 static void intel_crtc_destroy(struct drm_crtc *crtc)
10666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10667 struct drm_device *dev = crtc->dev;
10668 struct intel_unpin_work *work;
10670 spin_lock_irq(&dev->event_lock);
10671 work = intel_crtc->unpin_work;
10672 intel_crtc->unpin_work = NULL;
10673 spin_unlock_irq(&dev->event_lock);
10676 cancel_work_sync(&work->work);
10680 drm_crtc_cleanup(crtc);
10685 static void intel_unpin_work_fn(struct work_struct *__work)
10687 struct intel_unpin_work *work =
10688 container_of(__work, struct intel_unpin_work, work);
10689 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10690 struct drm_device *dev = crtc->base.dev;
10691 struct drm_plane *primary = crtc->base.primary;
10693 mutex_lock(&dev->struct_mutex);
10694 intel_unpin_fb_obj(work->old_fb, primary->state);
10695 drm_gem_object_unreference(&work->pending_flip_obj->base);
10697 intel_fbc_update(dev);
10699 if (work->flip_queued_req)
10700 i915_gem_request_assign(&work->flip_queued_req, NULL);
10701 mutex_unlock(&dev->struct_mutex);
10703 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10704 drm_framebuffer_unreference(work->old_fb);
10706 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10707 atomic_dec(&crtc->unpin_work_count);
10712 static void do_intel_finish_page_flip(struct drm_device *dev,
10713 struct drm_crtc *crtc)
10715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10716 struct intel_unpin_work *work;
10717 unsigned long flags;
10719 /* Ignore early vblank irqs */
10720 if (intel_crtc == NULL)
10724 * This is called both by irq handlers and the reset code (to complete
10725 * lost pageflips) so needs the full irqsave spinlocks.
10727 spin_lock_irqsave(&dev->event_lock, flags);
10728 work = intel_crtc->unpin_work;
10730 /* Ensure we don't miss a work->pending update ... */
10733 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10734 spin_unlock_irqrestore(&dev->event_lock, flags);
10738 page_flip_completed(intel_crtc);
10740 spin_unlock_irqrestore(&dev->event_lock, flags);
10743 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10745 struct drm_i915_private *dev_priv = dev->dev_private;
10746 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10748 do_intel_finish_page_flip(dev, crtc);
10751 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10753 struct drm_i915_private *dev_priv = dev->dev_private;
10754 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10756 do_intel_finish_page_flip(dev, crtc);
10759 /* Is 'a' after or equal to 'b'? */
10760 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10762 return !((a - b) & 0x80000000);
10765 static bool page_flip_finished(struct intel_crtc *crtc)
10767 struct drm_device *dev = crtc->base.dev;
10768 struct drm_i915_private *dev_priv = dev->dev_private;
10770 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10771 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10775 * The relevant registers doen't exist on pre-ctg.
10776 * As the flip done interrupt doesn't trigger for mmio
10777 * flips on gmch platforms, a flip count check isn't
10778 * really needed there. But since ctg has the registers,
10779 * include it in the check anyway.
10781 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10785 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10786 * used the same base address. In that case the mmio flip might
10787 * have completed, but the CS hasn't even executed the flip yet.
10789 * A flip count check isn't enough as the CS might have updated
10790 * the base address just after start of vblank, but before we
10791 * managed to process the interrupt. This means we'd complete the
10792 * CS flip too soon.
10794 * Combining both checks should get us a good enough result. It may
10795 * still happen that the CS flip has been executed, but has not
10796 * yet actually completed. But in case the base address is the same
10797 * anyway, we don't really care.
10799 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10800 crtc->unpin_work->gtt_offset &&
10801 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10802 crtc->unpin_work->flip_count);
10805 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10807 struct drm_i915_private *dev_priv = dev->dev_private;
10808 struct intel_crtc *intel_crtc =
10809 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10810 unsigned long flags;
10814 * This is called both by irq handlers and the reset code (to complete
10815 * lost pageflips) so needs the full irqsave spinlocks.
10817 * NB: An MMIO update of the plane base pointer will also
10818 * generate a page-flip completion irq, i.e. every modeset
10819 * is also accompanied by a spurious intel_prepare_page_flip().
10821 spin_lock_irqsave(&dev->event_lock, flags);
10822 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10823 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10824 spin_unlock_irqrestore(&dev->event_lock, flags);
10827 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10829 /* Ensure that the work item is consistent when activating it ... */
10831 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10832 /* and that it is marked active as soon as the irq could fire. */
10836 static int intel_gen2_queue_flip(struct drm_device *dev,
10837 struct drm_crtc *crtc,
10838 struct drm_framebuffer *fb,
10839 struct drm_i915_gem_object *obj,
10840 struct drm_i915_gem_request *req,
10843 struct intel_engine_cs *ring = req->ring;
10844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10848 ret = intel_ring_begin(req, 6);
10852 /* Can't queue multiple flips, so wait for the previous
10853 * one to finish before executing the next.
10855 if (intel_crtc->plane)
10856 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10858 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10859 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10860 intel_ring_emit(ring, MI_NOOP);
10861 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10862 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10863 intel_ring_emit(ring, fb->pitches[0]);
10864 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10865 intel_ring_emit(ring, 0); /* aux display base address, unused */
10867 intel_mark_page_flip_active(intel_crtc);
10871 static int intel_gen3_queue_flip(struct drm_device *dev,
10872 struct drm_crtc *crtc,
10873 struct drm_framebuffer *fb,
10874 struct drm_i915_gem_object *obj,
10875 struct drm_i915_gem_request *req,
10878 struct intel_engine_cs *ring = req->ring;
10879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10883 ret = intel_ring_begin(req, 6);
10887 if (intel_crtc->plane)
10888 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10890 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10891 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10892 intel_ring_emit(ring, MI_NOOP);
10893 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10894 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10895 intel_ring_emit(ring, fb->pitches[0]);
10896 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10897 intel_ring_emit(ring, MI_NOOP);
10899 intel_mark_page_flip_active(intel_crtc);
10903 static int intel_gen4_queue_flip(struct drm_device *dev,
10904 struct drm_crtc *crtc,
10905 struct drm_framebuffer *fb,
10906 struct drm_i915_gem_object *obj,
10907 struct drm_i915_gem_request *req,
10910 struct intel_engine_cs *ring = req->ring;
10911 struct drm_i915_private *dev_priv = dev->dev_private;
10912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10913 uint32_t pf, pipesrc;
10916 ret = intel_ring_begin(req, 4);
10920 /* i965+ uses the linear or tiled offsets from the
10921 * Display Registers (which do not change across a page-flip)
10922 * so we need only reprogram the base address.
10924 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10925 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10926 intel_ring_emit(ring, fb->pitches[0]);
10927 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10930 /* XXX Enabling the panel-fitter across page-flip is so far
10931 * untested on non-native modes, so ignore it for now.
10932 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10935 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10936 intel_ring_emit(ring, pf | pipesrc);
10938 intel_mark_page_flip_active(intel_crtc);
10942 static int intel_gen6_queue_flip(struct drm_device *dev,
10943 struct drm_crtc *crtc,
10944 struct drm_framebuffer *fb,
10945 struct drm_i915_gem_object *obj,
10946 struct drm_i915_gem_request *req,
10949 struct intel_engine_cs *ring = req->ring;
10950 struct drm_i915_private *dev_priv = dev->dev_private;
10951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10952 uint32_t pf, pipesrc;
10955 ret = intel_ring_begin(req, 4);
10959 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10960 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10961 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10962 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10964 /* Contrary to the suggestions in the documentation,
10965 * "Enable Panel Fitter" does not seem to be required when page
10966 * flipping with a non-native mode, and worse causes a normal
10968 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10971 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10972 intel_ring_emit(ring, pf | pipesrc);
10974 intel_mark_page_flip_active(intel_crtc);
10978 static int intel_gen7_queue_flip(struct drm_device *dev,
10979 struct drm_crtc *crtc,
10980 struct drm_framebuffer *fb,
10981 struct drm_i915_gem_object *obj,
10982 struct drm_i915_gem_request *req,
10985 struct intel_engine_cs *ring = req->ring;
10986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10987 uint32_t plane_bit = 0;
10990 switch (intel_crtc->plane) {
10992 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10995 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10998 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11001 WARN_ONCE(1, "unknown plane in flip command\n");
11006 if (ring->id == RCS) {
11009 * On Gen 8, SRM is now taking an extra dword to accommodate
11010 * 48bits addresses, and we need a NOOP for the batch size to
11018 * BSpec MI_DISPLAY_FLIP for IVB:
11019 * "The full packet must be contained within the same cache line."
11021 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11022 * cacheline, if we ever start emitting more commands before
11023 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11024 * then do the cacheline alignment, and finally emit the
11027 ret = intel_ring_cacheline_align(req);
11031 ret = intel_ring_begin(req, len);
11035 /* Unmask the flip-done completion message. Note that the bspec says that
11036 * we should do this for both the BCS and RCS, and that we must not unmask
11037 * more than one flip event at any time (or ensure that one flip message
11038 * can be sent by waiting for flip-done prior to queueing new flips).
11039 * Experimentation says that BCS works despite DERRMR masking all
11040 * flip-done completion events and that unmasking all planes at once
11041 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11042 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11044 if (ring->id == RCS) {
11045 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11046 intel_ring_emit(ring, DERRMR);
11047 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11048 DERRMR_PIPEB_PRI_FLIP_DONE |
11049 DERRMR_PIPEC_PRI_FLIP_DONE));
11051 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11052 MI_SRM_LRM_GLOBAL_GTT);
11054 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11055 MI_SRM_LRM_GLOBAL_GTT);
11056 intel_ring_emit(ring, DERRMR);
11057 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11058 if (IS_GEN8(dev)) {
11059 intel_ring_emit(ring, 0);
11060 intel_ring_emit(ring, MI_NOOP);
11064 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11065 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11066 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11067 intel_ring_emit(ring, (MI_NOOP));
11069 intel_mark_page_flip_active(intel_crtc);
11073 static bool use_mmio_flip(struct intel_engine_cs *ring,
11074 struct drm_i915_gem_object *obj)
11077 * This is not being used for older platforms, because
11078 * non-availability of flip done interrupt forces us to use
11079 * CS flips. Older platforms derive flip done using some clever
11080 * tricks involving the flip_pending status bits and vblank irqs.
11081 * So using MMIO flips there would disrupt this mechanism.
11087 if (INTEL_INFO(ring->dev)->gen < 5)
11090 if (i915.use_mmio_flip < 0)
11092 else if (i915.use_mmio_flip > 0)
11094 else if (i915.enable_execlists)
11097 return ring != i915_gem_request_get_ring(obj->last_write_req);
11100 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11102 struct drm_device *dev = intel_crtc->base.dev;
11103 struct drm_i915_private *dev_priv = dev->dev_private;
11104 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11105 const enum pipe pipe = intel_crtc->pipe;
11108 ctl = I915_READ(PLANE_CTL(pipe, 0));
11109 ctl &= ~PLANE_CTL_TILED_MASK;
11110 switch (fb->modifier[0]) {
11111 case DRM_FORMAT_MOD_NONE:
11113 case I915_FORMAT_MOD_X_TILED:
11114 ctl |= PLANE_CTL_TILED_X;
11116 case I915_FORMAT_MOD_Y_TILED:
11117 ctl |= PLANE_CTL_TILED_Y;
11119 case I915_FORMAT_MOD_Yf_TILED:
11120 ctl |= PLANE_CTL_TILED_YF;
11123 MISSING_CASE(fb->modifier[0]);
11127 * The stride is either expressed as a multiple of 64 bytes chunks for
11128 * linear buffers or in number of tiles for tiled buffers.
11130 stride = fb->pitches[0] /
11131 intel_fb_stride_alignment(dev, fb->modifier[0],
11135 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11136 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11138 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11139 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11141 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11142 POSTING_READ(PLANE_SURF(pipe, 0));
11145 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11147 struct drm_device *dev = intel_crtc->base.dev;
11148 struct drm_i915_private *dev_priv = dev->dev_private;
11149 struct intel_framebuffer *intel_fb =
11150 to_intel_framebuffer(intel_crtc->base.primary->fb);
11151 struct drm_i915_gem_object *obj = intel_fb->obj;
11155 reg = DSPCNTR(intel_crtc->plane);
11156 dspcntr = I915_READ(reg);
11158 if (obj->tiling_mode != I915_TILING_NONE)
11159 dspcntr |= DISPPLANE_TILED;
11161 dspcntr &= ~DISPPLANE_TILED;
11163 I915_WRITE(reg, dspcntr);
11165 I915_WRITE(DSPSURF(intel_crtc->plane),
11166 intel_crtc->unpin_work->gtt_offset);
11167 POSTING_READ(DSPSURF(intel_crtc->plane));
11172 * XXX: This is the temporary way to update the plane registers until we get
11173 * around to using the usual plane update functions for MMIO flips
11175 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11177 struct drm_device *dev = intel_crtc->base.dev;
11178 bool atomic_update;
11179 u32 start_vbl_count;
11181 intel_mark_page_flip_active(intel_crtc);
11183 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11185 if (INTEL_INFO(dev)->gen >= 9)
11186 skl_do_mmio_flip(intel_crtc);
11188 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11189 ilk_do_mmio_flip(intel_crtc);
11192 intel_pipe_update_end(intel_crtc, start_vbl_count);
11195 static void intel_mmio_flip_work_func(struct work_struct *work)
11197 struct intel_mmio_flip *mmio_flip =
11198 container_of(work, struct intel_mmio_flip, work);
11200 if (mmio_flip->req)
11201 WARN_ON(__i915_wait_request(mmio_flip->req,
11202 mmio_flip->crtc->reset_counter,
11204 &mmio_flip->i915->rps.mmioflips));
11206 intel_do_mmio_flip(mmio_flip->crtc);
11208 i915_gem_request_unreference__unlocked(mmio_flip->req);
11212 static int intel_queue_mmio_flip(struct drm_device *dev,
11213 struct drm_crtc *crtc,
11214 struct drm_framebuffer *fb,
11215 struct drm_i915_gem_object *obj,
11216 struct intel_engine_cs *ring,
11219 struct intel_mmio_flip *mmio_flip;
11221 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11222 if (mmio_flip == NULL)
11225 mmio_flip->i915 = to_i915(dev);
11226 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11227 mmio_flip->crtc = to_intel_crtc(crtc);
11229 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11230 schedule_work(&mmio_flip->work);
11235 static int intel_default_queue_flip(struct drm_device *dev,
11236 struct drm_crtc *crtc,
11237 struct drm_framebuffer *fb,
11238 struct drm_i915_gem_object *obj,
11239 struct drm_i915_gem_request *req,
11245 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11246 struct drm_crtc *crtc)
11248 struct drm_i915_private *dev_priv = dev->dev_private;
11249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11250 struct intel_unpin_work *work = intel_crtc->unpin_work;
11253 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11256 if (!work->enable_stall_check)
11259 if (work->flip_ready_vblank == 0) {
11260 if (work->flip_queued_req &&
11261 !i915_gem_request_completed(work->flip_queued_req, true))
11264 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11267 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11270 /* Potential stall - if we see that the flip has happened,
11271 * assume a missed interrupt. */
11272 if (INTEL_INFO(dev)->gen >= 4)
11273 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11275 addr = I915_READ(DSPADDR(intel_crtc->plane));
11277 /* There is a potential issue here with a false positive after a flip
11278 * to the same address. We could address this by checking for a
11279 * non-incrementing frame counter.
11281 return addr == work->gtt_offset;
11284 void intel_check_page_flip(struct drm_device *dev, int pipe)
11286 struct drm_i915_private *dev_priv = dev->dev_private;
11287 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11289 struct intel_unpin_work *work;
11291 WARN_ON(!in_interrupt());
11296 spin_lock(&dev->event_lock);
11297 work = intel_crtc->unpin_work;
11298 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11299 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11300 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11301 page_flip_completed(intel_crtc);
11304 if (work != NULL &&
11305 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11306 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11307 spin_unlock(&dev->event_lock);
11310 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11311 struct drm_framebuffer *fb,
11312 struct drm_pending_vblank_event *event,
11313 uint32_t page_flip_flags)
11315 struct drm_device *dev = crtc->dev;
11316 struct drm_i915_private *dev_priv = dev->dev_private;
11317 struct drm_framebuffer *old_fb = crtc->primary->fb;
11318 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11320 struct drm_plane *primary = crtc->primary;
11321 enum pipe pipe = intel_crtc->pipe;
11322 struct intel_unpin_work *work;
11323 struct intel_engine_cs *ring;
11325 struct drm_i915_gem_request *request = NULL;
11329 * drm_mode_page_flip_ioctl() should already catch this, but double
11330 * check to be safe. In the future we may enable pageflipping from
11331 * a disabled primary plane.
11333 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11336 /* Can't change pixel format via MI display flips. */
11337 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11341 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11342 * Note that pitch changes could also affect these register.
11344 if (INTEL_INFO(dev)->gen > 3 &&
11345 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11346 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11349 if (i915_terminally_wedged(&dev_priv->gpu_error))
11352 work = kzalloc(sizeof(*work), GFP_KERNEL);
11356 work->event = event;
11358 work->old_fb = old_fb;
11359 INIT_WORK(&work->work, intel_unpin_work_fn);
11361 ret = drm_crtc_vblank_get(crtc);
11365 /* We borrow the event spin lock for protecting unpin_work */
11366 spin_lock_irq(&dev->event_lock);
11367 if (intel_crtc->unpin_work) {
11368 /* Before declaring the flip queue wedged, check if
11369 * the hardware completed the operation behind our backs.
11371 if (__intel_pageflip_stall_check(dev, crtc)) {
11372 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11373 page_flip_completed(intel_crtc);
11375 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11376 spin_unlock_irq(&dev->event_lock);
11378 drm_crtc_vblank_put(crtc);
11383 intel_crtc->unpin_work = work;
11384 spin_unlock_irq(&dev->event_lock);
11386 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11387 flush_workqueue(dev_priv->wq);
11389 /* Reference the objects for the scheduled work. */
11390 drm_framebuffer_reference(work->old_fb);
11391 drm_gem_object_reference(&obj->base);
11393 crtc->primary->fb = fb;
11394 update_state_fb(crtc->primary);
11396 work->pending_flip_obj = obj;
11398 ret = i915_mutex_lock_interruptible(dev);
11402 atomic_inc(&intel_crtc->unpin_work_count);
11403 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11405 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11406 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11408 if (IS_VALLEYVIEW(dev)) {
11409 ring = &dev_priv->ring[BCS];
11410 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11411 /* vlv: DISPLAY_FLIP fails to change tiling */
11413 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11414 ring = &dev_priv->ring[BCS];
11415 } else if (INTEL_INFO(dev)->gen >= 7) {
11416 ring = i915_gem_request_get_ring(obj->last_write_req);
11417 if (ring == NULL || ring->id != RCS)
11418 ring = &dev_priv->ring[BCS];
11420 ring = &dev_priv->ring[RCS];
11423 mmio_flip = use_mmio_flip(ring, obj);
11425 /* When using CS flips, we want to emit semaphores between rings.
11426 * However, when using mmio flips we will create a task to do the
11427 * synchronisation, so all we want here is to pin the framebuffer
11428 * into the display plane and skip any waits.
11430 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11431 crtc->primary->state,
11432 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11434 goto cleanup_pending;
11436 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11437 + intel_crtc->dspaddr_offset;
11440 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11443 goto cleanup_unpin;
11445 i915_gem_request_assign(&work->flip_queued_req,
11446 obj->last_write_req);
11449 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11451 goto cleanup_unpin;
11454 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11457 goto cleanup_unpin;
11459 i915_gem_request_assign(&work->flip_queued_req, request);
11463 i915_add_request_no_flush(request);
11465 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11466 work->enable_stall_check = true;
11468 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11469 to_intel_plane(primary)->frontbuffer_bit);
11470 mutex_unlock(&dev->struct_mutex);
11472 intel_fbc_disable(dev);
11473 intel_frontbuffer_flip_prepare(dev,
11474 to_intel_plane(primary)->frontbuffer_bit);
11476 trace_i915_flip_request(intel_crtc->plane, obj);
11481 intel_unpin_fb_obj(fb, crtc->primary->state);
11484 i915_gem_request_cancel(request);
11485 atomic_dec(&intel_crtc->unpin_work_count);
11486 mutex_unlock(&dev->struct_mutex);
11488 crtc->primary->fb = old_fb;
11489 update_state_fb(crtc->primary);
11491 drm_gem_object_unreference_unlocked(&obj->base);
11492 drm_framebuffer_unreference(work->old_fb);
11494 spin_lock_irq(&dev->event_lock);
11495 intel_crtc->unpin_work = NULL;
11496 spin_unlock_irq(&dev->event_lock);
11498 drm_crtc_vblank_put(crtc);
11503 struct drm_atomic_state *state;
11504 struct drm_plane_state *plane_state;
11507 state = drm_atomic_state_alloc(dev);
11510 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11513 plane_state = drm_atomic_get_plane_state(state, primary);
11514 ret = PTR_ERR_OR_ZERO(plane_state);
11516 drm_atomic_set_fb_for_plane(plane_state, fb);
11518 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11520 ret = drm_atomic_commit(state);
11523 if (ret == -EDEADLK) {
11524 drm_modeset_backoff(state->acquire_ctx);
11525 drm_atomic_state_clear(state);
11530 drm_atomic_state_free(state);
11532 if (ret == 0 && event) {
11533 spin_lock_irq(&dev->event_lock);
11534 drm_send_vblank_event(dev, pipe, event);
11535 spin_unlock_irq(&dev->event_lock);
11543 * intel_wm_need_update - Check whether watermarks need updating
11544 * @plane: drm plane
11545 * @state: new plane state
11547 * Check current plane state versus the new one to determine whether
11548 * watermarks need to be recalculated.
11550 * Returns true or false.
11552 static bool intel_wm_need_update(struct drm_plane *plane,
11553 struct drm_plane_state *state)
11555 /* Update watermarks on tiling changes. */
11556 if (!plane->state->fb || !state->fb ||
11557 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11558 plane->state->rotation != state->rotation)
11561 if (plane->state->crtc_w != state->crtc_w)
11567 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11568 struct drm_plane_state *plane_state)
11570 struct drm_crtc *crtc = crtc_state->crtc;
11571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11572 struct drm_plane *plane = plane_state->plane;
11573 struct drm_device *dev = crtc->dev;
11574 struct drm_i915_private *dev_priv = dev->dev_private;
11575 struct intel_plane_state *old_plane_state =
11576 to_intel_plane_state(plane->state);
11577 int idx = intel_crtc->base.base.id, ret;
11578 int i = drm_plane_index(plane);
11579 bool mode_changed = needs_modeset(crtc_state);
11580 bool was_crtc_enabled = crtc->state->active;
11581 bool is_crtc_enabled = crtc_state->active;
11583 bool turn_off, turn_on, visible, was_visible;
11584 struct drm_framebuffer *fb = plane_state->fb;
11586 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11587 plane->type != DRM_PLANE_TYPE_CURSOR) {
11588 ret = skl_update_scaler_plane(
11589 to_intel_crtc_state(crtc_state),
11590 to_intel_plane_state(plane_state));
11596 * Disabling a plane is always okay; we just need to update
11597 * fb tracking in a special way since cleanup_fb() won't
11598 * get called by the plane helpers.
11600 if (old_plane_state->base.fb && !fb)
11601 intel_crtc->atomic.disabled_planes |= 1 << i;
11603 was_visible = old_plane_state->visible;
11604 visible = to_intel_plane_state(plane_state)->visible;
11606 if (!was_crtc_enabled && WARN_ON(was_visible))
11607 was_visible = false;
11609 if (!is_crtc_enabled && WARN_ON(visible))
11612 if (!was_visible && !visible)
11615 turn_off = was_visible && (!visible || mode_changed);
11616 turn_on = visible && (!was_visible || mode_changed);
11618 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11619 plane->base.id, fb ? fb->base.id : -1);
11621 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11622 plane->base.id, was_visible, visible,
11623 turn_off, turn_on, mode_changed);
11626 intel_crtc->atomic.update_wm_pre = true;
11627 /* must disable cxsr around plane enable/disable */
11628 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11629 intel_crtc->atomic.disable_cxsr = true;
11630 /* to potentially re-enable cxsr */
11631 intel_crtc->atomic.wait_vblank = true;
11632 intel_crtc->atomic.update_wm_post = true;
11634 } else if (turn_off) {
11635 intel_crtc->atomic.update_wm_post = true;
11636 /* must disable cxsr around plane enable/disable */
11637 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11638 if (is_crtc_enabled)
11639 intel_crtc->atomic.wait_vblank = true;
11640 intel_crtc->atomic.disable_cxsr = true;
11642 } else if (intel_wm_need_update(plane, plane_state)) {
11643 intel_crtc->atomic.update_wm_pre = true;
11647 intel_crtc->atomic.fb_bits |=
11648 to_intel_plane(plane)->frontbuffer_bit;
11650 switch (plane->type) {
11651 case DRM_PLANE_TYPE_PRIMARY:
11652 intel_crtc->atomic.wait_for_flips = true;
11653 intel_crtc->atomic.pre_disable_primary = turn_off;
11654 intel_crtc->atomic.post_enable_primary = turn_on;
11658 * FIXME: Actually if we will still have any other
11659 * plane enabled on the pipe we could let IPS enabled
11660 * still, but for now lets consider that when we make
11661 * primary invisible by setting DSPCNTR to 0 on
11662 * update_primary_plane function IPS needs to be
11665 intel_crtc->atomic.disable_ips = true;
11667 intel_crtc->atomic.disable_fbc = true;
11671 * FBC does not work on some platforms for rotated
11672 * planes, so disable it when rotation is not 0 and
11673 * update it when rotation is set back to 0.
11675 * FIXME: This is redundant with the fbc update done in
11676 * the primary plane enable function except that that
11677 * one is done too late. We eventually need to unify
11682 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11683 dev_priv->fbc.crtc == intel_crtc &&
11684 plane_state->rotation != BIT(DRM_ROTATE_0))
11685 intel_crtc->atomic.disable_fbc = true;
11688 * BDW signals flip done immediately if the plane
11689 * is disabled, even if the plane enable is already
11690 * armed to occur at the next vblank :(
11692 if (turn_on && IS_BROADWELL(dev))
11693 intel_crtc->atomic.wait_vblank = true;
11695 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11697 case DRM_PLANE_TYPE_CURSOR:
11699 case DRM_PLANE_TYPE_OVERLAY:
11700 if (turn_off && !mode_changed) {
11701 intel_crtc->atomic.wait_vblank = true;
11702 intel_crtc->atomic.update_sprite_watermarks |=
11709 static bool encoders_cloneable(const struct intel_encoder *a,
11710 const struct intel_encoder *b)
11712 /* masks could be asymmetric, so check both ways */
11713 return a == b || (a->cloneable & (1 << b->type) &&
11714 b->cloneable & (1 << a->type));
11717 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11718 struct intel_crtc *crtc,
11719 struct intel_encoder *encoder)
11721 struct intel_encoder *source_encoder;
11722 struct drm_connector *connector;
11723 struct drm_connector_state *connector_state;
11726 for_each_connector_in_state(state, connector, connector_state, i) {
11727 if (connector_state->crtc != &crtc->base)
11731 to_intel_encoder(connector_state->best_encoder);
11732 if (!encoders_cloneable(encoder, source_encoder))
11739 static bool check_encoder_cloning(struct drm_atomic_state *state,
11740 struct intel_crtc *crtc)
11742 struct intel_encoder *encoder;
11743 struct drm_connector *connector;
11744 struct drm_connector_state *connector_state;
11747 for_each_connector_in_state(state, connector, connector_state, i) {
11748 if (connector_state->crtc != &crtc->base)
11751 encoder = to_intel_encoder(connector_state->best_encoder);
11752 if (!check_single_encoder_cloning(state, crtc, encoder))
11759 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11760 struct drm_crtc_state *crtc_state)
11762 struct intel_crtc_state *pipe_config =
11763 to_intel_crtc_state(crtc_state);
11764 struct drm_plane *p;
11765 unsigned visible_mask = 0;
11767 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11768 struct drm_plane_state *plane_state =
11769 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11771 if (WARN_ON(!plane_state))
11774 if (!plane_state->fb)
11775 crtc_state->plane_mask &=
11776 ~(1 << drm_plane_index(p));
11777 else if (to_intel_plane_state(plane_state)->visible)
11778 visible_mask |= 1 << drm_plane_index(p);
11784 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11787 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11788 struct drm_crtc_state *crtc_state)
11790 struct drm_device *dev = crtc->dev;
11791 struct drm_i915_private *dev_priv = dev->dev_private;
11792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11793 struct intel_crtc_state *pipe_config =
11794 to_intel_crtc_state(crtc_state);
11795 struct drm_atomic_state *state = crtc_state->state;
11796 int ret, idx = crtc->base.id;
11797 bool mode_changed = needs_modeset(crtc_state);
11799 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11800 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11804 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11805 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11806 idx, crtc->state->active, intel_crtc->active);
11808 /* plane mask is fixed up after all initial planes are calculated */
11809 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11810 intel_crtc_check_initial_planes(crtc, crtc_state);
11812 if (mode_changed && !crtc_state->active)
11813 intel_crtc->atomic.update_wm_post = true;
11815 if (mode_changed && crtc_state->enable &&
11816 dev_priv->display.crtc_compute_clock &&
11817 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11818 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11824 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11827 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11828 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11829 .load_lut = intel_crtc_load_lut,
11830 .atomic_begin = intel_begin_crtc_commit,
11831 .atomic_flush = intel_finish_crtc_commit,
11832 .atomic_check = intel_crtc_atomic_check,
11836 * intel_modeset_update_staged_output_state
11838 * Updates the staged output configuration state, e.g. after we've read out the
11839 * current hw state.
11841 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11843 struct intel_crtc *crtc;
11844 struct intel_encoder *encoder;
11845 struct intel_connector *connector;
11847 for_each_intel_connector(dev, connector) {
11848 connector->new_encoder =
11849 to_intel_encoder(connector->base.encoder);
11852 for_each_intel_encoder(dev, encoder) {
11853 encoder->new_crtc =
11854 to_intel_crtc(encoder->base.crtc);
11857 for_each_intel_crtc(dev, crtc) {
11858 crtc->new_enabled = crtc->base.state->enable;
11862 /* Transitional helper to copy current connector/encoder state to
11863 * connector->state. This is needed so that code that is partially
11864 * converted to atomic does the right thing.
11866 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11868 struct intel_connector *connector;
11870 for_each_intel_connector(dev, connector) {
11871 if (connector->base.encoder) {
11872 connector->base.state->best_encoder =
11873 connector->base.encoder;
11874 connector->base.state->crtc =
11875 connector->base.encoder->crtc;
11877 connector->base.state->best_encoder = NULL;
11878 connector->base.state->crtc = NULL;
11884 connected_sink_compute_bpp(struct intel_connector *connector,
11885 struct intel_crtc_state *pipe_config)
11887 int bpp = pipe_config->pipe_bpp;
11889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11890 connector->base.base.id,
11891 connector->base.name);
11893 /* Don't use an invalid EDID bpc value */
11894 if (connector->base.display_info.bpc &&
11895 connector->base.display_info.bpc * 3 < bpp) {
11896 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11897 bpp, connector->base.display_info.bpc*3);
11898 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11901 /* Clamp bpp to 8 on screens without EDID 1.4 */
11902 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11903 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11905 pipe_config->pipe_bpp = 24;
11910 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11911 struct intel_crtc_state *pipe_config)
11913 struct drm_device *dev = crtc->base.dev;
11914 struct drm_atomic_state *state;
11915 struct drm_connector *connector;
11916 struct drm_connector_state *connector_state;
11919 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11921 else if (INTEL_INFO(dev)->gen >= 5)
11927 pipe_config->pipe_bpp = bpp;
11929 state = pipe_config->base.state;
11931 /* Clamp display bpp to EDID value */
11932 for_each_connector_in_state(state, connector, connector_state, i) {
11933 if (connector_state->crtc != &crtc->base)
11936 connected_sink_compute_bpp(to_intel_connector(connector),
11943 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11945 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11946 "type: 0x%x flags: 0x%x\n",
11948 mode->crtc_hdisplay, mode->crtc_hsync_start,
11949 mode->crtc_hsync_end, mode->crtc_htotal,
11950 mode->crtc_vdisplay, mode->crtc_vsync_start,
11951 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11954 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11955 struct intel_crtc_state *pipe_config,
11956 const char *context)
11958 struct drm_device *dev = crtc->base.dev;
11959 struct drm_plane *plane;
11960 struct intel_plane *intel_plane;
11961 struct intel_plane_state *state;
11962 struct drm_framebuffer *fb;
11964 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11965 context, pipe_config, pipe_name(crtc->pipe));
11967 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11968 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11969 pipe_config->pipe_bpp, pipe_config->dither);
11970 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11971 pipe_config->has_pch_encoder,
11972 pipe_config->fdi_lanes,
11973 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11974 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11975 pipe_config->fdi_m_n.tu);
11976 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11977 pipe_config->has_dp_encoder,
11978 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11979 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11980 pipe_config->dp_m_n.tu);
11982 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11983 pipe_config->has_dp_encoder,
11984 pipe_config->dp_m2_n2.gmch_m,
11985 pipe_config->dp_m2_n2.gmch_n,
11986 pipe_config->dp_m2_n2.link_m,
11987 pipe_config->dp_m2_n2.link_n,
11988 pipe_config->dp_m2_n2.tu);
11990 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11991 pipe_config->has_audio,
11992 pipe_config->has_infoframe);
11994 DRM_DEBUG_KMS("requested mode:\n");
11995 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11996 DRM_DEBUG_KMS("adjusted mode:\n");
11997 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11998 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11999 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12000 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12001 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12002 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12004 pipe_config->scaler_state.scaler_users,
12005 pipe_config->scaler_state.scaler_id);
12006 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12007 pipe_config->gmch_pfit.control,
12008 pipe_config->gmch_pfit.pgm_ratios,
12009 pipe_config->gmch_pfit.lvds_border_bits);
12010 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12011 pipe_config->pch_pfit.pos,
12012 pipe_config->pch_pfit.size,
12013 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12014 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12015 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12017 if (IS_BROXTON(dev)) {
12018 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12019 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12020 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12021 pipe_config->ddi_pll_sel,
12022 pipe_config->dpll_hw_state.ebb0,
12023 pipe_config->dpll_hw_state.ebb4,
12024 pipe_config->dpll_hw_state.pll0,
12025 pipe_config->dpll_hw_state.pll1,
12026 pipe_config->dpll_hw_state.pll2,
12027 pipe_config->dpll_hw_state.pll3,
12028 pipe_config->dpll_hw_state.pll6,
12029 pipe_config->dpll_hw_state.pll8,
12030 pipe_config->dpll_hw_state.pll9,
12031 pipe_config->dpll_hw_state.pll10,
12032 pipe_config->dpll_hw_state.pcsdw12);
12033 } else if (IS_SKYLAKE(dev)) {
12034 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12035 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12036 pipe_config->ddi_pll_sel,
12037 pipe_config->dpll_hw_state.ctrl1,
12038 pipe_config->dpll_hw_state.cfgcr1,
12039 pipe_config->dpll_hw_state.cfgcr2);
12040 } else if (HAS_DDI(dev)) {
12041 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12042 pipe_config->ddi_pll_sel,
12043 pipe_config->dpll_hw_state.wrpll);
12045 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12046 "fp0: 0x%x, fp1: 0x%x\n",
12047 pipe_config->dpll_hw_state.dpll,
12048 pipe_config->dpll_hw_state.dpll_md,
12049 pipe_config->dpll_hw_state.fp0,
12050 pipe_config->dpll_hw_state.fp1);
12053 DRM_DEBUG_KMS("planes on this crtc\n");
12054 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12055 intel_plane = to_intel_plane(plane);
12056 if (intel_plane->pipe != crtc->pipe)
12059 state = to_intel_plane_state(plane->state);
12060 fb = state->base.fb;
12062 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12063 "disabled, scaler_id = %d\n",
12064 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12065 plane->base.id, intel_plane->pipe,
12066 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12067 drm_plane_index(plane), state->scaler_id);
12071 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12072 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12073 plane->base.id, intel_plane->pipe,
12074 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12075 drm_plane_index(plane));
12076 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12077 fb->base.id, fb->width, fb->height, fb->pixel_format);
12078 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12080 state->src.x1 >> 16, state->src.y1 >> 16,
12081 drm_rect_width(&state->src) >> 16,
12082 drm_rect_height(&state->src) >> 16,
12083 state->dst.x1, state->dst.y1,
12084 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12088 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12090 struct drm_device *dev = state->dev;
12091 struct intel_encoder *encoder;
12092 struct drm_connector *connector;
12093 struct drm_connector_state *connector_state;
12094 unsigned int used_ports = 0;
12098 * Walk the connector list instead of the encoder
12099 * list to detect the problem on ddi platforms
12100 * where there's just one encoder per digital port.
12102 for_each_connector_in_state(state, connector, connector_state, i) {
12103 if (!connector_state->best_encoder)
12106 encoder = to_intel_encoder(connector_state->best_encoder);
12108 WARN_ON(!connector_state->crtc);
12110 switch (encoder->type) {
12111 unsigned int port_mask;
12112 case INTEL_OUTPUT_UNKNOWN:
12113 if (WARN_ON(!HAS_DDI(dev)))
12115 case INTEL_OUTPUT_DISPLAYPORT:
12116 case INTEL_OUTPUT_HDMI:
12117 case INTEL_OUTPUT_EDP:
12118 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12120 /* the same port mustn't appear more than once */
12121 if (used_ports & port_mask)
12124 used_ports |= port_mask;
12134 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12136 struct drm_crtc_state tmp_state;
12137 struct intel_crtc_scaler_state scaler_state;
12138 struct intel_dpll_hw_state dpll_hw_state;
12139 enum intel_dpll_id shared_dpll;
12140 uint32_t ddi_pll_sel;
12142 /* FIXME: before the switch to atomic started, a new pipe_config was
12143 * kzalloc'd. Code that depends on any field being zero should be
12144 * fixed, so that the crtc_state can be safely duplicated. For now,
12145 * only fields that are know to not cause problems are preserved. */
12147 tmp_state = crtc_state->base;
12148 scaler_state = crtc_state->scaler_state;
12149 shared_dpll = crtc_state->shared_dpll;
12150 dpll_hw_state = crtc_state->dpll_hw_state;
12151 ddi_pll_sel = crtc_state->ddi_pll_sel;
12153 memset(crtc_state, 0, sizeof *crtc_state);
12155 crtc_state->base = tmp_state;
12156 crtc_state->scaler_state = scaler_state;
12157 crtc_state->shared_dpll = shared_dpll;
12158 crtc_state->dpll_hw_state = dpll_hw_state;
12159 crtc_state->ddi_pll_sel = ddi_pll_sel;
12163 intel_modeset_pipe_config(struct drm_crtc *crtc,
12164 struct intel_crtc_state *pipe_config)
12166 struct drm_atomic_state *state = pipe_config->base.state;
12167 struct intel_encoder *encoder;
12168 struct drm_connector *connector;
12169 struct drm_connector_state *connector_state;
12170 int base_bpp, ret = -EINVAL;
12174 clear_intel_crtc_state(pipe_config);
12176 pipe_config->cpu_transcoder =
12177 (enum transcoder) to_intel_crtc(crtc)->pipe;
12180 * Sanitize sync polarity flags based on requested ones. If neither
12181 * positive or negative polarity is requested, treat this as meaning
12182 * negative polarity.
12184 if (!(pipe_config->base.adjusted_mode.flags &
12185 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12186 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12188 if (!(pipe_config->base.adjusted_mode.flags &
12189 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12190 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12192 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12193 * plane pixel format and any sink constraints into account. Returns the
12194 * source plane bpp so that dithering can be selected on mismatches
12195 * after encoders and crtc also have had their say. */
12196 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12202 * Determine the real pipe dimensions. Note that stereo modes can
12203 * increase the actual pipe size due to the frame doubling and
12204 * insertion of additional space for blanks between the frame. This
12205 * is stored in the crtc timings. We use the requested mode to do this
12206 * computation to clearly distinguish it from the adjusted mode, which
12207 * can be changed by the connectors in the below retry loop.
12209 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12210 &pipe_config->pipe_src_w,
12211 &pipe_config->pipe_src_h);
12214 /* Ensure the port clock defaults are reset when retrying. */
12215 pipe_config->port_clock = 0;
12216 pipe_config->pixel_multiplier = 1;
12218 /* Fill in default crtc timings, allow encoders to overwrite them. */
12219 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12220 CRTC_STEREO_DOUBLE);
12222 /* Pass our mode to the connectors and the CRTC to give them a chance to
12223 * adjust it according to limitations or connector properties, and also
12224 * a chance to reject the mode entirely.
12226 for_each_connector_in_state(state, connector, connector_state, i) {
12227 if (connector_state->crtc != crtc)
12230 encoder = to_intel_encoder(connector_state->best_encoder);
12232 if (!(encoder->compute_config(encoder, pipe_config))) {
12233 DRM_DEBUG_KMS("Encoder config failure\n");
12238 /* Set default port clock if not overwritten by the encoder. Needs to be
12239 * done afterwards in case the encoder adjusts the mode. */
12240 if (!pipe_config->port_clock)
12241 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12242 * pipe_config->pixel_multiplier;
12244 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12246 DRM_DEBUG_KMS("CRTC fixup failed\n");
12250 if (ret == RETRY) {
12251 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12256 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12258 goto encoder_retry;
12261 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12262 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12263 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12265 /* Check if we need to force a modeset */
12266 if (pipe_config->has_audio !=
12267 to_intel_crtc_state(crtc->state)->has_audio) {
12268 pipe_config->base.mode_changed = true;
12269 ret = drm_atomic_add_affected_planes(state, crtc);
12273 * Note we have an issue here with infoframes: current code
12274 * only updates them on the full mode set path per hw
12275 * requirements. So here we should be checking for any
12276 * required changes and forcing a mode set.
12282 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12284 struct drm_encoder *encoder;
12285 struct drm_device *dev = crtc->dev;
12287 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12288 if (encoder->crtc == crtc)
12295 intel_modeset_update_state(struct drm_atomic_state *state)
12297 struct drm_device *dev = state->dev;
12298 struct intel_encoder *intel_encoder;
12299 struct drm_crtc *crtc;
12300 struct drm_crtc_state *crtc_state;
12301 struct drm_connector *connector;
12303 intel_shared_dpll_commit(state);
12305 for_each_intel_encoder(dev, intel_encoder) {
12306 if (!intel_encoder->base.crtc)
12309 crtc = intel_encoder->base.crtc;
12310 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12311 if (!crtc_state || !needs_modeset(crtc->state))
12314 intel_encoder->connectors_active = false;
12317 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12318 intel_modeset_update_staged_output_state(state->dev);
12320 /* Double check state. */
12321 for_each_crtc(dev, crtc) {
12322 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12324 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12326 /* Update hwmode for vblank functions */
12327 if (crtc->state->active)
12328 crtc->hwmode = crtc->state->adjusted_mode;
12330 crtc->hwmode.crtc_clock = 0;
12333 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12334 if (!connector->encoder || !connector->encoder->crtc)
12337 crtc = connector->encoder->crtc;
12338 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12339 if (!crtc_state || !needs_modeset(crtc->state))
12342 if (crtc->state->active) {
12343 struct drm_property *dpms_property =
12344 dev->mode_config.dpms_property;
12346 connector->dpms = DRM_MODE_DPMS_ON;
12347 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12349 intel_encoder = to_intel_encoder(connector->encoder);
12350 intel_encoder->connectors_active = true;
12352 connector->dpms = DRM_MODE_DPMS_OFF;
12356 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12360 if (clock1 == clock2)
12363 if (!clock1 || !clock2)
12366 diff = abs(clock1 - clock2);
12368 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12374 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12375 list_for_each_entry((intel_crtc), \
12376 &(dev)->mode_config.crtc_list, \
12378 if (mask & (1 <<(intel_crtc)->pipe))
12381 intel_pipe_config_compare(struct drm_device *dev,
12382 struct intel_crtc_state *current_config,
12383 struct intel_crtc_state *pipe_config)
12385 #define PIPE_CONF_CHECK_X(name) \
12386 if (current_config->name != pipe_config->name) { \
12387 DRM_ERROR("mismatch in " #name " " \
12388 "(expected 0x%08x, found 0x%08x)\n", \
12389 current_config->name, \
12390 pipe_config->name); \
12394 #define PIPE_CONF_CHECK_I(name) \
12395 if (current_config->name != pipe_config->name) { \
12396 DRM_ERROR("mismatch in " #name " " \
12397 "(expected %i, found %i)\n", \
12398 current_config->name, \
12399 pipe_config->name); \
12403 /* This is required for BDW+ where there is only one set of registers for
12404 * switching between high and low RR.
12405 * This macro can be used whenever a comparison has to be made between one
12406 * hw state and multiple sw state variables.
12408 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12409 if ((current_config->name != pipe_config->name) && \
12410 (current_config->alt_name != pipe_config->name)) { \
12411 DRM_ERROR("mismatch in " #name " " \
12412 "(expected %i or %i, found %i)\n", \
12413 current_config->name, \
12414 current_config->alt_name, \
12415 pipe_config->name); \
12419 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12420 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12421 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12422 "(expected %i, found %i)\n", \
12423 current_config->name & (mask), \
12424 pipe_config->name & (mask)); \
12428 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12429 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12430 DRM_ERROR("mismatch in " #name " " \
12431 "(expected %i, found %i)\n", \
12432 current_config->name, \
12433 pipe_config->name); \
12437 #define PIPE_CONF_QUIRK(quirk) \
12438 ((current_config->quirks | pipe_config->quirks) & (quirk))
12440 PIPE_CONF_CHECK_I(cpu_transcoder);
12442 PIPE_CONF_CHECK_I(has_pch_encoder);
12443 PIPE_CONF_CHECK_I(fdi_lanes);
12444 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12445 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12446 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12447 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12448 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12450 PIPE_CONF_CHECK_I(has_dp_encoder);
12452 if (INTEL_INFO(dev)->gen < 8) {
12453 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12454 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12455 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12456 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12457 PIPE_CONF_CHECK_I(dp_m_n.tu);
12459 if (current_config->has_drrs) {
12460 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12461 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12462 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12463 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12464 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12467 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12468 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12469 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12470 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12471 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12474 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12475 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12476 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12477 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12478 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12488 PIPE_CONF_CHECK_I(pixel_multiplier);
12489 PIPE_CONF_CHECK_I(has_hdmi_sink);
12490 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12491 IS_VALLEYVIEW(dev))
12492 PIPE_CONF_CHECK_I(limited_color_range);
12493 PIPE_CONF_CHECK_I(has_infoframe);
12495 PIPE_CONF_CHECK_I(has_audio);
12497 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12498 DRM_MODE_FLAG_INTERLACE);
12500 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12501 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12502 DRM_MODE_FLAG_PHSYNC);
12503 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12504 DRM_MODE_FLAG_NHSYNC);
12505 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12506 DRM_MODE_FLAG_PVSYNC);
12507 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12508 DRM_MODE_FLAG_NVSYNC);
12511 PIPE_CONF_CHECK_I(pipe_src_w);
12512 PIPE_CONF_CHECK_I(pipe_src_h);
12515 * FIXME: BIOS likes to set up a cloned config with lvds+external
12516 * screen. Since we don't yet re-compute the pipe config when moving
12517 * just the lvds port away to another pipe the sw tracking won't match.
12519 * Proper atomic modesets with recomputed global state will fix this.
12520 * Until then just don't check gmch state for inherited modes.
12522 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12523 PIPE_CONF_CHECK_I(gmch_pfit.control);
12524 /* pfit ratios are autocomputed by the hw on gen4+ */
12525 if (INTEL_INFO(dev)->gen < 4)
12526 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12527 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12530 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12531 if (current_config->pch_pfit.enabled) {
12532 PIPE_CONF_CHECK_I(pch_pfit.pos);
12533 PIPE_CONF_CHECK_I(pch_pfit.size);
12536 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12538 /* BDW+ don't expose a synchronous way to read the state */
12539 if (IS_HASWELL(dev))
12540 PIPE_CONF_CHECK_I(ips_enabled);
12542 PIPE_CONF_CHECK_I(double_wide);
12544 PIPE_CONF_CHECK_X(ddi_pll_sel);
12546 PIPE_CONF_CHECK_I(shared_dpll);
12547 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12548 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12549 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12550 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12551 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12552 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12553 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12554 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12556 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12557 PIPE_CONF_CHECK_I(pipe_bpp);
12559 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12560 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12562 #undef PIPE_CONF_CHECK_X
12563 #undef PIPE_CONF_CHECK_I
12564 #undef PIPE_CONF_CHECK_I_ALT
12565 #undef PIPE_CONF_CHECK_FLAGS
12566 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12567 #undef PIPE_CONF_QUIRK
12572 static void check_wm_state(struct drm_device *dev)
12574 struct drm_i915_private *dev_priv = dev->dev_private;
12575 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12576 struct intel_crtc *intel_crtc;
12579 if (INTEL_INFO(dev)->gen < 9)
12582 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12583 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12585 for_each_intel_crtc(dev, intel_crtc) {
12586 struct skl_ddb_entry *hw_entry, *sw_entry;
12587 const enum pipe pipe = intel_crtc->pipe;
12589 if (!intel_crtc->active)
12593 for_each_plane(dev_priv, pipe, plane) {
12594 hw_entry = &hw_ddb.plane[pipe][plane];
12595 sw_entry = &sw_ddb->plane[pipe][plane];
12597 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12600 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12601 "(expected (%u,%u), found (%u,%u))\n",
12602 pipe_name(pipe), plane + 1,
12603 sw_entry->start, sw_entry->end,
12604 hw_entry->start, hw_entry->end);
12608 hw_entry = &hw_ddb.cursor[pipe];
12609 sw_entry = &sw_ddb->cursor[pipe];
12611 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12614 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12615 "(expected (%u,%u), found (%u,%u))\n",
12617 sw_entry->start, sw_entry->end,
12618 hw_entry->start, hw_entry->end);
12623 check_connector_state(struct drm_device *dev)
12625 struct intel_connector *connector;
12627 for_each_intel_connector(dev, connector) {
12628 /* This also checks the encoder/connector hw state with the
12629 * ->get_hw_state callbacks. */
12630 intel_connector_check_state(connector);
12632 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12633 "connector's staged encoder doesn't match current encoder\n");
12638 check_encoder_state(struct drm_device *dev)
12640 struct intel_encoder *encoder;
12641 struct intel_connector *connector;
12643 for_each_intel_encoder(dev, encoder) {
12644 bool enabled = false;
12645 bool active = false;
12646 enum pipe pipe, tracked_pipe;
12648 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12649 encoder->base.base.id,
12650 encoder->base.name);
12652 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12653 "encoder's stage crtc doesn't match current crtc\n");
12654 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12655 "encoder's active_connectors set, but no crtc\n");
12657 for_each_intel_connector(dev, connector) {
12658 if (connector->base.encoder != &encoder->base)
12661 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12665 * for MST connectors if we unplug the connector is gone
12666 * away but the encoder is still connected to a crtc
12667 * until a modeset happens in response to the hotplug.
12669 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12672 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12673 "encoder's enabled state mismatch "
12674 "(expected %i, found %i)\n",
12675 !!encoder->base.crtc, enabled);
12676 I915_STATE_WARN(active && !encoder->base.crtc,
12677 "active encoder with no crtc\n");
12679 I915_STATE_WARN(encoder->connectors_active != active,
12680 "encoder's computed active state doesn't match tracked active state "
12681 "(expected %i, found %i)\n", active, encoder->connectors_active);
12683 active = encoder->get_hw_state(encoder, &pipe);
12684 I915_STATE_WARN(active != encoder->connectors_active,
12685 "encoder's hw state doesn't match sw tracking "
12686 "(expected %i, found %i)\n",
12687 encoder->connectors_active, active);
12689 if (!encoder->base.crtc)
12692 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12693 I915_STATE_WARN(active && pipe != tracked_pipe,
12694 "active encoder's pipe doesn't match"
12695 "(expected %i, found %i)\n",
12696 tracked_pipe, pipe);
12702 check_crtc_state(struct drm_device *dev)
12704 struct drm_i915_private *dev_priv = dev->dev_private;
12705 struct intel_crtc *crtc;
12706 struct intel_encoder *encoder;
12707 struct intel_crtc_state pipe_config;
12709 for_each_intel_crtc(dev, crtc) {
12710 bool enabled = false;
12711 bool active = false;
12713 memset(&pipe_config, 0, sizeof(pipe_config));
12715 DRM_DEBUG_KMS("[CRTC:%d]\n",
12716 crtc->base.base.id);
12718 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12719 "active crtc, but not enabled in sw tracking\n");
12721 for_each_intel_encoder(dev, encoder) {
12722 if (encoder->base.crtc != &crtc->base)
12725 if (encoder->connectors_active)
12729 I915_STATE_WARN(active != crtc->active,
12730 "crtc's computed active state doesn't match tracked active state "
12731 "(expected %i, found %i)\n", active, crtc->active);
12732 I915_STATE_WARN(enabled != crtc->base.state->enable,
12733 "crtc's computed enabled state doesn't match tracked enabled state "
12734 "(expected %i, found %i)\n", enabled,
12735 crtc->base.state->enable);
12737 active = dev_priv->display.get_pipe_config(crtc,
12740 /* hw state is inconsistent with the pipe quirk */
12741 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12742 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12743 active = crtc->active;
12745 for_each_intel_encoder(dev, encoder) {
12747 if (encoder->base.crtc != &crtc->base)
12749 if (encoder->get_hw_state(encoder, &pipe))
12750 encoder->get_config(encoder, &pipe_config);
12753 I915_STATE_WARN(crtc->active != active,
12754 "crtc active state doesn't match with hw state "
12755 "(expected %i, found %i)\n", crtc->active, active);
12757 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12758 "transitional active state does not match atomic hw state "
12759 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12762 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12763 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12764 intel_dump_pipe_config(crtc, &pipe_config,
12766 intel_dump_pipe_config(crtc, crtc->config,
12773 check_shared_dpll_state(struct drm_device *dev)
12775 struct drm_i915_private *dev_priv = dev->dev_private;
12776 struct intel_crtc *crtc;
12777 struct intel_dpll_hw_state dpll_hw_state;
12780 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12781 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12782 int enabled_crtcs = 0, active_crtcs = 0;
12785 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12787 DRM_DEBUG_KMS("%s\n", pll->name);
12789 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12791 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12792 "more active pll users than references: %i vs %i\n",
12793 pll->active, hweight32(pll->config.crtc_mask));
12794 I915_STATE_WARN(pll->active && !pll->on,
12795 "pll in active use but not on in sw tracking\n");
12796 I915_STATE_WARN(pll->on && !pll->active,
12797 "pll in on but not on in use in sw tracking\n");
12798 I915_STATE_WARN(pll->on != active,
12799 "pll on state mismatch (expected %i, found %i)\n",
12802 for_each_intel_crtc(dev, crtc) {
12803 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12805 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12808 I915_STATE_WARN(pll->active != active_crtcs,
12809 "pll active crtcs mismatch (expected %i, found %i)\n",
12810 pll->active, active_crtcs);
12811 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12812 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12813 hweight32(pll->config.crtc_mask), enabled_crtcs);
12815 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12816 sizeof(dpll_hw_state)),
12817 "pll hw state mismatch\n");
12822 intel_modeset_check_state(struct drm_device *dev)
12824 check_wm_state(dev);
12825 check_connector_state(dev);
12826 check_encoder_state(dev);
12827 check_crtc_state(dev);
12828 check_shared_dpll_state(dev);
12831 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12835 * FDI already provided one idea for the dotclock.
12836 * Yell if the encoder disagrees.
12838 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12839 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12840 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12843 static void update_scanline_offset(struct intel_crtc *crtc)
12845 struct drm_device *dev = crtc->base.dev;
12848 * The scanline counter increments at the leading edge of hsync.
12850 * On most platforms it starts counting from vtotal-1 on the
12851 * first active line. That means the scanline counter value is
12852 * always one less than what we would expect. Ie. just after
12853 * start of vblank, which also occurs at start of hsync (on the
12854 * last active line), the scanline counter will read vblank_start-1.
12856 * On gen2 the scanline counter starts counting from 1 instead
12857 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12858 * to keep the value positive), instead of adding one.
12860 * On HSW+ the behaviour of the scanline counter depends on the output
12861 * type. For DP ports it behaves like most other platforms, but on HDMI
12862 * there's an extra 1 line difference. So we need to add two instead of
12863 * one to the value.
12865 if (IS_GEN2(dev)) {
12866 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12869 vtotal = mode->crtc_vtotal;
12870 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12873 crtc->scanline_offset = vtotal - 1;
12874 } else if (HAS_DDI(dev) &&
12875 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12876 crtc->scanline_offset = 2;
12878 crtc->scanline_offset = 1;
12881 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12883 struct drm_device *dev = state->dev;
12884 struct drm_i915_private *dev_priv = to_i915(dev);
12885 struct intel_shared_dpll_config *shared_dpll = NULL;
12886 struct intel_crtc *intel_crtc;
12887 struct intel_crtc_state *intel_crtc_state;
12888 struct drm_crtc *crtc;
12889 struct drm_crtc_state *crtc_state;
12892 if (!dev_priv->display.crtc_compute_clock)
12895 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12898 intel_crtc = to_intel_crtc(crtc);
12899 intel_crtc_state = to_intel_crtc_state(crtc_state);
12900 dpll = intel_crtc_state->shared_dpll;
12902 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12905 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12908 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12910 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12915 * This implements the workaround described in the "notes" section of the mode
12916 * set sequence documentation. When going from no pipes or single pipe to
12917 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12918 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12920 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12922 struct drm_crtc_state *crtc_state;
12923 struct intel_crtc *intel_crtc;
12924 struct drm_crtc *crtc;
12925 struct intel_crtc_state *first_crtc_state = NULL;
12926 struct intel_crtc_state *other_crtc_state = NULL;
12927 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12930 /* look at all crtc's that are going to be enabled in during modeset */
12931 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12932 intel_crtc = to_intel_crtc(crtc);
12934 if (!crtc_state->active || !needs_modeset(crtc_state))
12937 if (first_crtc_state) {
12938 other_crtc_state = to_intel_crtc_state(crtc_state);
12941 first_crtc_state = to_intel_crtc_state(crtc_state);
12942 first_pipe = intel_crtc->pipe;
12946 /* No workaround needed? */
12947 if (!first_crtc_state)
12950 /* w/a possibly needed, check how many crtc's are already enabled. */
12951 for_each_intel_crtc(state->dev, intel_crtc) {
12952 struct intel_crtc_state *pipe_config;
12954 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12955 if (IS_ERR(pipe_config))
12956 return PTR_ERR(pipe_config);
12958 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12960 if (!pipe_config->base.active ||
12961 needs_modeset(&pipe_config->base))
12964 /* 2 or more enabled crtcs means no need for w/a */
12965 if (enabled_pipe != INVALID_PIPE)
12968 enabled_pipe = intel_crtc->pipe;
12971 if (enabled_pipe != INVALID_PIPE)
12972 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12973 else if (other_crtc_state)
12974 other_crtc_state->hsw_workaround_pipe = first_pipe;
12979 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12981 struct drm_crtc *crtc;
12982 struct drm_crtc_state *crtc_state;
12985 /* add all active pipes to the state */
12986 for_each_crtc(state->dev, crtc) {
12987 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12988 if (IS_ERR(crtc_state))
12989 return PTR_ERR(crtc_state);
12991 if (!crtc_state->active || needs_modeset(crtc_state))
12994 crtc_state->mode_changed = true;
12996 ret = drm_atomic_add_affected_connectors(state, crtc);
13000 ret = drm_atomic_add_affected_planes(state, crtc);
13009 /* Code that should eventually be part of atomic_check() */
13010 static int intel_modeset_checks(struct drm_atomic_state *state)
13012 struct drm_device *dev = state->dev;
13013 struct drm_i915_private *dev_priv = dev->dev_private;
13016 if (!check_digital_port_conflicts(state)) {
13017 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13022 * See if the config requires any additional preparation, e.g.
13023 * to adjust global state with pipes off. We need to do this
13024 * here so we can get the modeset_pipe updated config for the new
13025 * mode set on this crtc. For other crtcs we need to use the
13026 * adjusted_mode bits in the crtc directly.
13028 if (dev_priv->display.modeset_calc_cdclk) {
13029 unsigned int cdclk;
13031 ret = dev_priv->display.modeset_calc_cdclk(state);
13033 cdclk = to_intel_atomic_state(state)->cdclk;
13034 if (!ret && cdclk != dev_priv->cdclk_freq)
13035 ret = intel_modeset_all_pipes(state);
13040 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13042 intel_modeset_clear_plls(state);
13044 if (IS_HASWELL(dev))
13045 return haswell_mode_set_planes_workaround(state);
13051 intel_modeset_compute_config(struct drm_atomic_state *state)
13053 struct drm_crtc *crtc;
13054 struct drm_crtc_state *crtc_state;
13056 bool any_ms = false;
13058 ret = drm_atomic_helper_check_modeset(state->dev, state);
13062 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13063 if (!crtc_state->enable) {
13064 if (needs_modeset(crtc_state))
13069 if (to_intel_crtc_state(crtc_state)->quirks &
13070 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13071 ret = drm_atomic_add_affected_planes(state, crtc);
13076 * We ought to handle i915.fastboot here.
13077 * If no modeset is required and the primary plane has
13078 * a fb, update the members of crtc_state as needed,
13079 * and run the necessary updates during vblank evasion.
13083 if (!needs_modeset(crtc_state)) {
13084 ret = drm_atomic_add_affected_connectors(state, crtc);
13089 ret = intel_modeset_pipe_config(crtc,
13090 to_intel_crtc_state(crtc_state));
13094 if (needs_modeset(crtc_state))
13097 intel_dump_pipe_config(to_intel_crtc(crtc),
13098 to_intel_crtc_state(crtc_state),
13103 ret = intel_modeset_checks(state);
13108 to_intel_atomic_state(state)->cdclk =
13109 to_i915(state->dev)->cdclk_freq;
13111 return drm_atomic_helper_check_planes(state->dev, state);
13114 static int __intel_set_mode(struct drm_atomic_state *state)
13116 struct drm_device *dev = state->dev;
13117 struct drm_i915_private *dev_priv = dev->dev_private;
13118 struct drm_crtc *crtc;
13119 struct drm_crtc_state *crtc_state;
13122 bool any_ms = false;
13124 ret = drm_atomic_helper_prepare_planes(dev, state);
13128 drm_atomic_helper_swap_state(dev, state);
13130 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13133 if (!needs_modeset(crtc->state))
13137 intel_pre_plane_update(intel_crtc);
13139 if (crtc_state->active) {
13140 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13141 dev_priv->display.crtc_disable(crtc);
13142 intel_crtc->active = false;
13143 intel_disable_shared_dpll(intel_crtc);
13147 /* Only after disabling all output pipelines that will be changed can we
13148 * update the the output configuration. */
13149 intel_modeset_update_state(state);
13151 /* The state has been swaped above, so state actually contains the
13152 * old state now. */
13154 modeset_update_crtc_power_domains(state);
13156 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13157 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13158 if (needs_modeset(crtc->state) && crtc->state->active) {
13159 update_scanline_offset(to_intel_crtc(crtc));
13160 dev_priv->display.crtc_enable(crtc);
13163 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13166 /* FIXME: add subpixel order */
13168 drm_atomic_helper_cleanup_planes(dev, state);
13170 drm_atomic_state_free(state);
13175 static int intel_set_mode_checked(struct drm_atomic_state *state)
13177 struct drm_device *dev = state->dev;
13180 ret = __intel_set_mode(state);
13182 intel_modeset_check_state(dev);
13187 static int intel_set_mode(struct drm_atomic_state *state)
13191 ret = intel_modeset_compute_config(state);
13195 return intel_set_mode_checked(state);
13198 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13200 struct drm_device *dev = crtc->dev;
13201 struct drm_atomic_state *state;
13202 struct intel_encoder *encoder;
13203 struct intel_connector *connector;
13204 struct drm_connector_state *connector_state;
13205 struct intel_crtc_state *crtc_state;
13208 state = drm_atomic_state_alloc(dev);
13210 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13215 state->acquire_ctx = dev->mode_config.acquire_ctx;
13217 /* The force restore path in the HW readout code relies on the staged
13218 * config still keeping the user requested config while the actual
13219 * state has been overwritten by the configuration read from HW. We
13220 * need to copy the staged config to the atomic state, otherwise the
13221 * mode set will just reapply the state the HW is already in. */
13222 for_each_intel_encoder(dev, encoder) {
13223 if (&encoder->new_crtc->base != crtc)
13226 for_each_intel_connector(dev, connector) {
13227 if (connector->new_encoder != encoder)
13230 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13231 if (IS_ERR(connector_state)) {
13232 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13233 connector->base.base.id,
13234 connector->base.name,
13235 PTR_ERR(connector_state));
13239 connector_state->crtc = crtc;
13240 connector_state->best_encoder = &encoder->base;
13244 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13245 if (IS_ERR(crtc_state)) {
13246 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13247 crtc->base.id, PTR_ERR(crtc_state));
13248 drm_atomic_state_free(state);
13252 crtc_state->base.active = crtc_state->base.enable =
13253 to_intel_crtc(crtc)->new_enabled;
13255 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13257 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13258 crtc->primary->fb, crtc->x, crtc->y);
13260 ret = intel_set_mode(state);
13262 drm_atomic_state_free(state);
13265 #undef for_each_intel_crtc_masked
13267 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13268 struct drm_mode_set *set)
13272 for (ro = 0; ro < set->num_connectors; ro++)
13273 if (set->connectors[ro] == &connector->base)
13280 intel_modeset_stage_output_state(struct drm_device *dev,
13281 struct drm_mode_set *set,
13282 struct drm_atomic_state *state)
13284 struct intel_connector *connector;
13285 struct drm_connector *drm_connector;
13286 struct drm_connector_state *connector_state;
13287 struct drm_crtc *crtc;
13288 struct drm_crtc_state *crtc_state;
13291 /* The upper layers ensure that we either disable a crtc or have a list
13292 * of connectors. For paranoia, double-check this. */
13293 WARN_ON(!set->fb && (set->num_connectors != 0));
13294 WARN_ON(set->fb && (set->num_connectors == 0));
13296 for_each_intel_connector(dev, connector) {
13297 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13299 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13303 drm_atomic_get_connector_state(state, &connector->base);
13304 if (IS_ERR(connector_state))
13305 return PTR_ERR(connector_state);
13308 int pipe = to_intel_crtc(set->crtc)->pipe;
13309 connector_state->best_encoder =
13310 &intel_find_encoder(connector, pipe)->base;
13313 if (connector->base.state->crtc != set->crtc)
13316 /* If we disable the crtc, disable all its connectors. Also, if
13317 * the connector is on the changing crtc but not on the new
13318 * connector list, disable it. */
13319 if (!set->fb || !in_mode_set) {
13320 connector_state->best_encoder = NULL;
13322 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13323 connector->base.base.id,
13324 connector->base.name);
13327 /* connector->new_encoder is now updated for all connectors. */
13329 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13330 connector = to_intel_connector(drm_connector);
13332 if (!connector_state->best_encoder) {
13333 ret = drm_atomic_set_crtc_for_connector(connector_state,
13341 if (intel_connector_in_mode_set(connector, set)) {
13342 struct drm_crtc *crtc = connector->base.state->crtc;
13344 /* If this connector was in a previous crtc, add it
13345 * to the state. We might need to disable it. */
13348 drm_atomic_get_crtc_state(state, crtc);
13349 if (IS_ERR(crtc_state))
13350 return PTR_ERR(crtc_state);
13353 ret = drm_atomic_set_crtc_for_connector(connector_state,
13359 /* Make sure the new CRTC will work with the encoder */
13360 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13361 connector_state->crtc)) {
13365 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13366 connector->base.base.id,
13367 connector->base.name,
13368 connector_state->crtc->base.id);
13370 if (connector_state->best_encoder != &connector->encoder->base)
13371 connector->encoder =
13372 to_intel_encoder(connector_state->best_encoder);
13375 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13376 bool has_connectors;
13378 ret = drm_atomic_add_affected_connectors(state, crtc);
13382 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13383 if (has_connectors != crtc_state->enable)
13384 crtc_state->enable =
13385 crtc_state->active = has_connectors;
13388 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13389 set->fb, set->x, set->y);
13393 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13394 if (IS_ERR(crtc_state))
13395 return PTR_ERR(crtc_state);
13397 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13401 if (set->num_connectors)
13402 crtc_state->active = true;
13407 static int intel_crtc_set_config(struct drm_mode_set *set)
13409 struct drm_device *dev;
13410 struct drm_atomic_state *state = NULL;
13414 BUG_ON(!set->crtc);
13415 BUG_ON(!set->crtc->helper_private);
13417 /* Enforce sane interface api - has been abused by the fb helper. */
13418 BUG_ON(!set->mode && set->fb);
13419 BUG_ON(set->fb && set->num_connectors == 0);
13422 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13423 set->crtc->base.id, set->fb->base.id,
13424 (int)set->num_connectors, set->x, set->y);
13426 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13429 dev = set->crtc->dev;
13431 state = drm_atomic_state_alloc(dev);
13435 state->acquire_ctx = dev->mode_config.acquire_ctx;
13437 ret = intel_modeset_stage_output_state(dev, set, state);
13441 ret = intel_modeset_compute_config(state);
13445 intel_update_pipe_size(to_intel_crtc(set->crtc));
13447 ret = intel_set_mode_checked(state);
13449 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13450 set->crtc->base.id, ret);
13455 drm_atomic_state_free(state);
13459 static const struct drm_crtc_funcs intel_crtc_funcs = {
13460 .gamma_set = intel_crtc_gamma_set,
13461 .set_config = intel_crtc_set_config,
13462 .destroy = intel_crtc_destroy,
13463 .page_flip = intel_crtc_page_flip,
13464 .atomic_duplicate_state = intel_crtc_duplicate_state,
13465 .atomic_destroy_state = intel_crtc_destroy_state,
13468 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13469 struct intel_shared_dpll *pll,
13470 struct intel_dpll_hw_state *hw_state)
13474 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13477 val = I915_READ(PCH_DPLL(pll->id));
13478 hw_state->dpll = val;
13479 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13480 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13482 return val & DPLL_VCO_ENABLE;
13485 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13486 struct intel_shared_dpll *pll)
13488 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13489 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13492 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13493 struct intel_shared_dpll *pll)
13495 /* PCH refclock must be enabled first */
13496 ibx_assert_pch_refclk_enabled(dev_priv);
13498 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13500 /* Wait for the clocks to stabilize. */
13501 POSTING_READ(PCH_DPLL(pll->id));
13504 /* The pixel multiplier can only be updated once the
13505 * DPLL is enabled and the clocks are stable.
13507 * So write it again.
13509 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13510 POSTING_READ(PCH_DPLL(pll->id));
13514 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13515 struct intel_shared_dpll *pll)
13517 struct drm_device *dev = dev_priv->dev;
13518 struct intel_crtc *crtc;
13520 /* Make sure no transcoder isn't still depending on us. */
13521 for_each_intel_crtc(dev, crtc) {
13522 if (intel_crtc_to_shared_dpll(crtc) == pll)
13523 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13526 I915_WRITE(PCH_DPLL(pll->id), 0);
13527 POSTING_READ(PCH_DPLL(pll->id));
13531 static char *ibx_pch_dpll_names[] = {
13536 static void ibx_pch_dpll_init(struct drm_device *dev)
13538 struct drm_i915_private *dev_priv = dev->dev_private;
13541 dev_priv->num_shared_dpll = 2;
13543 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13544 dev_priv->shared_dplls[i].id = i;
13545 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13546 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13547 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13548 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13549 dev_priv->shared_dplls[i].get_hw_state =
13550 ibx_pch_dpll_get_hw_state;
13554 static void intel_shared_dpll_init(struct drm_device *dev)
13556 struct drm_i915_private *dev_priv = dev->dev_private;
13558 intel_update_cdclk(dev);
13561 intel_ddi_pll_init(dev);
13562 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13563 ibx_pch_dpll_init(dev);
13565 dev_priv->num_shared_dpll = 0;
13567 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13571 * intel_prepare_plane_fb - Prepare fb for usage on plane
13572 * @plane: drm plane to prepare for
13573 * @fb: framebuffer to prepare for presentation
13575 * Prepares a framebuffer for usage on a display plane. Generally this
13576 * involves pinning the underlying object and updating the frontbuffer tracking
13577 * bits. Some older platforms need special physical address handling for
13580 * Returns 0 on success, negative error code on failure.
13583 intel_prepare_plane_fb(struct drm_plane *plane,
13584 struct drm_framebuffer *fb,
13585 const struct drm_plane_state *new_state)
13587 struct drm_device *dev = plane->dev;
13588 struct intel_plane *intel_plane = to_intel_plane(plane);
13589 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13590 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13596 mutex_lock(&dev->struct_mutex);
13598 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13599 INTEL_INFO(dev)->cursor_needs_physical) {
13600 int align = IS_I830(dev) ? 16 * 1024 : 256;
13601 ret = i915_gem_object_attach_phys(obj, align);
13603 DRM_DEBUG_KMS("failed to attach phys object\n");
13605 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13609 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13611 mutex_unlock(&dev->struct_mutex);
13617 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13618 * @plane: drm plane to clean up for
13619 * @fb: old framebuffer that was on plane
13621 * Cleans up a framebuffer that has just been removed from a plane.
13624 intel_cleanup_plane_fb(struct drm_plane *plane,
13625 struct drm_framebuffer *fb,
13626 const struct drm_plane_state *old_state)
13628 struct drm_device *dev = plane->dev;
13629 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13634 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13635 !INTEL_INFO(dev)->cursor_needs_physical) {
13636 mutex_lock(&dev->struct_mutex);
13637 intel_unpin_fb_obj(fb, old_state);
13638 mutex_unlock(&dev->struct_mutex);
13643 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13646 struct drm_device *dev;
13647 struct drm_i915_private *dev_priv;
13648 int crtc_clock, cdclk;
13650 if (!intel_crtc || !crtc_state)
13651 return DRM_PLANE_HELPER_NO_SCALING;
13653 dev = intel_crtc->base.dev;
13654 dev_priv = dev->dev_private;
13655 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13656 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13658 if (!crtc_clock || !cdclk)
13659 return DRM_PLANE_HELPER_NO_SCALING;
13662 * skl max scale is lower of:
13663 * close to 3 but not 3, -1 is for that purpose
13667 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13673 intel_check_primary_plane(struct drm_plane *plane,
13674 struct intel_crtc_state *crtc_state,
13675 struct intel_plane_state *state)
13677 struct drm_crtc *crtc = state->base.crtc;
13678 struct drm_framebuffer *fb = state->base.fb;
13679 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13680 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13681 bool can_position = false;
13683 /* use scaler when colorkey is not required */
13684 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13685 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13687 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13688 can_position = true;
13691 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13692 &state->dst, &state->clip,
13693 min_scale, max_scale,
13694 can_position, true,
13699 intel_commit_primary_plane(struct drm_plane *plane,
13700 struct intel_plane_state *state)
13702 struct drm_crtc *crtc = state->base.crtc;
13703 struct drm_framebuffer *fb = state->base.fb;
13704 struct drm_device *dev = plane->dev;
13705 struct drm_i915_private *dev_priv = dev->dev_private;
13706 struct intel_crtc *intel_crtc;
13707 struct drm_rect *src = &state->src;
13709 crtc = crtc ? crtc : plane->crtc;
13710 intel_crtc = to_intel_crtc(crtc);
13713 crtc->x = src->x1 >> 16;
13714 crtc->y = src->y1 >> 16;
13716 if (!crtc->state->active)
13719 if (state->visible)
13720 /* FIXME: kill this fastboot hack */
13721 intel_update_pipe_size(intel_crtc);
13723 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13727 intel_disable_primary_plane(struct drm_plane *plane,
13728 struct drm_crtc *crtc)
13730 struct drm_device *dev = plane->dev;
13731 struct drm_i915_private *dev_priv = dev->dev_private;
13733 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13736 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13738 struct drm_device *dev = crtc->dev;
13739 struct drm_i915_private *dev_priv = dev->dev_private;
13740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13742 if (!needs_modeset(crtc->state))
13743 intel_pre_plane_update(intel_crtc);
13745 if (intel_crtc->atomic.update_wm_pre)
13746 intel_update_watermarks(crtc);
13748 intel_runtime_pm_get(dev_priv);
13750 /* Perform vblank evasion around commit operation */
13751 if (crtc->state->active)
13752 intel_crtc->atomic.evade =
13753 intel_pipe_update_start(intel_crtc,
13754 &intel_crtc->atomic.start_vbl_count);
13756 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13757 skl_detach_scalers(intel_crtc);
13760 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13762 struct drm_device *dev = crtc->dev;
13763 struct drm_i915_private *dev_priv = dev->dev_private;
13764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13766 if (intel_crtc->atomic.evade)
13767 intel_pipe_update_end(intel_crtc,
13768 intel_crtc->atomic.start_vbl_count);
13770 intel_runtime_pm_put(dev_priv);
13772 intel_post_plane_update(intel_crtc);
13776 * intel_plane_destroy - destroy a plane
13777 * @plane: plane to destroy
13779 * Common destruction function for all types of planes (primary, cursor,
13782 void intel_plane_destroy(struct drm_plane *plane)
13784 struct intel_plane *intel_plane = to_intel_plane(plane);
13785 drm_plane_cleanup(plane);
13786 kfree(intel_plane);
13789 const struct drm_plane_funcs intel_plane_funcs = {
13790 .update_plane = drm_atomic_helper_update_plane,
13791 .disable_plane = drm_atomic_helper_disable_plane,
13792 .destroy = intel_plane_destroy,
13793 .set_property = drm_atomic_helper_plane_set_property,
13794 .atomic_get_property = intel_plane_atomic_get_property,
13795 .atomic_set_property = intel_plane_atomic_set_property,
13796 .atomic_duplicate_state = intel_plane_duplicate_state,
13797 .atomic_destroy_state = intel_plane_destroy_state,
13801 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13804 struct intel_plane *primary;
13805 struct intel_plane_state *state;
13806 const uint32_t *intel_primary_formats;
13809 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13810 if (primary == NULL)
13813 state = intel_create_plane_state(&primary->base);
13818 primary->base.state = &state->base;
13820 primary->can_scale = false;
13821 primary->max_downscale = 1;
13822 if (INTEL_INFO(dev)->gen >= 9) {
13823 primary->can_scale = true;
13824 state->scaler_id = -1;
13826 primary->pipe = pipe;
13827 primary->plane = pipe;
13828 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13829 primary->check_plane = intel_check_primary_plane;
13830 primary->commit_plane = intel_commit_primary_plane;
13831 primary->disable_plane = intel_disable_primary_plane;
13832 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13833 primary->plane = !pipe;
13835 if (INTEL_INFO(dev)->gen >= 9) {
13836 intel_primary_formats = skl_primary_formats;
13837 num_formats = ARRAY_SIZE(skl_primary_formats);
13838 } else if (INTEL_INFO(dev)->gen >= 4) {
13839 intel_primary_formats = i965_primary_formats;
13840 num_formats = ARRAY_SIZE(i965_primary_formats);
13842 intel_primary_formats = i8xx_primary_formats;
13843 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13846 drm_universal_plane_init(dev, &primary->base, 0,
13847 &intel_plane_funcs,
13848 intel_primary_formats, num_formats,
13849 DRM_PLANE_TYPE_PRIMARY);
13851 if (INTEL_INFO(dev)->gen >= 4)
13852 intel_create_rotation_property(dev, primary);
13854 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13856 return &primary->base;
13859 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13861 if (!dev->mode_config.rotation_property) {
13862 unsigned long flags = BIT(DRM_ROTATE_0) |
13863 BIT(DRM_ROTATE_180);
13865 if (INTEL_INFO(dev)->gen >= 9)
13866 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13868 dev->mode_config.rotation_property =
13869 drm_mode_create_rotation_property(dev, flags);
13871 if (dev->mode_config.rotation_property)
13872 drm_object_attach_property(&plane->base.base,
13873 dev->mode_config.rotation_property,
13874 plane->base.state->rotation);
13878 intel_check_cursor_plane(struct drm_plane *plane,
13879 struct intel_crtc_state *crtc_state,
13880 struct intel_plane_state *state)
13882 struct drm_crtc *crtc = crtc_state->base.crtc;
13883 struct drm_framebuffer *fb = state->base.fb;
13884 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13888 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13889 &state->dst, &state->clip,
13890 DRM_PLANE_HELPER_NO_SCALING,
13891 DRM_PLANE_HELPER_NO_SCALING,
13892 true, true, &state->visible);
13896 /* if we want to turn off the cursor ignore width and height */
13900 /* Check for which cursor types we support */
13901 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13902 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13903 state->base.crtc_w, state->base.crtc_h);
13907 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13908 if (obj->base.size < stride * state->base.crtc_h) {
13909 DRM_DEBUG_KMS("buffer is too small\n");
13913 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13914 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13922 intel_disable_cursor_plane(struct drm_plane *plane,
13923 struct drm_crtc *crtc)
13925 intel_crtc_update_cursor(crtc, false);
13929 intel_commit_cursor_plane(struct drm_plane *plane,
13930 struct intel_plane_state *state)
13932 struct drm_crtc *crtc = state->base.crtc;
13933 struct drm_device *dev = plane->dev;
13934 struct intel_crtc *intel_crtc;
13935 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13938 crtc = crtc ? crtc : plane->crtc;
13939 intel_crtc = to_intel_crtc(crtc);
13941 plane->fb = state->base.fb;
13942 crtc->cursor_x = state->base.crtc_x;
13943 crtc->cursor_y = state->base.crtc_y;
13945 if (intel_crtc->cursor_bo == obj)
13950 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13951 addr = i915_gem_obj_ggtt_offset(obj);
13953 addr = obj->phys_handle->busaddr;
13955 intel_crtc->cursor_addr = addr;
13956 intel_crtc->cursor_bo = obj;
13959 if (crtc->state->active)
13960 intel_crtc_update_cursor(crtc, state->visible);
13963 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13966 struct intel_plane *cursor;
13967 struct intel_plane_state *state;
13969 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13970 if (cursor == NULL)
13973 state = intel_create_plane_state(&cursor->base);
13978 cursor->base.state = &state->base;
13980 cursor->can_scale = false;
13981 cursor->max_downscale = 1;
13982 cursor->pipe = pipe;
13983 cursor->plane = pipe;
13984 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13985 cursor->check_plane = intel_check_cursor_plane;
13986 cursor->commit_plane = intel_commit_cursor_plane;
13987 cursor->disable_plane = intel_disable_cursor_plane;
13989 drm_universal_plane_init(dev, &cursor->base, 0,
13990 &intel_plane_funcs,
13991 intel_cursor_formats,
13992 ARRAY_SIZE(intel_cursor_formats),
13993 DRM_PLANE_TYPE_CURSOR);
13995 if (INTEL_INFO(dev)->gen >= 4) {
13996 if (!dev->mode_config.rotation_property)
13997 dev->mode_config.rotation_property =
13998 drm_mode_create_rotation_property(dev,
13999 BIT(DRM_ROTATE_0) |
14000 BIT(DRM_ROTATE_180));
14001 if (dev->mode_config.rotation_property)
14002 drm_object_attach_property(&cursor->base.base,
14003 dev->mode_config.rotation_property,
14004 state->base.rotation);
14007 if (INTEL_INFO(dev)->gen >=9)
14008 state->scaler_id = -1;
14010 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14012 return &cursor->base;
14015 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14016 struct intel_crtc_state *crtc_state)
14019 struct intel_scaler *intel_scaler;
14020 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14022 for (i = 0; i < intel_crtc->num_scalers; i++) {
14023 intel_scaler = &scaler_state->scalers[i];
14024 intel_scaler->in_use = 0;
14025 intel_scaler->mode = PS_SCALER_MODE_DYN;
14028 scaler_state->scaler_id = -1;
14031 static void intel_crtc_init(struct drm_device *dev, int pipe)
14033 struct drm_i915_private *dev_priv = dev->dev_private;
14034 struct intel_crtc *intel_crtc;
14035 struct intel_crtc_state *crtc_state = NULL;
14036 struct drm_plane *primary = NULL;
14037 struct drm_plane *cursor = NULL;
14040 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14041 if (intel_crtc == NULL)
14044 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14047 intel_crtc->config = crtc_state;
14048 intel_crtc->base.state = &crtc_state->base;
14049 crtc_state->base.crtc = &intel_crtc->base;
14051 /* initialize shared scalers */
14052 if (INTEL_INFO(dev)->gen >= 9) {
14053 if (pipe == PIPE_C)
14054 intel_crtc->num_scalers = 1;
14056 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14058 skl_init_scalers(dev, intel_crtc, crtc_state);
14061 primary = intel_primary_plane_create(dev, pipe);
14065 cursor = intel_cursor_plane_create(dev, pipe);
14069 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14070 cursor, &intel_crtc_funcs);
14074 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14075 for (i = 0; i < 256; i++) {
14076 intel_crtc->lut_r[i] = i;
14077 intel_crtc->lut_g[i] = i;
14078 intel_crtc->lut_b[i] = i;
14082 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14083 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14085 intel_crtc->pipe = pipe;
14086 intel_crtc->plane = pipe;
14087 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14088 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14089 intel_crtc->plane = !pipe;
14092 intel_crtc->cursor_base = ~0;
14093 intel_crtc->cursor_cntl = ~0;
14094 intel_crtc->cursor_size = ~0;
14096 intel_crtc->wm.cxsr_allowed = true;
14098 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14099 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14100 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14101 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14103 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14105 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14110 drm_plane_cleanup(primary);
14112 drm_plane_cleanup(cursor);
14117 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14119 struct drm_encoder *encoder = connector->base.encoder;
14120 struct drm_device *dev = connector->base.dev;
14122 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14124 if (!encoder || WARN_ON(!encoder->crtc))
14125 return INVALID_PIPE;
14127 return to_intel_crtc(encoder->crtc)->pipe;
14130 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14131 struct drm_file *file)
14133 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14134 struct drm_crtc *drmmode_crtc;
14135 struct intel_crtc *crtc;
14137 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14139 if (!drmmode_crtc) {
14140 DRM_ERROR("no such CRTC id\n");
14144 crtc = to_intel_crtc(drmmode_crtc);
14145 pipe_from_crtc_id->pipe = crtc->pipe;
14150 static int intel_encoder_clones(struct intel_encoder *encoder)
14152 struct drm_device *dev = encoder->base.dev;
14153 struct intel_encoder *source_encoder;
14154 int index_mask = 0;
14157 for_each_intel_encoder(dev, source_encoder) {
14158 if (encoders_cloneable(encoder, source_encoder))
14159 index_mask |= (1 << entry);
14167 static bool has_edp_a(struct drm_device *dev)
14169 struct drm_i915_private *dev_priv = dev->dev_private;
14171 if (!IS_MOBILE(dev))
14174 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14177 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14183 static bool intel_crt_present(struct drm_device *dev)
14185 struct drm_i915_private *dev_priv = dev->dev_private;
14187 if (INTEL_INFO(dev)->gen >= 9)
14190 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14193 if (IS_CHERRYVIEW(dev))
14196 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14202 static void intel_setup_outputs(struct drm_device *dev)
14204 struct drm_i915_private *dev_priv = dev->dev_private;
14205 struct intel_encoder *encoder;
14206 bool dpd_is_edp = false;
14208 intel_lvds_init(dev);
14210 if (intel_crt_present(dev))
14211 intel_crt_init(dev);
14213 if (IS_BROXTON(dev)) {
14215 * FIXME: Broxton doesn't support port detection via the
14216 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14217 * detect the ports.
14219 intel_ddi_init(dev, PORT_A);
14220 intel_ddi_init(dev, PORT_B);
14221 intel_ddi_init(dev, PORT_C);
14222 } else if (HAS_DDI(dev)) {
14226 * Haswell uses DDI functions to detect digital outputs.
14227 * On SKL pre-D0 the strap isn't connected, so we assume
14230 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14231 /* WaIgnoreDDIAStrap: skl */
14233 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14234 intel_ddi_init(dev, PORT_A);
14236 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14238 found = I915_READ(SFUSE_STRAP);
14240 if (found & SFUSE_STRAP_DDIB_DETECTED)
14241 intel_ddi_init(dev, PORT_B);
14242 if (found & SFUSE_STRAP_DDIC_DETECTED)
14243 intel_ddi_init(dev, PORT_C);
14244 if (found & SFUSE_STRAP_DDID_DETECTED)
14245 intel_ddi_init(dev, PORT_D);
14246 } else if (HAS_PCH_SPLIT(dev)) {
14248 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14250 if (has_edp_a(dev))
14251 intel_dp_init(dev, DP_A, PORT_A);
14253 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14254 /* PCH SDVOB multiplex with HDMIB */
14255 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14257 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14258 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14259 intel_dp_init(dev, PCH_DP_B, PORT_B);
14262 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14263 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14265 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14266 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14268 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14269 intel_dp_init(dev, PCH_DP_C, PORT_C);
14271 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14272 intel_dp_init(dev, PCH_DP_D, PORT_D);
14273 } else if (IS_VALLEYVIEW(dev)) {
14275 * The DP_DETECTED bit is the latched state of the DDC
14276 * SDA pin at boot. However since eDP doesn't require DDC
14277 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14278 * eDP ports may have been muxed to an alternate function.
14279 * Thus we can't rely on the DP_DETECTED bit alone to detect
14280 * eDP ports. Consult the VBT as well as DP_DETECTED to
14281 * detect eDP ports.
14283 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14284 !intel_dp_is_edp(dev, PORT_B))
14285 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14287 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14288 intel_dp_is_edp(dev, PORT_B))
14289 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14291 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14292 !intel_dp_is_edp(dev, PORT_C))
14293 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14295 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14296 intel_dp_is_edp(dev, PORT_C))
14297 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14299 if (IS_CHERRYVIEW(dev)) {
14300 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14301 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14303 /* eDP not supported on port D, so don't check VBT */
14304 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14305 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14308 intel_dsi_init(dev);
14309 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14310 bool found = false;
14312 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14313 DRM_DEBUG_KMS("probing SDVOB\n");
14314 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14315 if (!found && IS_G4X(dev)) {
14316 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14317 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14320 if (!found && IS_G4X(dev))
14321 intel_dp_init(dev, DP_B, PORT_B);
14324 /* Before G4X SDVOC doesn't have its own detect register */
14326 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14327 DRM_DEBUG_KMS("probing SDVOC\n");
14328 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14331 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14334 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14335 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14338 intel_dp_init(dev, DP_C, PORT_C);
14342 (I915_READ(DP_D) & DP_DETECTED))
14343 intel_dp_init(dev, DP_D, PORT_D);
14344 } else if (IS_GEN2(dev))
14345 intel_dvo_init(dev);
14347 if (SUPPORTS_TV(dev))
14348 intel_tv_init(dev);
14350 intel_psr_init(dev);
14352 for_each_intel_encoder(dev, encoder) {
14353 encoder->base.possible_crtcs = encoder->crtc_mask;
14354 encoder->base.possible_clones =
14355 intel_encoder_clones(encoder);
14358 intel_init_pch_refclk(dev);
14360 drm_helper_move_panel_connectors_to_head(dev);
14363 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14365 struct drm_device *dev = fb->dev;
14366 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14368 drm_framebuffer_cleanup(fb);
14369 mutex_lock(&dev->struct_mutex);
14370 WARN_ON(!intel_fb->obj->framebuffer_references--);
14371 drm_gem_object_unreference(&intel_fb->obj->base);
14372 mutex_unlock(&dev->struct_mutex);
14376 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14377 struct drm_file *file,
14378 unsigned int *handle)
14380 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14381 struct drm_i915_gem_object *obj = intel_fb->obj;
14383 return drm_gem_handle_create(file, &obj->base, handle);
14386 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14387 .destroy = intel_user_framebuffer_destroy,
14388 .create_handle = intel_user_framebuffer_create_handle,
14392 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14393 uint32_t pixel_format)
14395 u32 gen = INTEL_INFO(dev)->gen;
14398 /* "The stride in bytes must not exceed the of the size of 8K
14399 * pixels and 32K bytes."
14401 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14402 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14404 } else if (gen >= 4) {
14405 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14409 } else if (gen >= 3) {
14410 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14415 /* XXX DSPC is limited to 4k tiled */
14420 static int intel_framebuffer_init(struct drm_device *dev,
14421 struct intel_framebuffer *intel_fb,
14422 struct drm_mode_fb_cmd2 *mode_cmd,
14423 struct drm_i915_gem_object *obj)
14425 unsigned int aligned_height;
14427 u32 pitch_limit, stride_alignment;
14429 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14431 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14432 /* Enforce that fb modifier and tiling mode match, but only for
14433 * X-tiled. This is needed for FBC. */
14434 if (!!(obj->tiling_mode == I915_TILING_X) !=
14435 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14436 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14440 if (obj->tiling_mode == I915_TILING_X)
14441 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14442 else if (obj->tiling_mode == I915_TILING_Y) {
14443 DRM_DEBUG("No Y tiling for legacy addfb\n");
14448 /* Passed in modifier sanity checking. */
14449 switch (mode_cmd->modifier[0]) {
14450 case I915_FORMAT_MOD_Y_TILED:
14451 case I915_FORMAT_MOD_Yf_TILED:
14452 if (INTEL_INFO(dev)->gen < 9) {
14453 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14454 mode_cmd->modifier[0]);
14457 case DRM_FORMAT_MOD_NONE:
14458 case I915_FORMAT_MOD_X_TILED:
14461 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14462 mode_cmd->modifier[0]);
14466 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14467 mode_cmd->pixel_format);
14468 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14469 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14470 mode_cmd->pitches[0], stride_alignment);
14474 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14475 mode_cmd->pixel_format);
14476 if (mode_cmd->pitches[0] > pitch_limit) {
14477 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14478 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14479 "tiled" : "linear",
14480 mode_cmd->pitches[0], pitch_limit);
14484 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14485 mode_cmd->pitches[0] != obj->stride) {
14486 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14487 mode_cmd->pitches[0], obj->stride);
14491 /* Reject formats not supported by any plane early. */
14492 switch (mode_cmd->pixel_format) {
14493 case DRM_FORMAT_C8:
14494 case DRM_FORMAT_RGB565:
14495 case DRM_FORMAT_XRGB8888:
14496 case DRM_FORMAT_ARGB8888:
14498 case DRM_FORMAT_XRGB1555:
14499 if (INTEL_INFO(dev)->gen > 3) {
14500 DRM_DEBUG("unsupported pixel format: %s\n",
14501 drm_get_format_name(mode_cmd->pixel_format));
14505 case DRM_FORMAT_ABGR8888:
14506 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14507 DRM_DEBUG("unsupported pixel format: %s\n",
14508 drm_get_format_name(mode_cmd->pixel_format));
14512 case DRM_FORMAT_XBGR8888:
14513 case DRM_FORMAT_XRGB2101010:
14514 case DRM_FORMAT_XBGR2101010:
14515 if (INTEL_INFO(dev)->gen < 4) {
14516 DRM_DEBUG("unsupported pixel format: %s\n",
14517 drm_get_format_name(mode_cmd->pixel_format));
14521 case DRM_FORMAT_ABGR2101010:
14522 if (!IS_VALLEYVIEW(dev)) {
14523 DRM_DEBUG("unsupported pixel format: %s\n",
14524 drm_get_format_name(mode_cmd->pixel_format));
14528 case DRM_FORMAT_YUYV:
14529 case DRM_FORMAT_UYVY:
14530 case DRM_FORMAT_YVYU:
14531 case DRM_FORMAT_VYUY:
14532 if (INTEL_INFO(dev)->gen < 5) {
14533 DRM_DEBUG("unsupported pixel format: %s\n",
14534 drm_get_format_name(mode_cmd->pixel_format));
14539 DRM_DEBUG("unsupported pixel format: %s\n",
14540 drm_get_format_name(mode_cmd->pixel_format));
14544 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14545 if (mode_cmd->offsets[0] != 0)
14548 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14549 mode_cmd->pixel_format,
14550 mode_cmd->modifier[0]);
14551 /* FIXME drm helper for size checks (especially planar formats)? */
14552 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14555 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14556 intel_fb->obj = obj;
14557 intel_fb->obj->framebuffer_references++;
14559 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14561 DRM_ERROR("framebuffer init failed %d\n", ret);
14568 static struct drm_framebuffer *
14569 intel_user_framebuffer_create(struct drm_device *dev,
14570 struct drm_file *filp,
14571 struct drm_mode_fb_cmd2 *mode_cmd)
14573 struct drm_i915_gem_object *obj;
14575 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14576 mode_cmd->handles[0]));
14577 if (&obj->base == NULL)
14578 return ERR_PTR(-ENOENT);
14580 return intel_framebuffer_create(dev, mode_cmd, obj);
14583 #ifndef CONFIG_DRM_I915_FBDEV
14584 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14589 static const struct drm_mode_config_funcs intel_mode_funcs = {
14590 .fb_create = intel_user_framebuffer_create,
14591 .output_poll_changed = intel_fbdev_output_poll_changed,
14592 .atomic_check = intel_atomic_check,
14593 .atomic_commit = intel_atomic_commit,
14594 .atomic_state_alloc = intel_atomic_state_alloc,
14595 .atomic_state_clear = intel_atomic_state_clear,
14598 /* Set up chip specific display functions */
14599 static void intel_init_display(struct drm_device *dev)
14601 struct drm_i915_private *dev_priv = dev->dev_private;
14603 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14604 dev_priv->display.find_dpll = g4x_find_best_dpll;
14605 else if (IS_CHERRYVIEW(dev))
14606 dev_priv->display.find_dpll = chv_find_best_dpll;
14607 else if (IS_VALLEYVIEW(dev))
14608 dev_priv->display.find_dpll = vlv_find_best_dpll;
14609 else if (IS_PINEVIEW(dev))
14610 dev_priv->display.find_dpll = pnv_find_best_dpll;
14612 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14614 if (INTEL_INFO(dev)->gen >= 9) {
14615 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14616 dev_priv->display.get_initial_plane_config =
14617 skylake_get_initial_plane_config;
14618 dev_priv->display.crtc_compute_clock =
14619 haswell_crtc_compute_clock;
14620 dev_priv->display.crtc_enable = haswell_crtc_enable;
14621 dev_priv->display.crtc_disable = haswell_crtc_disable;
14622 dev_priv->display.update_primary_plane =
14623 skylake_update_primary_plane;
14624 } else if (HAS_DDI(dev)) {
14625 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14626 dev_priv->display.get_initial_plane_config =
14627 ironlake_get_initial_plane_config;
14628 dev_priv->display.crtc_compute_clock =
14629 haswell_crtc_compute_clock;
14630 dev_priv->display.crtc_enable = haswell_crtc_enable;
14631 dev_priv->display.crtc_disable = haswell_crtc_disable;
14632 dev_priv->display.update_primary_plane =
14633 ironlake_update_primary_plane;
14634 } else if (HAS_PCH_SPLIT(dev)) {
14635 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14636 dev_priv->display.get_initial_plane_config =
14637 ironlake_get_initial_plane_config;
14638 dev_priv->display.crtc_compute_clock =
14639 ironlake_crtc_compute_clock;
14640 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14641 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14642 dev_priv->display.update_primary_plane =
14643 ironlake_update_primary_plane;
14644 } else if (IS_VALLEYVIEW(dev)) {
14645 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14646 dev_priv->display.get_initial_plane_config =
14647 i9xx_get_initial_plane_config;
14648 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14649 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14650 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14651 dev_priv->display.update_primary_plane =
14652 i9xx_update_primary_plane;
14654 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14655 dev_priv->display.get_initial_plane_config =
14656 i9xx_get_initial_plane_config;
14657 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14658 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14659 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14660 dev_priv->display.update_primary_plane =
14661 i9xx_update_primary_plane;
14664 /* Returns the core display clock speed */
14665 if (IS_SKYLAKE(dev))
14666 dev_priv->display.get_display_clock_speed =
14667 skylake_get_display_clock_speed;
14668 else if (IS_BROXTON(dev))
14669 dev_priv->display.get_display_clock_speed =
14670 broxton_get_display_clock_speed;
14671 else if (IS_BROADWELL(dev))
14672 dev_priv->display.get_display_clock_speed =
14673 broadwell_get_display_clock_speed;
14674 else if (IS_HASWELL(dev))
14675 dev_priv->display.get_display_clock_speed =
14676 haswell_get_display_clock_speed;
14677 else if (IS_VALLEYVIEW(dev))
14678 dev_priv->display.get_display_clock_speed =
14679 valleyview_get_display_clock_speed;
14680 else if (IS_GEN5(dev))
14681 dev_priv->display.get_display_clock_speed =
14682 ilk_get_display_clock_speed;
14683 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14684 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14685 dev_priv->display.get_display_clock_speed =
14686 i945_get_display_clock_speed;
14687 else if (IS_GM45(dev))
14688 dev_priv->display.get_display_clock_speed =
14689 gm45_get_display_clock_speed;
14690 else if (IS_CRESTLINE(dev))
14691 dev_priv->display.get_display_clock_speed =
14692 i965gm_get_display_clock_speed;
14693 else if (IS_PINEVIEW(dev))
14694 dev_priv->display.get_display_clock_speed =
14695 pnv_get_display_clock_speed;
14696 else if (IS_G33(dev) || IS_G4X(dev))
14697 dev_priv->display.get_display_clock_speed =
14698 g33_get_display_clock_speed;
14699 else if (IS_I915G(dev))
14700 dev_priv->display.get_display_clock_speed =
14701 i915_get_display_clock_speed;
14702 else if (IS_I945GM(dev) || IS_845G(dev))
14703 dev_priv->display.get_display_clock_speed =
14704 i9xx_misc_get_display_clock_speed;
14705 else if (IS_PINEVIEW(dev))
14706 dev_priv->display.get_display_clock_speed =
14707 pnv_get_display_clock_speed;
14708 else if (IS_I915GM(dev))
14709 dev_priv->display.get_display_clock_speed =
14710 i915gm_get_display_clock_speed;
14711 else if (IS_I865G(dev))
14712 dev_priv->display.get_display_clock_speed =
14713 i865_get_display_clock_speed;
14714 else if (IS_I85X(dev))
14715 dev_priv->display.get_display_clock_speed =
14716 i85x_get_display_clock_speed;
14718 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14719 dev_priv->display.get_display_clock_speed =
14720 i830_get_display_clock_speed;
14723 if (IS_GEN5(dev)) {
14724 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14725 } else if (IS_GEN6(dev)) {
14726 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14727 } else if (IS_IVYBRIDGE(dev)) {
14728 /* FIXME: detect B0+ stepping and use auto training */
14729 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14730 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14731 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14732 if (IS_BROADWELL(dev)) {
14733 dev_priv->display.modeset_commit_cdclk =
14734 broadwell_modeset_commit_cdclk;
14735 dev_priv->display.modeset_calc_cdclk =
14736 broadwell_modeset_calc_cdclk;
14738 } else if (IS_VALLEYVIEW(dev)) {
14739 dev_priv->display.modeset_commit_cdclk =
14740 valleyview_modeset_commit_cdclk;
14741 dev_priv->display.modeset_calc_cdclk =
14742 valleyview_modeset_calc_cdclk;
14743 } else if (IS_BROXTON(dev)) {
14744 dev_priv->display.modeset_commit_cdclk =
14745 broxton_modeset_commit_cdclk;
14746 dev_priv->display.modeset_calc_cdclk =
14747 broxton_modeset_calc_cdclk;
14750 switch (INTEL_INFO(dev)->gen) {
14752 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14756 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14761 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14765 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14768 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14769 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14772 /* Drop through - unsupported since execlist only. */
14774 /* Default just returns -ENODEV to indicate unsupported */
14775 dev_priv->display.queue_flip = intel_default_queue_flip;
14778 intel_panel_init_backlight_funcs(dev);
14780 mutex_init(&dev_priv->pps_mutex);
14784 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14785 * resume, or other times. This quirk makes sure that's the case for
14786 * affected systems.
14788 static void quirk_pipea_force(struct drm_device *dev)
14790 struct drm_i915_private *dev_priv = dev->dev_private;
14792 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14793 DRM_INFO("applying pipe a force quirk\n");
14796 static void quirk_pipeb_force(struct drm_device *dev)
14798 struct drm_i915_private *dev_priv = dev->dev_private;
14800 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14801 DRM_INFO("applying pipe b force quirk\n");
14805 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14807 static void quirk_ssc_force_disable(struct drm_device *dev)
14809 struct drm_i915_private *dev_priv = dev->dev_private;
14810 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14811 DRM_INFO("applying lvds SSC disable quirk\n");
14815 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14818 static void quirk_invert_brightness(struct drm_device *dev)
14820 struct drm_i915_private *dev_priv = dev->dev_private;
14821 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14822 DRM_INFO("applying inverted panel brightness quirk\n");
14825 /* Some VBT's incorrectly indicate no backlight is present */
14826 static void quirk_backlight_present(struct drm_device *dev)
14828 struct drm_i915_private *dev_priv = dev->dev_private;
14829 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14830 DRM_INFO("applying backlight present quirk\n");
14833 struct intel_quirk {
14835 int subsystem_vendor;
14836 int subsystem_device;
14837 void (*hook)(struct drm_device *dev);
14840 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14841 struct intel_dmi_quirk {
14842 void (*hook)(struct drm_device *dev);
14843 const struct dmi_system_id (*dmi_id_list)[];
14846 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14848 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14852 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14854 .dmi_id_list = &(const struct dmi_system_id[]) {
14856 .callback = intel_dmi_reverse_brightness,
14857 .ident = "NCR Corporation",
14858 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14859 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14862 { } /* terminating entry */
14864 .hook = quirk_invert_brightness,
14868 static struct intel_quirk intel_quirks[] = {
14869 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14870 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14872 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14873 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14875 /* 830 needs to leave pipe A & dpll A up */
14876 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14878 /* 830 needs to leave pipe B & dpll B up */
14879 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14881 /* Lenovo U160 cannot use SSC on LVDS */
14882 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14884 /* Sony Vaio Y cannot use SSC on LVDS */
14885 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14887 /* Acer Aspire 5734Z must invert backlight brightness */
14888 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14890 /* Acer/eMachines G725 */
14891 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14893 /* Acer/eMachines e725 */
14894 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14896 /* Acer/Packard Bell NCL20 */
14897 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14899 /* Acer Aspire 4736Z */
14900 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14902 /* Acer Aspire 5336 */
14903 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14905 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14906 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14908 /* Acer C720 Chromebook (Core i3 4005U) */
14909 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14911 /* Apple Macbook 2,1 (Core 2 T7400) */
14912 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14914 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14915 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14917 /* HP Chromebook 14 (Celeron 2955U) */
14918 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14920 /* Dell Chromebook 11 */
14921 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14924 static void intel_init_quirks(struct drm_device *dev)
14926 struct pci_dev *d = dev->pdev;
14929 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14930 struct intel_quirk *q = &intel_quirks[i];
14932 if (d->device == q->device &&
14933 (d->subsystem_vendor == q->subsystem_vendor ||
14934 q->subsystem_vendor == PCI_ANY_ID) &&
14935 (d->subsystem_device == q->subsystem_device ||
14936 q->subsystem_device == PCI_ANY_ID))
14939 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14940 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14941 intel_dmi_quirks[i].hook(dev);
14945 /* Disable the VGA plane that we never use */
14946 static void i915_disable_vga(struct drm_device *dev)
14948 struct drm_i915_private *dev_priv = dev->dev_private;
14950 u32 vga_reg = i915_vgacntrl_reg(dev);
14952 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14953 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14954 outb(SR01, VGA_SR_INDEX);
14955 sr1 = inb(VGA_SR_DATA);
14956 outb(sr1 | 1<<5, VGA_SR_DATA);
14957 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14960 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14961 POSTING_READ(vga_reg);
14964 void intel_modeset_init_hw(struct drm_device *dev)
14966 intel_update_cdclk(dev);
14967 intel_prepare_ddi(dev);
14968 intel_init_clock_gating(dev);
14969 intel_enable_gt_powersave(dev);
14972 void intel_modeset_init(struct drm_device *dev)
14974 struct drm_i915_private *dev_priv = dev->dev_private;
14977 struct intel_crtc *crtc;
14979 drm_mode_config_init(dev);
14981 dev->mode_config.min_width = 0;
14982 dev->mode_config.min_height = 0;
14984 dev->mode_config.preferred_depth = 24;
14985 dev->mode_config.prefer_shadow = 1;
14987 dev->mode_config.allow_fb_modifiers = true;
14989 dev->mode_config.funcs = &intel_mode_funcs;
14991 intel_init_quirks(dev);
14993 intel_init_pm(dev);
14995 if (INTEL_INFO(dev)->num_pipes == 0)
14998 intel_init_display(dev);
14999 intel_init_audio(dev);
15001 if (IS_GEN2(dev)) {
15002 dev->mode_config.max_width = 2048;
15003 dev->mode_config.max_height = 2048;
15004 } else if (IS_GEN3(dev)) {
15005 dev->mode_config.max_width = 4096;
15006 dev->mode_config.max_height = 4096;
15008 dev->mode_config.max_width = 8192;
15009 dev->mode_config.max_height = 8192;
15012 if (IS_845G(dev) || IS_I865G(dev)) {
15013 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15014 dev->mode_config.cursor_height = 1023;
15015 } else if (IS_GEN2(dev)) {
15016 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15017 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15019 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15020 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15023 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15025 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15026 INTEL_INFO(dev)->num_pipes,
15027 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15029 for_each_pipe(dev_priv, pipe) {
15030 intel_crtc_init(dev, pipe);
15031 for_each_sprite(dev_priv, pipe, sprite) {
15032 ret = intel_plane_init(dev, pipe, sprite);
15034 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15035 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15039 intel_init_dpio(dev);
15041 intel_shared_dpll_init(dev);
15043 /* Just disable it once at startup */
15044 i915_disable_vga(dev);
15045 intel_setup_outputs(dev);
15047 /* Just in case the BIOS is doing something questionable. */
15048 intel_fbc_disable(dev);
15050 drm_modeset_lock_all(dev);
15051 intel_modeset_setup_hw_state(dev, false);
15052 drm_modeset_unlock_all(dev);
15054 for_each_intel_crtc(dev, crtc) {
15059 * Note that reserving the BIOS fb up front prevents us
15060 * from stuffing other stolen allocations like the ring
15061 * on top. This prevents some ugliness at boot time, and
15062 * can even allow for smooth boot transitions if the BIOS
15063 * fb is large enough for the active pipe configuration.
15065 if (dev_priv->display.get_initial_plane_config) {
15066 dev_priv->display.get_initial_plane_config(crtc,
15067 &crtc->plane_config);
15069 * If the fb is shared between multiple heads, we'll
15070 * just get the first one.
15072 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15077 static void intel_enable_pipe_a(struct drm_device *dev)
15079 struct intel_connector *connector;
15080 struct drm_connector *crt = NULL;
15081 struct intel_load_detect_pipe load_detect_temp;
15082 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15084 /* We can't just switch on the pipe A, we need to set things up with a
15085 * proper mode and output configuration. As a gross hack, enable pipe A
15086 * by enabling the load detect pipe once. */
15087 for_each_intel_connector(dev, connector) {
15088 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15089 crt = &connector->base;
15097 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15098 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15102 intel_check_plane_mapping(struct intel_crtc *crtc)
15104 struct drm_device *dev = crtc->base.dev;
15105 struct drm_i915_private *dev_priv = dev->dev_private;
15108 if (INTEL_INFO(dev)->num_pipes == 1)
15111 reg = DSPCNTR(!crtc->plane);
15112 val = I915_READ(reg);
15114 if ((val & DISPLAY_PLANE_ENABLE) &&
15115 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15121 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15123 struct drm_device *dev = crtc->base.dev;
15124 struct drm_i915_private *dev_priv = dev->dev_private;
15125 struct intel_encoder *encoder;
15129 /* Clear any frame start delays used for debugging left by the BIOS */
15130 reg = PIPECONF(crtc->config->cpu_transcoder);
15131 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15133 /* restore vblank interrupts to correct state */
15134 drm_crtc_vblank_reset(&crtc->base);
15135 if (crtc->active) {
15136 update_scanline_offset(crtc);
15137 drm_crtc_vblank_on(&crtc->base);
15140 /* We need to sanitize the plane -> pipe mapping first because this will
15141 * disable the crtc (and hence change the state) if it is wrong. Note
15142 * that gen4+ has a fixed plane -> pipe mapping. */
15143 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15146 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15147 crtc->base.base.id);
15149 /* Pipe has the wrong plane attached and the plane is active.
15150 * Temporarily change the plane mapping and disable everything
15152 plane = crtc->plane;
15153 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15154 crtc->plane = !plane;
15155 intel_crtc_disable_noatomic(&crtc->base);
15156 crtc->plane = plane;
15159 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15160 crtc->pipe == PIPE_A && !crtc->active) {
15161 /* BIOS forgot to enable pipe A, this mostly happens after
15162 * resume. Force-enable the pipe to fix this, the update_dpms
15163 * call below we restore the pipe to the right state, but leave
15164 * the required bits on. */
15165 intel_enable_pipe_a(dev);
15168 /* Adjust the state of the output pipe according to whether we
15169 * have active connectors/encoders. */
15171 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15172 enable |= encoder->connectors_active;
15175 intel_crtc_disable_noatomic(&crtc->base);
15177 if (crtc->active != crtc->base.state->active) {
15179 /* This can happen either due to bugs in the get_hw_state
15180 * functions or because of calls to intel_crtc_disable_noatomic,
15181 * or because the pipe is force-enabled due to the
15183 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15184 crtc->base.base.id,
15185 crtc->base.state->enable ? "enabled" : "disabled",
15186 crtc->active ? "enabled" : "disabled");
15188 crtc->base.state->enable = crtc->active;
15189 crtc->base.state->active = crtc->active;
15190 crtc->base.enabled = crtc->active;
15192 /* Because we only establish the connector -> encoder ->
15193 * crtc links if something is active, this means the
15194 * crtc is now deactivated. Break the links. connector
15195 * -> encoder links are only establish when things are
15196 * actually up, hence no need to break them. */
15197 WARN_ON(crtc->active);
15199 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15200 WARN_ON(encoder->connectors_active);
15201 encoder->base.crtc = NULL;
15205 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15207 * We start out with underrun reporting disabled to avoid races.
15208 * For correct bookkeeping mark this on active crtcs.
15210 * Also on gmch platforms we dont have any hardware bits to
15211 * disable the underrun reporting. Which means we need to start
15212 * out with underrun reporting disabled also on inactive pipes,
15213 * since otherwise we'll complain about the garbage we read when
15214 * e.g. coming up after runtime pm.
15216 * No protection against concurrent access is required - at
15217 * worst a fifo underrun happens which also sets this to false.
15219 crtc->cpu_fifo_underrun_disabled = true;
15220 crtc->pch_fifo_underrun_disabled = true;
15224 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15226 struct intel_connector *connector;
15227 struct drm_device *dev = encoder->base.dev;
15229 /* We need to check both for a crtc link (meaning that the
15230 * encoder is active and trying to read from a pipe) and the
15231 * pipe itself being active. */
15232 bool has_active_crtc = encoder->base.crtc &&
15233 to_intel_crtc(encoder->base.crtc)->active;
15235 if (encoder->connectors_active && !has_active_crtc) {
15236 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15237 encoder->base.base.id,
15238 encoder->base.name);
15240 /* Connector is active, but has no active pipe. This is
15241 * fallout from our resume register restoring. Disable
15242 * the encoder manually again. */
15243 if (encoder->base.crtc) {
15244 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15245 encoder->base.base.id,
15246 encoder->base.name);
15247 encoder->disable(encoder);
15248 if (encoder->post_disable)
15249 encoder->post_disable(encoder);
15251 encoder->base.crtc = NULL;
15252 encoder->connectors_active = false;
15254 /* Inconsistent output/port/pipe state happens presumably due to
15255 * a bug in one of the get_hw_state functions. Or someplace else
15256 * in our code, like the register restore mess on resume. Clamp
15257 * things to off as a safer default. */
15258 for_each_intel_connector(dev, connector) {
15259 if (connector->encoder != encoder)
15261 connector->base.dpms = DRM_MODE_DPMS_OFF;
15262 connector->base.encoder = NULL;
15265 /* Enabled encoders without active connectors will be fixed in
15266 * the crtc fixup. */
15269 void i915_redisable_vga_power_on(struct drm_device *dev)
15271 struct drm_i915_private *dev_priv = dev->dev_private;
15272 u32 vga_reg = i915_vgacntrl_reg(dev);
15274 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15275 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15276 i915_disable_vga(dev);
15280 void i915_redisable_vga(struct drm_device *dev)
15282 struct drm_i915_private *dev_priv = dev->dev_private;
15284 /* This function can be called both from intel_modeset_setup_hw_state or
15285 * at a very early point in our resume sequence, where the power well
15286 * structures are not yet restored. Since this function is at a very
15287 * paranoid "someone might have enabled VGA while we were not looking"
15288 * level, just check if the power well is enabled instead of trying to
15289 * follow the "don't touch the power well if we don't need it" policy
15290 * the rest of the driver uses. */
15291 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15294 i915_redisable_vga_power_on(dev);
15297 static bool primary_get_hw_state(struct intel_crtc *crtc)
15299 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15301 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15304 static void readout_plane_state(struct intel_crtc *crtc,
15305 struct intel_crtc_state *crtc_state)
15307 struct intel_plane *p;
15308 struct drm_plane_state *drm_plane_state;
15309 bool active = crtc_state->base.active;
15312 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15314 /* apply to previous sw state too */
15315 to_intel_crtc_state(crtc->base.state)->quirks |=
15316 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15319 for_each_intel_plane(crtc->base.dev, p) {
15320 bool visible = active;
15322 if (crtc->pipe != p->pipe)
15325 drm_plane_state = p->base.state;
15326 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15327 visible = primary_get_hw_state(crtc);
15328 to_intel_plane_state(drm_plane_state)->visible = visible;
15331 * unknown state, assume it's off to force a transition
15332 * to on when calculating state changes.
15334 to_intel_plane_state(drm_plane_state)->visible = false;
15338 crtc_state->base.plane_mask |=
15339 1 << drm_plane_index(&p->base);
15340 } else if (crtc_state->base.state) {
15341 /* Make this unconditional for atomic hw readout. */
15342 crtc_state->base.plane_mask &=
15343 ~(1 << drm_plane_index(&p->base));
15348 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15350 struct drm_i915_private *dev_priv = dev->dev_private;
15352 struct intel_crtc *crtc;
15353 struct intel_encoder *encoder;
15354 struct intel_connector *connector;
15357 for_each_intel_crtc(dev, crtc) {
15358 memset(crtc->config, 0, sizeof(*crtc->config));
15359 crtc->config->base.crtc = &crtc->base;
15361 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15363 crtc->active = dev_priv->display.get_pipe_config(crtc,
15366 crtc->base.state->enable = crtc->active;
15367 crtc->base.state->active = crtc->active;
15368 crtc->base.enabled = crtc->active;
15369 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15371 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15373 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15374 crtc->base.base.id,
15375 crtc->active ? "enabled" : "disabled");
15378 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15379 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15381 pll->on = pll->get_hw_state(dev_priv, pll,
15382 &pll->config.hw_state);
15384 pll->config.crtc_mask = 0;
15385 for_each_intel_crtc(dev, crtc) {
15386 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15388 pll->config.crtc_mask |= 1 << crtc->pipe;
15392 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15393 pll->name, pll->config.crtc_mask, pll->on);
15395 if (pll->config.crtc_mask)
15396 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15399 for_each_intel_encoder(dev, encoder) {
15402 if (encoder->get_hw_state(encoder, &pipe)) {
15403 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15404 encoder->base.crtc = &crtc->base;
15405 encoder->get_config(encoder, crtc->config);
15407 encoder->base.crtc = NULL;
15410 encoder->connectors_active = false;
15411 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15412 encoder->base.base.id,
15413 encoder->base.name,
15414 encoder->base.crtc ? "enabled" : "disabled",
15418 for_each_intel_connector(dev, connector) {
15419 if (connector->get_hw_state(connector)) {
15420 connector->base.dpms = DRM_MODE_DPMS_ON;
15421 connector->encoder->connectors_active = true;
15422 connector->base.encoder = &connector->encoder->base;
15424 connector->base.dpms = DRM_MODE_DPMS_OFF;
15425 connector->base.encoder = NULL;
15427 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15428 connector->base.base.id,
15429 connector->base.name,
15430 connector->base.encoder ? "enabled" : "disabled");
15434 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15435 * and i915 state tracking structures. */
15436 void intel_modeset_setup_hw_state(struct drm_device *dev,
15437 bool force_restore)
15439 struct drm_i915_private *dev_priv = dev->dev_private;
15441 struct intel_crtc *crtc;
15442 struct intel_encoder *encoder;
15445 intel_modeset_readout_hw_state(dev);
15448 * Now that we have the config, copy it to each CRTC struct
15449 * Note that this could go away if we move to using crtc_config
15450 * checking everywhere.
15452 for_each_intel_crtc(dev, crtc) {
15453 if (crtc->active && i915.fastboot) {
15454 intel_mode_from_pipe_config(&crtc->base.mode,
15456 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15457 crtc->base.base.id);
15458 drm_mode_debug_printmodeline(&crtc->base.mode);
15462 /* HW state is read out, now we need to sanitize this mess. */
15463 for_each_intel_encoder(dev, encoder) {
15464 intel_sanitize_encoder(encoder);
15467 for_each_pipe(dev_priv, pipe) {
15468 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15469 intel_sanitize_crtc(crtc);
15470 intel_dump_pipe_config(crtc, crtc->config,
15471 "[setup_hw_state]");
15474 intel_modeset_update_connector_atomic_state(dev);
15476 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15477 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15479 if (!pll->on || pll->active)
15482 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15484 pll->disable(dev_priv, pll);
15488 if (IS_VALLEYVIEW(dev))
15489 vlv_wm_get_hw_state(dev);
15490 else if (IS_GEN9(dev))
15491 skl_wm_get_hw_state(dev);
15492 else if (HAS_PCH_SPLIT(dev))
15493 ilk_wm_get_hw_state(dev);
15495 if (force_restore) {
15496 i915_redisable_vga(dev);
15499 * We need to use raw interfaces for restoring state to avoid
15500 * checking (bogus) intermediate states.
15502 for_each_pipe(dev_priv, pipe) {
15503 struct drm_crtc *crtc =
15504 dev_priv->pipe_to_crtc_mapping[pipe];
15506 intel_crtc_restore_mode(crtc);
15509 intel_modeset_update_staged_output_state(dev);
15512 intel_modeset_check_state(dev);
15515 void intel_modeset_gem_init(struct drm_device *dev)
15517 struct drm_i915_private *dev_priv = dev->dev_private;
15518 struct drm_crtc *c;
15519 struct drm_i915_gem_object *obj;
15522 mutex_lock(&dev->struct_mutex);
15523 intel_init_gt_powersave(dev);
15524 mutex_unlock(&dev->struct_mutex);
15527 * There may be no VBT; and if the BIOS enabled SSC we can
15528 * just keep using it to avoid unnecessary flicker. Whereas if the
15529 * BIOS isn't using it, don't assume it will work even if the VBT
15530 * indicates as much.
15532 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15533 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15536 intel_modeset_init_hw(dev);
15538 intel_setup_overlay(dev);
15541 * Make sure any fbs we allocated at startup are properly
15542 * pinned & fenced. When we do the allocation it's too early
15545 for_each_crtc(dev, c) {
15546 obj = intel_fb_obj(c->primary->fb);
15550 mutex_lock(&dev->struct_mutex);
15551 ret = intel_pin_and_fence_fb_obj(c->primary,
15555 mutex_unlock(&dev->struct_mutex);
15557 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15558 to_intel_crtc(c)->pipe);
15559 drm_framebuffer_unreference(c->primary->fb);
15560 c->primary->fb = NULL;
15561 c->primary->crtc = c->primary->state->crtc = NULL;
15562 update_state_fb(c->primary);
15563 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15567 intel_backlight_register(dev);
15570 void intel_connector_unregister(struct intel_connector *intel_connector)
15572 struct drm_connector *connector = &intel_connector->base;
15574 intel_panel_destroy_backlight(connector);
15575 drm_connector_unregister(connector);
15578 void intel_modeset_cleanup(struct drm_device *dev)
15580 struct drm_i915_private *dev_priv = dev->dev_private;
15581 struct drm_connector *connector;
15583 intel_disable_gt_powersave(dev);
15585 intel_backlight_unregister(dev);
15588 * Interrupts and polling as the first thing to avoid creating havoc.
15589 * Too much stuff here (turning of connectors, ...) would
15590 * experience fancy races otherwise.
15592 intel_irq_uninstall(dev_priv);
15595 * Due to the hpd irq storm handling the hotplug work can re-arm the
15596 * poll handlers. Hence disable polling after hpd handling is shut down.
15598 drm_kms_helper_poll_fini(dev);
15600 intel_unregister_dsm_handler();
15602 intel_fbc_disable(dev);
15604 /* flush any delayed tasks or pending work */
15605 flush_scheduled_work();
15607 /* destroy the backlight and sysfs files before encoders/connectors */
15608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15609 struct intel_connector *intel_connector;
15611 intel_connector = to_intel_connector(connector);
15612 intel_connector->unregister(intel_connector);
15615 drm_mode_config_cleanup(dev);
15617 intel_cleanup_overlay(dev);
15619 mutex_lock(&dev->struct_mutex);
15620 intel_cleanup_gt_powersave(dev);
15621 mutex_unlock(&dev->struct_mutex);
15625 * Return which encoder is currently attached for connector.
15627 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15629 return &intel_attached_encoder(connector)->base;
15632 void intel_connector_attach_encoder(struct intel_connector *connector,
15633 struct intel_encoder *encoder)
15635 connector->encoder = encoder;
15636 drm_mode_connector_attach_encoder(&connector->base,
15641 * set vga decode state - true == enable VGA decode
15643 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15645 struct drm_i915_private *dev_priv = dev->dev_private;
15646 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15649 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15650 DRM_ERROR("failed to read control word\n");
15654 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15658 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15660 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15662 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15663 DRM_ERROR("failed to write control word\n");
15670 struct intel_display_error_state {
15672 u32 power_well_driver;
15674 int num_transcoders;
15676 struct intel_cursor_error_state {
15681 } cursor[I915_MAX_PIPES];
15683 struct intel_pipe_error_state {
15684 bool power_domain_on;
15687 } pipe[I915_MAX_PIPES];
15689 struct intel_plane_error_state {
15697 } plane[I915_MAX_PIPES];
15699 struct intel_transcoder_error_state {
15700 bool power_domain_on;
15701 enum transcoder cpu_transcoder;
15714 struct intel_display_error_state *
15715 intel_display_capture_error_state(struct drm_device *dev)
15717 struct drm_i915_private *dev_priv = dev->dev_private;
15718 struct intel_display_error_state *error;
15719 int transcoders[] = {
15727 if (INTEL_INFO(dev)->num_pipes == 0)
15730 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15734 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15735 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15737 for_each_pipe(dev_priv, i) {
15738 error->pipe[i].power_domain_on =
15739 __intel_display_power_is_enabled(dev_priv,
15740 POWER_DOMAIN_PIPE(i));
15741 if (!error->pipe[i].power_domain_on)
15744 error->cursor[i].control = I915_READ(CURCNTR(i));
15745 error->cursor[i].position = I915_READ(CURPOS(i));
15746 error->cursor[i].base = I915_READ(CURBASE(i));
15748 error->plane[i].control = I915_READ(DSPCNTR(i));
15749 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15750 if (INTEL_INFO(dev)->gen <= 3) {
15751 error->plane[i].size = I915_READ(DSPSIZE(i));
15752 error->plane[i].pos = I915_READ(DSPPOS(i));
15754 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15755 error->plane[i].addr = I915_READ(DSPADDR(i));
15756 if (INTEL_INFO(dev)->gen >= 4) {
15757 error->plane[i].surface = I915_READ(DSPSURF(i));
15758 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15761 error->pipe[i].source = I915_READ(PIPESRC(i));
15763 if (HAS_GMCH_DISPLAY(dev))
15764 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15767 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15768 if (HAS_DDI(dev_priv->dev))
15769 error->num_transcoders++; /* Account for eDP. */
15771 for (i = 0; i < error->num_transcoders; i++) {
15772 enum transcoder cpu_transcoder = transcoders[i];
15774 error->transcoder[i].power_domain_on =
15775 __intel_display_power_is_enabled(dev_priv,
15776 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15777 if (!error->transcoder[i].power_domain_on)
15780 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15782 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15783 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15784 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15785 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15786 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15787 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15788 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15794 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15797 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15798 struct drm_device *dev,
15799 struct intel_display_error_state *error)
15801 struct drm_i915_private *dev_priv = dev->dev_private;
15807 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15809 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15810 error->power_well_driver);
15811 for_each_pipe(dev_priv, i) {
15812 err_printf(m, "Pipe [%d]:\n", i);
15813 err_printf(m, " Power: %s\n",
15814 error->pipe[i].power_domain_on ? "on" : "off");
15815 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15816 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15818 err_printf(m, "Plane [%d]:\n", i);
15819 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15820 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15821 if (INTEL_INFO(dev)->gen <= 3) {
15822 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15823 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15825 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15826 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15827 if (INTEL_INFO(dev)->gen >= 4) {
15828 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15829 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15832 err_printf(m, "Cursor [%d]:\n", i);
15833 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15834 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15835 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15838 for (i = 0; i < error->num_transcoders; i++) {
15839 err_printf(m, "CPU transcoder: %c\n",
15840 transcoder_name(error->transcoder[i].cpu_transcoder));
15841 err_printf(m, " Power: %s\n",
15842 error->transcoder[i].power_domain_on ? "on" : "off");
15843 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15844 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15845 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15846 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15847 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15848 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15849 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15853 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15855 struct intel_crtc *crtc;
15857 for_each_intel_crtc(dev, crtc) {
15858 struct intel_unpin_work *work;
15860 spin_lock_irq(&dev->event_lock);
15862 work = crtc->unpin_work;
15864 if (work && work->event &&
15865 work->event->base.file_priv == file) {
15866 kfree(work->event);
15867 work->event = NULL;
15870 spin_unlock_irq(&dev->event_lock);