drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv_dac = {
 313         .dot = { .min = 25000, .max = 270000 },
 314         .vco = { .min = 4000000, .max = 6000000 },
 315         .n = { .min = 1, .max = 7 },
 316         .m = { .min = 22, .max = 450 }, /* guess */
 317         .m1 = { .min = 2, .max = 3 },
 318         .m2 = { .min = 11, .max = 156 },
 319         .p = { .min = 10, .max = 30 },
 320         .p1 = { .min = 1, .max = 3 },
 321         .p2 = { .dot_limit = 270000,
 322                 .p2_slow = 2, .p2_fast = 20 },
 323 };
 324
 325 static const intel_limit_t intel_limits_vlv_hdmi = {
 326         .dot = { .min = 25000, .max = 270000 },
 327         .vco = { .min = 4000000, .max = 6000000 },
 328         .n = { .min = 1, .max = 7 },
 329         .m = { .min = 60, .max = 300 }, /* guess */
 330         .m1 = { .min = 2, .max = 3 },
 331         .m2 = { .min = 11, .max = 156 },
 332         .p = { .min = 10, .max = 30 },
 333         .p1 = { .min = 2, .max = 3 },
 334         .p2 = { .dot_limit = 270000,
 335                 .p2_slow = 2, .p2_fast = 20 },
 336 };
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 414                         limit = &intel_limits_vlv_dac;
 415                 else
 416                         limit = &intel_limits_vlv_hdmi;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         clock->vco = refclk * clock->m / clock->n;
 439         clock->dot = clock->vco / clock->p;
 440 }
 441
 442 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 443 {
 444         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 445 }
 446
 447 static void i9xx_clock(int refclk, intel_clock_t *clock)
 448 {
 449         clock->m = i9xx_dpll_compute_m(clock);
 450         clock->p = clock->p1 * clock->p2;
 451         clock->vco = refclk * clock->m / (clock->n + 2);
 452         clock->dot = clock->vco / clock->p;
 453 }
 454
 455 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 456 /**
 457  * Returns whether the given set of divisors are valid for a given refclk with
 458  * the given connectors.
 459  */
 460
 461 static bool intel_PLL_is_valid(struct drm_device *dev,
 462                                const intel_limit_t *limit,
 463                                const intel_clock_t *clock)
 464 {
 465         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 466                 INTELPllInvalid("p1 out of range\n");
 467         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 468                 INTELPllInvalid("p out of range\n");
 469         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 470                 INTELPllInvalid("m2 out of range\n");
 471         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 472                 INTELPllInvalid("m1 out of range\n");
 473         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 474                 INTELPllInvalid("m1 <= m2\n");
 475         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 476                 INTELPllInvalid("m out of range\n");
 477         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 478                 INTELPllInvalid("n out of range\n");
 479         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 480                 INTELPllInvalid("vco out of range\n");
 481         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 482          * connector, etc., rather than just a single range.
 483          */
 484         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 485                 INTELPllInvalid("dot out of range\n");
 486
 487         return true;
 488 }
 489
 490 static bool
 491 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 492                     int target, int refclk, intel_clock_t *match_clock,
 493                     intel_clock_t *best_clock)
 494 {
 495         struct drm_device *dev = crtc->dev;
 496         intel_clock_t clock;
 497         int err = target;
 498
 499         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 500                 /*
 501                  * For LVDS just rely on its current settings for dual-channel.
 502                  * We haven't figured out how to reliably set up different
 503                  * single/dual channel state, if we even can.
 504                  */
 505                 if (intel_is_dual_link_lvds(dev))
 506                         clock.p2 = limit->p2.p2_fast;
 507                 else
 508                         clock.p2 = limit->p2.p2_slow;
 509         } else {
 510                 if (target < limit->p2.dot_limit)
 511                         clock.p2 = limit->p2.p2_slow;
 512                 else
 513                         clock.p2 = limit->p2.p2_fast;
 514         }
 515
 516         memset(best_clock, 0, sizeof(*best_clock));
 517
 518         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 519              clock.m1++) {
 520                 for (clock.m2 = limit->m2.min;
 521                      clock.m2 <= limit->m2.max; clock.m2++) {
 522                         if (clock.m2 >= clock.m1)
 523                                 break;
 524                         for (clock.n = limit->n.min;
 525                              clock.n <= limit->n.max; clock.n++) {
 526                                 for (clock.p1 = limit->p1.min;
 527                                         clock.p1 <= limit->p1.max; clock.p1++) {
 528                                         int this_err;
 529
 530                                         i9xx_clock(refclk, &clock);
 531                                         if (!intel_PLL_is_valid(dev, limit,
 532                                                                 &clock))
 533                                                 continue;
 534                                         if (match_clock &&
 535                                             clock.p != match_clock->p)
 536                                                 continue;
 537
 538                                         this_err = abs(clock.dot - target);
 539                                         if (this_err < err) {
 540                                                 *best_clock = clock;
 541                                                 err = this_err;
 542                                         }
 543                                 }
 544                         }
 545                 }
 546         }
 547
 548         return (err != target);
 549 }
 550
 551 static bool
 552 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 553                    int target, int refclk, intel_clock_t *match_clock,
 554                    intel_clock_t *best_clock)
 555 {
 556         struct drm_device *dev = crtc->dev;
 557         intel_clock_t clock;
 558         int err = target;
 559
 560         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 561                 /*
 562                  * For LVDS just rely on its current settings for dual-channel.
 563                  * We haven't figured out how to reliably set up different
 564                  * single/dual channel state, if we even can.
 565                  */
 566                 if (intel_is_dual_link_lvds(dev))
 567                         clock.p2 = limit->p2.p2_fast;
 568                 else
 569                         clock.p2 = limit->p2.p2_slow;
 570         } else {
 571                 if (target < limit->p2.dot_limit)
 572                         clock.p2 = limit->p2.p2_slow;
 573                 else
 574                         clock.p2 = limit->p2.p2_fast;
 575         }
 576
 577         memset(best_clock, 0, sizeof(*best_clock));
 578
 579         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 580              clock.m1++) {
 581                 for (clock.m2 = limit->m2.min;
 582                      clock.m2 <= limit->m2.max; clock.m2++) {
 583                         for (clock.n = limit->n.min;
 584                              clock.n <= limit->n.max; clock.n++) {
 585                                 for (clock.p1 = limit->p1.min;
 586                                         clock.p1 <= limit->p1.max; clock.p1++) {
 587                                         int this_err;
 588
 589                                         pineview_clock(refclk, &clock);
 590                                         if (!intel_PLL_is_valid(dev, limit,
 591                                                                 &clock))
 592                                                 continue;
 593                                         if (match_clock &&
 594                                             clock.p != match_clock->p)
 595                                                 continue;
 596
 597                                         this_err = abs(clock.dot - target);
 598                                         if (this_err < err) {
 599                                                 *best_clock = clock;
 600                                                 err = this_err;
 601                                         }
 602                                 }
 603                         }
 604                 }
 605         }
 606
 607         return (err != target);
 608 }
 609
 610 static bool
 611 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 612                    int target, int refclk, intel_clock_t *match_clock,
 613                    intel_clock_t *best_clock)
 614 {
 615         struct drm_device *dev = crtc->dev;
 616         intel_clock_t clock;
 617         int max_n;
 618         bool found;
 619         /* approximately equals target * 0.00585 */
 620         int err_most = (target >> 8) + (target >> 9);
 621         found = false;
 622
 623         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 624                 if (intel_is_dual_link_lvds(dev))
 625                         clock.p2 = limit->p2.p2_fast;
 626                 else
 627                         clock.p2 = limit->p2.p2_slow;
 628         } else {
 629                 if (target < limit->p2.dot_limit)
 630                         clock.p2 = limit->p2.p2_slow;
 631                 else
 632                         clock.p2 = limit->p2.p2_fast;
 633         }
 634
 635         memset(best_clock, 0, sizeof(*best_clock));
 636         max_n = limit->n.max;
 637         /* based on hardware requirement, prefer smaller n to precision */
 638         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 639                 /* based on hardware requirement, prefere larger m1,m2 */
 640                 for (clock.m1 = limit->m1.max;
 641                      clock.m1 >= limit->m1.min; clock.m1--) {
 642                         for (clock.m2 = limit->m2.max;
 643                              clock.m2 >= limit->m2.min; clock.m2--) {
 644                                 for (clock.p1 = limit->p1.max;
 645                                      clock.p1 >= limit->p1.min; clock.p1--) {
 646                                         int this_err;
 647
 648                                         i9xx_clock(refclk, &clock);
 649                                         if (!intel_PLL_is_valid(dev, limit,
 650                                                                 &clock))
 651                                                 continue;
 652
 653                                         this_err = abs(clock.dot - target);
 654                                         if (this_err < err_most) {
 655                                                 *best_clock = clock;
 656                                                 err_most = this_err;
 657                                                 max_n = clock.n;
 658                                                 found = true;
 659                                         }
 660                                 }
 661                         }
 662                 }
 663         }
 664         return found;
 665 }
 666
 667 static bool
 668 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 669                    int target, int refclk, intel_clock_t *match_clock,
 670                    intel_clock_t *best_clock)
 671 {
 672         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 673         u32 m, n, fastclk;
 674         u32 updrate, minupdate, p;
 675         unsigned long bestppm, ppm, absppm;
 676         int dotclk, flag;
 677
 678         flag = 0;
 679         dotclk = target * 1000;
 680         bestppm = 1000000;
 681         ppm = absppm = 0;
 682         fastclk = dotclk / (2*100);
 683         updrate = 0;
 684         minupdate = 19200;
 685         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 686         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 687
 688         /* based on hardware requirement, prefer smaller n to precision */
 689         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 690                 updrate = refclk / n;
 691                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 692                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 693                                 if (p2 > 10)
 694                                         p2 = p2 - 1;
 695                                 p = p1 * p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 698                                         m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
 699                                         m = m1 * m2;
 700                                         vco = updrate * m;
 701
 702                                         if (vco < limit->vco.min || vco >= limit->vco.max)
 703                                                 continue;
 704
 705                                         ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 706                                         absppm = (ppm > 0) ? ppm : (-ppm);
 707                                         if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 708                                                 bestppm = 0;
 709                                                 flag = 1;
 710                                         }
 711                                         if (absppm < bestppm - 10) {
 712                                                 bestppm = absppm;
 713                                                 flag = 1;
 714                                         }
 715                                         if (flag) {
 716                                                 bestn = n;
 717                                                 bestm1 = m1;
 718                                                 bestm2 = m2;
 719                                                 bestp1 = p1;
 720                                                 bestp2 = p2;
 721                                                 flag = 0;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727         best_clock->n = bestn;
 728         best_clock->m1 = bestm1;
 729         best_clock->m2 = bestm2;
 730         best_clock->p1 = bestp1;
 731         best_clock->p2 = bestp2;
 732
 733         return true;
 734 }
 735
 736 bool intel_crtc_active(struct drm_crtc *crtc)
 737 {
 738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 739
 740         /* Be paranoid as we can arrive here with only partial
 741          * state retrieved from the hardware during setup.
 742          *
 743          * We can ditch the adjusted_mode.crtc_clock check as soon
 744          * as Haswell has gained clock readout/fastboot support.
 745          *
 746          * We can ditch the crtc->fb check as soon as we can
 747          * properly reconstruct framebuffers.
 748          */
 749         return intel_crtc->active && crtc->fb &&
 750                 intel_crtc->config.adjusted_mode.crtc_clock;
 751 }
 752
 753 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 754                                              enum pipe pipe)
 755 {
 756         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 758
 759         return intel_crtc->config.cpu_transcoder;
 760 }
 761
 762 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         u32 frame, frame_reg = PIPEFRAME(pipe);
 766
 767         frame = I915_READ(frame_reg);
 768
 769         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 770                 DRM_DEBUG_KMS("vblank wait timed out\n");
 771 }
 772
 773 /**
 774  * intel_wait_for_vblank - wait for vblank on a given pipe
 775  * @dev: drm device
 776  * @pipe: pipe to wait for
 777  *
 778  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 779  * mode setting code.
 780  */
 781 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         int pipestat_reg = PIPESTAT(pipe);
 785
 786         if (INTEL_INFO(dev)->gen >= 5) {
 787                 ironlake_wait_for_vblank(dev, pipe);
 788                 return;
 789         }
 790
 791         /* Clear existing vblank status. Note this will clear any other
 792          * sticky status fields as well.
 793          *
 794          * This races with i915_driver_irq_handler() with the result
 795          * that either function could miss a vblank event.  Here it is not
 796          * fatal, as we will either wait upon the next vblank interrupt or
 797          * timeout.  Generally speaking intel_wait_for_vblank() is only
 798          * called during modeset at which time the GPU should be idle and
 799          * should *not* be performing page flips and thus not waiting on
 800          * vblanks...
 801          * Currently, the result of us stealing a vblank from the irq
 802          * handler is that a single frame will be skipped during swapbuffers.
 803          */
 804         I915_WRITE(pipestat_reg,
 805                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 806
 807         /* Wait for vblank interrupt bit to set */
 808         if (wait_for(I915_READ(pipestat_reg) &
 809                      PIPE_VBLANK_INTERRUPT_STATUS,
 810                      50))
 811                 DRM_DEBUG_KMS("vblank wait timed out\n");
 812 }
 813
 814 /*
 815  * intel_wait_for_pipe_off - wait for pipe to turn off
 816  * @dev: drm device
 817  * @pipe: pipe to wait for
 818  *
 819  * After disabling a pipe, we can't wait for vblank in the usual way,
 820  * spinning on the vblank interrupt status bit, since we won't actually
 821  * see an interrupt when the pipe is disabled.
 822  *
 823  * On Gen4 and above:
 824  *   wait for the pipe register state bit to turn off
 825  *
 826  * Otherwise:
 827  *   wait for the display line value to settle (it usually
 828  *   ends up stopping at the start of the next frame).
 829  *
 830  */
 831 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 832 {
 833         struct drm_i915_private *dev_priv = dev->dev_private;
 834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 835                                                                       pipe);
 836
 837         if (INTEL_INFO(dev)->gen >= 4) {
 838                 int reg = PIPECONF(cpu_transcoder);
 839
 840                 /* Wait for the Pipe State to go off */
 841                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 842                              100))
 843                         WARN(1, "pipe_off wait timed out\n");
 844         } else {
 845                 u32 last_line, line_mask;
 846                 int reg = PIPEDSL(pipe);
 847                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 848
 849                 if (IS_GEN2(dev))
 850                         line_mask = DSL_LINEMASK_GEN2;
 851                 else
 852                         line_mask = DSL_LINEMASK_GEN3;
 853
 854                 /* Wait for the display line to settle */
 855                 do {
 856                         last_line = I915_READ(reg) & line_mask;
 857                         mdelay(5);
 858                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 859                          time_after(timeout, jiffies));
 860                 if (time_after(jiffies, timeout))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         if (HAS_PCH_LPT(dev_priv->dev)) {
1220                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221                 return;
1222         }
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         /*
1371          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1372          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1373          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1374          *   b. The other bits such as sfr settings / modesel may all be set
1375          *      to 0.
1376          *
1377          * This should only be done on init and resume from S3 with both
1378          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1379          */
1380         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1381 }
1382
1383 static void vlv_enable_pll(struct intel_crtc *crtc)
1384 {
1385         struct drm_device *dev = crtc->base.dev;
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387         int reg = DPLL(crtc->pipe);
1388         u32 dpll = crtc->config.dpll_hw_state.dpll;
1389
1390         assert_pipe_disabled(dev_priv, crtc->pipe);
1391
1392         /* No really, not for ILK+ */
1393         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1394
1395         /* PLL is protected by panel, make sure we can write it */
1396         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1397                 assert_panel_unlocked(dev_priv, crtc->pipe);
1398
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150);
1402
1403         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1404                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1405
1406         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1407         POSTING_READ(DPLL_MD(crtc->pipe));
1408
1409         /* We do this three times for luck */
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150); /* wait for warmup */
1413         I915_WRITE(reg, dpll);
1414         POSTING_READ(reg);
1415         udelay(150); /* wait for warmup */
1416         I915_WRITE(reg, dpll);
1417         POSTING_READ(reg);
1418         udelay(150); /* wait for warmup */
1419 }
1420
1421 static void i9xx_enable_pll(struct intel_crtc *crtc)
1422 {
1423         struct drm_device *dev = crtc->base.dev;
1424         struct drm_i915_private *dev_priv = dev->dev_private;
1425         int reg = DPLL(crtc->pipe);
1426         u32 dpll = crtc->config.dpll_hw_state.dpll;
1427
1428         assert_pipe_disabled(dev_priv, crtc->pipe);
1429
1430         /* No really, not for ILK+ */
1431         BUG_ON(dev_priv->info->gen >= 5);
1432
1433         /* PLL is protected by panel, make sure we can write it */
1434         if (IS_MOBILE(dev) && !IS_I830(dev))
1435                 assert_panel_unlocked(dev_priv, crtc->pipe);
1436
1437         I915_WRITE(reg, dpll);
1438
1439         /* Wait for the clocks to stabilize. */
1440         POSTING_READ(reg);
1441         udelay(150);
1442
1443         if (INTEL_INFO(dev)->gen >= 4) {
1444                 I915_WRITE(DPLL_MD(crtc->pipe),
1445                            crtc->config.dpll_hw_state.dpll_md);
1446         } else {
1447                 /* The pixel multiplier can only be updated once the
1448                  * DPLL is enabled and the clocks are stable.
1449                  *
1450                  * So write it again.
1451                  */
1452                 I915_WRITE(reg, dpll);
1453         }
1454
1455         /* We do this three times for luck */
1456         I915_WRITE(reg, dpll);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459         I915_WRITE(reg, dpll);
1460         POSTING_READ(reg);
1461         udelay(150); /* wait for warmup */
1462         I915_WRITE(reg, dpll);
1463         POSTING_READ(reg);
1464         udelay(150); /* wait for warmup */
1465 }
1466
1467 /**
1468  * i9xx_disable_pll - disable a PLL
1469  * @dev_priv: i915 private structure
1470  * @pipe: pipe PLL to disable
1471  *
1472  * Disable the PLL for @pipe, making sure the pipe is off first.
1473  *
1474  * Note!  This is for pre-ILK only.
1475  */
1476 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1477 {
1478         /* Don't disable pipe A or pipe A PLLs if needed */
1479         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1480                 return;
1481
1482         /* Make sure the pipe isn't still relying on us */
1483         assert_pipe_disabled(dev_priv, pipe);
1484
1485         I915_WRITE(DPLL(pipe), 0);
1486         POSTING_READ(DPLL(pipe));
1487 }
1488
1489 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1490 {
1491         u32 val = 0;
1492
1493         /* Make sure the pipe isn't still relying on us */
1494         assert_pipe_disabled(dev_priv, pipe);
1495
1496         /* Leave integrated clock source enabled */
1497         if (pipe == PIPE_B)
1498                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1499         I915_WRITE(DPLL(pipe), val);
1500         POSTING_READ(DPLL(pipe));
1501 }
1502
1503 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1504 {
1505         u32 port_mask;
1506
1507         if (!port)
1508                 port_mask = DPLL_PORTB_READY_MASK;
1509         else
1510                 port_mask = DPLL_PORTC_READY_MASK;
1511
1512         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1513                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1514                      'B' + port, I915_READ(DPLL(0)));
1515 }
1516
1517 /**
1518  * ironlake_enable_shared_dpll - enable PCH PLL
1519  * @dev_priv: i915 private structure
1520  * @pipe: pipe PLL to enable
1521  *
1522  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523  * drives the transcoder clock.
1524  */
1525 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1526 {
1527         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1528         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1529
1530         /* PCH PLLs only available on ILK, SNB and IVB */
1531         BUG_ON(dev_priv->info->gen < 5);
1532         if (WARN_ON(pll == NULL))
1533                 return;
1534
1535         if (WARN_ON(pll->refcount == 0))
1536                 return;
1537
1538         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1539                       pll->name, pll->active, pll->on,
1540                       crtc->base.base.id);
1541
1542         if (pll->active++) {
1543                 WARN_ON(!pll->on);
1544                 assert_shared_dpll_enabled(dev_priv, pll);
1545                 return;
1546         }
1547         WARN_ON(pll->on);
1548
1549         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1550         pll->enable(dev_priv, pll);
1551         pll->on = true;
1552 }
1553
1554 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1555 {
1556         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH only available on ILK+ */
1560         BUG_ON(dev_priv->info->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (WARN_ON(pll->active == 0)) {
1572                 assert_shared_dpll_disabled(dev_priv, pll);
1573                 return;
1574         }
1575
1576         assert_shared_dpll_enabled(dev_priv, pll);
1577         WARN_ON(!pll->on);
1578         if (--pll->active)
1579                 return;
1580
1581         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1582         pll->disable(dev_priv, pll);
1583         pll->on = false;
1584 }
1585
1586 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1587                                            enum pipe pipe)
1588 {
1589         struct drm_device *dev = dev_priv->dev;
1590         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1592         uint32_t reg, val, pipeconf_val;
1593
1594         /* PCH only available on ILK+ */
1595         BUG_ON(dev_priv->info->gen < 5);
1596
1597         /* Make sure PCH DPLL is enabled */
1598         assert_shared_dpll_enabled(dev_priv,
1599                                    intel_crtc_to_shared_dpll(intel_crtc));
1600
1601         /* FDI must be feeding us bits for PCH ports */
1602         assert_fdi_tx_enabled(dev_priv, pipe);
1603         assert_fdi_rx_enabled(dev_priv, pipe);
1604
1605         if (HAS_PCH_CPT(dev)) {
1606                 /* Workaround: Set the timing override bit before enabling the
1607                  * pch transcoder. */
1608                 reg = TRANS_CHICKEN2(pipe);
1609                 val = I915_READ(reg);
1610                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1611                 I915_WRITE(reg, val);
1612         }
1613
1614         reg = PCH_TRANSCONF(pipe);
1615         val = I915_READ(reg);
1616         pipeconf_val = I915_READ(PIPECONF(pipe));
1617
1618         if (HAS_PCH_IBX(dev_priv->dev)) {
1619                 /*
1620                  * make the BPC in transcoder be consistent with
1621                  * that in pipeconf reg.
1622                  */
1623                 val &= ~PIPECONF_BPC_MASK;
1624                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1625         }
1626
1627         val &= ~TRANS_INTERLACE_MASK;
1628         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1629                 if (HAS_PCH_IBX(dev_priv->dev) &&
1630                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1631                         val |= TRANS_LEGACY_INTERLACED_ILK;
1632                 else
1633                         val |= TRANS_INTERLACED;
1634         else
1635                 val |= TRANS_PROGRESSIVE;
1636
1637         I915_WRITE(reg, val | TRANS_ENABLE);
1638         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1639                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1640 }
1641
1642 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1643                                       enum transcoder cpu_transcoder)
1644 {
1645         u32 val, pipeconf_val;
1646
1647         /* PCH only available on ILK+ */
1648         BUG_ON(dev_priv->info->gen < 5);
1649
1650         /* FDI must be feeding us bits for PCH ports */
1651         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1652         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1653
1654         /* Workaround: set timing override bit. */
1655         val = I915_READ(_TRANSA_CHICKEN2);
1656         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1657         I915_WRITE(_TRANSA_CHICKEN2, val);
1658
1659         val = TRANS_ENABLE;
1660         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1661
1662         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1663             PIPECONF_INTERLACED_ILK)
1664                 val |= TRANS_INTERLACED;
1665         else
1666                 val |= TRANS_PROGRESSIVE;
1667
1668         I915_WRITE(LPT_TRANSCONF, val);
1669         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1670                 DRM_ERROR("Failed to enable PCH transcoder\n");
1671 }
1672
1673 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                             enum pipe pipe)
1675 {
1676         struct drm_device *dev = dev_priv->dev;
1677         uint32_t reg, val;
1678
1679         /* FDI relies on the transcoder */
1680         assert_fdi_tx_disabled(dev_priv, pipe);
1681         assert_fdi_rx_disabled(dev_priv, pipe);
1682
1683         /* Ports must be off as well */
1684         assert_pch_ports_disabled(dev_priv, pipe);
1685
1686         reg = PCH_TRANSCONF(pipe);
1687         val = I915_READ(reg);
1688         val &= ~TRANS_ENABLE;
1689         I915_WRITE(reg, val);
1690         /* wait for PCH transcoder off, transcoder state */
1691         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1692                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1693
1694         if (!HAS_PCH_IBX(dev)) {
1695                 /* Workaround: Clear the timing override chicken bit again. */
1696                 reg = TRANS_CHICKEN2(pipe);
1697                 val = I915_READ(reg);
1698                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1699                 I915_WRITE(reg, val);
1700         }
1701 }
1702
1703 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1704 {
1705         u32 val;
1706
1707         val = I915_READ(LPT_TRANSCONF);
1708         val &= ~TRANS_ENABLE;
1709         I915_WRITE(LPT_TRANSCONF, val);
1710         /* wait for PCH transcoder off, transcoder state */
1711         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1712                 DRM_ERROR("Failed to disable PCH transcoder\n");
1713
1714         /* Workaround: clear timing override bit. */
1715         val = I915_READ(_TRANSA_CHICKEN2);
1716         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1717         I915_WRITE(_TRANSA_CHICKEN2, val);
1718 }
1719
1720 /**
1721  * intel_enable_pipe - enable a pipe, asserting requirements
1722  * @dev_priv: i915 private structure
1723  * @pipe: pipe to enable
1724  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1725  *
1726  * Enable @pipe, making sure that various hardware specific requirements
1727  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1728  *
1729  * @pipe should be %PIPE_A or %PIPE_B.
1730  *
1731  * Will wait until the pipe is actually running (i.e. first vblank) before
1732  * returning.
1733  */
1734 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1735                               bool pch_port, bool dsi)
1736 {
1737         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1738                                                                       pipe);
1739         enum pipe pch_transcoder;
1740         int reg;
1741         u32 val;
1742
1743         assert_planes_disabled(dev_priv, pipe);
1744         assert_cursor_disabled(dev_priv, pipe);
1745         assert_sprites_disabled(dev_priv, pipe);
1746
1747         if (HAS_PCH_LPT(dev_priv->dev))
1748                 pch_transcoder = TRANSCODER_A;
1749         else
1750                 pch_transcoder = pipe;
1751
1752         /*
1753          * A pipe without a PLL won't actually be able to drive bits from
1754          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1755          * need the check.
1756          */
1757         if (!HAS_PCH_SPLIT(dev_priv->dev))
1758                 if (dsi)
1759                         assert_dsi_pll_enabled(dev_priv);
1760                 else
1761                         assert_pll_enabled(dev_priv, pipe);
1762         else {
1763                 if (pch_port) {
1764                         /* if driving the PCH, we need FDI enabled */
1765                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1766                         assert_fdi_tx_pll_enabled(dev_priv,
1767                                                   (enum pipe) cpu_transcoder);
1768                 }
1769                 /* FIXME: assert CPU port conditions for SNB+ */
1770         }
1771
1772         reg = PIPECONF(cpu_transcoder);
1773         val = I915_READ(reg);
1774         if (val & PIPECONF_ENABLE)
1775                 return;
1776
1777         I915_WRITE(reg, val | PIPECONF_ENABLE);
1778         intel_wait_for_vblank(dev_priv->dev, pipe);
1779 }
1780
1781 /**
1782  * intel_disable_pipe - disable a pipe, asserting requirements
1783  * @dev_priv: i915 private structure
1784  * @pipe: pipe to disable
1785  *
1786  * Disable @pipe, making sure that various hardware specific requirements
1787  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1788  *
1789  * @pipe should be %PIPE_A or %PIPE_B.
1790  *
1791  * Will wait until the pipe has shut down before returning.
1792  */
1793 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1794                                enum pipe pipe)
1795 {
1796         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1797                                                                       pipe);
1798         int reg;
1799         u32 val;
1800
1801         /*
1802          * Make sure planes won't keep trying to pump pixels to us,
1803          * or we might hang the display.
1804          */
1805         assert_planes_disabled(dev_priv, pipe);
1806         assert_cursor_disabled(dev_priv, pipe);
1807         assert_sprites_disabled(dev_priv, pipe);
1808
1809         /* Don't disable pipe A or pipe A PLLs if needed */
1810         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1811                 return;
1812
1813         reg = PIPECONF(cpu_transcoder);
1814         val = I915_READ(reg);
1815         if ((val & PIPECONF_ENABLE) == 0)
1816                 return;
1817
1818         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1819         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1820 }
1821
1822 /*
1823  * Plane regs are double buffered, going from enabled->disabled needs a
1824  * trigger in order to latch.  The display address reg provides this.
1825  */
1826 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1827                                       enum plane plane)
1828 {
1829         if (dev_priv->info->gen >= 4)
1830                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1831         else
1832                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1833 }
1834
1835 /**
1836  * intel_enable_plane - enable a display plane on a given pipe
1837  * @dev_priv: i915 private structure
1838  * @plane: plane to enable
1839  * @pipe: pipe being fed
1840  *
1841  * Enable @plane on @pipe, making sure that @pipe is running first.
1842  */
1843 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1844                                enum plane plane, enum pipe pipe)
1845 {
1846         int reg;
1847         u32 val;
1848
1849         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1850         assert_pipe_enabled(dev_priv, pipe);
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_display_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_plane - disable a display plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1871                                 enum plane plane, enum pipe pipe)
1872 {
1873         int reg;
1874         u32 val;
1875
1876         reg = DSPCNTR(plane);
1877         val = I915_READ(reg);
1878         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1879                 return;
1880
1881         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1882         intel_flush_display_plane(dev_priv, plane);
1883         intel_wait_for_vblank(dev_priv->dev, pipe);
1884 }
1885
1886 static bool need_vtd_wa(struct drm_device *dev)
1887 {
1888 #ifdef CONFIG_INTEL_IOMMU
1889         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1890                 return true;
1891 #endif
1892         return false;
1893 }
1894
1895 int
1896 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1897                            struct drm_i915_gem_object *obj,
1898                            struct intel_ring_buffer *pipelined)
1899 {
1900         struct drm_i915_private *dev_priv = dev->dev_private;
1901         u32 alignment;
1902         int ret;
1903
1904         switch (obj->tiling_mode) {
1905         case I915_TILING_NONE:
1906                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1907                         alignment = 128 * 1024;
1908                 else if (INTEL_INFO(dev)->gen >= 4)
1909                         alignment = 4 * 1024;
1910                 else
1911                         alignment = 64 * 1024;
1912                 break;
1913         case I915_TILING_X:
1914                 /* pin() will align the object as required by fence */
1915                 alignment = 0;
1916                 break;
1917         case I915_TILING_Y:
1918                 /* Despite that we check this in framebuffer_init userspace can
1919                  * screw us over and change the tiling after the fact. Only
1920                  * pinned buffers can't change their tiling. */
1921                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1922                 return -EINVAL;
1923         default:
1924                 BUG();
1925         }
1926
1927         /* Note that the w/a also requires 64 PTE of padding following the
1928          * bo. We currently fill all unused PTE with the shadow page and so
1929          * we should always have valid PTE following the scanout preventing
1930          * the VT-d warning.
1931          */
1932         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1933                 alignment = 256 * 1024;
1934
1935         dev_priv->mm.interruptible = false;
1936         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1937         if (ret)
1938                 goto err_interruptible;
1939
1940         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1941          * fence, whereas 965+ only requires a fence if using
1942          * framebuffer compression.  For simplicity, we always install
1943          * a fence as the cost is not that onerous.
1944          */
1945         ret = i915_gem_object_get_fence(obj);
1946         if (ret)
1947                 goto err_unpin;
1948
1949         i915_gem_object_pin_fence(obj);
1950
1951         dev_priv->mm.interruptible = true;
1952         return 0;
1953
1954 err_unpin:
1955         i915_gem_object_unpin_from_display_plane(obj);
1956 err_interruptible:
1957         dev_priv->mm.interruptible = true;
1958         return ret;
1959 }
1960
1961 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1962 {
1963         i915_gem_object_unpin_fence(obj);
1964         i915_gem_object_unpin_from_display_plane(obj);
1965 }
1966
1967 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1968  * is assumed to be a power-of-two. */
1969 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1970                                              unsigned int tiling_mode,
1971                                              unsigned int cpp,
1972                                              unsigned int pitch)
1973 {
1974         if (tiling_mode != I915_TILING_NONE) {
1975                 unsigned int tile_rows, tiles;
1976
1977                 tile_rows = *y / 8;
1978                 *y %= 8;
1979
1980                 tiles = *x / (512/cpp);
1981                 *x %= 512/cpp;
1982
1983                 return tile_rows * pitch * 8 + tiles * 4096;
1984         } else {
1985                 unsigned int offset;
1986
1987                 offset = *y * pitch + *x * cpp;
1988                 *y = 0;
1989                 *x = (offset & 4095) / cpp;
1990                 return offset & -4096;
1991         }
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995                              int x, int y)
1996 {
1997         struct drm_device *dev = crtc->dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000         struct intel_framebuffer *intel_fb;
2001         struct drm_i915_gem_object *obj;
2002         int plane = intel_crtc->plane;
2003         unsigned long linear_offset;
2004         u32 dspcntr;
2005         u32 reg;
2006
2007         switch (plane) {
2008         case 0:
2009         case 1:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->pixel_format) {
2024         case DRM_FORMAT_C8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case DRM_FORMAT_XRGB1555:
2028         case DRM_FORMAT_ARGB1555:
2029                 dspcntr |= DISPPLANE_BGRX555;
2030                 break;
2031         case DRM_FORMAT_RGB565:
2032                 dspcntr |= DISPPLANE_BGRX565;
2033                 break;
2034         case DRM_FORMAT_XRGB8888:
2035         case DRM_FORMAT_ARGB8888:
2036                 dspcntr |= DISPPLANE_BGRX888;
2037                 break;
2038         case DRM_FORMAT_XBGR8888:
2039         case DRM_FORMAT_ABGR8888:
2040                 dspcntr |= DISPPLANE_RGBX888;
2041                 break;
2042         case DRM_FORMAT_XRGB2101010:
2043         case DRM_FORMAT_ARGB2101010:
2044                 dspcntr |= DISPPLANE_BGRX101010;
2045                 break;
2046         case DRM_FORMAT_XBGR2101010:
2047         case DRM_FORMAT_ABGR2101010:
2048                 dspcntr |= DISPPLANE_RGBX101010;
2049                 break;
2050         default:
2051                 BUG();
2052         }
2053
2054         if (INTEL_INFO(dev)->gen >= 4) {
2055                 if (obj->tiling_mode != I915_TILING_NONE)
2056                         dspcntr |= DISPPLANE_TILED;
2057                 else
2058                         dspcntr &= ~DISPPLANE_TILED;
2059         }
2060
2061         if (IS_G4X(dev))
2062                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2063
2064         I915_WRITE(reg, dspcntr);
2065
2066         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2067
2068         if (INTEL_INFO(dev)->gen >= 4) {
2069                 intel_crtc->dspaddr_offset =
2070                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2071                                                        fb->bits_per_pixel / 8,
2072                                                        fb->pitches[0]);
2073                 linear_offset -= intel_crtc->dspaddr_offset;
2074         } else {
2075                 intel_crtc->dspaddr_offset = linear_offset;
2076         }
2077
2078         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2080                       fb->pitches[0]);
2081         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2082         if (INTEL_INFO(dev)->gen >= 4) {
2083                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2084                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2085                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2086                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2087         } else
2088                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2089         POSTING_READ(reg);
2090
2091         return 0;
2092 }
2093
2094 static int ironlake_update_plane(struct drm_crtc *crtc,
2095                                  struct drm_framebuffer *fb, int x, int y)
2096 {
2097         struct drm_device *dev = crtc->dev;
2098         struct drm_i915_private *dev_priv = dev->dev_private;
2099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2100         struct intel_framebuffer *intel_fb;
2101         struct drm_i915_gem_object *obj;
2102         int plane = intel_crtc->plane;
2103         unsigned long linear_offset;
2104         u32 dspcntr;
2105         u32 reg;
2106
2107         switch (plane) {
2108         case 0:
2109         case 1:
2110         case 2:
2111                 break;
2112         default:
2113                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2114                 return -EINVAL;
2115         }
2116
2117         intel_fb = to_intel_framebuffer(fb);
2118         obj = intel_fb->obj;
2119
2120         reg = DSPCNTR(plane);
2121         dspcntr = I915_READ(reg);
2122         /* Mask out pixel format bits in case we change it */
2123         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2124         switch (fb->pixel_format) {
2125         case DRM_FORMAT_C8:
2126                 dspcntr |= DISPPLANE_8BPP;
2127                 break;
2128         case DRM_FORMAT_RGB565:
2129                 dspcntr |= DISPPLANE_BGRX565;
2130                 break;
2131         case DRM_FORMAT_XRGB8888:
2132         case DRM_FORMAT_ARGB8888:
2133                 dspcntr |= DISPPLANE_BGRX888;
2134                 break;
2135         case DRM_FORMAT_XBGR8888:
2136         case DRM_FORMAT_ABGR8888:
2137                 dspcntr |= DISPPLANE_RGBX888;
2138                 break;
2139         case DRM_FORMAT_XRGB2101010:
2140         case DRM_FORMAT_ARGB2101010:
2141                 dspcntr |= DISPPLANE_BGRX101010;
2142                 break;
2143         case DRM_FORMAT_XBGR2101010:
2144         case DRM_FORMAT_ABGR2101010:
2145                 dspcntr |= DISPPLANE_RGBX101010;
2146                 break;
2147         default:
2148                 BUG();
2149         }
2150
2151         if (obj->tiling_mode != I915_TILING_NONE)
2152                 dspcntr |= DISPPLANE_TILED;
2153         else
2154                 dspcntr &= ~DISPPLANE_TILED;
2155
2156         if (IS_HASWELL(dev))
2157                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2158         else
2159                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2160
2161         I915_WRITE(reg, dspcntr);
2162
2163         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2164         intel_crtc->dspaddr_offset =
2165                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2166                                                fb->bits_per_pixel / 8,
2167                                                fb->pitches[0]);
2168         linear_offset -= intel_crtc->dspaddr_offset;
2169
2170         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2171                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2172                       fb->pitches[0]);
2173         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2174         I915_MODIFY_DISPBASE(DSPSURF(plane),
2175                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2176         if (IS_HASWELL(dev)) {
2177                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2178         } else {
2179                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2180                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2181         }
2182         POSTING_READ(reg);
2183
2184         return 0;
2185 }
2186
2187 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2188 static int
2189 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2190                            int x, int y, enum mode_set_atomic state)
2191 {
2192         struct drm_device *dev = crtc->dev;
2193         struct drm_i915_private *dev_priv = dev->dev_private;
2194
2195         if (dev_priv->display.disable_fbc)
2196                 dev_priv->display.disable_fbc(dev);
2197         intel_increase_pllclock(crtc);
2198
2199         return dev_priv->display.update_plane(crtc, fb, x, y);
2200 }
2201
2202 void intel_display_handle_reset(struct drm_device *dev)
2203 {
2204         struct drm_i915_private *dev_priv = dev->dev_private;
2205         struct drm_crtc *crtc;
2206
2207         /*
2208          * Flips in the rings have been nuked by the reset,
2209          * so complete all pending flips so that user space
2210          * will get its events and not get stuck.
2211          *
2212          * Also update the base address of all primary
2213          * planes to the the last fb to make sure we're
2214          * showing the correct fb after a reset.
2215          *
2216          * Need to make two loops over the crtcs so that we
2217          * don't try to grab a crtc mutex before the
2218          * pending_flip_queue really got woken up.
2219          */
2220
2221         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2222                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2223                 enum plane plane = intel_crtc->plane;
2224
2225                 intel_prepare_page_flip(dev, plane);
2226                 intel_finish_page_flip_plane(dev, plane);
2227         }
2228
2229         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2230                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2231
2232                 mutex_lock(&crtc->mutex);
2233                 if (intel_crtc->active)
2234                         dev_priv->display.update_plane(crtc, crtc->fb,
2235                                                        crtc->x, crtc->y);
2236                 mutex_unlock(&crtc->mutex);
2237         }
2238 }
2239
2240 static int
2241 intel_finish_fb(struct drm_framebuffer *old_fb)
2242 {
2243         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2244         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2245         bool was_interruptible = dev_priv->mm.interruptible;
2246         int ret;
2247
2248         /* Big Hammer, we also need to ensure that any pending
2249          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250          * current scanout is retired before unpinning the old
2251          * framebuffer.
2252          *
2253          * This should only fail upon a hung GPU, in which case we
2254          * can safely continue.
2255          */
2256         dev_priv->mm.interruptible = false;
2257         ret = i915_gem_object_finish_gpu(obj);
2258         dev_priv->mm.interruptible = was_interruptible;
2259
2260         return ret;
2261 }
2262
2263 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2264 {
2265         struct drm_device *dev = crtc->dev;
2266         struct drm_i915_master_private *master_priv;
2267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2268
2269         if (!dev->primary->master)
2270                 return;
2271
2272         master_priv = dev->primary->master->driver_priv;
2273         if (!master_priv->sarea_priv)
2274                 return;
2275
2276         switch (intel_crtc->pipe) {
2277         case 0:
2278                 master_priv->sarea_priv->pipeA_x = x;
2279                 master_priv->sarea_priv->pipeA_y = y;
2280                 break;
2281         case 1:
2282                 master_priv->sarea_priv->pipeB_x = x;
2283                 master_priv->sarea_priv->pipeB_y = y;
2284                 break;
2285         default:
2286                 break;
2287         }
2288 }
2289
2290 static int
2291 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2292                     struct drm_framebuffer *fb)
2293 {
2294         struct drm_device *dev = crtc->dev;
2295         struct drm_i915_private *dev_priv = dev->dev_private;
2296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297         struct drm_framebuffer *old_fb;
2298         int ret;
2299
2300         /* no fb bound */
2301         if (!fb) {
2302                 DRM_ERROR("No FB bound\n");
2303                 return 0;
2304         }
2305
2306         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2307                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2308                           plane_name(intel_crtc->plane),
2309                           INTEL_INFO(dev)->num_pipes);
2310                 return -EINVAL;
2311         }
2312
2313         mutex_lock(&dev->struct_mutex);
2314         ret = intel_pin_and_fence_fb_obj(dev,
2315                                          to_intel_framebuffer(fb)->obj,
2316                                          NULL);
2317         if (ret != 0) {
2318                 mutex_unlock(&dev->struct_mutex);
2319                 DRM_ERROR("pin & fence failed\n");
2320                 return ret;
2321         }
2322
2323         /*
2324          * Update pipe size and adjust fitter if needed: the reason for this is
2325          * that in compute_mode_changes we check the native mode (not the pfit
2326          * mode) to see if we can flip rather than do a full mode set. In the
2327          * fastboot case, we'll flip, but if we don't update the pipesrc and
2328          * pfit state, we'll end up with a big fb scanned out into the wrong
2329          * sized surface.
2330          *
2331          * To fix this properly, we need to hoist the checks up into
2332          * compute_mode_changes (or above), check the actual pfit state and
2333          * whether the platform allows pfit disable with pipe active, and only
2334          * then update the pipesrc and pfit state, even on the flip path.
2335          */
2336         if (i915_fastboot) {
2337                 const struct drm_display_mode *adjusted_mode =
2338                         &intel_crtc->config.adjusted_mode;
2339
2340                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2341                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2342                            (adjusted_mode->crtc_vdisplay - 1));
2343                 if (!intel_crtc->config.pch_pfit.enabled &&
2344                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2345                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2346                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2347                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2348                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2349                 }
2350         }
2351
2352         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2353         if (ret) {
2354                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2355                 mutex_unlock(&dev->struct_mutex);
2356                 DRM_ERROR("failed to update base address\n");
2357                 return ret;
2358         }
2359
2360         old_fb = crtc->fb;
2361         crtc->fb = fb;
2362         crtc->x = x;
2363         crtc->y = y;
2364
2365         if (old_fb) {
2366                 if (intel_crtc->active && old_fb != fb)
2367                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2368                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2369         }
2370
2371         intel_update_fbc(dev);
2372         intel_edp_psr_update(dev);
2373         mutex_unlock(&dev->struct_mutex);
2374
2375         intel_crtc_update_sarea_pos(crtc, x, y);
2376
2377         return 0;
2378 }
2379
2380 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2381 {
2382         struct drm_device *dev = crtc->dev;
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385         int pipe = intel_crtc->pipe;
2386         u32 reg, temp;
2387
2388         /* enable normal train */
2389         reg = FDI_TX_CTL(pipe);
2390         temp = I915_READ(reg);
2391         if (IS_IVYBRIDGE(dev)) {
2392                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2393                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2394         } else {
2395                 temp &= ~FDI_LINK_TRAIN_NONE;
2396                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2397         }
2398         I915_WRITE(reg, temp);
2399
2400         reg = FDI_RX_CTL(pipe);
2401         temp = I915_READ(reg);
2402         if (HAS_PCH_CPT(dev)) {
2403                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2404                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2405         } else {
2406                 temp &= ~FDI_LINK_TRAIN_NONE;
2407                 temp |= FDI_LINK_TRAIN_NONE;
2408         }
2409         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2410
2411         /* wait one idle pattern time */
2412         POSTING_READ(reg);
2413         udelay(1000);
2414
2415         /* IVB wants error correction enabled */
2416         if (IS_IVYBRIDGE(dev))
2417                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2418                            FDI_FE_ERRC_ENABLE);
2419 }
2420
2421 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2422 {
2423         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2424 }
2425
2426 static void ivb_modeset_global_resources(struct drm_device *dev)
2427 {
2428         struct drm_i915_private *dev_priv = dev->dev_private;
2429         struct intel_crtc *pipe_B_crtc =
2430                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2431         struct intel_crtc *pipe_C_crtc =
2432                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2433         uint32_t temp;
2434
2435         /*
2436          * When everything is off disable fdi C so that we could enable fdi B
2437          * with all lanes. Note that we don't care about enabled pipes without
2438          * an enabled pch encoder.
2439          */
2440         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2441             !pipe_has_enabled_pch(pipe_C_crtc)) {
2442                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2443                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2444
2445                 temp = I915_READ(SOUTH_CHICKEN1);
2446                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2447                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2448                 I915_WRITE(SOUTH_CHICKEN1, temp);
2449         }
2450 }
2451
2452 /* The FDI link training functions for ILK/Ibexpeak. */
2453 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2454 {
2455         struct drm_device *dev = crtc->dev;
2456         struct drm_i915_private *dev_priv = dev->dev_private;
2457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2458         int pipe = intel_crtc->pipe;
2459         int plane = intel_crtc->plane;
2460         u32 reg, temp, tries;
2461
2462         /* FDI needs bits from pipe & plane first */
2463         assert_pipe_enabled(dev_priv, pipe);
2464         assert_plane_enabled(dev_priv, plane);
2465
2466         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2467            for train result */
2468         reg = FDI_RX_IMR(pipe);
2469         temp = I915_READ(reg);
2470         temp &= ~FDI_RX_SYMBOL_LOCK;
2471         temp &= ~FDI_RX_BIT_LOCK;
2472         I915_WRITE(reg, temp);
2473         I915_READ(reg);
2474         udelay(150);
2475
2476         /* enable CPU FDI TX and PCH FDI RX */
2477         reg = FDI_TX_CTL(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2480         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2481         temp &= ~FDI_LINK_TRAIN_NONE;
2482         temp |= FDI_LINK_TRAIN_PATTERN_1;
2483         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2484
2485         reg = FDI_RX_CTL(pipe);
2486         temp = I915_READ(reg);
2487         temp &= ~FDI_LINK_TRAIN_NONE;
2488         temp |= FDI_LINK_TRAIN_PATTERN_1;
2489         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2490
2491         POSTING_READ(reg);
2492         udelay(150);
2493
2494         /* Ironlake workaround, enable clock pointer after FDI enable*/
2495         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2496         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2497                    FDI_RX_PHASE_SYNC_POINTER_EN);
2498
2499         reg = FDI_RX_IIR(pipe);
2500         for (tries = 0; tries < 5; tries++) {
2501                 temp = I915_READ(reg);
2502                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503
2504                 if ((temp & FDI_RX_BIT_LOCK)) {
2505                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2506                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2507                         break;
2508                 }
2509         }
2510         if (tries == 5)
2511                 DRM_ERROR("FDI train 1 fail!\n");
2512
2513         /* Train 2 */
2514         reg = FDI_TX_CTL(pipe);
2515         temp = I915_READ(reg);
2516         temp &= ~FDI_LINK_TRAIN_NONE;
2517         temp |= FDI_LINK_TRAIN_PATTERN_2;
2518         I915_WRITE(reg, temp);
2519
2520         reg = FDI_RX_CTL(pipe);
2521         temp = I915_READ(reg);
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_2;
2524         I915_WRITE(reg, temp);
2525
2526         POSTING_READ(reg);
2527         udelay(150);
2528
2529         reg = FDI_RX_IIR(pipe);
2530         for (tries = 0; tries < 5; tries++) {
2531                 temp = I915_READ(reg);
2532                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533
2534                 if (temp & FDI_RX_SYMBOL_LOCK) {
2535                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2536                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2537                         break;
2538                 }
2539         }
2540         if (tries == 5)
2541                 DRM_ERROR("FDI train 2 fail!\n");
2542
2543         DRM_DEBUG_KMS("FDI train done\n");
2544
2545 }
2546
2547 static const int snb_b_fdi_train_param[] = {
2548         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2549         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2550         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2551         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2552 };
2553
2554 /* The FDI link training functions for SNB/Cougarpoint. */
2555 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2556 {
2557         struct drm_device *dev = crtc->dev;
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560         int pipe = intel_crtc->pipe;
2561         u32 reg, temp, i, retry;
2562
2563         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564            for train result */
2565         reg = FDI_RX_IMR(pipe);
2566         temp = I915_READ(reg);
2567         temp &= ~FDI_RX_SYMBOL_LOCK;
2568         temp &= ~FDI_RX_BIT_LOCK;
2569         I915_WRITE(reg, temp);
2570
2571         POSTING_READ(reg);
2572         udelay(150);
2573
2574         /* enable CPU FDI TX and PCH FDI RX */
2575         reg = FDI_TX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2578         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2579         temp &= ~FDI_LINK_TRAIN_NONE;
2580         temp |= FDI_LINK_TRAIN_PATTERN_1;
2581         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582         /* SNB-B */
2583         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2585
2586         I915_WRITE(FDI_RX_MISC(pipe),
2587                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2588
2589         reg = FDI_RX_CTL(pipe);
2590         temp = I915_READ(reg);
2591         if (HAS_PCH_CPT(dev)) {
2592                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2593                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2594         } else {
2595                 temp &= ~FDI_LINK_TRAIN_NONE;
2596                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2597         }
2598         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2599
2600         POSTING_READ(reg);
2601         udelay(150);
2602
2603         for (i = 0; i < 4; i++) {
2604                 reg = FDI_TX_CTL(pipe);
2605                 temp = I915_READ(reg);
2606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607                 temp |= snb_b_fdi_train_param[i];
2608                 I915_WRITE(reg, temp);
2609
2610                 POSTING_READ(reg);
2611                 udelay(500);
2612
2613                 for (retry = 0; retry < 5; retry++) {
2614                         reg = FDI_RX_IIR(pipe);
2615                         temp = I915_READ(reg);
2616                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617                         if (temp & FDI_RX_BIT_LOCK) {
2618                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2619                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2620                                 break;
2621                         }
2622                         udelay(50);
2623                 }
2624                 if (retry < 5)
2625                         break;
2626         }
2627         if (i == 4)
2628                 DRM_ERROR("FDI train 1 fail!\n");
2629
2630         /* Train 2 */
2631         reg = FDI_TX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_LINK_TRAIN_NONE;
2634         temp |= FDI_LINK_TRAIN_PATTERN_2;
2635         if (IS_GEN6(dev)) {
2636                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637                 /* SNB-B */
2638                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639         }
2640         I915_WRITE(reg, temp);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         if (HAS_PCH_CPT(dev)) {
2645                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647         } else {
2648                 temp &= ~FDI_LINK_TRAIN_NONE;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650         }
2651         I915_WRITE(reg, temp);
2652
2653         POSTING_READ(reg);
2654         udelay(150);
2655
2656         for (i = 0; i < 4; i++) {
2657                 reg = FDI_TX_CTL(pipe);
2658                 temp = I915_READ(reg);
2659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660                 temp |= snb_b_fdi_train_param[i];
2661                 I915_WRITE(reg, temp);
2662
2663                 POSTING_READ(reg);
2664                 udelay(500);
2665
2666                 for (retry = 0; retry < 5; retry++) {
2667                         reg = FDI_RX_IIR(pipe);
2668                         temp = I915_READ(reg);
2669                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2670                         if (temp & FDI_RX_SYMBOL_LOCK) {
2671                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2672                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2673                                 break;
2674                         }
2675                         udelay(50);
2676                 }
2677                 if (retry < 5)
2678                         break;
2679         }
2680         if (i == 4)
2681                 DRM_ERROR("FDI train 2 fail!\n");
2682
2683         DRM_DEBUG_KMS("FDI train done.\n");
2684 }
2685
2686 /* Manual link training for Ivy Bridge A0 parts */
2687 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2688 {
2689         struct drm_device *dev = crtc->dev;
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692         int pipe = intel_crtc->pipe;
2693         u32 reg, temp, i, j;
2694
2695         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2696            for train result */
2697         reg = FDI_RX_IMR(pipe);
2698         temp = I915_READ(reg);
2699         temp &= ~FDI_RX_SYMBOL_LOCK;
2700         temp &= ~FDI_RX_BIT_LOCK;
2701         I915_WRITE(reg, temp);
2702
2703         POSTING_READ(reg);
2704         udelay(150);
2705
2706         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2707                       I915_READ(FDI_RX_IIR(pipe)));
2708
2709         /* Try each vswing and preemphasis setting twice before moving on */
2710         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2711                 /* disable first in case we need to retry */
2712                 reg = FDI_TX_CTL(pipe);
2713                 temp = I915_READ(reg);
2714                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2715                 temp &= ~FDI_TX_ENABLE;
2716                 I915_WRITE(reg, temp);
2717
2718                 reg = FDI_RX_CTL(pipe);
2719                 temp = I915_READ(reg);
2720                 temp &= ~FDI_LINK_TRAIN_AUTO;
2721                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722                 temp &= ~FDI_RX_ENABLE;
2723                 I915_WRITE(reg, temp);
2724
2725                 /* enable CPU FDI TX and PCH FDI RX */
2726                 reg = FDI_TX_CTL(pipe);
2727                 temp = I915_READ(reg);
2728                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2729                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2730                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2731                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732                 temp |= snb_b_fdi_train_param[j/2];
2733                 temp |= FDI_COMPOSITE_SYNC;
2734                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2735
2736                 I915_WRITE(FDI_RX_MISC(pipe),
2737                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2738
2739                 reg = FDI_RX_CTL(pipe);
2740                 temp = I915_READ(reg);
2741                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742                 temp |= FDI_COMPOSITE_SYNC;
2743                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2744
2745                 POSTING_READ(reg);
2746                 udelay(1); /* should be 0.5us */
2747
2748                 for (i = 0; i < 4; i++) {
2749                         reg = FDI_RX_IIR(pipe);
2750                         temp = I915_READ(reg);
2751                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753                         if (temp & FDI_RX_BIT_LOCK ||
2754                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2755                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2756                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2757                                               i);
2758                                 break;
2759                         }
2760                         udelay(1); /* should be 0.5us */
2761                 }
2762                 if (i == 4) {
2763                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2764                         continue;
2765                 }
2766
2767                 /* Train 2 */
2768                 reg = FDI_TX_CTL(pipe);
2769                 temp = I915_READ(reg);
2770                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2771                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2772                 I915_WRITE(reg, temp);
2773
2774                 reg = FDI_RX_CTL(pipe);
2775                 temp = I915_READ(reg);
2776                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2777                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2778                 I915_WRITE(reg, temp);
2779
2780                 POSTING_READ(reg);
2781                 udelay(2); /* should be 1.5us */
2782
2783                 for (i = 0; i < 4; i++) {
2784                         reg = FDI_RX_IIR(pipe);
2785                         temp = I915_READ(reg);
2786                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788                         if (temp & FDI_RX_SYMBOL_LOCK ||
2789                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2790                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2791                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2792                                               i);
2793                                 goto train_done;
2794                         }
2795                         udelay(2); /* should be 1.5us */
2796                 }
2797                 if (i == 4)
2798                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2799         }
2800
2801 train_done:
2802         DRM_DEBUG_KMS("FDI train done.\n");
2803 }
2804
2805 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2806 {
2807         struct drm_device *dev = intel_crtc->base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         int pipe = intel_crtc->pipe;
2810         u32 reg, temp;
2811
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2817         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* Enable CPU FDI TX PLL, always on for Ironlake */
2832         reg = FDI_TX_CTL(pipe);
2833         temp = I915_READ(reg);
2834         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2835                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2836
2837                 POSTING_READ(reg);
2838                 udelay(100);
2839         }
2840 }
2841
2842 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2843 {
2844         struct drm_device *dev = intel_crtc->base.dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         int pipe = intel_crtc->pipe;
2847         u32 reg, temp;
2848
2849         /* Switch from PCDclk to Rawclk */
2850         reg = FDI_RX_CTL(pipe);
2851         temp = I915_READ(reg);
2852         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2853
2854         /* Disable CPU FDI TX PLL */
2855         reg = FDI_TX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2858
2859         POSTING_READ(reg);
2860         udelay(100);
2861
2862         reg = FDI_RX_CTL(pipe);
2863         temp = I915_READ(reg);
2864         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2865
2866         /* Wait for the clocks to turn off. */
2867         POSTING_READ(reg);
2868         udelay(100);
2869 }
2870
2871 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2872 {
2873         struct drm_device *dev = crtc->dev;
2874         struct drm_i915_private *dev_priv = dev->dev_private;
2875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2876         int pipe = intel_crtc->pipe;
2877         u32 reg, temp;
2878
2879         /* disable CPU FDI tx and PCH FDI rx */
2880         reg = FDI_TX_CTL(pipe);
2881         temp = I915_READ(reg);
2882         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2883         POSTING_READ(reg);
2884
2885         reg = FDI_RX_CTL(pipe);
2886         temp = I915_READ(reg);
2887         temp &= ~(0x7 << 16);
2888         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2889         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2890
2891         POSTING_READ(reg);
2892         udelay(100);
2893
2894         /* Ironlake workaround, disable clock pointer after downing FDI */
2895         if (HAS_PCH_IBX(dev)) {
2896                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2897         }
2898
2899         /* still set train pattern 1 */
2900         reg = FDI_TX_CTL(pipe);
2901         temp = I915_READ(reg);
2902         temp &= ~FDI_LINK_TRAIN_NONE;
2903         temp |= FDI_LINK_TRAIN_PATTERN_1;
2904         I915_WRITE(reg, temp);
2905
2906         reg = FDI_RX_CTL(pipe);
2907         temp = I915_READ(reg);
2908         if (HAS_PCH_CPT(dev)) {
2909                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2910                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2911         } else {
2912                 temp &= ~FDI_LINK_TRAIN_NONE;
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2914         }
2915         /* BPC in FDI rx is consistent with that in PIPECONF */
2916         temp &= ~(0x07 << 16);
2917         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2918         I915_WRITE(reg, temp);
2919
2920         POSTING_READ(reg);
2921         udelay(100);
2922 }
2923
2924 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2925 {
2926         struct drm_device *dev = crtc->dev;
2927         struct drm_i915_private *dev_priv = dev->dev_private;
2928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2929         unsigned long flags;
2930         bool pending;
2931
2932         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2933             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2934                 return false;
2935
2936         spin_lock_irqsave(&dev->event_lock, flags);
2937         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2938         spin_unlock_irqrestore(&dev->event_lock, flags);
2939
2940         return pending;
2941 }
2942
2943 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2944 {
2945         struct drm_device *dev = crtc->dev;
2946         struct drm_i915_private *dev_priv = dev->dev_private;
2947
2948         if (crtc->fb == NULL)
2949                 return;
2950
2951         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2952
2953         wait_event(dev_priv->pending_flip_queue,
2954                    !intel_crtc_has_pending_flip(crtc));
2955
2956         mutex_lock(&dev->struct_mutex);
2957         intel_finish_fb(crtc->fb);
2958         mutex_unlock(&dev->struct_mutex);
2959 }
2960
2961 /* Program iCLKIP clock to the desired frequency */
2962 static void lpt_program_iclkip(struct drm_crtc *crtc)
2963 {
2964         struct drm_device *dev = crtc->dev;
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2967         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2968         u32 temp;
2969
2970         mutex_lock(&dev_priv->dpio_lock);
2971
2972         /* It is necessary to ungate the pixclk gate prior to programming
2973          * the divisors, and gate it back when it is done.
2974          */
2975         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2976
2977         /* Disable SSCCTL */
2978         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2979                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2980                                 SBI_SSCCTL_DISABLE,
2981                         SBI_ICLK);
2982
2983         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2984         if (clock == 20000) {
2985                 auxdiv = 1;
2986                 divsel = 0x41;
2987                 phaseinc = 0x20;
2988         } else {
2989                 /* The iCLK virtual clock root frequency is in MHz,
2990                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2991                  * divisors, it is necessary to divide one by another, so we
2992                  * convert the virtual clock precision to KHz here for higher
2993                  * precision.
2994                  */
2995                 u32 iclk_virtual_root_freq = 172800 * 1000;
2996                 u32 iclk_pi_range = 64;
2997                 u32 desired_divisor, msb_divisor_value, pi_value;
2998
2999                 desired_divisor = (iclk_virtual_root_freq / clock);
3000                 msb_divisor_value = desired_divisor / iclk_pi_range;
3001                 pi_value = desired_divisor % iclk_pi_range;
3002
3003                 auxdiv = 0;
3004                 divsel = msb_divisor_value - 2;
3005                 phaseinc = pi_value;
3006         }
3007
3008         /* This should not happen with any sane values */
3009         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3010                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3011         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3012                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3013
3014         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3015                         clock,
3016                         auxdiv,
3017                         divsel,
3018                         phasedir,
3019                         phaseinc);
3020
3021         /* Program SSCDIVINTPHASE6 */
3022         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3023         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3024         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3025         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3026         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3027         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3028         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3029         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3030
3031         /* Program SSCAUXDIV */
3032         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3033         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3034         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3035         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3036
3037         /* Enable modulator and associated divider */
3038         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3039         temp &= ~SBI_SSCCTL_DISABLE;
3040         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3041
3042         /* Wait for initialization time */
3043         udelay(24);
3044
3045         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3046
3047         mutex_unlock(&dev_priv->dpio_lock);
3048 }
3049
3050 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3051                                                 enum pipe pch_transcoder)
3052 {
3053         struct drm_device *dev = crtc->base.dev;
3054         struct drm_i915_private *dev_priv = dev->dev_private;
3055         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3056
3057         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3058                    I915_READ(HTOTAL(cpu_transcoder)));
3059         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3060                    I915_READ(HBLANK(cpu_transcoder)));
3061         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3062                    I915_READ(HSYNC(cpu_transcoder)));
3063
3064         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3065                    I915_READ(VTOTAL(cpu_transcoder)));
3066         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3067                    I915_READ(VBLANK(cpu_transcoder)));
3068         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3069                    I915_READ(VSYNC(cpu_transcoder)));
3070         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3071                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3072 }
3073
3074 /*
3075  * Enable PCH resources required for PCH ports:
3076  *   - PCH PLLs
3077  *   - FDI training & RX/TX
3078  *   - update transcoder timings
3079  *   - DP transcoding bits
3080  *   - transcoder
3081  */
3082 static void ironlake_pch_enable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         u32 reg, temp;
3089
3090         assert_pch_transcoder_disabled(dev_priv, pipe);
3091
3092         /* Write the TU size bits before fdi link training, so that error
3093          * detection works. */
3094         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3095                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3096
3097         /* For PCH output, training FDI link */
3098         dev_priv->display.fdi_link_train(crtc);
3099
3100         /* We need to program the right clock selection before writing the pixel
3101          * mutliplier into the DPLL. */
3102         if (HAS_PCH_CPT(dev)) {
3103                 u32 sel;
3104
3105                 temp = I915_READ(PCH_DPLL_SEL);
3106                 temp |= TRANS_DPLL_ENABLE(pipe);
3107                 sel = TRANS_DPLLB_SEL(pipe);
3108                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3109                         temp |= sel;
3110                 else
3111                         temp &= ~sel;
3112                 I915_WRITE(PCH_DPLL_SEL, temp);
3113         }
3114
3115         /* XXX: pch pll's can be enabled any time before we enable the PCH
3116          * transcoder, and we actually should do this to not upset any PCH
3117          * transcoder that already use the clock when we share it.
3118          *
3119          * Note that enable_shared_dpll tries to do the right thing, but
3120          * get_shared_dpll unconditionally resets the pll - we need that to have
3121          * the right LVDS enable sequence. */
3122         ironlake_enable_shared_dpll(intel_crtc);
3123
3124         /* set transcoder timing, panel must allow it */
3125         assert_panel_unlocked(dev_priv, pipe);
3126         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3127
3128         intel_fdi_normal_train(crtc);
3129
3130         /* For PCH DP, enable TRANS_DP_CTL */
3131         if (HAS_PCH_CPT(dev) &&
3132             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3133              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3134                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3135                 reg = TRANS_DP_CTL(pipe);
3136                 temp = I915_READ(reg);
3137                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3138                           TRANS_DP_SYNC_MASK |
3139                           TRANS_DP_BPC_MASK);
3140                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3141                          TRANS_DP_ENH_FRAMING);
3142                 temp |= bpc << 9; /* same format but at 11:9 */
3143
3144                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3145                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3146                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3147                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3148
3149                 switch (intel_trans_dp_port_sel(crtc)) {
3150                 case PCH_DP_B:
3151                         temp |= TRANS_DP_PORT_SEL_B;
3152                         break;
3153                 case PCH_DP_C:
3154                         temp |= TRANS_DP_PORT_SEL_C;
3155                         break;
3156                 case PCH_DP_D:
3157                         temp |= TRANS_DP_PORT_SEL_D;
3158                         break;
3159                 default:
3160                         BUG();
3161                 }
3162
3163                 I915_WRITE(reg, temp);
3164         }
3165
3166         ironlake_enable_pch_transcoder(dev_priv, pipe);
3167 }
3168
3169 static void lpt_pch_enable(struct drm_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->dev;
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3175
3176         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3177
3178         lpt_program_iclkip(crtc);
3179
3180         /* Set transcoder timing. */
3181         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3182
3183         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3184 }
3185
3186 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3187 {
3188         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3189
3190         if (pll == NULL)
3191                 return;
3192
3193         if (pll->refcount == 0) {
3194                 WARN(1, "bad %s refcount\n", pll->name);
3195                 return;
3196         }
3197
3198         if (--pll->refcount == 0) {
3199                 WARN_ON(pll->on);
3200                 WARN_ON(pll->active);
3201         }
3202
3203         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3204 }
3205
3206 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3207 {
3208         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3209         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3210         enum intel_dpll_id i;
3211
3212         if (pll) {
3213                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3214                               crtc->base.base.id, pll->name);
3215                 intel_put_shared_dpll(crtc);
3216         }
3217
3218         if (HAS_PCH_IBX(dev_priv->dev)) {
3219                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3220                 i = (enum intel_dpll_id) crtc->pipe;
3221                 pll = &dev_priv->shared_dplls[i];
3222
3223                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3224                               crtc->base.base.id, pll->name);
3225
3226                 goto found;
3227         }
3228
3229         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3230                 pll = &dev_priv->shared_dplls[i];
3231
3232                 /* Only want to check enabled timings first */
3233                 if (pll->refcount == 0)
3234                         continue;
3235
3236                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3237                            sizeof(pll->hw_state)) == 0) {
3238                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3239                                       crtc->base.base.id,
3240                                       pll->name, pll->refcount, pll->active);
3241
3242                         goto found;
3243                 }
3244         }
3245
3246         /* Ok no matching timings, maybe there's a free one? */
3247         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3248                 pll = &dev_priv->shared_dplls[i];
3249                 if (pll->refcount == 0) {
3250                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3251                                       crtc->base.base.id, pll->name);
3252                         goto found;
3253                 }
3254         }
3255
3256         return NULL;
3257
3258 found:
3259         crtc->config.shared_dpll = i;
3260         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3261                          pipe_name(crtc->pipe));
3262
3263         if (pll->active == 0) {
3264                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3265                        sizeof(pll->hw_state));
3266
3267                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3268                 WARN_ON(pll->on);
3269                 assert_shared_dpll_disabled(dev_priv, pll);
3270
3271                 pll->mode_set(dev_priv, pll);
3272         }
3273         pll->refcount++;
3274
3275         return pll;
3276 }
3277
3278 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3279 {
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281         int dslreg = PIPEDSL(pipe);
3282         u32 temp;
3283
3284         temp = I915_READ(dslreg);
3285         udelay(500);
3286         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3287                 if (wait_for(I915_READ(dslreg) != temp, 5))
3288                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3289         }
3290 }
3291
3292 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3293 {
3294         struct drm_device *dev = crtc->base.dev;
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296         int pipe = crtc->pipe;
3297
3298         if (crtc->config.pch_pfit.enabled) {
3299                 /* Force use of hard-coded filter coefficients
3300                  * as some pre-programmed values are broken,
3301                  * e.g. x201.
3302                  */
3303                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3304                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3305                                                  PF_PIPE_SEL_IVB(pipe));
3306                 else
3307                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3308                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3309                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3310         }
3311 }
3312
3313 static void intel_enable_planes(struct drm_crtc *crtc)
3314 {
3315         struct drm_device *dev = crtc->dev;
3316         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3317         struct intel_plane *intel_plane;
3318
3319         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3320                 if (intel_plane->pipe == pipe)
3321                         intel_plane_restore(&intel_plane->base);
3322 }
3323
3324 static void intel_disable_planes(struct drm_crtc *crtc)
3325 {
3326         struct drm_device *dev = crtc->dev;
3327         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3328         struct intel_plane *intel_plane;
3329
3330         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3331                 if (intel_plane->pipe == pipe)
3332                         intel_plane_disable(&intel_plane->base);
3333 }
3334
3335 static void hsw_enable_ips(struct intel_crtc *crtc)
3336 {
3337         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3338
3339         if (!crtc->config.ips_enabled)
3340                 return;
3341
3342         /* We can only enable IPS after we enable a plane and wait for a vblank.
3343          * We guarantee that the plane is enabled by calling intel_enable_ips
3344          * only after intel_enable_plane. And intel_enable_plane already waits
3345          * for a vblank, so all we need to do here is to enable the IPS bit. */
3346         assert_plane_enabled(dev_priv, crtc->plane);
3347         I915_WRITE(IPS_CTL, IPS_ENABLE);
3348 }
3349
3350 static void hsw_disable_ips(struct intel_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->base.dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354
3355         if (!crtc->config.ips_enabled)
3356                 return;
3357
3358         assert_plane_enabled(dev_priv, crtc->plane);
3359         I915_WRITE(IPS_CTL, 0);
3360         POSTING_READ(IPS_CTL);
3361
3362         /* We need to wait for a vblank before we can disable the plane. */
3363         intel_wait_for_vblank(dev, crtc->pipe);
3364 }
3365
3366 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3367 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3368 {
3369         struct drm_device *dev = crtc->dev;
3370         struct drm_i915_private *dev_priv = dev->dev_private;
3371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3372         enum pipe pipe = intel_crtc->pipe;
3373         int palreg = PALETTE(pipe);
3374         int i;
3375         bool reenable_ips = false;
3376
3377         /* The clocks have to be on to load the palette. */
3378         if (!crtc->enabled || !intel_crtc->active)
3379                 return;
3380
3381         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3382                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3383                         assert_dsi_pll_enabled(dev_priv);
3384                 else
3385                         assert_pll_enabled(dev_priv, pipe);
3386         }
3387
3388         /* use legacy palette for Ironlake */
3389         if (HAS_PCH_SPLIT(dev))
3390                 palreg = LGC_PALETTE(pipe);
3391
3392         /* Workaround : Do not read or write the pipe palette/gamma data while
3393          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3394          */
3395         if (intel_crtc->config.ips_enabled &&
3396             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3397              GAMMA_MODE_MODE_SPLIT)) {
3398                 hsw_disable_ips(intel_crtc);
3399                 reenable_ips = true;
3400         }
3401
3402         for (i = 0; i < 256; i++) {
3403                 I915_WRITE(palreg + 4 * i,
3404                            (intel_crtc->lut_r[i] << 16) |
3405                            (intel_crtc->lut_g[i] << 8) |
3406                            intel_crtc->lut_b[i]);
3407         }
3408
3409         if (reenable_ips)
3410                 hsw_enable_ips(intel_crtc);
3411 }
3412
3413 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3414 {
3415         struct drm_device *dev = crtc->dev;
3416         struct drm_i915_private *dev_priv = dev->dev_private;
3417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3418         struct intel_encoder *encoder;
3419         int pipe = intel_crtc->pipe;
3420         int plane = intel_crtc->plane;
3421
3422         WARN_ON(!crtc->enabled);
3423
3424         if (intel_crtc->active)
3425                 return;
3426
3427         intel_crtc->active = true;
3428
3429         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3430         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3431
3432         for_each_encoder_on_crtc(dev, crtc, encoder)
3433                 if (encoder->pre_enable)
3434                         encoder->pre_enable(encoder);
3435
3436         if (intel_crtc->config.has_pch_encoder) {
3437                 /* Note: FDI PLL enabling _must_ be done before we enable the
3438                  * cpu pipes, hence this is separate from all the other fdi/pch
3439                  * enabling. */
3440                 ironlake_fdi_pll_enable(intel_crtc);
3441         } else {
3442                 assert_fdi_tx_disabled(dev_priv, pipe);
3443                 assert_fdi_rx_disabled(dev_priv, pipe);
3444         }
3445
3446         ironlake_pfit_enable(intel_crtc);
3447
3448         /*
3449          * On ILK+ LUT must be loaded before the pipe is running but with
3450          * clocks enabled
3451          */
3452         intel_crtc_load_lut(crtc);
3453
3454         intel_update_watermarks(crtc);
3455         intel_enable_pipe(dev_priv, pipe,
3456                           intel_crtc->config.has_pch_encoder, false);
3457         intel_enable_plane(dev_priv, plane, pipe);
3458         intel_enable_planes(crtc);
3459         intel_crtc_update_cursor(crtc, true);
3460
3461         if (intel_crtc->config.has_pch_encoder)
3462                 ironlake_pch_enable(crtc);
3463
3464         mutex_lock(&dev->struct_mutex);
3465         intel_update_fbc(dev);
3466         mutex_unlock(&dev->struct_mutex);
3467
3468         for_each_encoder_on_crtc(dev, crtc, encoder)
3469                 encoder->enable(encoder);
3470
3471         if (HAS_PCH_CPT(dev))
3472                 cpt_verify_modeset(dev, intel_crtc->pipe);
3473
3474         /*
3475          * There seems to be a race in PCH platform hw (at least on some
3476          * outputs) where an enabled pipe still completes any pageflip right
3477          * away (as if the pipe is off) instead of waiting for vblank. As soon
3478          * as the first vblank happend, everything works as expected. Hence just
3479          * wait for one vblank before returning to avoid strange things
3480          * happening.
3481          */
3482         intel_wait_for_vblank(dev, intel_crtc->pipe);
3483 }
3484
3485 /* IPS only exists on ULT machines and is tied to pipe A. */
3486 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3487 {
3488         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3489 }
3490
3491 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3492 {
3493         struct drm_device *dev = crtc->dev;
3494         struct drm_i915_private *dev_priv = dev->dev_private;
3495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496         int pipe = intel_crtc->pipe;
3497         int plane = intel_crtc->plane;
3498
3499         intel_enable_plane(dev_priv, plane, pipe);
3500         intel_enable_planes(crtc);
3501         intel_crtc_update_cursor(crtc, true);
3502
3503         hsw_enable_ips(intel_crtc);
3504
3505         mutex_lock(&dev->struct_mutex);
3506         intel_update_fbc(dev);
3507         mutex_unlock(&dev->struct_mutex);
3508 }
3509
3510 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3511 {
3512         struct drm_device *dev = crtc->dev;
3513         struct drm_i915_private *dev_priv = dev->dev_private;
3514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3515         int pipe = intel_crtc->pipe;
3516         int plane = intel_crtc->plane;
3517
3518         intel_crtc_wait_for_pending_flips(crtc);
3519         drm_vblank_off(dev, pipe);
3520
3521         /* FBC must be disabled before disabling the plane on HSW. */
3522         if (dev_priv->fbc.plane == plane)
3523                 intel_disable_fbc(dev);
3524
3525         hsw_disable_ips(intel_crtc);
3526
3527         intel_crtc_update_cursor(crtc, false);
3528         intel_disable_planes(crtc);
3529         intel_disable_plane(dev_priv, plane, pipe);
3530 }
3531
3532 /*
3533  * This implements the workaround described in the "notes" section of the mode
3534  * set sequence documentation. When going from no pipes or single pipe to
3535  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3536  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3537  */
3538 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3539 {
3540         struct drm_device *dev = crtc->base.dev;
3541         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3542
3543         /* We want to get the other_active_crtc only if there's only 1 other
3544          * active crtc. */
3545         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3546                 if (!crtc_it->active || crtc_it == crtc)
3547                         continue;
3548
3549                 if (other_active_crtc)
3550                         return;
3551
3552                 other_active_crtc = crtc_it;
3553         }
3554         if (!other_active_crtc)
3555                 return;
3556
3557         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3558         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3559 }
3560
3561 static void haswell_crtc_enable(struct drm_crtc *crtc)
3562 {
3563         struct drm_device *dev = crtc->dev;
3564         struct drm_i915_private *dev_priv = dev->dev_private;
3565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3566         struct intel_encoder *encoder;
3567         int pipe = intel_crtc->pipe;
3568
3569         WARN_ON(!crtc->enabled);
3570
3571         if (intel_crtc->active)
3572                 return;
3573
3574         intel_crtc->active = true;
3575
3576         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3577         if (intel_crtc->config.has_pch_encoder)
3578                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3579
3580         if (intel_crtc->config.has_pch_encoder)
3581                 dev_priv->display.fdi_link_train(crtc);
3582
3583         for_each_encoder_on_crtc(dev, crtc, encoder)
3584                 if (encoder->pre_enable)
3585                         encoder->pre_enable(encoder);
3586
3587         intel_ddi_enable_pipe_clock(intel_crtc);
3588
3589         ironlake_pfit_enable(intel_crtc);
3590
3591         /*
3592          * On ILK+ LUT must be loaded before the pipe is running but with
3593          * clocks enabled
3594          */
3595         intel_crtc_load_lut(crtc);
3596
3597         intel_ddi_set_pipe_settings(crtc);
3598         intel_ddi_enable_transcoder_func(crtc);
3599
3600         intel_update_watermarks(crtc);
3601         intel_enable_pipe(dev_priv, pipe,
3602                           intel_crtc->config.has_pch_encoder, false);
3603
3604         if (intel_crtc->config.has_pch_encoder)
3605                 lpt_pch_enable(crtc);
3606
3607         for_each_encoder_on_crtc(dev, crtc, encoder) {
3608                 encoder->enable(encoder);
3609                 intel_opregion_notify_encoder(encoder, true);
3610         }
3611
3612         /* If we change the relative order between pipe/planes enabling, we need
3613          * to change the workaround. */
3614         haswell_mode_set_planes_workaround(intel_crtc);
3615         haswell_crtc_enable_planes(crtc);
3616
3617         /*
3618          * There seems to be a race in PCH platform hw (at least on some
3619          * outputs) where an enabled pipe still completes any pageflip right
3620          * away (as if the pipe is off) instead of waiting for vblank. As soon
3621          * as the first vblank happend, everything works as expected. Hence just
3622          * wait for one vblank before returning to avoid strange things
3623          * happening.
3624          */
3625         intel_wait_for_vblank(dev, intel_crtc->pipe);
3626 }
3627
3628 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3629 {
3630         struct drm_device *dev = crtc->base.dev;
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632         int pipe = crtc->pipe;
3633
3634         /* To avoid upsetting the power well on haswell only disable the pfit if
3635          * it's in use. The hw state code will make sure we get this right. */
3636         if (crtc->config.pch_pfit.enabled) {
3637                 I915_WRITE(PF_CTL(pipe), 0);
3638                 I915_WRITE(PF_WIN_POS(pipe), 0);
3639                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3640         }
3641 }
3642
3643 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3644 {
3645         struct drm_device *dev = crtc->dev;
3646         struct drm_i915_private *dev_priv = dev->dev_private;
3647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648         struct intel_encoder *encoder;
3649         int pipe = intel_crtc->pipe;
3650         int plane = intel_crtc->plane;
3651         u32 reg, temp;
3652
3653
3654         if (!intel_crtc->active)
3655                 return;
3656
3657         for_each_encoder_on_crtc(dev, crtc, encoder)
3658                 encoder->disable(encoder);
3659
3660         intel_crtc_wait_for_pending_flips(crtc);
3661         drm_vblank_off(dev, pipe);
3662
3663         if (dev_priv->fbc.plane == plane)
3664                 intel_disable_fbc(dev);
3665
3666         intel_crtc_update_cursor(crtc, false);
3667         intel_disable_planes(crtc);
3668         intel_disable_plane(dev_priv, plane, pipe);
3669
3670         if (intel_crtc->config.has_pch_encoder)
3671                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3672
3673         intel_disable_pipe(dev_priv, pipe);
3674
3675         ironlake_pfit_disable(intel_crtc);
3676
3677         for_each_encoder_on_crtc(dev, crtc, encoder)
3678                 if (encoder->post_disable)
3679                         encoder->post_disable(encoder);
3680
3681         if (intel_crtc->config.has_pch_encoder) {
3682                 ironlake_fdi_disable(crtc);
3683
3684                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3685                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3686
3687                 if (HAS_PCH_CPT(dev)) {
3688                         /* disable TRANS_DP_CTL */
3689                         reg = TRANS_DP_CTL(pipe);
3690                         temp = I915_READ(reg);
3691                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3692                                   TRANS_DP_PORT_SEL_MASK);
3693                         temp |= TRANS_DP_PORT_SEL_NONE;
3694                         I915_WRITE(reg, temp);
3695
3696                         /* disable DPLL_SEL */
3697                         temp = I915_READ(PCH_DPLL_SEL);
3698                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3699                         I915_WRITE(PCH_DPLL_SEL, temp);
3700                 }
3701
3702                 /* disable PCH DPLL */
3703                 intel_disable_shared_dpll(intel_crtc);
3704
3705                 ironlake_fdi_pll_disable(intel_crtc);
3706         }
3707
3708         intel_crtc->active = false;
3709         intel_update_watermarks(crtc);
3710
3711         mutex_lock(&dev->struct_mutex);
3712         intel_update_fbc(dev);
3713         mutex_unlock(&dev->struct_mutex);
3714 }
3715
3716 static void haswell_crtc_disable(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         struct intel_encoder *encoder;
3722         int pipe = intel_crtc->pipe;
3723         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3724
3725         if (!intel_crtc->active)
3726                 return;
3727
3728         haswell_crtc_disable_planes(crtc);
3729
3730         for_each_encoder_on_crtc(dev, crtc, encoder) {
3731                 intel_opregion_notify_encoder(encoder, false);
3732                 encoder->disable(encoder);
3733         }
3734
3735         if (intel_crtc->config.has_pch_encoder)
3736                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3737         intel_disable_pipe(dev_priv, pipe);
3738
3739         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3740
3741         ironlake_pfit_disable(intel_crtc);
3742
3743         intel_ddi_disable_pipe_clock(intel_crtc);
3744
3745         for_each_encoder_on_crtc(dev, crtc, encoder)
3746                 if (encoder->post_disable)
3747                         encoder->post_disable(encoder);
3748
3749         if (intel_crtc->config.has_pch_encoder) {
3750                 lpt_disable_pch_transcoder(dev_priv);
3751                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3752                 intel_ddi_fdi_disable(crtc);
3753         }
3754
3755         intel_crtc->active = false;
3756         intel_update_watermarks(crtc);
3757
3758         mutex_lock(&dev->struct_mutex);
3759         intel_update_fbc(dev);
3760         mutex_unlock(&dev->struct_mutex);
3761 }
3762
3763 static void ironlake_crtc_off(struct drm_crtc *crtc)
3764 {
3765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3766         intel_put_shared_dpll(intel_crtc);
3767 }
3768
3769 static void haswell_crtc_off(struct drm_crtc *crtc)
3770 {
3771         intel_ddi_put_crtc_pll(crtc);
3772 }
3773
3774 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3775 {
3776         if (!enable && intel_crtc->overlay) {
3777                 struct drm_device *dev = intel_crtc->base.dev;
3778                 struct drm_i915_private *dev_priv = dev->dev_private;
3779
3780                 mutex_lock(&dev->struct_mutex);
3781                 dev_priv->mm.interruptible = false;
3782                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3783                 dev_priv->mm.interruptible = true;
3784                 mutex_unlock(&dev->struct_mutex);
3785         }
3786
3787         /* Let userspace switch the overlay on again. In most cases userspace
3788          * has to recompute where to put it anyway.
3789          */
3790 }
3791
3792 /**
3793  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3794  * cursor plane briefly if not already running after enabling the display
3795  * plane.
3796  * This workaround avoids occasional blank screens when self refresh is
3797  * enabled.
3798  */
3799 static void
3800 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3801 {
3802         u32 cntl = I915_READ(CURCNTR(pipe));
3803
3804         if ((cntl & CURSOR_MODE) == 0) {
3805                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3806
3807                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3808                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3809                 intel_wait_for_vblank(dev_priv->dev, pipe);
3810                 I915_WRITE(CURCNTR(pipe), cntl);
3811                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3812                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3813         }
3814 }
3815
3816 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3817 {
3818         struct drm_device *dev = crtc->base.dev;
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820         struct intel_crtc_config *pipe_config = &crtc->config;
3821
3822         if (!crtc->config.gmch_pfit.control)
3823                 return;
3824
3825         /*
3826          * The panel fitter should only be adjusted whilst the pipe is disabled,
3827          * according to register description and PRM.
3828          */
3829         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3830         assert_pipe_disabled(dev_priv, crtc->pipe);
3831
3832         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3833         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3834
3835         /* Border color in case we don't scale up to the full screen. Black by
3836          * default, change to something else for debugging. */
3837         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3838 }
3839
3840 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3841 {
3842         struct drm_device *dev = crtc->dev;
3843         struct drm_i915_private *dev_priv = dev->dev_private;
3844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3845         struct intel_encoder *encoder;
3846         int pipe = intel_crtc->pipe;
3847         int plane = intel_crtc->plane;
3848         bool is_dsi;
3849
3850         WARN_ON(!crtc->enabled);
3851
3852         if (intel_crtc->active)
3853                 return;
3854
3855         intel_crtc->active = true;
3856
3857         for_each_encoder_on_crtc(dev, crtc, encoder)
3858                 if (encoder->pre_pll_enable)
3859                         encoder->pre_pll_enable(encoder);
3860
3861         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3862
3863         if (!is_dsi)
3864                 vlv_enable_pll(intel_crtc);
3865
3866         for_each_encoder_on_crtc(dev, crtc, encoder)
3867                 if (encoder->pre_enable)
3868                         encoder->pre_enable(encoder);
3869
3870         i9xx_pfit_enable(intel_crtc);
3871
3872         intel_crtc_load_lut(crtc);
3873
3874         intel_update_watermarks(crtc);
3875         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3876         intel_enable_plane(dev_priv, plane, pipe);
3877         intel_enable_planes(crtc);
3878         intel_crtc_update_cursor(crtc, true);
3879
3880         intel_update_fbc(dev);
3881
3882         for_each_encoder_on_crtc(dev, crtc, encoder)
3883                 encoder->enable(encoder);
3884 }
3885
3886 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3887 {
3888         struct drm_device *dev = crtc->dev;
3889         struct drm_i915_private *dev_priv = dev->dev_private;
3890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3891         struct intel_encoder *encoder;
3892         int pipe = intel_crtc->pipe;
3893         int plane = intel_crtc->plane;
3894
3895         WARN_ON(!crtc->enabled);
3896
3897         if (intel_crtc->active)
3898                 return;
3899
3900         intel_crtc->active = true;
3901
3902         for_each_encoder_on_crtc(dev, crtc, encoder)
3903                 if (encoder->pre_enable)
3904                         encoder->pre_enable(encoder);
3905
3906         i9xx_enable_pll(intel_crtc);
3907
3908         i9xx_pfit_enable(intel_crtc);
3909
3910         intel_crtc_load_lut(crtc);
3911
3912         intel_update_watermarks(crtc);
3913         intel_enable_pipe(dev_priv, pipe, false, false);
3914         intel_enable_plane(dev_priv, plane, pipe);
3915         intel_enable_planes(crtc);
3916         /* The fixup needs to happen before cursor is enabled */
3917         if (IS_G4X(dev))
3918                 g4x_fixup_plane(dev_priv, pipe);
3919         intel_crtc_update_cursor(crtc, true);
3920
3921         /* Give the overlay scaler a chance to enable if it's on this pipe */
3922         intel_crtc_dpms_overlay(intel_crtc, true);
3923
3924         intel_update_fbc(dev);
3925
3926         for_each_encoder_on_crtc(dev, crtc, encoder)
3927                 encoder->enable(encoder);
3928 }
3929
3930 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3931 {
3932         struct drm_device *dev = crtc->base.dev;
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934
3935         if (!crtc->config.gmch_pfit.control)
3936                 return;
3937
3938         assert_pipe_disabled(dev_priv, crtc->pipe);
3939
3940         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3941                          I915_READ(PFIT_CONTROL));
3942         I915_WRITE(PFIT_CONTROL, 0);
3943 }
3944
3945 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3946 {
3947         struct drm_device *dev = crtc->dev;
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950         struct intel_encoder *encoder;
3951         int pipe = intel_crtc->pipe;
3952         int plane = intel_crtc->plane;
3953
3954         if (!intel_crtc->active)
3955                 return;
3956
3957         for_each_encoder_on_crtc(dev, crtc, encoder)
3958                 encoder->disable(encoder);
3959
3960         /* Give the overlay scaler a chance to disable if it's on this pipe */
3961         intel_crtc_wait_for_pending_flips(crtc);
3962         drm_vblank_off(dev, pipe);
3963
3964         if (dev_priv->fbc.plane == plane)
3965                 intel_disable_fbc(dev);
3966
3967         intel_crtc_dpms_overlay(intel_crtc, false);
3968         intel_crtc_update_cursor(crtc, false);
3969         intel_disable_planes(crtc);
3970         intel_disable_plane(dev_priv, plane, pipe);
3971
3972         intel_disable_pipe(dev_priv, pipe);
3973
3974         i9xx_pfit_disable(intel_crtc);
3975
3976         for_each_encoder_on_crtc(dev, crtc, encoder)
3977                 if (encoder->post_disable)
3978                         encoder->post_disable(encoder);
3979
3980         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3981                 vlv_disable_pll(dev_priv, pipe);
3982         else if (!IS_VALLEYVIEW(dev))
3983                 i9xx_disable_pll(dev_priv, pipe);
3984
3985         intel_crtc->active = false;
3986         intel_update_watermarks(crtc);
3987
3988         intel_update_fbc(dev);
3989 }
3990
3991 static void i9xx_crtc_off(struct drm_crtc *crtc)
3992 {
3993 }
3994
3995 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3996                                     bool enabled)
3997 {
3998         struct drm_device *dev = crtc->dev;
3999         struct drm_i915_master_private *master_priv;
4000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4001         int pipe = intel_crtc->pipe;
4002
4003         if (!dev->primary->master)
4004                 return;
4005
4006         master_priv = dev->primary->master->driver_priv;
4007         if (!master_priv->sarea_priv)
4008                 return;
4009
4010         switch (pipe) {
4011         case 0:
4012                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4013                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4014                 break;
4015         case 1:
4016                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4017                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4018                 break;
4019         default:
4020                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4021                 break;
4022         }
4023 }
4024
4025 /**
4026  * Sets the power management mode of the pipe and plane.
4027  */
4028 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4029 {
4030         struct drm_device *dev = crtc->dev;
4031         struct drm_i915_private *dev_priv = dev->dev_private;
4032         struct intel_encoder *intel_encoder;
4033         bool enable = false;
4034
4035         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4036                 enable |= intel_encoder->connectors_active;
4037
4038         if (enable)
4039                 dev_priv->display.crtc_enable(crtc);
4040         else
4041                 dev_priv->display.crtc_disable(crtc);
4042
4043         intel_crtc_update_sarea(crtc, enable);
4044 }
4045
4046 static void intel_crtc_disable(struct drm_crtc *crtc)
4047 {
4048         struct drm_device *dev = crtc->dev;
4049         struct drm_connector *connector;
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4052
4053         /* crtc should still be enabled when we disable it. */
4054         WARN_ON(!crtc->enabled);
4055
4056         dev_priv->display.crtc_disable(crtc);
4057         intel_crtc->eld_vld = false;
4058         intel_crtc_update_sarea(crtc, false);
4059         dev_priv->display.off(crtc);
4060
4061         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4062         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4063         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4064
4065         if (crtc->fb) {
4066                 mutex_lock(&dev->struct_mutex);
4067                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4068                 mutex_unlock(&dev->struct_mutex);
4069                 crtc->fb = NULL;
4070         }
4071
4072         /* Update computed state. */
4073         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4074                 if (!connector->encoder || !connector->encoder->crtc)
4075                         continue;
4076
4077                 if (connector->encoder->crtc != crtc)
4078                         continue;
4079
4080                 connector->dpms = DRM_MODE_DPMS_OFF;
4081                 to_intel_encoder(connector->encoder)->connectors_active = false;
4082         }
4083 }
4084
4085 void intel_encoder_destroy(struct drm_encoder *encoder)
4086 {
4087         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4088
4089         drm_encoder_cleanup(encoder);
4090         kfree(intel_encoder);
4091 }
4092
4093 /* Simple dpms helper for encoders with just one connector, no cloning and only
4094  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4095  * state of the entire output pipe. */
4096 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4097 {
4098         if (mode == DRM_MODE_DPMS_ON) {
4099                 encoder->connectors_active = true;
4100
4101                 intel_crtc_update_dpms(encoder->base.crtc);
4102         } else {
4103                 encoder->connectors_active = false;
4104
4105                 intel_crtc_update_dpms(encoder->base.crtc);
4106         }
4107 }
4108
4109 /* Cross check the actual hw state with our own modeset state tracking (and it's
4110  * internal consistency). */
4111 static void intel_connector_check_state(struct intel_connector *connector)
4112 {
4113         if (connector->get_hw_state(connector)) {
4114                 struct intel_encoder *encoder = connector->encoder;
4115                 struct drm_crtc *crtc;
4116                 bool encoder_enabled;
4117                 enum pipe pipe;
4118
4119                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4120                               connector->base.base.id,
4121                               drm_get_connector_name(&connector->base));
4122
4123                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4124                      "wrong connector dpms state\n");
4125                 WARN(connector->base.encoder != &encoder->base,
4126                      "active connector not linked to encoder\n");
4127                 WARN(!encoder->connectors_active,
4128                      "encoder->connectors_active not set\n");
4129
4130                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4131                 WARN(!encoder_enabled, "encoder not enabled\n");
4132                 if (WARN_ON(!encoder->base.crtc))
4133                         return;
4134
4135                 crtc = encoder->base.crtc;
4136
4137                 WARN(!crtc->enabled, "crtc not enabled\n");
4138                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4139                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4140                      "encoder active on the wrong pipe\n");
4141         }
4142 }
4143
4144 /* Even simpler default implementation, if there's really no special case to
4145  * consider. */
4146 void intel_connector_dpms(struct drm_connector *connector, int mode)
4147 {
4148         struct intel_encoder *encoder = intel_attached_encoder(connector);
4149
4150         /* All the simple cases only support two dpms states. */
4151         if (mode != DRM_MODE_DPMS_ON)
4152                 mode = DRM_MODE_DPMS_OFF;
4153
4154         if (mode == connector->dpms)
4155                 return;
4156
4157         connector->dpms = mode;
4158
4159         /* Only need to change hw state when actually enabled */
4160         if (encoder->base.crtc)
4161                 intel_encoder_dpms(encoder, mode);
4162         else
4163                 WARN_ON(encoder->connectors_active != false);
4164
4165         intel_modeset_check_state(connector->dev);
4166 }
4167
4168 /* Simple connector->get_hw_state implementation for encoders that support only
4169  * one connector and no cloning and hence the encoder state determines the state
4170  * of the connector. */
4171 bool intel_connector_get_hw_state(struct intel_connector *connector)
4172 {
4173         enum pipe pipe = 0;
4174         struct intel_encoder *encoder = connector->encoder;
4175
4176         return encoder->get_hw_state(encoder, &pipe);
4177 }
4178
4179 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4180                                      struct intel_crtc_config *pipe_config)
4181 {
4182         struct drm_i915_private *dev_priv = dev->dev_private;
4183         struct intel_crtc *pipe_B_crtc =
4184                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4185
4186         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4187                       pipe_name(pipe), pipe_config->fdi_lanes);
4188         if (pipe_config->fdi_lanes > 4) {
4189                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4190                               pipe_name(pipe), pipe_config->fdi_lanes);
4191                 return false;
4192         }
4193
4194         if (IS_HASWELL(dev)) {
4195                 if (pipe_config->fdi_lanes > 2) {
4196                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4197                                       pipe_config->fdi_lanes);
4198                         return false;
4199                 } else {
4200                         return true;
4201                 }
4202         }
4203
4204         if (INTEL_INFO(dev)->num_pipes == 2)
4205                 return true;
4206
4207         /* Ivybridge 3 pipe is really complicated */
4208         switch (pipe) {
4209         case PIPE_A:
4210                 return true;
4211         case PIPE_B:
4212                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4213                     pipe_config->fdi_lanes > 2) {
4214                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4215                                       pipe_name(pipe), pipe_config->fdi_lanes);
4216                         return false;
4217                 }
4218                 return true;
4219         case PIPE_C:
4220                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4221                     pipe_B_crtc->config.fdi_lanes <= 2) {
4222                         if (pipe_config->fdi_lanes > 2) {
4223                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4224                                               pipe_name(pipe), pipe_config->fdi_lanes);
4225                                 return false;
4226                         }
4227                 } else {
4228                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4229                         return false;
4230                 }
4231                 return true;
4232         default:
4233                 BUG();
4234         }
4235 }
4236
4237 #define RETRY 1
4238 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4239                                        struct intel_crtc_config *pipe_config)
4240 {
4241         struct drm_device *dev = intel_crtc->base.dev;
4242         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4243         int lane, link_bw, fdi_dotclock;
4244         bool setup_ok, needs_recompute = false;
4245
4246 retry:
4247         /* FDI is a binary signal running at ~2.7GHz, encoding
4248          * each output octet as 10 bits. The actual frequency
4249          * is stored as a divider into a 100MHz clock, and the
4250          * mode pixel clock is stored in units of 1KHz.
4251          * Hence the bw of each lane in terms of the mode signal
4252          * is:
4253          */
4254         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4255
4256         fdi_dotclock = adjusted_mode->crtc_clock;
4257
4258         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4259                                            pipe_config->pipe_bpp);
4260
4261         pipe_config->fdi_lanes = lane;
4262
4263         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4264                                link_bw, &pipe_config->fdi_m_n);
4265
4266         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4267                                             intel_crtc->pipe, pipe_config);
4268         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4269                 pipe_config->pipe_bpp -= 2*3;
4270                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4271                               pipe_config->pipe_bpp);
4272                 needs_recompute = true;
4273                 pipe_config->bw_constrained = true;
4274
4275                 goto retry;
4276         }
4277
4278         if (needs_recompute)
4279                 return RETRY;
4280
4281         return setup_ok ? 0 : -EINVAL;
4282 }
4283
4284 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4285                                    struct intel_crtc_config *pipe_config)
4286 {
4287         pipe_config->ips_enabled = i915_enable_ips &&
4288                                    hsw_crtc_supports_ips(crtc) &&
4289                                    pipe_config->pipe_bpp <= 24;
4290 }
4291
4292 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4293                                      struct intel_crtc_config *pipe_config)
4294 {
4295         struct drm_device *dev = crtc->base.dev;
4296         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4297
4298         /* FIXME should check pixel clock limits on all platforms */
4299         if (INTEL_INFO(dev)->gen < 4) {
4300                 struct drm_i915_private *dev_priv = dev->dev_private;
4301                 int clock_limit =
4302                         dev_priv->display.get_display_clock_speed(dev);
4303
4304                 /*
4305                  * Enable pixel doubling when the dot clock
4306                  * is > 90% of the (display) core speed.
4307                  *
4308                  * GDG double wide on either pipe,
4309                  * otherwise pipe A only.
4310                  */
4311                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4312                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4313                         clock_limit *= 2;
4314                         pipe_config->double_wide = true;
4315                 }
4316
4317                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4318                         return -EINVAL;
4319         }
4320
4321         /*
4322          * Pipe horizontal size must be even in:
4323          * - DVO ganged mode
4324          * - LVDS dual channel mode
4325          * - Double wide pipe
4326          */
4327         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4328              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4329                 pipe_config->pipe_src_w &= ~1;
4330
4331         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4332          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4333          */
4334         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4335                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4336                 return -EINVAL;
4337
4338         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4339                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4340         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4341                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4342                  * for lvds. */
4343                 pipe_config->pipe_bpp = 8*3;
4344         }
4345
4346         if (HAS_IPS(dev))
4347                 hsw_compute_ips_config(crtc, pipe_config);
4348
4349         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4350          * clock survives for now. */
4351         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4352                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4353
4354         if (pipe_config->has_pch_encoder)
4355                 return ironlake_fdi_compute_config(crtc, pipe_config);
4356
4357         return 0;
4358 }
4359
4360 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4361 {
4362         return 400000; /* FIXME */
4363 }
4364
4365 static int i945_get_display_clock_speed(struct drm_device *dev)
4366 {
4367         return 400000;
4368 }
4369
4370 static int i915_get_display_clock_speed(struct drm_device *dev)
4371 {
4372         return 333000;
4373 }
4374
4375 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4376 {
4377         return 200000;
4378 }
4379
4380 static int pnv_get_display_clock_speed(struct drm_device *dev)
4381 {
4382         u16 gcfgc = 0;
4383
4384         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4385
4386         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4387         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4388                 return 267000;
4389         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4390                 return 333000;
4391         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4392                 return 444000;
4393         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4394                 return 200000;
4395         default:
4396                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4397         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4398                 return 133000;
4399         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4400                 return 167000;
4401         }
4402 }
4403
4404 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4405 {
4406         u16 gcfgc = 0;
4407
4408         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4409
4410         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4411                 return 133000;
4412         else {
4413                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4414                 case GC_DISPLAY_CLOCK_333_MHZ:
4415                         return 333000;
4416                 default:
4417                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4418                         return 190000;
4419                 }
4420         }
4421 }
4422
4423 static int i865_get_display_clock_speed(struct drm_device *dev)
4424 {
4425         return 266000;
4426 }
4427
4428 static int i855_get_display_clock_speed(struct drm_device *dev)
4429 {
4430         u16 hpllcc = 0;
4431         /* Assume that the hardware is in the high speed state.  This
4432          * should be the default.
4433          */
4434         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4435         case GC_CLOCK_133_200:
4436         case GC_CLOCK_100_200:
4437                 return 200000;
4438         case GC_CLOCK_166_250:
4439                 return 250000;
4440         case GC_CLOCK_100_133:
4441                 return 133000;
4442         }
4443
4444         /* Shouldn't happen */
4445         return 0;
4446 }
4447
4448 static int i830_get_display_clock_speed(struct drm_device *dev)
4449 {
4450         return 133000;
4451 }
4452
4453 static void
4454 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4455 {
4456         while (*num > DATA_LINK_M_N_MASK ||
4457                *den > DATA_LINK_M_N_MASK) {
4458                 *num >>= 1;
4459                 *den >>= 1;
4460         }
4461 }
4462
4463 static void compute_m_n(unsigned int m, unsigned int n,
4464                         uint32_t *ret_m, uint32_t *ret_n)
4465 {
4466         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4467         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4468         intel_reduce_m_n_ratio(ret_m, ret_n);
4469 }
4470
4471 void
4472 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4473                        int pixel_clock, int link_clock,
4474                        struct intel_link_m_n *m_n)
4475 {
4476         m_n->tu = 64;
4477
4478         compute_m_n(bits_per_pixel * pixel_clock,
4479                     link_clock * nlanes * 8,
4480                     &m_n->gmch_m, &m_n->gmch_n);
4481
4482         compute_m_n(pixel_clock, link_clock,
4483                     &m_n->link_m, &m_n->link_n);
4484 }
4485
4486 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4487 {
4488         if (i915_panel_use_ssc >= 0)
4489                 return i915_panel_use_ssc != 0;
4490         return dev_priv->vbt.lvds_use_ssc
4491                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4492 }
4493
4494 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4495 {
4496         struct drm_device *dev = crtc->dev;
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498         int refclk;
4499
4500         if (IS_VALLEYVIEW(dev)) {
4501                 refclk = 100000;
4502         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4503             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4504                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4505                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4506                               refclk / 1000);
4507         } else if (!IS_GEN2(dev)) {
4508                 refclk = 96000;
4509         } else {
4510                 refclk = 48000;
4511         }
4512
4513         return refclk;
4514 }
4515
4516 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4517 {
4518         return (1 << dpll->n) << 16 | dpll->m2;
4519 }
4520
4521 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4522 {
4523         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4524 }
4525
4526 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4527                                      intel_clock_t *reduced_clock)
4528 {
4529         struct drm_device *dev = crtc->base.dev;
4530         struct drm_i915_private *dev_priv = dev->dev_private;
4531         int pipe = crtc->pipe;
4532         u32 fp, fp2 = 0;
4533
4534         if (IS_PINEVIEW(dev)) {
4535                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4536                 if (reduced_clock)
4537                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4538         } else {
4539                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4540                 if (reduced_clock)
4541                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4542         }
4543
4544         I915_WRITE(FP0(pipe), fp);
4545         crtc->config.dpll_hw_state.fp0 = fp;
4546
4547         crtc->lowfreq_avail = false;
4548         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4549             reduced_clock && i915_powersave) {
4550                 I915_WRITE(FP1(pipe), fp2);
4551                 crtc->config.dpll_hw_state.fp1 = fp2;
4552                 crtc->lowfreq_avail = true;
4553         } else {
4554                 I915_WRITE(FP1(pipe), fp);
4555                 crtc->config.dpll_hw_state.fp1 = fp;
4556         }
4557 }
4558
4559 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4560                 pipe)
4561 {
4562         u32 reg_val;
4563
4564         /*
4565          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4566          * and set it to a reasonable value instead.
4567          */
4568         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4569         reg_val &= 0xffffff00;
4570         reg_val |= 0x00000030;
4571         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4572
4573         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4574         reg_val &= 0x8cffffff;
4575         reg_val = 0x8c000000;
4576         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4577
4578         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4579         reg_val &= 0xffffff00;
4580         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4581
4582         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4583         reg_val &= 0x00ffffff;
4584         reg_val |= 0xb0000000;
4585         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4586 }
4587
4588 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4589                                          struct intel_link_m_n *m_n)
4590 {
4591         struct drm_device *dev = crtc->base.dev;
4592         struct drm_i915_private *dev_priv = dev->dev_private;
4593         int pipe = crtc->pipe;
4594
4595         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4596         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4597         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4598         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4599 }
4600
4601 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4602                                          struct intel_link_m_n *m_n)
4603 {
4604         struct drm_device *dev = crtc->base.dev;
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         int pipe = crtc->pipe;
4607         enum transcoder transcoder = crtc->config.cpu_transcoder;
4608
4609         if (INTEL_INFO(dev)->gen >= 5) {
4610                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4611                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4612                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4613                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4614         } else {
4615                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4616                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4617                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4618                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4619         }
4620 }
4621
4622 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4623 {
4624         if (crtc->config.has_pch_encoder)
4625                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4626         else
4627                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4628 }
4629
4630 static void vlv_update_pll(struct intel_crtc *crtc)
4631 {
4632         struct drm_device *dev = crtc->base.dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         int pipe = crtc->pipe;
4635         u32 dpll, mdiv;
4636         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4637         u32 coreclk, reg_val, dpll_md;
4638
4639         mutex_lock(&dev_priv->dpio_lock);
4640
4641         bestn = crtc->config.dpll.n;
4642         bestm1 = crtc->config.dpll.m1;
4643         bestm2 = crtc->config.dpll.m2;
4644         bestp1 = crtc->config.dpll.p1;
4645         bestp2 = crtc->config.dpll.p2;
4646
4647         /* See eDP HDMI DPIO driver vbios notes doc */
4648
4649         /* PLL B needs special handling */
4650         if (pipe)
4651                 vlv_pllb_recal_opamp(dev_priv, pipe);
4652
4653         /* Set up Tx target for periodic Rcomp update */
4654         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4655
4656         /* Disable target IRef on PLL */
4657         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4658         reg_val &= 0x00ffffff;
4659         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4660
4661         /* Disable fast lock */
4662         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4663
4664         /* Set idtafcrecal before PLL is enabled */
4665         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4666         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4667         mdiv |= ((bestn << DPIO_N_SHIFT));
4668         mdiv |= (1 << DPIO_K_SHIFT);
4669
4670         /*
4671          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4672          * but we don't support that).
4673          * Note: don't use the DAC post divider as it seems unstable.
4674          */
4675         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4676         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4677
4678         mdiv |= DPIO_ENABLE_CALIBRATION;
4679         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4680
4681         /* Set HBR and RBR LPF coefficients */
4682         if (crtc->config.port_clock == 162000 ||
4683             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4684             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4685                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4686                                  0x009f0003);
4687         else
4688                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4689                                  0x00d0000f);
4690
4691         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4692             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4693                 /* Use SSC source */
4694                 if (!pipe)
4695                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4696                                          0x0df40000);
4697                 else
4698                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4699                                          0x0df70000);
4700         } else { /* HDMI or VGA */
4701                 /* Use bend source */
4702                 if (!pipe)
4703                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4704                                          0x0df70000);
4705                 else
4706                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4707                                          0x0df40000);
4708         }
4709
4710         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4711         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4712         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4713             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4714                 coreclk |= 0x01000000;
4715         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4716
4717         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4718
4719         /* Enable DPIO clock input */
4720         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4721                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4722         /* We should never disable this, set it here for state tracking */
4723         if (pipe == PIPE_B)
4724                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4725         dpll |= DPLL_VCO_ENABLE;
4726         crtc->config.dpll_hw_state.dpll = dpll;
4727
4728         dpll_md = (crtc->config.pixel_multiplier - 1)
4729                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4730         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4731
4732         if (crtc->config.has_dp_encoder)
4733                 intel_dp_set_m_n(crtc);
4734
4735         mutex_unlock(&dev_priv->dpio_lock);
4736 }
4737
4738 static void i9xx_update_pll(struct intel_crtc *crtc,
4739                             intel_clock_t *reduced_clock,
4740                             int num_connectors)
4741 {
4742         struct drm_device *dev = crtc->base.dev;
4743         struct drm_i915_private *dev_priv = dev->dev_private;
4744         u32 dpll;
4745         bool is_sdvo;
4746         struct dpll *clock = &crtc->config.dpll;
4747
4748         i9xx_update_pll_dividers(crtc, reduced_clock);
4749
4750         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4751                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4752
4753         dpll = DPLL_VGA_MODE_DIS;
4754
4755         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4756                 dpll |= DPLLB_MODE_LVDS;
4757         else
4758                 dpll |= DPLLB_MODE_DAC_SERIAL;
4759
4760         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4761                 dpll |= (crtc->config.pixel_multiplier - 1)
4762                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4763         }
4764
4765         if (is_sdvo)
4766                 dpll |= DPLL_SDVO_HIGH_SPEED;
4767
4768         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4769                 dpll |= DPLL_SDVO_HIGH_SPEED;
4770
4771         /* compute bitmask from p1 value */
4772         if (IS_PINEVIEW(dev))
4773                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4774         else {
4775                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4776                 if (IS_G4X(dev) && reduced_clock)
4777                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4778         }
4779         switch (clock->p2) {
4780         case 5:
4781                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4782                 break;
4783         case 7:
4784                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4785                 break;
4786         case 10:
4787                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4788                 break;
4789         case 14:
4790                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4791                 break;
4792         }
4793         if (INTEL_INFO(dev)->gen >= 4)
4794                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4795
4796         if (crtc->config.sdvo_tv_clock)
4797                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4798         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4799                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4800                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4801         else
4802                 dpll |= PLL_REF_INPUT_DREFCLK;
4803
4804         dpll |= DPLL_VCO_ENABLE;
4805         crtc->config.dpll_hw_state.dpll = dpll;
4806
4807         if (INTEL_INFO(dev)->gen >= 4) {
4808                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4809                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4810                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4811         }
4812
4813         if (crtc->config.has_dp_encoder)
4814                 intel_dp_set_m_n(crtc);
4815 }
4816
4817 static void i8xx_update_pll(struct intel_crtc *crtc,
4818                             intel_clock_t *reduced_clock,
4819                             int num_connectors)
4820 {
4821         struct drm_device *dev = crtc->base.dev;
4822         struct drm_i915_private *dev_priv = dev->dev_private;
4823         u32 dpll;
4824         struct dpll *clock = &crtc->config.dpll;
4825
4826         i9xx_update_pll_dividers(crtc, reduced_clock);
4827
4828         dpll = DPLL_VGA_MODE_DIS;
4829
4830         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4831                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4832         } else {
4833                 if (clock->p1 == 2)
4834                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4835                 else
4836                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4837                 if (clock->p2 == 4)
4838                         dpll |= PLL_P2_DIVIDE_BY_4;
4839         }
4840
4841         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4842                 dpll |= DPLL_DVO_2X_MODE;
4843
4844         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4845                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4846                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4847         else
4848                 dpll |= PLL_REF_INPUT_DREFCLK;
4849
4850         dpll |= DPLL_VCO_ENABLE;
4851         crtc->config.dpll_hw_state.dpll = dpll;
4852 }
4853
4854 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4855 {
4856         struct drm_device *dev = intel_crtc->base.dev;
4857         struct drm_i915_private *dev_priv = dev->dev_private;
4858         enum pipe pipe = intel_crtc->pipe;
4859         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4860         struct drm_display_mode *adjusted_mode =
4861                 &intel_crtc->config.adjusted_mode;
4862         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4863
4864         /* We need to be careful not to changed the adjusted mode, for otherwise
4865          * the hw state checker will get angry at the mismatch. */
4866         crtc_vtotal = adjusted_mode->crtc_vtotal;
4867         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4868
4869         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4870                 /* the chip adds 2 halflines automatically */
4871                 crtc_vtotal -= 1;
4872                 crtc_vblank_end -= 1;
4873                 vsyncshift = adjusted_mode->crtc_hsync_start
4874                              - adjusted_mode->crtc_htotal / 2;
4875         } else {
4876                 vsyncshift = 0;
4877         }
4878
4879         if (INTEL_INFO(dev)->gen > 3)
4880                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4881
4882         I915_WRITE(HTOTAL(cpu_transcoder),
4883                    (adjusted_mode->crtc_hdisplay - 1) |
4884                    ((adjusted_mode->crtc_htotal - 1) << 16));
4885         I915_WRITE(HBLANK(cpu_transcoder),
4886                    (adjusted_mode->crtc_hblank_start - 1) |
4887                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4888         I915_WRITE(HSYNC(cpu_transcoder),
4889                    (adjusted_mode->crtc_hsync_start - 1) |
4890                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4891
4892         I915_WRITE(VTOTAL(cpu_transcoder),
4893                    (adjusted_mode->crtc_vdisplay - 1) |
4894                    ((crtc_vtotal - 1) << 16));
4895         I915_WRITE(VBLANK(cpu_transcoder),
4896                    (adjusted_mode->crtc_vblank_start - 1) |
4897                    ((crtc_vblank_end - 1) << 16));
4898         I915_WRITE(VSYNC(cpu_transcoder),
4899                    (adjusted_mode->crtc_vsync_start - 1) |
4900                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4901
4902         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4903          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4904          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4905          * bits. */
4906         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4907             (pipe == PIPE_B || pipe == PIPE_C))
4908                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4909
4910         /* pipesrc controls the size that is scaled from, which should
4911          * always be the user's requested size.
4912          */
4913         I915_WRITE(PIPESRC(pipe),
4914                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4915                    (intel_crtc->config.pipe_src_h - 1));
4916 }
4917
4918 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4919                                    struct intel_crtc_config *pipe_config)
4920 {
4921         struct drm_device *dev = crtc->base.dev;
4922         struct drm_i915_private *dev_priv = dev->dev_private;
4923         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4924         uint32_t tmp;
4925
4926         tmp = I915_READ(HTOTAL(cpu_transcoder));
4927         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4928         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4929         tmp = I915_READ(HBLANK(cpu_transcoder));
4930         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4931         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4932         tmp = I915_READ(HSYNC(cpu_transcoder));
4933         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4934         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4935
4936         tmp = I915_READ(VTOTAL(cpu_transcoder));
4937         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4938         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4939         tmp = I915_READ(VBLANK(cpu_transcoder));
4940         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4941         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4942         tmp = I915_READ(VSYNC(cpu_transcoder));
4943         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4944         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4945
4946         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4947                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4948                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4949                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4950         }
4951
4952         tmp = I915_READ(PIPESRC(crtc->pipe));
4953         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4954         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4955
4956         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4957         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4958 }
4959
4960 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4961                                              struct intel_crtc_config *pipe_config)
4962 {
4963         struct drm_crtc *crtc = &intel_crtc->base;
4964
4965         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4966         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4967         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4968         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4969
4970         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4971         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4972         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4973         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4974
4975         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4976
4977         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4978         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4979 }
4980
4981 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4982 {
4983         struct drm_device *dev = intel_crtc->base.dev;
4984         struct drm_i915_private *dev_priv = dev->dev_private;
4985         uint32_t pipeconf;
4986
4987         pipeconf = 0;
4988
4989         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4990             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4991                 pipeconf |= PIPECONF_ENABLE;
4992
4993         if (intel_crtc->config.double_wide)
4994                 pipeconf |= PIPECONF_DOUBLE_WIDE;
4995
4996         /* only g4x and later have fancy bpc/dither controls */
4997         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4998                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4999                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5000                         pipeconf |= PIPECONF_DITHER_EN |
5001                                     PIPECONF_DITHER_TYPE_SP;
5002
5003                 switch (intel_crtc->config.pipe_bpp) {
5004                 case 18:
5005                         pipeconf |= PIPECONF_6BPC;
5006                         break;
5007                 case 24:
5008                         pipeconf |= PIPECONF_8BPC;
5009                         break;
5010                 case 30:
5011                         pipeconf |= PIPECONF_10BPC;
5012                         break;
5013                 default:
5014                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5015                         BUG();
5016                 }
5017         }
5018
5019         if (HAS_PIPE_CXSR(dev)) {
5020                 if (intel_crtc->lowfreq_avail) {
5021                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5022                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5023                 } else {
5024                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5025                 }
5026         }
5027
5028         if (!IS_GEN2(dev) &&
5029             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5030                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5031         else
5032                 pipeconf |= PIPECONF_PROGRESSIVE;
5033
5034         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5035                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5036
5037         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5038         POSTING_READ(PIPECONF(intel_crtc->pipe));
5039 }
5040
5041 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5042                               int x, int y,
5043                               struct drm_framebuffer *fb)
5044 {
5045         struct drm_device *dev = crtc->dev;
5046         struct drm_i915_private *dev_priv = dev->dev_private;
5047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048         int pipe = intel_crtc->pipe;
5049         int plane = intel_crtc->plane;
5050         int refclk, num_connectors = 0;
5051         intel_clock_t clock, reduced_clock;
5052         u32 dspcntr;
5053         bool ok, has_reduced_clock = false;
5054         bool is_lvds = false, is_dsi = false;
5055         struct intel_encoder *encoder;
5056         const intel_limit_t *limit;
5057         int ret;
5058
5059         for_each_encoder_on_crtc(dev, crtc, encoder) {
5060                 switch (encoder->type) {
5061                 case INTEL_OUTPUT_LVDS:
5062                         is_lvds = true;
5063                         break;
5064                 case INTEL_OUTPUT_DSI:
5065                         is_dsi = true;
5066                         break;
5067                 }
5068
5069                 num_connectors++;
5070         }
5071
5072         if (is_dsi)
5073                 goto skip_dpll;
5074
5075         if (!intel_crtc->config.clock_set) {
5076                 refclk = i9xx_get_refclk(crtc, num_connectors);
5077
5078                 /*
5079                  * Returns a set of divisors for the desired target clock with
5080                  * the given refclk, or FALSE.  The returned values represent
5081                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5082                  * 2) / p1 / p2.
5083                  */
5084                 limit = intel_limit(crtc, refclk);
5085                 ok = dev_priv->display.find_dpll(limit, crtc,
5086                                                  intel_crtc->config.port_clock,
5087                                                  refclk, NULL, &clock);
5088                 if (!ok) {
5089                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5090                         return -EINVAL;
5091                 }
5092
5093                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5094                         /*
5095                          * Ensure we match the reduced clock's P to the target
5096                          * clock.  If the clocks don't match, we can't switch
5097                          * the display clock by using the FP0/FP1. In such case
5098                          * we will disable the LVDS downclock feature.
5099                          */
5100                         has_reduced_clock =
5101                                 dev_priv->display.find_dpll(limit, crtc,
5102                                                             dev_priv->lvds_downclock,
5103                                                             refclk, &clock,
5104                                                             &reduced_clock);
5105                 }
5106                 /* Compat-code for transition, will disappear. */
5107                 intel_crtc->config.dpll.n = clock.n;
5108                 intel_crtc->config.dpll.m1 = clock.m1;
5109                 intel_crtc->config.dpll.m2 = clock.m2;
5110                 intel_crtc->config.dpll.p1 = clock.p1;
5111                 intel_crtc->config.dpll.p2 = clock.p2;
5112         }
5113
5114         if (IS_GEN2(dev)) {
5115                 i8xx_update_pll(intel_crtc,
5116                                 has_reduced_clock ? &reduced_clock : NULL,
5117                                 num_connectors);
5118         } else if (IS_VALLEYVIEW(dev)) {
5119                 vlv_update_pll(intel_crtc);
5120         } else {
5121                 i9xx_update_pll(intel_crtc,
5122                                 has_reduced_clock ? &reduced_clock : NULL,
5123                                 num_connectors);
5124         }
5125
5126 skip_dpll:
5127         /* Set up the display plane register */
5128         dspcntr = DISPPLANE_GAMMA_ENABLE;
5129
5130         if (!IS_VALLEYVIEW(dev)) {
5131                 if (pipe == 0)
5132                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5133                 else
5134                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5135         }
5136
5137         intel_set_pipe_timings(intel_crtc);
5138
5139         /* pipesrc and dspsize control the size that is scaled from,
5140          * which should always be the user's requested size.
5141          */
5142         I915_WRITE(DSPSIZE(plane),
5143                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5144                    (intel_crtc->config.pipe_src_w - 1));
5145         I915_WRITE(DSPPOS(plane), 0);
5146
5147         i9xx_set_pipeconf(intel_crtc);
5148
5149         I915_WRITE(DSPCNTR(plane), dspcntr);
5150         POSTING_READ(DSPCNTR(plane));
5151
5152         ret = intel_pipe_set_base(crtc, x, y, fb);
5153
5154         return ret;
5155 }
5156
5157 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5158                                  struct intel_crtc_config *pipe_config)
5159 {
5160         struct drm_device *dev = crtc->base.dev;
5161         struct drm_i915_private *dev_priv = dev->dev_private;
5162         uint32_t tmp;
5163
5164         tmp = I915_READ(PFIT_CONTROL);
5165         if (!(tmp & PFIT_ENABLE))
5166                 return;
5167
5168         /* Check whether the pfit is attached to our pipe. */
5169         if (INTEL_INFO(dev)->gen < 4) {
5170                 if (crtc->pipe != PIPE_B)
5171                         return;
5172         } else {
5173                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5174                         return;
5175         }
5176
5177         pipe_config->gmch_pfit.control = tmp;
5178         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5179         if (INTEL_INFO(dev)->gen < 5)
5180                 pipe_config->gmch_pfit.lvds_border_bits =
5181                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5182 }
5183
5184 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5185                                struct intel_crtc_config *pipe_config)
5186 {
5187         struct drm_device *dev = crtc->base.dev;
5188         struct drm_i915_private *dev_priv = dev->dev_private;
5189         int pipe = pipe_config->cpu_transcoder;
5190         intel_clock_t clock;
5191         u32 mdiv;
5192         int refclk = 100000;
5193
5194         mutex_lock(&dev_priv->dpio_lock);
5195         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5196         mutex_unlock(&dev_priv->dpio_lock);
5197
5198         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5199         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5200         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5201         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5202         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5203
5204         clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5205         clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
5206
5207         pipe_config->port_clock = clock.dot / 10;
5208 }
5209
5210 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5211                                  struct intel_crtc_config *pipe_config)
5212 {
5213         struct drm_device *dev = crtc->base.dev;
5214         struct drm_i915_private *dev_priv = dev->dev_private;
5215         uint32_t tmp;
5216
5217         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5218         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5219
5220         tmp = I915_READ(PIPECONF(crtc->pipe));
5221         if (!(tmp & PIPECONF_ENABLE))
5222                 return false;
5223
5224         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5225                 switch (tmp & PIPECONF_BPC_MASK) {
5226                 case PIPECONF_6BPC:
5227                         pipe_config->pipe_bpp = 18;
5228                         break;
5229                 case PIPECONF_8BPC:
5230                         pipe_config->pipe_bpp = 24;
5231                         break;
5232                 case PIPECONF_10BPC:
5233                         pipe_config->pipe_bpp = 30;
5234                         break;
5235                 default:
5236                         break;
5237                 }
5238         }
5239
5240         if (INTEL_INFO(dev)->gen < 4)
5241                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5242
5243         intel_get_pipe_timings(crtc, pipe_config);
5244
5245         i9xx_get_pfit_config(crtc, pipe_config);
5246
5247         if (INTEL_INFO(dev)->gen >= 4) {
5248                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5249                 pipe_config->pixel_multiplier =
5250                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5251                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5252                 pipe_config->dpll_hw_state.dpll_md = tmp;
5253         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5254                 tmp = I915_READ(DPLL(crtc->pipe));
5255                 pipe_config->pixel_multiplier =
5256                         ((tmp & SDVO_MULTIPLIER_MASK)
5257                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5258         } else {
5259                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5260                  * port and will be fixed up in the encoder->get_config
5261                  * function. */
5262                 pipe_config->pixel_multiplier = 1;
5263         }
5264         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5265         if (!IS_VALLEYVIEW(dev)) {
5266                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5267                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5268         } else {
5269                 /* Mask out read-only status bits. */
5270                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5271                                                      DPLL_PORTC_READY_MASK |
5272                                                      DPLL_PORTB_READY_MASK);
5273         }
5274
5275         if (IS_VALLEYVIEW(dev))
5276                 vlv_crtc_clock_get(crtc, pipe_config);
5277         else
5278                 i9xx_crtc_clock_get(crtc, pipe_config);
5279
5280         return true;
5281 }
5282
5283 static void ironlake_init_pch_refclk(struct drm_device *dev)
5284 {
5285         struct drm_i915_private *dev_priv = dev->dev_private;
5286         struct drm_mode_config *mode_config = &dev->mode_config;
5287         struct intel_encoder *encoder;
5288         u32 val, final;
5289         bool has_lvds = false;
5290         bool has_cpu_edp = false;
5291         bool has_panel = false;
5292         bool has_ck505 = false;
5293         bool can_ssc = false;
5294
5295         /* We need to take the global config into account */
5296         list_for_each_entry(encoder, &mode_config->encoder_list,
5297                             base.head) {
5298                 switch (encoder->type) {
5299                 case INTEL_OUTPUT_LVDS:
5300                         has_panel = true;
5301                         has_lvds = true;
5302                         break;
5303                 case INTEL_OUTPUT_EDP:
5304                         has_panel = true;
5305                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5306                                 has_cpu_edp = true;
5307                         break;
5308                 }
5309         }
5310
5311         if (HAS_PCH_IBX(dev)) {
5312                 has_ck505 = dev_priv->vbt.display_clock_mode;
5313                 can_ssc = has_ck505;
5314         } else {
5315                 has_ck505 = false;
5316                 can_ssc = true;
5317         }
5318
5319         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5320                       has_panel, has_lvds, has_ck505);
5321
5322         /* Ironlake: try to setup display ref clock before DPLL
5323          * enabling. This is only under driver's control after
5324          * PCH B stepping, previous chipset stepping should be
5325          * ignoring this setting.
5326          */
5327         val = I915_READ(PCH_DREF_CONTROL);
5328
5329         /* As we must carefully and slowly disable/enable each source in turn,
5330          * compute the final state we want first and check if we need to
5331          * make any changes at all.
5332          */
5333         final = val;
5334         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5335         if (has_ck505)
5336                 final |= DREF_NONSPREAD_CK505_ENABLE;
5337         else
5338                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5339
5340         final &= ~DREF_SSC_SOURCE_MASK;
5341         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5342         final &= ~DREF_SSC1_ENABLE;
5343
5344         if (has_panel) {
5345                 final |= DREF_SSC_SOURCE_ENABLE;
5346
5347                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5348                         final |= DREF_SSC1_ENABLE;
5349
5350                 if (has_cpu_edp) {
5351                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5352                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5353                         else
5354                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5355                 } else
5356                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5357         } else {
5358                 final |= DREF_SSC_SOURCE_DISABLE;
5359                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5360         }
5361
5362         if (final == val)
5363                 return;
5364
5365         /* Always enable nonspread source */
5366         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5367
5368         if (has_ck505)
5369                 val |= DREF_NONSPREAD_CK505_ENABLE;
5370         else
5371                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5372
5373         if (has_panel) {
5374                 val &= ~DREF_SSC_SOURCE_MASK;
5375                 val |= DREF_SSC_SOURCE_ENABLE;
5376
5377                 /* SSC must be turned on before enabling the CPU output  */
5378                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5379                         DRM_DEBUG_KMS("Using SSC on panel\n");
5380                         val |= DREF_SSC1_ENABLE;
5381                 } else
5382                         val &= ~DREF_SSC1_ENABLE;
5383
5384                 /* Get SSC going before enabling the outputs */
5385                 I915_WRITE(PCH_DREF_CONTROL, val);
5386                 POSTING_READ(PCH_DREF_CONTROL);
5387                 udelay(200);
5388
5389                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5390
5391                 /* Enable CPU source on CPU attached eDP */
5392                 if (has_cpu_edp) {
5393                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5394                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5395                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5396                         }
5397                         else
5398                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5399                 } else
5400                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5401
5402                 I915_WRITE(PCH_DREF_CONTROL, val);
5403                 POSTING_READ(PCH_DREF_CONTROL);
5404                 udelay(200);
5405         } else {
5406                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5407
5408                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5409
5410                 /* Turn off CPU output */
5411                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5412
5413                 I915_WRITE(PCH_DREF_CONTROL, val);
5414                 POSTING_READ(PCH_DREF_CONTROL);
5415                 udelay(200);
5416
5417                 /* Turn off the SSC source */
5418                 val &= ~DREF_SSC_SOURCE_MASK;
5419                 val |= DREF_SSC_SOURCE_DISABLE;
5420
5421                 /* Turn off SSC1 */
5422                 val &= ~DREF_SSC1_ENABLE;
5423
5424                 I915_WRITE(PCH_DREF_CONTROL, val);
5425                 POSTING_READ(PCH_DREF_CONTROL);
5426                 udelay(200);
5427         }
5428
5429         BUG_ON(val != final);
5430 }
5431
5432 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5433 {
5434         uint32_t tmp;
5435
5436         tmp = I915_READ(SOUTH_CHICKEN2);
5437         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5438         I915_WRITE(SOUTH_CHICKEN2, tmp);
5439
5440         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5441                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5442                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5443
5444         tmp = I915_READ(SOUTH_CHICKEN2);
5445         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5446         I915_WRITE(SOUTH_CHICKEN2, tmp);
5447
5448         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5449                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5450                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5451 }
5452
5453 /* WaMPhyProgramming:hsw */
5454 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5455 {
5456         uint32_t tmp;
5457
5458         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5459         tmp &= ~(0xFF << 24);
5460         tmp |= (0x12 << 24);
5461         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5462
5463         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5464         tmp |= (1 << 11);
5465         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5466
5467         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5468         tmp |= (1 << 11);
5469         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5470
5471         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5472         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5473         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5474
5475         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5476         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5477         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5478
5479         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5480         tmp &= ~(7 << 13);
5481         tmp |= (5 << 13);
5482         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5483
5484         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5485         tmp &= ~(7 << 13);
5486         tmp |= (5 << 13);
5487         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5488
5489         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5490         tmp &= ~0xFF;
5491         tmp |= 0x1C;
5492         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5493
5494         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5495         tmp &= ~0xFF;
5496         tmp |= 0x1C;
5497         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5498
5499         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5500         tmp &= ~(0xFF << 16);
5501         tmp |= (0x1C << 16);
5502         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5503
5504         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5505         tmp &= ~(0xFF << 16);
5506         tmp |= (0x1C << 16);
5507         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5508
5509         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5510         tmp |= (1 << 27);
5511         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5512
5513         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5514         tmp |= (1 << 27);
5515         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5516
5517         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5518         tmp &= ~(0xF << 28);
5519         tmp |= (4 << 28);
5520         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5521
5522         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5523         tmp &= ~(0xF << 28);
5524         tmp |= (4 << 28);
5525         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5526 }
5527
5528 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5529  * Programming" based on the parameters passed:
5530  * - Sequence to enable CLKOUT_DP
5531  * - Sequence to enable CLKOUT_DP without spread
5532  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5533  */
5534 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5535                                  bool with_fdi)
5536 {
5537         struct drm_i915_private *dev_priv = dev->dev_private;
5538         uint32_t reg, tmp;
5539
5540         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5541                 with_spread = true;
5542         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5543                  with_fdi, "LP PCH doesn't have FDI\n"))
5544                 with_fdi = false;
5545
5546         mutex_lock(&dev_priv->dpio_lock);
5547
5548         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5549         tmp &= ~SBI_SSCCTL_DISABLE;
5550         tmp |= SBI_SSCCTL_PATHALT;
5551         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5552
5553         udelay(24);
5554
5555         if (with_spread) {
5556                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5557                 tmp &= ~SBI_SSCCTL_PATHALT;
5558                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5559
5560                 if (with_fdi) {
5561                         lpt_reset_fdi_mphy(dev_priv);
5562                         lpt_program_fdi_mphy(dev_priv);
5563                 }
5564         }
5565
5566         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5567                SBI_GEN0 : SBI_DBUFF0;
5568         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5569         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5570         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5571
5572         mutex_unlock(&dev_priv->dpio_lock);
5573 }
5574
5575 /* Sequence to disable CLKOUT_DP */
5576 static void lpt_disable_clkout_dp(struct drm_device *dev)
5577 {
5578         struct drm_i915_private *dev_priv = dev->dev_private;
5579         uint32_t reg, tmp;
5580
5581         mutex_lock(&dev_priv->dpio_lock);
5582
5583         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5584                SBI_GEN0 : SBI_DBUFF0;
5585         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5586         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5587         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5588
5589         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5590         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5591                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5592                         tmp |= SBI_SSCCTL_PATHALT;
5593                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5594                         udelay(32);
5595                 }
5596                 tmp |= SBI_SSCCTL_DISABLE;
5597                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5598         }
5599
5600         mutex_unlock(&dev_priv->dpio_lock);
5601 }
5602
5603 static void lpt_init_pch_refclk(struct drm_device *dev)
5604 {
5605         struct drm_mode_config *mode_config = &dev->mode_config;
5606         struct intel_encoder *encoder;
5607         bool has_vga = false;
5608
5609         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5610                 switch (encoder->type) {
5611                 case INTEL_OUTPUT_ANALOG:
5612                         has_vga = true;
5613                         break;
5614                 }
5615         }
5616
5617         if (has_vga)
5618                 lpt_enable_clkout_dp(dev, true, true);
5619         else
5620                 lpt_disable_clkout_dp(dev);
5621 }
5622
5623 /*
5624  * Initialize reference clocks when the driver loads
5625  */
5626 void intel_init_pch_refclk(struct drm_device *dev)
5627 {
5628         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5629                 ironlake_init_pch_refclk(dev);
5630         else if (HAS_PCH_LPT(dev))
5631                 lpt_init_pch_refclk(dev);
5632 }
5633
5634 static int ironlake_get_refclk(struct drm_crtc *crtc)
5635 {
5636         struct drm_device *dev = crtc->dev;
5637         struct drm_i915_private *dev_priv = dev->dev_private;
5638         struct intel_encoder *encoder;
5639         int num_connectors = 0;
5640         bool is_lvds = false;
5641
5642         for_each_encoder_on_crtc(dev, crtc, encoder) {
5643                 switch (encoder->type) {
5644                 case INTEL_OUTPUT_LVDS:
5645                         is_lvds = true;
5646                         break;
5647                 }
5648                 num_connectors++;
5649         }
5650
5651         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5652                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5653                               dev_priv->vbt.lvds_ssc_freq);
5654                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5655         }
5656
5657         return 120000;
5658 }
5659
5660 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5661 {
5662         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5664         int pipe = intel_crtc->pipe;
5665         uint32_t val;
5666
5667         val = 0;
5668
5669         switch (intel_crtc->config.pipe_bpp) {
5670         case 18:
5671                 val |= PIPECONF_6BPC;
5672                 break;
5673         case 24:
5674                 val |= PIPECONF_8BPC;
5675                 break;
5676         case 30:
5677                 val |= PIPECONF_10BPC;
5678                 break;
5679         case 36:
5680                 val |= PIPECONF_12BPC;
5681                 break;
5682         default:
5683                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5684                 BUG();
5685         }
5686
5687         if (intel_crtc->config.dither)
5688                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5689
5690         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5691                 val |= PIPECONF_INTERLACED_ILK;
5692         else
5693                 val |= PIPECONF_PROGRESSIVE;
5694
5695         if (intel_crtc->config.limited_color_range)
5696                 val |= PIPECONF_COLOR_RANGE_SELECT;
5697
5698         I915_WRITE(PIPECONF(pipe), val);
5699         POSTING_READ(PIPECONF(pipe));
5700 }
5701
5702 /*
5703  * Set up the pipe CSC unit.
5704  *
5705  * Currently only full range RGB to limited range RGB conversion
5706  * is supported, but eventually this should handle various
5707  * RGB<->YCbCr scenarios as well.
5708  */
5709 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5710 {
5711         struct drm_device *dev = crtc->dev;
5712         struct drm_i915_private *dev_priv = dev->dev_private;
5713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5714         int pipe = intel_crtc->pipe;
5715         uint16_t coeff = 0x7800; /* 1.0 */
5716
5717         /*
5718          * TODO: Check what kind of values actually come out of the pipe
5719          * with these coeff/postoff values and adjust to get the best
5720          * accuracy. Perhaps we even need to take the bpc value into
5721          * consideration.
5722          */
5723
5724         if (intel_crtc->config.limited_color_range)
5725                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5726
5727         /*
5728          * GY/GU and RY/RU should be the other way around according
5729          * to BSpec, but reality doesn't agree. Just set them up in
5730          * a way that results in the correct picture.
5731          */
5732         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5733         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5734
5735         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5736         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5737
5738         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5739         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5740
5741         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5742         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5743         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5744
5745         if (INTEL_INFO(dev)->gen > 6) {
5746                 uint16_t postoff = 0;
5747
5748                 if (intel_crtc->config.limited_color_range)
5749                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5750
5751                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5752                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5753                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5754
5755                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5756         } else {
5757                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5758
5759                 if (intel_crtc->config.limited_color_range)
5760                         mode |= CSC_BLACK_SCREEN_OFFSET;
5761
5762                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5763         }
5764 }
5765
5766 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5767 {
5768         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5770         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5771         uint32_t val;
5772
5773         val = 0;
5774
5775         if (intel_crtc->config.dither)
5776                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5777
5778         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5779                 val |= PIPECONF_INTERLACED_ILK;
5780         else
5781                 val |= PIPECONF_PROGRESSIVE;
5782
5783         I915_WRITE(PIPECONF(cpu_transcoder), val);
5784         POSTING_READ(PIPECONF(cpu_transcoder));
5785
5786         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5787         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5788 }
5789
5790 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5791                                     intel_clock_t *clock,
5792                                     bool *has_reduced_clock,
5793                                     intel_clock_t *reduced_clock)
5794 {
5795         struct drm_device *dev = crtc->dev;
5796         struct drm_i915_private *dev_priv = dev->dev_private;
5797         struct intel_encoder *intel_encoder;
5798         int refclk;
5799         const intel_limit_t *limit;
5800         bool ret, is_lvds = false;
5801
5802         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5803                 switch (intel_encoder->type) {
5804                 case INTEL_OUTPUT_LVDS:
5805                         is_lvds = true;
5806                         break;
5807                 }
5808         }
5809
5810         refclk = ironlake_get_refclk(crtc);
5811
5812         /*
5813          * Returns a set of divisors for the desired target clock with the given
5814          * refclk, or FALSE.  The returned values represent the clock equation:
5815          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5816          */
5817         limit = intel_limit(crtc, refclk);
5818         ret = dev_priv->display.find_dpll(limit, crtc,
5819                                           to_intel_crtc(crtc)->config.port_clock,
5820                                           refclk, NULL, clock);
5821         if (!ret)
5822                 return false;
5823
5824         if (is_lvds && dev_priv->lvds_downclock_avail) {
5825                 /*
5826                  * Ensure we match the reduced clock's P to the target clock.
5827                  * If the clocks don't match, we can't switch the display clock
5828                  * by using the FP0/FP1. In such case we will disable the LVDS
5829                  * downclock feature.
5830                 */
5831                 *has_reduced_clock =
5832                         dev_priv->display.find_dpll(limit, crtc,
5833                                                     dev_priv->lvds_downclock,
5834                                                     refclk, clock,
5835                                                     reduced_clock);
5836         }
5837
5838         return true;
5839 }
5840
5841 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5842 {
5843         struct drm_i915_private *dev_priv = dev->dev_private;
5844         uint32_t temp;
5845
5846         temp = I915_READ(SOUTH_CHICKEN1);
5847         if (temp & FDI_BC_BIFURCATION_SELECT)
5848                 return;
5849
5850         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5851         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5852
5853         temp |= FDI_BC_BIFURCATION_SELECT;
5854         DRM_DEBUG_KMS("enabling fdi C rx\n");
5855         I915_WRITE(SOUTH_CHICKEN1, temp);
5856         POSTING_READ(SOUTH_CHICKEN1);
5857 }
5858
5859 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5860 {
5861         struct drm_device *dev = intel_crtc->base.dev;
5862         struct drm_i915_private *dev_priv = dev->dev_private;
5863
5864         switch (intel_crtc->pipe) {
5865         case PIPE_A:
5866                 break;
5867         case PIPE_B:
5868                 if (intel_crtc->config.fdi_lanes > 2)
5869                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5870                 else
5871                         cpt_enable_fdi_bc_bifurcation(dev);
5872
5873                 break;
5874         case PIPE_C:
5875                 cpt_enable_fdi_bc_bifurcation(dev);
5876
5877                 break;
5878         default:
5879                 BUG();
5880         }
5881 }
5882
5883 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5884 {
5885         /*
5886          * Account for spread spectrum to avoid
5887          * oversubscribing the link. Max center spread
5888          * is 2.5%; use 5% for safety's sake.
5889          */
5890         u32 bps = target_clock * bpp * 21 / 20;
5891         return bps / (link_bw * 8) + 1;
5892 }
5893
5894 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5895 {
5896         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5897 }
5898
5899 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5900                                       u32 *fp,
5901                                       intel_clock_t *reduced_clock, u32 *fp2)
5902 {
5903         struct drm_crtc *crtc = &intel_crtc->base;
5904         struct drm_device *dev = crtc->dev;
5905         struct drm_i915_private *dev_priv = dev->dev_private;
5906         struct intel_encoder *intel_encoder;
5907         uint32_t dpll;
5908         int factor, num_connectors = 0;
5909         bool is_lvds = false, is_sdvo = false;
5910
5911         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5912                 switch (intel_encoder->type) {
5913                 case INTEL_OUTPUT_LVDS:
5914                         is_lvds = true;
5915                         break;
5916                 case INTEL_OUTPUT_SDVO:
5917                 case INTEL_OUTPUT_HDMI:
5918                         is_sdvo = true;
5919                         break;
5920                 }
5921
5922                 num_connectors++;
5923         }
5924
5925         /* Enable autotuning of the PLL clock (if permissible) */
5926         factor = 21;
5927         if (is_lvds) {
5928                 if ((intel_panel_use_ssc(dev_priv) &&
5929                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5930                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5931                         factor = 25;
5932         } else if (intel_crtc->config.sdvo_tv_clock)
5933                 factor = 20;
5934
5935         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5936                 *fp |= FP_CB_TUNE;
5937
5938         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5939                 *fp2 |= FP_CB_TUNE;
5940
5941         dpll = 0;
5942
5943         if (is_lvds)
5944                 dpll |= DPLLB_MODE_LVDS;
5945         else
5946                 dpll |= DPLLB_MODE_DAC_SERIAL;
5947
5948         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5949                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5950
5951         if (is_sdvo)
5952                 dpll |= DPLL_SDVO_HIGH_SPEED;
5953         if (intel_crtc->config.has_dp_encoder)
5954                 dpll |= DPLL_SDVO_HIGH_SPEED;
5955
5956         /* compute bitmask from p1 value */
5957         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5958         /* also FPA1 */
5959         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5960
5961         switch (intel_crtc->config.dpll.p2) {
5962         case 5:
5963                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5964                 break;
5965         case 7:
5966                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5967                 break;
5968         case 10:
5969                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5970                 break;
5971         case 14:
5972                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5973                 break;
5974         }
5975
5976         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5977                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5978         else
5979                 dpll |= PLL_REF_INPUT_DREFCLK;
5980
5981         return dpll | DPLL_VCO_ENABLE;
5982 }
5983
5984 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5985                                   int x, int y,
5986                                   struct drm_framebuffer *fb)
5987 {
5988         struct drm_device *dev = crtc->dev;
5989         struct drm_i915_private *dev_priv = dev->dev_private;
5990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5991         int pipe = intel_crtc->pipe;
5992         int plane = intel_crtc->plane;
5993         int num_connectors = 0;
5994         intel_clock_t clock, reduced_clock;
5995         u32 dpll = 0, fp = 0, fp2 = 0;
5996         bool ok, has_reduced_clock = false;
5997         bool is_lvds = false;
5998         struct intel_encoder *encoder;
5999         struct intel_shared_dpll *pll;
6000         int ret;
6001
6002         for_each_encoder_on_crtc(dev, crtc, encoder) {
6003                 switch (encoder->type) {
6004                 case INTEL_OUTPUT_LVDS:
6005                         is_lvds = true;
6006                         break;
6007                 }
6008
6009                 num_connectors++;
6010         }
6011
6012         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6013              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6014
6015         ok = ironlake_compute_clocks(crtc, &clock,
6016                                      &has_reduced_clock, &reduced_clock);
6017         if (!ok && !intel_crtc->config.clock_set) {
6018                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6019                 return -EINVAL;
6020         }
6021         /* Compat-code for transition, will disappear. */
6022         if (!intel_crtc->config.clock_set) {
6023                 intel_crtc->config.dpll.n = clock.n;
6024                 intel_crtc->config.dpll.m1 = clock.m1;
6025                 intel_crtc->config.dpll.m2 = clock.m2;
6026                 intel_crtc->config.dpll.p1 = clock.p1;
6027                 intel_crtc->config.dpll.p2 = clock.p2;
6028         }
6029
6030         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6031         if (intel_crtc->config.has_pch_encoder) {
6032                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6033                 if (has_reduced_clock)
6034                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6035
6036                 dpll = ironlake_compute_dpll(intel_crtc,
6037                                              &fp, &reduced_clock,
6038                                              has_reduced_clock ? &fp2 : NULL);
6039
6040                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6041                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6042                 if (has_reduced_clock)
6043                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6044                 else
6045                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6046
6047                 pll = intel_get_shared_dpll(intel_crtc);
6048                 if (pll == NULL) {
6049                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6050                                          pipe_name(pipe));
6051                         return -EINVAL;
6052                 }
6053         } else
6054                 intel_put_shared_dpll(intel_crtc);
6055
6056         if (intel_crtc->config.has_dp_encoder)
6057                 intel_dp_set_m_n(intel_crtc);
6058
6059         if (is_lvds && has_reduced_clock && i915_powersave)
6060                 intel_crtc->lowfreq_avail = true;
6061         else
6062                 intel_crtc->lowfreq_avail = false;
6063
6064         if (intel_crtc->config.has_pch_encoder) {
6065                 pll = intel_crtc_to_shared_dpll(intel_crtc);
6066
6067         }
6068
6069         intel_set_pipe_timings(intel_crtc);
6070
6071         if (intel_crtc->config.has_pch_encoder) {
6072                 intel_cpu_transcoder_set_m_n(intel_crtc,
6073                                              &intel_crtc->config.fdi_m_n);
6074         }
6075
6076         if (IS_IVYBRIDGE(dev))
6077                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6078
6079         ironlake_set_pipeconf(crtc);
6080
6081         /* Set up the display plane register */
6082         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6083         POSTING_READ(DSPCNTR(plane));
6084
6085         ret = intel_pipe_set_base(crtc, x, y, fb);
6086
6087         return ret;
6088 }
6089
6090 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6091                                          struct intel_link_m_n *m_n)
6092 {
6093         struct drm_device *dev = crtc->base.dev;
6094         struct drm_i915_private *dev_priv = dev->dev_private;
6095         enum pipe pipe = crtc->pipe;
6096
6097         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6098         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6099         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6100                 & ~TU_SIZE_MASK;
6101         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6102         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6103                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6104 }
6105
6106 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6107                                          enum transcoder transcoder,
6108                                          struct intel_link_m_n *m_n)
6109 {
6110         struct drm_device *dev = crtc->base.dev;
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112         enum pipe pipe = crtc->pipe;
6113
6114         if (INTEL_INFO(dev)->gen >= 5) {
6115                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6116                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6117                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6118                         & ~TU_SIZE_MASK;
6119                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6120                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6121                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6122         } else {
6123                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6124                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6125                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6126                         & ~TU_SIZE_MASK;
6127                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6128                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6129                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6130         }
6131 }
6132
6133 void intel_dp_get_m_n(struct intel_crtc *crtc,
6134                       struct intel_crtc_config *pipe_config)
6135 {
6136         if (crtc->config.has_pch_encoder)
6137                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6138         else
6139                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6140                                              &pipe_config->dp_m_n);
6141 }
6142
6143 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6144                                         struct intel_crtc_config *pipe_config)
6145 {
6146         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6147                                      &pipe_config->fdi_m_n);
6148 }
6149
6150 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6151                                      struct intel_crtc_config *pipe_config)
6152 {
6153         struct drm_device *dev = crtc->base.dev;
6154         struct drm_i915_private *dev_priv = dev->dev_private;
6155         uint32_t tmp;
6156
6157         tmp = I915_READ(PF_CTL(crtc->pipe));
6158
6159         if (tmp & PF_ENABLE) {
6160                 pipe_config->pch_pfit.enabled = true;
6161                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6162                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6163
6164                 /* We currently do not free assignements of panel fitters on
6165                  * ivb/hsw (since we don't use the higher upscaling modes which
6166                  * differentiates them) so just WARN about this case for now. */
6167                 if (IS_GEN7(dev)) {
6168                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6169                                 PF_PIPE_SEL_IVB(crtc->pipe));
6170                 }
6171         }
6172 }
6173
6174 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6175                                      struct intel_crtc_config *pipe_config)
6176 {
6177         struct drm_device *dev = crtc->base.dev;
6178         struct drm_i915_private *dev_priv = dev->dev_private;
6179         uint32_t tmp;
6180
6181         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6182         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6183
6184         tmp = I915_READ(PIPECONF(crtc->pipe));
6185         if (!(tmp & PIPECONF_ENABLE))
6186                 return false;
6187
6188         switch (tmp & PIPECONF_BPC_MASK) {
6189         case PIPECONF_6BPC:
6190                 pipe_config->pipe_bpp = 18;
6191                 break;
6192         case PIPECONF_8BPC:
6193                 pipe_config->pipe_bpp = 24;
6194                 break;
6195         case PIPECONF_10BPC:
6196                 pipe_config->pipe_bpp = 30;
6197                 break;
6198         case PIPECONF_12BPC:
6199                 pipe_config->pipe_bpp = 36;
6200                 break;
6201         default:
6202                 break;
6203         }
6204
6205         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6206                 struct intel_shared_dpll *pll;
6207
6208                 pipe_config->has_pch_encoder = true;
6209
6210                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6211                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6212                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6213
6214                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6215
6216                 if (HAS_PCH_IBX(dev_priv->dev)) {
6217                         pipe_config->shared_dpll =
6218                                 (enum intel_dpll_id) crtc->pipe;
6219                 } else {
6220                         tmp = I915_READ(PCH_DPLL_SEL);
6221                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6222                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6223                         else
6224                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6225                 }
6226
6227                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6228
6229                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6230                                            &pipe_config->dpll_hw_state));
6231
6232                 tmp = pipe_config->dpll_hw_state.dpll;
6233                 pipe_config->pixel_multiplier =
6234                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6235                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6236
6237                 ironlake_pch_clock_get(crtc, pipe_config);
6238         } else {
6239                 pipe_config->pixel_multiplier = 1;
6240         }
6241
6242         intel_get_pipe_timings(crtc, pipe_config);
6243
6244         ironlake_get_pfit_config(crtc, pipe_config);
6245
6246         return true;
6247 }
6248
6249 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6250 {
6251         struct drm_device *dev = dev_priv->dev;
6252         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6253         struct intel_crtc *crtc;
6254         unsigned long irqflags;
6255         uint32_t val;
6256
6257         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6258                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6259                      pipe_name(crtc->pipe));
6260
6261         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6262         WARN(plls->spll_refcount, "SPLL enabled\n");
6263         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6264         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6265         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6266         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6267              "CPU PWM1 enabled\n");
6268         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6269              "CPU PWM2 enabled\n");
6270         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6271              "PCH PWM1 enabled\n");
6272         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6273              "Utility pin enabled\n");
6274         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6275
6276         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6277         val = I915_READ(DEIMR);
6278         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6279              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6280         val = I915_READ(SDEIMR);
6281         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6282              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6283         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6284 }
6285
6286 /*
6287  * This function implements pieces of two sequences from BSpec:
6288  * - Sequence for display software to disable LCPLL
6289  * - Sequence for display software to allow package C8+
6290  * The steps implemented here are just the steps that actually touch the LCPLL
6291  * register. Callers should take care of disabling all the display engine
6292  * functions, doing the mode unset, fixing interrupts, etc.
6293  */
6294 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6295                               bool switch_to_fclk, bool allow_power_down)
6296 {
6297         uint32_t val;
6298
6299         assert_can_disable_lcpll(dev_priv);
6300
6301         val = I915_READ(LCPLL_CTL);
6302
6303         if (switch_to_fclk) {
6304                 val |= LCPLL_CD_SOURCE_FCLK;
6305                 I915_WRITE(LCPLL_CTL, val);
6306
6307                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6308                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6309                         DRM_ERROR("Switching to FCLK failed\n");
6310
6311                 val = I915_READ(LCPLL_CTL);
6312         }
6313
6314         val |= LCPLL_PLL_DISABLE;
6315         I915_WRITE(LCPLL_CTL, val);
6316         POSTING_READ(LCPLL_CTL);
6317
6318         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6319                 DRM_ERROR("LCPLL still locked\n");
6320
6321         val = I915_READ(D_COMP);
6322         val |= D_COMP_COMP_DISABLE;
6323         mutex_lock(&dev_priv->rps.hw_lock);
6324         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6325                 DRM_ERROR("Failed to disable D_COMP\n");
6326         mutex_unlock(&dev_priv->rps.hw_lock);
6327         POSTING_READ(D_COMP);
6328         ndelay(100);
6329
6330         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6331                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6332
6333         if (allow_power_down) {
6334                 val = I915_READ(LCPLL_CTL);
6335                 val |= LCPLL_POWER_DOWN_ALLOW;
6336                 I915_WRITE(LCPLL_CTL, val);
6337                 POSTING_READ(LCPLL_CTL);
6338         }
6339 }
6340
6341 /*
6342  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6343  * source.
6344  */
6345 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6346 {
6347         uint32_t val;
6348
6349         val = I915_READ(LCPLL_CTL);
6350
6351         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6352                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6353                 return;
6354
6355         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6356          * we'll hang the machine! */
6357         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6358
6359         if (val & LCPLL_POWER_DOWN_ALLOW) {
6360                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6361                 I915_WRITE(LCPLL_CTL, val);
6362                 POSTING_READ(LCPLL_CTL);
6363         }
6364
6365         val = I915_READ(D_COMP);
6366         val |= D_COMP_COMP_FORCE;
6367         val &= ~D_COMP_COMP_DISABLE;
6368         mutex_lock(&dev_priv->rps.hw_lock);
6369         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6370                 DRM_ERROR("Failed to enable D_COMP\n");
6371         mutex_unlock(&dev_priv->rps.hw_lock);
6372         POSTING_READ(D_COMP);
6373
6374         val = I915_READ(LCPLL_CTL);
6375         val &= ~LCPLL_PLL_DISABLE;
6376         I915_WRITE(LCPLL_CTL, val);
6377
6378         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6379                 DRM_ERROR("LCPLL not locked yet\n");
6380
6381         if (val & LCPLL_CD_SOURCE_FCLK) {
6382                 val = I915_READ(LCPLL_CTL);
6383                 val &= ~LCPLL_CD_SOURCE_FCLK;
6384                 I915_WRITE(LCPLL_CTL, val);
6385
6386                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6387                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6388                         DRM_ERROR("Switching back to LCPLL failed\n");
6389         }
6390
6391         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6392 }
6393
6394 void hsw_enable_pc8_work(struct work_struct *__work)
6395 {
6396         struct drm_i915_private *dev_priv =
6397                 container_of(to_delayed_work(__work), struct drm_i915_private,
6398                              pc8.enable_work);
6399         struct drm_device *dev = dev_priv->dev;
6400         uint32_t val;
6401
6402         if (dev_priv->pc8.enabled)
6403                 return;
6404
6405         DRM_DEBUG_KMS("Enabling package C8+\n");
6406
6407         dev_priv->pc8.enabled = true;
6408
6409         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6410                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6411                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6412                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6413         }
6414
6415         lpt_disable_clkout_dp(dev);
6416         hsw_pc8_disable_interrupts(dev);
6417         hsw_disable_lcpll(dev_priv, true, true);
6418 }
6419
6420 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6421 {
6422         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6423         WARN(dev_priv->pc8.disable_count < 1,
6424              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6425
6426         dev_priv->pc8.disable_count--;
6427         if (dev_priv->pc8.disable_count != 0)
6428                 return;
6429
6430         schedule_delayed_work(&dev_priv->pc8.enable_work,
6431                               msecs_to_jiffies(i915_pc8_timeout));
6432 }
6433
6434 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6435 {
6436         struct drm_device *dev = dev_priv->dev;
6437         uint32_t val;
6438
6439         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6440         WARN(dev_priv->pc8.disable_count < 0,
6441              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6442
6443         dev_priv->pc8.disable_count++;
6444         if (dev_priv->pc8.disable_count != 1)
6445                 return;
6446
6447         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6448         if (!dev_priv->pc8.enabled)
6449                 return;
6450
6451         DRM_DEBUG_KMS("Disabling package C8+\n");
6452
6453         hsw_restore_lcpll(dev_priv);
6454         hsw_pc8_restore_interrupts(dev);
6455         lpt_init_pch_refclk(dev);
6456
6457         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6458                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6459                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6460                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6461         }
6462
6463         intel_prepare_ddi(dev);
6464         i915_gem_init_swizzling(dev);
6465         mutex_lock(&dev_priv->rps.hw_lock);
6466         gen6_update_ring_freq(dev);
6467         mutex_unlock(&dev_priv->rps.hw_lock);
6468         dev_priv->pc8.enabled = false;
6469 }
6470
6471 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6472 {
6473         mutex_lock(&dev_priv->pc8.lock);
6474         __hsw_enable_package_c8(dev_priv);
6475         mutex_unlock(&dev_priv->pc8.lock);
6476 }
6477
6478 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6479 {
6480         mutex_lock(&dev_priv->pc8.lock);
6481         __hsw_disable_package_c8(dev_priv);
6482         mutex_unlock(&dev_priv->pc8.lock);
6483 }
6484
6485 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6486 {
6487         struct drm_device *dev = dev_priv->dev;
6488         struct intel_crtc *crtc;
6489         uint32_t val;
6490
6491         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6492                 if (crtc->base.enabled)
6493                         return false;
6494
6495         /* This case is still possible since we have the i915.disable_power_well
6496          * parameter and also the KVMr or something else might be requesting the
6497          * power well. */
6498         val = I915_READ(HSW_PWR_WELL_DRIVER);
6499         if (val != 0) {
6500                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6501                 return false;
6502         }
6503
6504         return true;
6505 }
6506
6507 /* Since we're called from modeset_global_resources there's no way to
6508  * symmetrically increase and decrease the refcount, so we use
6509  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6510  * or not.
6511  */
6512 static void hsw_update_package_c8(struct drm_device *dev)
6513 {
6514         struct drm_i915_private *dev_priv = dev->dev_private;
6515         bool allow;
6516
6517         if (!i915_enable_pc8)
6518                 return;
6519
6520         mutex_lock(&dev_priv->pc8.lock);
6521
6522         allow = hsw_can_enable_package_c8(dev_priv);
6523
6524         if (allow == dev_priv->pc8.requirements_met)
6525                 goto done;
6526
6527         dev_priv->pc8.requirements_met = allow;
6528
6529         if (allow)
6530                 __hsw_enable_package_c8(dev_priv);
6531         else
6532                 __hsw_disable_package_c8(dev_priv);
6533
6534 done:
6535         mutex_unlock(&dev_priv->pc8.lock);
6536 }
6537
6538 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6539 {
6540         if (!dev_priv->pc8.gpu_idle) {
6541                 dev_priv->pc8.gpu_idle = true;
6542                 hsw_enable_package_c8(dev_priv);
6543         }
6544 }
6545
6546 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6547 {
6548         if (dev_priv->pc8.gpu_idle) {
6549                 dev_priv->pc8.gpu_idle = false;
6550                 hsw_disable_package_c8(dev_priv);
6551         }
6552 }
6553
6554 static void haswell_modeset_global_resources(struct drm_device *dev)
6555 {
6556         bool enable = false;
6557         struct intel_crtc *crtc;
6558
6559         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6560                 if (!crtc->base.enabled)
6561                         continue;
6562
6563                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6564                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6565                         enable = true;
6566         }
6567
6568         intel_set_power_well(dev, enable);
6569
6570         hsw_update_package_c8(dev);
6571 }
6572
6573 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6574                                  int x, int y,
6575                                  struct drm_framebuffer *fb)
6576 {
6577         struct drm_device *dev = crtc->dev;
6578         struct drm_i915_private *dev_priv = dev->dev_private;
6579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6580         int plane = intel_crtc->plane;
6581         int ret;
6582
6583         if (!intel_ddi_pll_mode_set(crtc))
6584                 return -EINVAL;
6585
6586         if (intel_crtc->config.has_dp_encoder)
6587                 intel_dp_set_m_n(intel_crtc);
6588
6589         intel_crtc->lowfreq_avail = false;
6590
6591         intel_set_pipe_timings(intel_crtc);
6592
6593         if (intel_crtc->config.has_pch_encoder) {
6594                 intel_cpu_transcoder_set_m_n(intel_crtc,
6595                                              &intel_crtc->config.fdi_m_n);
6596         }
6597
6598         haswell_set_pipeconf(crtc);
6599
6600         intel_set_pipe_csc(crtc);
6601
6602         /* Set up the display plane register */
6603         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6604         POSTING_READ(DSPCNTR(plane));
6605
6606         ret = intel_pipe_set_base(crtc, x, y, fb);
6607
6608         return ret;
6609 }
6610
6611 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6612                                     struct intel_crtc_config *pipe_config)
6613 {
6614         struct drm_device *dev = crtc->base.dev;
6615         struct drm_i915_private *dev_priv = dev->dev_private;
6616         enum intel_display_power_domain pfit_domain;
6617         uint32_t tmp;
6618
6619         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6620         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6621
6622         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6623         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6624                 enum pipe trans_edp_pipe;
6625                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6626                 default:
6627                         WARN(1, "unknown pipe linked to edp transcoder\n");
6628                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6629                 case TRANS_DDI_EDP_INPUT_A_ON:
6630                         trans_edp_pipe = PIPE_A;
6631                         break;
6632                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6633                         trans_edp_pipe = PIPE_B;
6634                         break;
6635                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6636                         trans_edp_pipe = PIPE_C;
6637                         break;
6638                 }
6639
6640                 if (trans_edp_pipe == crtc->pipe)
6641                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6642         }
6643
6644         if (!intel_display_power_enabled(dev,
6645                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6646                 return false;
6647
6648         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6649         if (!(tmp & PIPECONF_ENABLE))
6650                 return false;
6651
6652         /*
6653          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6654          * DDI E. So just check whether this pipe is wired to DDI E and whether
6655          * the PCH transcoder is on.
6656          */
6657         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6658         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6659             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6660                 pipe_config->has_pch_encoder = true;
6661
6662                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6663                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6664                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6665
6666                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6667         }
6668
6669         intel_get_pipe_timings(crtc, pipe_config);
6670
6671         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6672         if (intel_display_power_enabled(dev, pfit_domain))
6673                 ironlake_get_pfit_config(crtc, pipe_config);
6674
6675         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6676                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6677
6678         pipe_config->pixel_multiplier = 1;
6679
6680         return true;
6681 }
6682
6683 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6684                                int x, int y,
6685                                struct drm_framebuffer *fb)
6686 {
6687         struct drm_device *dev = crtc->dev;
6688         struct drm_i915_private *dev_priv = dev->dev_private;
6689         struct intel_encoder *encoder;
6690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6691         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6692         int pipe = intel_crtc->pipe;
6693         int ret;
6694
6695         drm_vblank_pre_modeset(dev, pipe);
6696
6697         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6698
6699         drm_vblank_post_modeset(dev, pipe);
6700
6701         if (ret != 0)
6702                 return ret;
6703
6704         for_each_encoder_on_crtc(dev, crtc, encoder) {
6705                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6706                         encoder->base.base.id,
6707                         drm_get_encoder_name(&encoder->base),
6708                         mode->base.id, mode->name);
6709                 encoder->mode_set(encoder);
6710         }
6711
6712         return 0;
6713 }
6714
6715 static bool intel_eld_uptodate(struct drm_connector *connector,
6716                                int reg_eldv, uint32_t bits_eldv,
6717                                int reg_elda, uint32_t bits_elda,
6718                                int reg_edid)
6719 {
6720         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6721         uint8_t *eld = connector->eld;
6722         uint32_t i;
6723
6724         i = I915_READ(reg_eldv);
6725         i &= bits_eldv;
6726
6727         if (!eld[0])
6728                 return !i;
6729
6730         if (!i)
6731                 return false;
6732
6733         i = I915_READ(reg_elda);
6734         i &= ~bits_elda;
6735         I915_WRITE(reg_elda, i);
6736
6737         for (i = 0; i < eld[2]; i++)
6738                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6739                         return false;
6740
6741         return true;
6742 }
6743
6744 static void g4x_write_eld(struct drm_connector *connector,
6745                           struct drm_crtc *crtc)
6746 {
6747         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6748         uint8_t *eld = connector->eld;
6749         uint32_t eldv;
6750         uint32_t len;
6751         uint32_t i;
6752
6753         i = I915_READ(G4X_AUD_VID_DID);
6754
6755         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6756                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6757         else
6758                 eldv = G4X_ELDV_DEVCTG;
6759
6760         if (intel_eld_uptodate(connector,
6761                                G4X_AUD_CNTL_ST, eldv,
6762                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6763                                G4X_HDMIW_HDMIEDID))
6764                 return;
6765
6766         i = I915_READ(G4X_AUD_CNTL_ST);
6767         i &= ~(eldv | G4X_ELD_ADDR);
6768         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6769         I915_WRITE(G4X_AUD_CNTL_ST, i);
6770
6771         if (!eld[0])
6772                 return;
6773
6774         len = min_t(uint8_t, eld[2], len);
6775         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6776         for (i = 0; i < len; i++)
6777                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6778
6779         i = I915_READ(G4X_AUD_CNTL_ST);
6780         i |= eldv;
6781         I915_WRITE(G4X_AUD_CNTL_ST, i);
6782 }
6783
6784 static void haswell_write_eld(struct drm_connector *connector,
6785                                      struct drm_crtc *crtc)
6786 {
6787         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6788         uint8_t *eld = connector->eld;
6789         struct drm_device *dev = crtc->dev;
6790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6791         uint32_t eldv;
6792         uint32_t i;
6793         int len;
6794         int pipe = to_intel_crtc(crtc)->pipe;
6795         int tmp;
6796
6797         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6798         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6799         int aud_config = HSW_AUD_CFG(pipe);
6800         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6801
6802
6803         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6804
6805         /* Audio output enable */
6806         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6807         tmp = I915_READ(aud_cntrl_st2);
6808         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6809         I915_WRITE(aud_cntrl_st2, tmp);
6810
6811         /* Wait for 1 vertical blank */
6812         intel_wait_for_vblank(dev, pipe);
6813
6814         /* Set ELD valid state */
6815         tmp = I915_READ(aud_cntrl_st2);
6816         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6817         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6818         I915_WRITE(aud_cntrl_st2, tmp);
6819         tmp = I915_READ(aud_cntrl_st2);
6820         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6821
6822         /* Enable HDMI mode */
6823         tmp = I915_READ(aud_config);
6824         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6825         /* clear N_programing_enable and N_value_index */
6826         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6827         I915_WRITE(aud_config, tmp);
6828
6829         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6830
6831         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6832         intel_crtc->eld_vld = true;
6833
6834         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6835                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6836                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6837                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6838         } else
6839                 I915_WRITE(aud_config, 0);
6840
6841         if (intel_eld_uptodate(connector,
6842                                aud_cntrl_st2, eldv,
6843                                aud_cntl_st, IBX_ELD_ADDRESS,
6844                                hdmiw_hdmiedid))
6845                 return;
6846
6847         i = I915_READ(aud_cntrl_st2);
6848         i &= ~eldv;
6849         I915_WRITE(aud_cntrl_st2, i);
6850
6851         if (!eld[0])
6852                 return;
6853
6854         i = I915_READ(aud_cntl_st);
6855         i &= ~IBX_ELD_ADDRESS;
6856         I915_WRITE(aud_cntl_st, i);
6857         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6858         DRM_DEBUG_DRIVER("port num:%d\n", i);
6859
6860         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6861         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6862         for (i = 0; i < len; i++)
6863                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6864
6865         i = I915_READ(aud_cntrl_st2);
6866         i |= eldv;
6867         I915_WRITE(aud_cntrl_st2, i);
6868
6869 }
6870
6871 static void ironlake_write_eld(struct drm_connector *connector,
6872                                      struct drm_crtc *crtc)
6873 {
6874         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6875         uint8_t *eld = connector->eld;
6876         uint32_t eldv;
6877         uint32_t i;
6878         int len;
6879         int hdmiw_hdmiedid;
6880         int aud_config;
6881         int aud_cntl_st;
6882         int aud_cntrl_st2;
6883         int pipe = to_intel_crtc(crtc)->pipe;
6884
6885         if (HAS_PCH_IBX(connector->dev)) {
6886                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6887                 aud_config = IBX_AUD_CFG(pipe);
6888                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6889                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6890         } else {
6891                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6892                 aud_config = CPT_AUD_CFG(pipe);
6893                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6894                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6895         }
6896
6897         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6898
6899         i = I915_READ(aud_cntl_st);
6900         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6901         if (!i) {
6902                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6903                 /* operate blindly on all ports */
6904                 eldv = IBX_ELD_VALIDB;
6905                 eldv |= IBX_ELD_VALIDB << 4;
6906                 eldv |= IBX_ELD_VALIDB << 8;
6907         } else {
6908                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6909                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6910         }
6911
6912         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6913                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6914                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6915                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6916         } else
6917                 I915_WRITE(aud_config, 0);
6918
6919         if (intel_eld_uptodate(connector,
6920                                aud_cntrl_st2, eldv,
6921                                aud_cntl_st, IBX_ELD_ADDRESS,
6922                                hdmiw_hdmiedid))
6923                 return;
6924
6925         i = I915_READ(aud_cntrl_st2);
6926         i &= ~eldv;
6927         I915_WRITE(aud_cntrl_st2, i);
6928
6929         if (!eld[0])
6930                 return;
6931
6932         i = I915_READ(aud_cntl_st);
6933         i &= ~IBX_ELD_ADDRESS;
6934         I915_WRITE(aud_cntl_st, i);
6935
6936         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6937         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6938         for (i = 0; i < len; i++)
6939                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6940
6941         i = I915_READ(aud_cntrl_st2);
6942         i |= eldv;
6943         I915_WRITE(aud_cntrl_st2, i);
6944 }
6945
6946 void intel_write_eld(struct drm_encoder *encoder,
6947                      struct drm_display_mode *mode)
6948 {
6949         struct drm_crtc *crtc = encoder->crtc;
6950         struct drm_connector *connector;
6951         struct drm_device *dev = encoder->dev;
6952         struct drm_i915_private *dev_priv = dev->dev_private;
6953
6954         connector = drm_select_eld(encoder, mode);
6955         if (!connector)
6956                 return;
6957
6958         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6959                          connector->base.id,
6960                          drm_get_connector_name(connector),
6961                          connector->encoder->base.id,
6962                          drm_get_encoder_name(connector->encoder));
6963
6964         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6965
6966         if (dev_priv->display.write_eld)
6967                 dev_priv->display.write_eld(connector, crtc);
6968 }
6969
6970 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6971 {
6972         struct drm_device *dev = crtc->dev;
6973         struct drm_i915_private *dev_priv = dev->dev_private;
6974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6975         bool visible = base != 0;
6976         u32 cntl;
6977
6978         if (intel_crtc->cursor_visible == visible)
6979                 return;
6980
6981         cntl = I915_READ(_CURACNTR);
6982         if (visible) {
6983                 /* On these chipsets we can only modify the base whilst
6984                  * the cursor is disabled.
6985                  */
6986                 I915_WRITE(_CURABASE, base);
6987
6988                 cntl &= ~(CURSOR_FORMAT_MASK);
6989                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6990                 cntl |= CURSOR_ENABLE |
6991                         CURSOR_GAMMA_ENABLE |
6992                         CURSOR_FORMAT_ARGB;
6993         } else
6994                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6995         I915_WRITE(_CURACNTR, cntl);
6996
6997         intel_crtc->cursor_visible = visible;
6998 }
6999
7000 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7001 {
7002         struct drm_device *dev = crtc->dev;
7003         struct drm_i915_private *dev_priv = dev->dev_private;
7004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7005         int pipe = intel_crtc->pipe;
7006         bool visible = base != 0;
7007
7008         if (intel_crtc->cursor_visible != visible) {
7009                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7010                 if (base) {
7011                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7012                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7013                         cntl |= pipe << 28; /* Connect to correct pipe */
7014                 } else {
7015                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7016                         cntl |= CURSOR_MODE_DISABLE;
7017                 }
7018                 I915_WRITE(CURCNTR(pipe), cntl);
7019
7020                 intel_crtc->cursor_visible = visible;
7021         }
7022         /* and commit changes on next vblank */
7023         I915_WRITE(CURBASE(pipe), base);
7024 }
7025
7026 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7027 {
7028         struct drm_device *dev = crtc->dev;
7029         struct drm_i915_private *dev_priv = dev->dev_private;
7030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7031         int pipe = intel_crtc->pipe;
7032         bool visible = base != 0;
7033
7034         if (intel_crtc->cursor_visible != visible) {
7035                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7036                 if (base) {
7037                         cntl &= ~CURSOR_MODE;
7038                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7039                 } else {
7040                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7041                         cntl |= CURSOR_MODE_DISABLE;
7042                 }
7043                 if (IS_HASWELL(dev)) {
7044                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7045                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7046                 }
7047                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7048
7049                 intel_crtc->cursor_visible = visible;
7050         }
7051         /* and commit changes on next vblank */
7052         I915_WRITE(CURBASE_IVB(pipe), base);
7053 }
7054
7055 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7056 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7057                                      bool on)
7058 {
7059         struct drm_device *dev = crtc->dev;
7060         struct drm_i915_private *dev_priv = dev->dev_private;
7061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7062         int pipe = intel_crtc->pipe;
7063         int x = intel_crtc->cursor_x;
7064         int y = intel_crtc->cursor_y;
7065         u32 base = 0, pos = 0;
7066         bool visible;
7067
7068         if (on)
7069                 base = intel_crtc->cursor_addr;
7070
7071         if (x >= intel_crtc->config.pipe_src_w)
7072                 base = 0;
7073
7074         if (y >= intel_crtc->config.pipe_src_h)
7075                 base = 0;
7076
7077         if (x < 0) {
7078                 if (x + intel_crtc->cursor_width <= 0)
7079                         base = 0;
7080
7081                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7082                 x = -x;
7083         }
7084         pos |= x << CURSOR_X_SHIFT;
7085
7086         if (y < 0) {
7087                 if (y + intel_crtc->cursor_height <= 0)
7088                         base = 0;
7089
7090                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7091                 y = -y;
7092         }
7093         pos |= y << CURSOR_Y_SHIFT;
7094
7095         visible = base != 0;
7096         if (!visible && !intel_crtc->cursor_visible)
7097                 return;
7098
7099         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7100                 I915_WRITE(CURPOS_IVB(pipe), pos);
7101                 ivb_update_cursor(crtc, base);
7102         } else {
7103                 I915_WRITE(CURPOS(pipe), pos);
7104                 if (IS_845G(dev) || IS_I865G(dev))
7105                         i845_update_cursor(crtc, base);
7106                 else
7107                         i9xx_update_cursor(crtc, base);
7108         }
7109 }
7110
7111 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7112                                  struct drm_file *file,
7113                                  uint32_t handle,
7114                                  uint32_t width, uint32_t height)
7115 {
7116         struct drm_device *dev = crtc->dev;
7117         struct drm_i915_private *dev_priv = dev->dev_private;
7118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7119         struct drm_i915_gem_object *obj;
7120         uint32_t addr;
7121         int ret;
7122
7123         /* if we want to turn off the cursor ignore width and height */
7124         if (!handle) {
7125                 DRM_DEBUG_KMS("cursor off\n");
7126                 addr = 0;
7127                 obj = NULL;
7128                 mutex_lock(&dev->struct_mutex);
7129                 goto finish;
7130         }
7131
7132         /* Currently we only support 64x64 cursors */
7133         if (width != 64 || height != 64) {
7134                 DRM_ERROR("we currently only support 64x64 cursors\n");
7135                 return -EINVAL;
7136         }
7137
7138         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7139         if (&obj->base == NULL)
7140                 return -ENOENT;
7141
7142         if (obj->base.size < width * height * 4) {
7143                 DRM_ERROR("buffer is to small\n");
7144                 ret = -ENOMEM;
7145                 goto fail;
7146         }
7147
7148         /* we only need to pin inside GTT if cursor is non-phy */
7149         mutex_lock(&dev->struct_mutex);
7150         if (!dev_priv->info->cursor_needs_physical) {
7151                 unsigned alignment;
7152
7153                 if (obj->tiling_mode) {
7154                         DRM_ERROR("cursor cannot be tiled\n");
7155                         ret = -EINVAL;
7156                         goto fail_locked;
7157                 }
7158
7159                 /* Note that the w/a also requires 2 PTE of padding following
7160                  * the bo. We currently fill all unused PTE with the shadow
7161                  * page and so we should always have valid PTE following the
7162                  * cursor preventing the VT-d warning.
7163                  */
7164                 alignment = 0;
7165                 if (need_vtd_wa(dev))
7166                         alignment = 64*1024;
7167
7168                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7169                 if (ret) {
7170                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7171                         goto fail_locked;
7172                 }
7173
7174                 ret = i915_gem_object_put_fence(obj);
7175                 if (ret) {
7176                         DRM_ERROR("failed to release fence for cursor");
7177                         goto fail_unpin;
7178                 }
7179
7180                 addr = i915_gem_obj_ggtt_offset(obj);
7181         } else {
7182                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7183                 ret = i915_gem_attach_phys_object(dev, obj,
7184                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7185                                                   align);
7186                 if (ret) {
7187                         DRM_ERROR("failed to attach phys object\n");
7188                         goto fail_locked;
7189                 }
7190                 addr = obj->phys_obj->handle->busaddr;
7191         }
7192
7193         if (IS_GEN2(dev))
7194                 I915_WRITE(CURSIZE, (height << 12) | width);
7195
7196  finish:
7197         if (intel_crtc->cursor_bo) {
7198                 if (dev_priv->info->cursor_needs_physical) {
7199                         if (intel_crtc->cursor_bo != obj)
7200                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7201                 } else
7202                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7203                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7204         }
7205
7206         mutex_unlock(&dev->struct_mutex);
7207
7208         intel_crtc->cursor_addr = addr;
7209         intel_crtc->cursor_bo = obj;
7210         intel_crtc->cursor_width = width;
7211         intel_crtc->cursor_height = height;
7212
7213         if (intel_crtc->active)
7214                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7215
7216         return 0;
7217 fail_unpin:
7218         i915_gem_object_unpin_from_display_plane(obj);
7219 fail_locked:
7220         mutex_unlock(&dev->struct_mutex);
7221 fail:
7222         drm_gem_object_unreference_unlocked(&obj->base);
7223         return ret;
7224 }
7225
7226 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7227 {
7228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7229
7230         intel_crtc->cursor_x = x;
7231         intel_crtc->cursor_y = y;
7232
7233         if (intel_crtc->active)
7234                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7235
7236         return 0;
7237 }
7238
7239 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7240                                  u16 *blue, uint32_t start, uint32_t size)
7241 {
7242         int end = (start + size > 256) ? 256 : start + size, i;
7243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7244
7245         for (i = start; i < end; i++) {
7246                 intel_crtc->lut_r[i] = red[i] >> 8;
7247                 intel_crtc->lut_g[i] = green[i] >> 8;
7248                 intel_crtc->lut_b[i] = blue[i] >> 8;
7249         }
7250
7251         intel_crtc_load_lut(crtc);
7252 }
7253
7254 /* VESA 640x480x72Hz mode to set on the pipe */
7255 static struct drm_display_mode load_detect_mode = {
7256         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7257                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7258 };
7259
7260 static struct drm_framebuffer *
7261 intel_framebuffer_create(struct drm_device *dev,
7262                          struct drm_mode_fb_cmd2 *mode_cmd,
7263                          struct drm_i915_gem_object *obj)
7264 {
7265         struct intel_framebuffer *intel_fb;
7266         int ret;
7267
7268         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7269         if (!intel_fb) {
7270                 drm_gem_object_unreference_unlocked(&obj->base);
7271                 return ERR_PTR(-ENOMEM);
7272         }
7273
7274         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7275         if (ret) {
7276                 drm_gem_object_unreference_unlocked(&obj->base);
7277                 kfree(intel_fb);
7278                 return ERR_PTR(ret);
7279         }
7280
7281         return &intel_fb->base;
7282 }
7283
7284 static u32
7285 intel_framebuffer_pitch_for_width(int width, int bpp)
7286 {
7287         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7288         return ALIGN(pitch, 64);
7289 }
7290
7291 static u32
7292 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7293 {
7294         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7295         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7296 }
7297
7298 static struct drm_framebuffer *
7299 intel_framebuffer_create_for_mode(struct drm_device *dev,
7300                                   struct drm_display_mode *mode,
7301                                   int depth, int bpp)
7302 {
7303         struct drm_i915_gem_object *obj;
7304         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7305
7306         obj = i915_gem_alloc_object(dev,
7307                                     intel_framebuffer_size_for_mode(mode, bpp));
7308         if (obj == NULL)
7309                 return ERR_PTR(-ENOMEM);
7310
7311         mode_cmd.width = mode->hdisplay;
7312         mode_cmd.height = mode->vdisplay;
7313         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7314                                                                 bpp);
7315         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7316
7317         return intel_framebuffer_create(dev, &mode_cmd, obj);
7318 }
7319
7320 static struct drm_framebuffer *
7321 mode_fits_in_fbdev(struct drm_device *dev,
7322                    struct drm_display_mode *mode)
7323 {
7324         struct drm_i915_private *dev_priv = dev->dev_private;
7325         struct drm_i915_gem_object *obj;
7326         struct drm_framebuffer *fb;
7327
7328         if (dev_priv->fbdev == NULL)
7329                 return NULL;
7330
7331         obj = dev_priv->fbdev->ifb.obj;
7332         if (obj == NULL)
7333                 return NULL;
7334
7335         fb = &dev_priv->fbdev->ifb.base;
7336         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7337                                                                fb->bits_per_pixel))
7338                 return NULL;
7339
7340         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7341                 return NULL;
7342
7343         return fb;
7344 }
7345
7346 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7347                                 struct drm_display_mode *mode,
7348                                 struct intel_load_detect_pipe *old)
7349 {
7350         struct intel_crtc *intel_crtc;
7351         struct intel_encoder *intel_encoder =
7352                 intel_attached_encoder(connector);
7353         struct drm_crtc *possible_crtc;
7354         struct drm_encoder *encoder = &intel_encoder->base;
7355         struct drm_crtc *crtc = NULL;
7356         struct drm_device *dev = encoder->dev;
7357         struct drm_framebuffer *fb;
7358         int i = -1;
7359
7360         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7361                       connector->base.id, drm_get_connector_name(connector),
7362                       encoder->base.id, drm_get_encoder_name(encoder));
7363
7364         /*
7365          * Algorithm gets a little messy:
7366          *
7367          *   - if the connector already has an assigned crtc, use it (but make
7368          *     sure it's on first)
7369          *
7370          *   - try to find the first unused crtc that can drive this connector,
7371          *     and use that if we find one
7372          */
7373
7374         /* See if we already have a CRTC for this connector */
7375         if (encoder->crtc) {
7376                 crtc = encoder->crtc;
7377
7378                 mutex_lock(&crtc->mutex);
7379
7380                 old->dpms_mode = connector->dpms;
7381                 old->load_detect_temp = false;
7382
7383                 /* Make sure the crtc and connector are running */
7384                 if (connector->dpms != DRM_MODE_DPMS_ON)
7385                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7386
7387                 return true;
7388         }
7389
7390         /* Find an unused one (if possible) */
7391         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7392                 i++;
7393                 if (!(encoder->possible_crtcs & (1 << i)))
7394                         continue;
7395                 if (!possible_crtc->enabled) {
7396                         crtc = possible_crtc;
7397                         break;
7398                 }
7399         }
7400
7401         /*
7402          * If we didn't find an unused CRTC, don't use any.
7403          */
7404         if (!crtc) {
7405                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7406                 return false;
7407         }
7408
7409         mutex_lock(&crtc->mutex);
7410         intel_encoder->new_crtc = to_intel_crtc(crtc);
7411         to_intel_connector(connector)->new_encoder = intel_encoder;
7412
7413         intel_crtc = to_intel_crtc(crtc);
7414         old->dpms_mode = connector->dpms;
7415         old->load_detect_temp = true;
7416         old->release_fb = NULL;
7417
7418         if (!mode)
7419                 mode = &load_detect_mode;
7420
7421         /* We need a framebuffer large enough to accommodate all accesses
7422          * that the plane may generate whilst we perform load detection.
7423          * We can not rely on the fbcon either being present (we get called
7424          * during its initialisation to detect all boot displays, or it may
7425          * not even exist) or that it is large enough to satisfy the
7426          * requested mode.
7427          */
7428         fb = mode_fits_in_fbdev(dev, mode);
7429         if (fb == NULL) {
7430                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7431                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7432                 old->release_fb = fb;
7433         } else
7434                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7435         if (IS_ERR(fb)) {
7436                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7437                 mutex_unlock(&crtc->mutex);
7438                 return false;
7439         }
7440
7441         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7442                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7443                 if (old->release_fb)
7444                         old->release_fb->funcs->destroy(old->release_fb);
7445                 mutex_unlock(&crtc->mutex);
7446                 return false;
7447         }
7448
7449         /* let the connector get through one full cycle before testing */
7450         intel_wait_for_vblank(dev, intel_crtc->pipe);
7451         return true;
7452 }
7453
7454 void intel_release_load_detect_pipe(struct drm_connector *connector,
7455                                     struct intel_load_detect_pipe *old)
7456 {
7457         struct intel_encoder *intel_encoder =
7458                 intel_attached_encoder(connector);
7459         struct drm_encoder *encoder = &intel_encoder->base;
7460         struct drm_crtc *crtc = encoder->crtc;
7461
7462         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7463                       connector->base.id, drm_get_connector_name(connector),
7464                       encoder->base.id, drm_get_encoder_name(encoder));
7465
7466         if (old->load_detect_temp) {
7467                 to_intel_connector(connector)->new_encoder = NULL;
7468                 intel_encoder->new_crtc = NULL;
7469                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7470
7471                 if (old->release_fb) {
7472                         drm_framebuffer_unregister_private(old->release_fb);
7473                         drm_framebuffer_unreference(old->release_fb);
7474                 }
7475
7476                 mutex_unlock(&crtc->mutex);
7477                 return;
7478         }
7479
7480         /* Switch crtc and encoder back off if necessary */
7481         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7482                 connector->funcs->dpms(connector, old->dpms_mode);
7483
7484         mutex_unlock(&crtc->mutex);
7485 }
7486
7487 static int i9xx_pll_refclk(struct drm_device *dev,
7488                            const struct intel_crtc_config *pipe_config)
7489 {
7490         struct drm_i915_private *dev_priv = dev->dev_private;
7491         u32 dpll = pipe_config->dpll_hw_state.dpll;
7492
7493         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7494                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7495         else if (HAS_PCH_SPLIT(dev))
7496                 return 120000;
7497         else if (!IS_GEN2(dev))
7498                 return 96000;
7499         else
7500                 return 48000;
7501 }
7502
7503 /* Returns the clock of the currently programmed mode of the given pipe. */
7504 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7505                                 struct intel_crtc_config *pipe_config)
7506 {
7507         struct drm_device *dev = crtc->base.dev;
7508         struct drm_i915_private *dev_priv = dev->dev_private;
7509         int pipe = pipe_config->cpu_transcoder;
7510         u32 dpll = pipe_config->dpll_hw_state.dpll;
7511         u32 fp;
7512         intel_clock_t clock;
7513         int refclk = i9xx_pll_refclk(dev, pipe_config);
7514
7515         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7516                 fp = pipe_config->dpll_hw_state.fp0;
7517         else
7518                 fp = pipe_config->dpll_hw_state.fp1;
7519
7520         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7521         if (IS_PINEVIEW(dev)) {
7522                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7523                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7524         } else {
7525                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7526                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7527         }
7528
7529         if (!IS_GEN2(dev)) {
7530                 if (IS_PINEVIEW(dev))
7531                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7532                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7533                 else
7534                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7535                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7536
7537                 switch (dpll & DPLL_MODE_MASK) {
7538                 case DPLLB_MODE_DAC_SERIAL:
7539                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7540                                 5 : 10;
7541                         break;
7542                 case DPLLB_MODE_LVDS:
7543                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7544                                 7 : 14;
7545                         break;
7546                 default:
7547                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7548                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7549                         return;
7550                 }
7551
7552                 if (IS_PINEVIEW(dev))
7553                         pineview_clock(refclk, &clock);
7554                 else
7555                         i9xx_clock(refclk, &clock);
7556         } else {
7557                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7558
7559                 if (is_lvds) {
7560                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7561                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7562                         clock.p2 = 14;
7563                 } else {
7564                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7565                                 clock.p1 = 2;
7566                         else {
7567                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7568                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7569                         }
7570                         if (dpll & PLL_P2_DIVIDE_BY_4)
7571                                 clock.p2 = 4;
7572                         else
7573                                 clock.p2 = 2;
7574                 }
7575
7576                 i9xx_clock(refclk, &clock);
7577         }
7578
7579         /*
7580          * This value includes pixel_multiplier. We will use
7581          * port_clock to compute adjusted_mode.crtc_clock in the
7582          * encoder's get_config() function.
7583          */
7584         pipe_config->port_clock = clock.dot;
7585 }
7586
7587 int intel_dotclock_calculate(int link_freq,
7588                              const struct intel_link_m_n *m_n)
7589 {
7590         /*
7591          * The calculation for the data clock is:
7592          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7593          * But we want to avoid losing precison if possible, so:
7594          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7595          *
7596          * and the link clock is simpler:
7597          * link_clock = (m * link_clock) / n
7598          */
7599
7600         if (!m_n->link_n)
7601                 return 0;
7602
7603         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7604 }
7605
7606 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7607                                    struct intel_crtc_config *pipe_config)
7608 {
7609         struct drm_device *dev = crtc->base.dev;
7610
7611         /* read out port_clock from the DPLL */
7612         i9xx_crtc_clock_get(crtc, pipe_config);
7613
7614         /*
7615          * This value does not include pixel_multiplier.
7616          * We will check that port_clock and adjusted_mode.crtc_clock
7617          * agree once we know their relationship in the encoder's
7618          * get_config() function.
7619          */
7620         pipe_config->adjusted_mode.crtc_clock =
7621                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7622                                          &pipe_config->fdi_m_n);
7623 }
7624
7625 /** Returns the currently programmed mode of the given pipe. */
7626 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7627                                              struct drm_crtc *crtc)
7628 {
7629         struct drm_i915_private *dev_priv = dev->dev_private;
7630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7631         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7632         struct drm_display_mode *mode;
7633         struct intel_crtc_config pipe_config;
7634         int htot = I915_READ(HTOTAL(cpu_transcoder));
7635         int hsync = I915_READ(HSYNC(cpu_transcoder));
7636         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7637         int vsync = I915_READ(VSYNC(cpu_transcoder));
7638         enum pipe pipe = intel_crtc->pipe;
7639
7640         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7641         if (!mode)
7642                 return NULL;
7643
7644         /*
7645          * Construct a pipe_config sufficient for getting the clock info
7646          * back out of crtc_clock_get.
7647          *
7648          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7649          * to use a real value here instead.
7650          */
7651         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7652         pipe_config.pixel_multiplier = 1;
7653         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7654         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7655         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7656         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7657
7658         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7659         mode->hdisplay = (htot & 0xffff) + 1;
7660         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7661         mode->hsync_start = (hsync & 0xffff) + 1;
7662         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7663         mode->vdisplay = (vtot & 0xffff) + 1;
7664         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7665         mode->vsync_start = (vsync & 0xffff) + 1;
7666         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7667
7668         drm_mode_set_name(mode);
7669
7670         return mode;
7671 }
7672
7673 static void intel_increase_pllclock(struct drm_crtc *crtc)
7674 {
7675         struct drm_device *dev = crtc->dev;
7676         drm_i915_private_t *dev_priv = dev->dev_private;
7677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7678         int pipe = intel_crtc->pipe;
7679         int dpll_reg = DPLL(pipe);
7680         int dpll;
7681
7682         if (HAS_PCH_SPLIT(dev))
7683                 return;
7684
7685         if (!dev_priv->lvds_downclock_avail)
7686                 return;
7687
7688         dpll = I915_READ(dpll_reg);
7689         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7690                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7691
7692                 assert_panel_unlocked(dev_priv, pipe);
7693
7694                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7695                 I915_WRITE(dpll_reg, dpll);
7696                 intel_wait_for_vblank(dev, pipe);
7697
7698                 dpll = I915_READ(dpll_reg);
7699                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7700                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7701         }
7702 }
7703
7704 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7705 {
7706         struct drm_device *dev = crtc->dev;
7707         drm_i915_private_t *dev_priv = dev->dev_private;
7708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7709
7710         if (HAS_PCH_SPLIT(dev))
7711                 return;
7712
7713         if (!dev_priv->lvds_downclock_avail)
7714                 return;
7715
7716         /*
7717          * Since this is called by a timer, we should never get here in
7718          * the manual case.
7719          */
7720         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7721                 int pipe = intel_crtc->pipe;
7722                 int dpll_reg = DPLL(pipe);
7723                 int dpll;
7724
7725                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7726
7727                 assert_panel_unlocked(dev_priv, pipe);
7728
7729                 dpll = I915_READ(dpll_reg);
7730                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7731                 I915_WRITE(dpll_reg, dpll);
7732                 intel_wait_for_vblank(dev, pipe);
7733                 dpll = I915_READ(dpll_reg);
7734                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7735                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7736         }
7737
7738 }
7739
7740 void intel_mark_busy(struct drm_device *dev)
7741 {
7742         struct drm_i915_private *dev_priv = dev->dev_private;
7743
7744         hsw_package_c8_gpu_busy(dev_priv);
7745         i915_update_gfx_val(dev_priv);
7746 }
7747
7748 void intel_mark_idle(struct drm_device *dev)
7749 {
7750         struct drm_i915_private *dev_priv = dev->dev_private;
7751         struct drm_crtc *crtc;
7752
7753         hsw_package_c8_gpu_idle(dev_priv);
7754
7755         if (!i915_powersave)
7756                 return;
7757
7758         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7759                 if (!crtc->fb)
7760                         continue;
7761
7762                 intel_decrease_pllclock(crtc);
7763         }
7764
7765         if (dev_priv->info->gen >= 6)
7766                 gen6_rps_idle(dev->dev_private);
7767 }
7768
7769 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7770                         struct intel_ring_buffer *ring)
7771 {
7772         struct drm_device *dev = obj->base.dev;
7773         struct drm_crtc *crtc;
7774
7775         if (!i915_powersave)
7776                 return;
7777
7778         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7779                 if (!crtc->fb)
7780                         continue;
7781
7782                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7783                         continue;
7784
7785                 intel_increase_pllclock(crtc);
7786                 if (ring && intel_fbc_enabled(dev))
7787                         ring->fbc_dirty = true;
7788         }
7789 }
7790
7791 static void intel_crtc_destroy(struct drm_crtc *crtc)
7792 {
7793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7794         struct drm_device *dev = crtc->dev;
7795         struct intel_unpin_work *work;
7796         unsigned long flags;
7797
7798         spin_lock_irqsave(&dev->event_lock, flags);
7799         work = intel_crtc->unpin_work;
7800         intel_crtc->unpin_work = NULL;
7801         spin_unlock_irqrestore(&dev->event_lock, flags);
7802
7803         if (work) {
7804                 cancel_work_sync(&work->work);
7805                 kfree(work);
7806         }
7807
7808         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7809
7810         drm_crtc_cleanup(crtc);
7811
7812         kfree(intel_crtc);
7813 }
7814
7815 static void intel_unpin_work_fn(struct work_struct *__work)
7816 {
7817         struct intel_unpin_work *work =
7818                 container_of(__work, struct intel_unpin_work, work);
7819         struct drm_device *dev = work->crtc->dev;
7820
7821         mutex_lock(&dev->struct_mutex);
7822         intel_unpin_fb_obj(work->old_fb_obj);
7823         drm_gem_object_unreference(&work->pending_flip_obj->base);
7824         drm_gem_object_unreference(&work->old_fb_obj->base);
7825
7826         intel_update_fbc(dev);
7827         mutex_unlock(&dev->struct_mutex);
7828
7829         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7830         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7831
7832         kfree(work);
7833 }
7834
7835 static void do_intel_finish_page_flip(struct drm_device *dev,
7836                                       struct drm_crtc *crtc)
7837 {
7838         drm_i915_private_t *dev_priv = dev->dev_private;
7839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7840         struct intel_unpin_work *work;
7841         unsigned long flags;
7842
7843         /* Ignore early vblank irqs */
7844         if (intel_crtc == NULL)
7845                 return;
7846
7847         spin_lock_irqsave(&dev->event_lock, flags);
7848         work = intel_crtc->unpin_work;
7849
7850         /* Ensure we don't miss a work->pending update ... */
7851         smp_rmb();
7852
7853         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7854                 spin_unlock_irqrestore(&dev->event_lock, flags);
7855                 return;
7856         }
7857
7858         /* and that the unpin work is consistent wrt ->pending. */
7859         smp_rmb();
7860
7861         intel_crtc->unpin_work = NULL;
7862
7863         if (work->event)
7864                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7865
7866         drm_vblank_put(dev, intel_crtc->pipe);
7867
7868         spin_unlock_irqrestore(&dev->event_lock, flags);
7869
7870         wake_up_all(&dev_priv->pending_flip_queue);
7871
7872         queue_work(dev_priv->wq, &work->work);
7873
7874         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7875 }
7876
7877 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7878 {
7879         drm_i915_private_t *dev_priv = dev->dev_private;
7880         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7881
7882         do_intel_finish_page_flip(dev, crtc);
7883 }
7884
7885 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7886 {
7887         drm_i915_private_t *dev_priv = dev->dev_private;
7888         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7889
7890         do_intel_finish_page_flip(dev, crtc);
7891 }
7892
7893 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7894 {
7895         drm_i915_private_t *dev_priv = dev->dev_private;
7896         struct intel_crtc *intel_crtc =
7897                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7898         unsigned long flags;
7899
7900         /* NB: An MMIO update of the plane base pointer will also
7901          * generate a page-flip completion irq, i.e. every modeset
7902          * is also accompanied by a spurious intel_prepare_page_flip().
7903          */
7904         spin_lock_irqsave(&dev->event_lock, flags);
7905         if (intel_crtc->unpin_work)
7906                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7907         spin_unlock_irqrestore(&dev->event_lock, flags);
7908 }
7909
7910 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7911 {
7912         /* Ensure that the work item is consistent when activating it ... */
7913         smp_wmb();
7914         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7915         /* and that it is marked active as soon as the irq could fire. */
7916         smp_wmb();
7917 }
7918
7919 static int intel_gen2_queue_flip(struct drm_device *dev,
7920                                  struct drm_crtc *crtc,
7921                                  struct drm_framebuffer *fb,
7922                                  struct drm_i915_gem_object *obj,
7923                                  uint32_t flags)
7924 {
7925         struct drm_i915_private *dev_priv = dev->dev_private;
7926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7927         u32 flip_mask;
7928         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7929         int ret;
7930
7931         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7932         if (ret)
7933                 goto err;
7934
7935         ret = intel_ring_begin(ring, 6);
7936         if (ret)
7937                 goto err_unpin;
7938
7939         /* Can't queue multiple flips, so wait for the previous
7940          * one to finish before executing the next.
7941          */
7942         if (intel_crtc->plane)
7943                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7944         else
7945                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7946         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7947         intel_ring_emit(ring, MI_NOOP);
7948         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7949                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7950         intel_ring_emit(ring, fb->pitches[0]);
7951         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7952         intel_ring_emit(ring, 0); /* aux display base address, unused */
7953
7954         intel_mark_page_flip_active(intel_crtc);
7955         __intel_ring_advance(ring);
7956         return 0;
7957
7958 err_unpin:
7959         intel_unpin_fb_obj(obj);
7960 err:
7961         return ret;
7962 }
7963
7964 static int intel_gen3_queue_flip(struct drm_device *dev,
7965                                  struct drm_crtc *crtc,
7966                                  struct drm_framebuffer *fb,
7967                                  struct drm_i915_gem_object *obj,
7968                                  uint32_t flags)
7969 {
7970         struct drm_i915_private *dev_priv = dev->dev_private;
7971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7972         u32 flip_mask;
7973         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7974         int ret;
7975
7976         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7977         if (ret)
7978                 goto err;
7979
7980         ret = intel_ring_begin(ring, 6);
7981         if (ret)
7982                 goto err_unpin;
7983
7984         if (intel_crtc->plane)
7985                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7986         else
7987                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7988         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7989         intel_ring_emit(ring, MI_NOOP);
7990         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7991                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7992         intel_ring_emit(ring, fb->pitches[0]);
7993         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7994         intel_ring_emit(ring, MI_NOOP);
7995
7996         intel_mark_page_flip_active(intel_crtc);
7997         __intel_ring_advance(ring);
7998         return 0;
7999
8000 err_unpin:
8001         intel_unpin_fb_obj(obj);
8002 err:
8003         return ret;
8004 }
8005
8006 static int intel_gen4_queue_flip(struct drm_device *dev,
8007                                  struct drm_crtc *crtc,
8008                                  struct drm_framebuffer *fb,
8009                                  struct drm_i915_gem_object *obj,
8010                                  uint32_t flags)
8011 {
8012         struct drm_i915_private *dev_priv = dev->dev_private;
8013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8014         uint32_t pf, pipesrc;
8015         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8016         int ret;
8017
8018         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8019         if (ret)
8020                 goto err;
8021
8022         ret = intel_ring_begin(ring, 4);
8023         if (ret)
8024                 goto err_unpin;
8025
8026         /* i965+ uses the linear or tiled offsets from the
8027          * Display Registers (which do not change across a page-flip)
8028          * so we need only reprogram the base address.
8029          */
8030         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8031                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8032         intel_ring_emit(ring, fb->pitches[0]);
8033         intel_ring_emit(ring,
8034                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8035                         obj->tiling_mode);
8036
8037         /* XXX Enabling the panel-fitter across page-flip is so far
8038          * untested on non-native modes, so ignore it for now.
8039          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8040          */
8041         pf = 0;
8042         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8043         intel_ring_emit(ring, pf | pipesrc);
8044
8045         intel_mark_page_flip_active(intel_crtc);
8046         __intel_ring_advance(ring);
8047         return 0;
8048
8049 err_unpin:
8050         intel_unpin_fb_obj(obj);
8051 err:
8052         return ret;
8053 }
8054
8055 static int intel_gen6_queue_flip(struct drm_device *dev,
8056                                  struct drm_crtc *crtc,
8057                                  struct drm_framebuffer *fb,
8058                                  struct drm_i915_gem_object *obj,
8059                                  uint32_t flags)
8060 {
8061         struct drm_i915_private *dev_priv = dev->dev_private;
8062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8063         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8064         uint32_t pf, pipesrc;
8065         int ret;
8066
8067         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8068         if (ret)
8069                 goto err;
8070
8071         ret = intel_ring_begin(ring, 4);
8072         if (ret)
8073                 goto err_unpin;
8074
8075         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8076                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8077         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8078         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8079
8080         /* Contrary to the suggestions in the documentation,
8081          * "Enable Panel Fitter" does not seem to be required when page
8082          * flipping with a non-native mode, and worse causes a normal
8083          * modeset to fail.
8084          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8085          */
8086         pf = 0;
8087         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8088         intel_ring_emit(ring, pf | pipesrc);
8089
8090         intel_mark_page_flip_active(intel_crtc);
8091         __intel_ring_advance(ring);
8092         return 0;
8093
8094 err_unpin:
8095         intel_unpin_fb_obj(obj);
8096 err:
8097         return ret;
8098 }
8099
8100 static int intel_gen7_queue_flip(struct drm_device *dev,
8101                                  struct drm_crtc *crtc,
8102                                  struct drm_framebuffer *fb,
8103                                  struct drm_i915_gem_object *obj,
8104                                  uint32_t flags)
8105 {
8106         struct drm_i915_private *dev_priv = dev->dev_private;
8107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8108         struct intel_ring_buffer *ring;
8109         uint32_t plane_bit = 0;
8110         int len, ret;
8111
8112         ring = obj->ring;
8113         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8114                 ring = &dev_priv->ring[BCS];
8115
8116         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8117         if (ret)
8118                 goto err;
8119
8120         switch(intel_crtc->plane) {
8121         case PLANE_A:
8122                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8123                 break;
8124         case PLANE_B:
8125                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8126                 break;
8127         case PLANE_C:
8128                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8129                 break;
8130         default:
8131                 WARN_ONCE(1, "unknown plane in flip command\n");
8132                 ret = -ENODEV;
8133                 goto err_unpin;
8134         }
8135
8136         len = 4;
8137         if (ring->id == RCS)
8138                 len += 6;
8139
8140         ret = intel_ring_begin(ring, len);
8141         if (ret)
8142                 goto err_unpin;
8143
8144         /* Unmask the flip-done completion message. Note that the bspec says that
8145          * we should do this for both the BCS and RCS, and that we must not unmask
8146          * more than one flip event at any time (or ensure that one flip message
8147          * can be sent by waiting for flip-done prior to queueing new flips).
8148          * Experimentation says that BCS works despite DERRMR masking all
8149          * flip-done completion events and that unmasking all planes at once
8150          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8151          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8152          */
8153         if (ring->id == RCS) {
8154                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8155                 intel_ring_emit(ring, DERRMR);
8156                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8157                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8158                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8159                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8160                 intel_ring_emit(ring, DERRMR);
8161                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8162         }
8163
8164         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8165         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8166         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8167         intel_ring_emit(ring, (MI_NOOP));
8168
8169         intel_mark_page_flip_active(intel_crtc);
8170         __intel_ring_advance(ring);
8171         return 0;
8172
8173 err_unpin:
8174         intel_unpin_fb_obj(obj);
8175 err:
8176         return ret;
8177 }
8178
8179 static int intel_default_queue_flip(struct drm_device *dev,
8180                                     struct drm_crtc *crtc,
8181                                     struct drm_framebuffer *fb,
8182                                     struct drm_i915_gem_object *obj,
8183                                     uint32_t flags)
8184 {
8185         return -ENODEV;
8186 }
8187
8188 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8189                                 struct drm_framebuffer *fb,
8190                                 struct drm_pending_vblank_event *event,
8191                                 uint32_t page_flip_flags)
8192 {
8193         struct drm_device *dev = crtc->dev;
8194         struct drm_i915_private *dev_priv = dev->dev_private;
8195         struct drm_framebuffer *old_fb = crtc->fb;
8196         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8198         struct intel_unpin_work *work;
8199         unsigned long flags;
8200         int ret;
8201
8202         /* Can't change pixel format via MI display flips. */
8203         if (fb->pixel_format != crtc->fb->pixel_format)
8204                 return -EINVAL;
8205
8206         /*
8207          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8208          * Note that pitch changes could also affect these register.
8209          */
8210         if (INTEL_INFO(dev)->gen > 3 &&
8211             (fb->offsets[0] != crtc->fb->offsets[0] ||
8212              fb->pitches[0] != crtc->fb->pitches[0]))
8213                 return -EINVAL;
8214
8215         work = kzalloc(sizeof(*work), GFP_KERNEL);
8216         if (work == NULL)
8217                 return -ENOMEM;
8218
8219         work->event = event;
8220         work->crtc = crtc;
8221         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8222         INIT_WORK(&work->work, intel_unpin_work_fn);
8223
8224         ret = drm_vblank_get(dev, intel_crtc->pipe);
8225         if (ret)
8226                 goto free_work;
8227
8228         /* We borrow the event spin lock for protecting unpin_work */
8229         spin_lock_irqsave(&dev->event_lock, flags);
8230         if (intel_crtc->unpin_work) {
8231                 spin_unlock_irqrestore(&dev->event_lock, flags);
8232                 kfree(work);
8233                 drm_vblank_put(dev, intel_crtc->pipe);
8234
8235                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8236                 return -EBUSY;
8237         }
8238         intel_crtc->unpin_work = work;
8239         spin_unlock_irqrestore(&dev->event_lock, flags);
8240
8241         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8242                 flush_workqueue(dev_priv->wq);
8243
8244         ret = i915_mutex_lock_interruptible(dev);
8245         if (ret)
8246                 goto cleanup;
8247
8248         /* Reference the objects for the scheduled work. */
8249         drm_gem_object_reference(&work->old_fb_obj->base);
8250         drm_gem_object_reference(&obj->base);
8251
8252         crtc->fb = fb;
8253
8254         work->pending_flip_obj = obj;
8255
8256         work->enable_stall_check = true;
8257
8258         atomic_inc(&intel_crtc->unpin_work_count);
8259         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8260
8261         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8262         if (ret)
8263                 goto cleanup_pending;
8264
8265         intel_disable_fbc(dev);
8266         intel_mark_fb_busy(obj, NULL);
8267         mutex_unlock(&dev->struct_mutex);
8268
8269         trace_i915_flip_request(intel_crtc->plane, obj);
8270
8271         return 0;
8272
8273 cleanup_pending:
8274         atomic_dec(&intel_crtc->unpin_work_count);
8275         crtc->fb = old_fb;
8276         drm_gem_object_unreference(&work->old_fb_obj->base);
8277         drm_gem_object_unreference(&obj->base);
8278         mutex_unlock(&dev->struct_mutex);
8279
8280 cleanup:
8281         spin_lock_irqsave(&dev->event_lock, flags);
8282         intel_crtc->unpin_work = NULL;
8283         spin_unlock_irqrestore(&dev->event_lock, flags);
8284
8285         drm_vblank_put(dev, intel_crtc->pipe);
8286 free_work:
8287         kfree(work);
8288
8289         return ret;
8290 }
8291
8292 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8293         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8294         .load_lut = intel_crtc_load_lut,
8295 };
8296
8297 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8298                                   struct drm_crtc *crtc)
8299 {
8300         struct drm_device *dev;
8301         struct drm_crtc *tmp;
8302         int crtc_mask = 1;
8303
8304         WARN(!crtc, "checking null crtc?\n");
8305
8306         dev = crtc->dev;
8307
8308         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8309                 if (tmp == crtc)
8310                         break;
8311                 crtc_mask <<= 1;
8312         }
8313
8314         if (encoder->possible_crtcs & crtc_mask)
8315                 return true;
8316         return false;
8317 }
8318
8319 /**
8320  * intel_modeset_update_staged_output_state
8321  *
8322  * Updates the staged output configuration state, e.g. after we've read out the
8323  * current hw state.
8324  */
8325 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8326 {
8327         struct intel_encoder *encoder;
8328         struct intel_connector *connector;
8329
8330         list_for_each_entry(connector, &dev->mode_config.connector_list,
8331                             base.head) {
8332                 connector->new_encoder =
8333                         to_intel_encoder(connector->base.encoder);
8334         }
8335
8336         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8337                             base.head) {
8338                 encoder->new_crtc =
8339                         to_intel_crtc(encoder->base.crtc);
8340         }
8341 }
8342
8343 /**
8344  * intel_modeset_commit_output_state
8345  *
8346  * This function copies the stage display pipe configuration to the real one.
8347  */
8348 static void intel_modeset_commit_output_state(struct drm_device *dev)
8349 {
8350         struct intel_encoder *encoder;
8351         struct intel_connector *connector;
8352
8353         list_for_each_entry(connector, &dev->mode_config.connector_list,
8354                             base.head) {
8355                 connector->base.encoder = &connector->new_encoder->base;
8356         }
8357
8358         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8359                             base.head) {
8360                 encoder->base.crtc = &encoder->new_crtc->base;
8361         }
8362 }
8363
8364 static void
8365 connected_sink_compute_bpp(struct intel_connector * connector,
8366                            struct intel_crtc_config *pipe_config)
8367 {
8368         int bpp = pipe_config->pipe_bpp;
8369
8370         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8371                 connector->base.base.id,
8372                 drm_get_connector_name(&connector->base));
8373
8374         /* Don't use an invalid EDID bpc value */
8375         if (connector->base.display_info.bpc &&
8376             connector->base.display_info.bpc * 3 < bpp) {
8377                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8378                               bpp, connector->base.display_info.bpc*3);
8379                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8380         }
8381
8382         /* Clamp bpp to 8 on screens without EDID 1.4 */
8383         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8384                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8385                               bpp);
8386                 pipe_config->pipe_bpp = 24;
8387         }
8388 }
8389
8390 static int
8391 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8392                           struct drm_framebuffer *fb,
8393                           struct intel_crtc_config *pipe_config)
8394 {
8395         struct drm_device *dev = crtc->base.dev;
8396         struct intel_connector *connector;
8397         int bpp;
8398
8399         switch (fb->pixel_format) {
8400         case DRM_FORMAT_C8:
8401                 bpp = 8*3; /* since we go through a colormap */
8402                 break;
8403         case DRM_FORMAT_XRGB1555:
8404         case DRM_FORMAT_ARGB1555:
8405                 /* checked in intel_framebuffer_init already */
8406                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8407                         return -EINVAL;
8408         case DRM_FORMAT_RGB565:
8409                 bpp = 6*3; /* min is 18bpp */
8410                 break;
8411         case DRM_FORMAT_XBGR8888:
8412         case DRM_FORMAT_ABGR8888:
8413                 /* checked in intel_framebuffer_init already */
8414                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8415                         return -EINVAL;
8416         case DRM_FORMAT_XRGB8888:
8417         case DRM_FORMAT_ARGB8888:
8418                 bpp = 8*3;
8419                 break;
8420         case DRM_FORMAT_XRGB2101010:
8421         case DRM_FORMAT_ARGB2101010:
8422         case DRM_FORMAT_XBGR2101010:
8423         case DRM_FORMAT_ABGR2101010:
8424                 /* checked in intel_framebuffer_init already */
8425                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8426                         return -EINVAL;
8427                 bpp = 10*3;
8428                 break;
8429         /* TODO: gen4+ supports 16 bpc floating point, too. */
8430         default:
8431                 DRM_DEBUG_KMS("unsupported depth\n");
8432                 return -EINVAL;
8433         }
8434
8435         pipe_config->pipe_bpp = bpp;
8436
8437         /* Clamp display bpp to EDID value */
8438         list_for_each_entry(connector, &dev->mode_config.connector_list,
8439                             base.head) {
8440                 if (!connector->new_encoder ||
8441                     connector->new_encoder->new_crtc != crtc)
8442                         continue;
8443
8444                 connected_sink_compute_bpp(connector, pipe_config);
8445         }
8446
8447         return bpp;
8448 }
8449
8450 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8451 {
8452         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8453                         "type: 0x%x flags: 0x%x\n",
8454                 mode->crtc_clock,
8455                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8456                 mode->crtc_hsync_end, mode->crtc_htotal,
8457                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8458                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8459 }
8460
8461 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8462                                    struct intel_crtc_config *pipe_config,
8463                                    const char *context)
8464 {
8465         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8466                       context, pipe_name(crtc->pipe));
8467
8468         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8469         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8470                       pipe_config->pipe_bpp, pipe_config->dither);
8471         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8472                       pipe_config->has_pch_encoder,
8473                       pipe_config->fdi_lanes,
8474                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8475                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8476                       pipe_config->fdi_m_n.tu);
8477         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8478                       pipe_config->has_dp_encoder,
8479                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8480                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8481                       pipe_config->dp_m_n.tu);
8482         DRM_DEBUG_KMS("requested mode:\n");
8483         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8484         DRM_DEBUG_KMS("adjusted mode:\n");
8485         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8486         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8487         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8488         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8489                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8490         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8491                       pipe_config->gmch_pfit.control,
8492                       pipe_config->gmch_pfit.pgm_ratios,
8493                       pipe_config->gmch_pfit.lvds_border_bits);
8494         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8495                       pipe_config->pch_pfit.pos,
8496                       pipe_config->pch_pfit.size,
8497                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8498         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8499         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8500 }
8501
8502 static bool check_encoder_cloning(struct drm_crtc *crtc)
8503 {
8504         int num_encoders = 0;
8505         bool uncloneable_encoders = false;
8506         struct intel_encoder *encoder;
8507
8508         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8509                             base.head) {
8510                 if (&encoder->new_crtc->base != crtc)
8511                         continue;
8512
8513                 num_encoders++;
8514                 if (!encoder->cloneable)
8515                         uncloneable_encoders = true;
8516         }
8517
8518         return !(num_encoders > 1 && uncloneable_encoders);
8519 }
8520
8521 static struct intel_crtc_config *
8522 intel_modeset_pipe_config(struct drm_crtc *crtc,
8523                           struct drm_framebuffer *fb,
8524                           struct drm_display_mode *mode)
8525 {
8526         struct drm_device *dev = crtc->dev;
8527         struct intel_encoder *encoder;
8528         struct intel_crtc_config *pipe_config;
8529         int plane_bpp, ret = -EINVAL;
8530         bool retry = true;
8531
8532         if (!check_encoder_cloning(crtc)) {
8533                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8534                 return ERR_PTR(-EINVAL);
8535         }
8536
8537         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8538         if (!pipe_config)
8539                 return ERR_PTR(-ENOMEM);
8540
8541         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8542         drm_mode_copy(&pipe_config->requested_mode, mode);
8543
8544         pipe_config->cpu_transcoder =
8545                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8546         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8547
8548         /*
8549          * Sanitize sync polarity flags based on requested ones. If neither
8550          * positive or negative polarity is requested, treat this as meaning
8551          * negative polarity.
8552          */
8553         if (!(pipe_config->adjusted_mode.flags &
8554               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8555                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8556
8557         if (!(pipe_config->adjusted_mode.flags &
8558               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8559                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8560
8561         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8562          * plane pixel format and any sink constraints into account. Returns the
8563          * source plane bpp so that dithering can be selected on mismatches
8564          * after encoders and crtc also have had their say. */
8565         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8566                                               fb, pipe_config);
8567         if (plane_bpp < 0)
8568                 goto fail;
8569
8570         /*
8571          * Determine the real pipe dimensions. Note that stereo modes can
8572          * increase the actual pipe size due to the frame doubling and
8573          * insertion of additional space for blanks between the frame. This
8574          * is stored in the crtc timings. We use the requested mode to do this
8575          * computation to clearly distinguish it from the adjusted mode, which
8576          * can be changed by the connectors in the below retry loop.
8577          */
8578         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8579         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8580         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8581
8582 encoder_retry:
8583         /* Ensure the port clock defaults are reset when retrying. */
8584         pipe_config->port_clock = 0;
8585         pipe_config->pixel_multiplier = 1;
8586
8587         /* Fill in default crtc timings, allow encoders to overwrite them. */
8588         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8589
8590         /* Pass our mode to the connectors and the CRTC to give them a chance to
8591          * adjust it according to limitations or connector properties, and also
8592          * a chance to reject the mode entirely.
8593          */
8594         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8595                             base.head) {
8596
8597                 if (&encoder->new_crtc->base != crtc)
8598                         continue;
8599
8600                 if (!(encoder->compute_config(encoder, pipe_config))) {
8601                         DRM_DEBUG_KMS("Encoder config failure\n");
8602                         goto fail;
8603                 }
8604         }
8605
8606         /* Set default port clock if not overwritten by the encoder. Needs to be
8607          * done afterwards in case the encoder adjusts the mode. */
8608         if (!pipe_config->port_clock)
8609                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8610                         * pipe_config->pixel_multiplier;
8611
8612         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8613         if (ret < 0) {
8614                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8615                 goto fail;
8616         }
8617
8618         if (ret == RETRY) {
8619                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8620                         ret = -EINVAL;
8621                         goto fail;
8622                 }
8623
8624                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8625                 retry = false;
8626                 goto encoder_retry;
8627         }
8628
8629         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8630         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8631                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8632
8633         return pipe_config;
8634 fail:
8635         kfree(pipe_config);
8636         return ERR_PTR(ret);
8637 }
8638
8639 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8640  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8641 static void
8642 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8643                              unsigned *prepare_pipes, unsigned *disable_pipes)
8644 {
8645         struct intel_crtc *intel_crtc;
8646         struct drm_device *dev = crtc->dev;
8647         struct intel_encoder *encoder;
8648         struct intel_connector *connector;
8649         struct drm_crtc *tmp_crtc;
8650
8651         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8652
8653         /* Check which crtcs have changed outputs connected to them, these need
8654          * to be part of the prepare_pipes mask. We don't (yet) support global
8655          * modeset across multiple crtcs, so modeset_pipes will only have one
8656          * bit set at most. */
8657         list_for_each_entry(connector, &dev->mode_config.connector_list,
8658                             base.head) {
8659                 if (connector->base.encoder == &connector->new_encoder->base)
8660                         continue;
8661
8662                 if (connector->base.encoder) {
8663                         tmp_crtc = connector->base.encoder->crtc;
8664
8665                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8666                 }
8667
8668                 if (connector->new_encoder)
8669                         *prepare_pipes |=
8670                                 1 << connector->new_encoder->new_crtc->pipe;
8671         }
8672
8673         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8674                             base.head) {
8675                 if (encoder->base.crtc == &encoder->new_crtc->base)
8676                         continue;
8677
8678                 if (encoder->base.crtc) {
8679                         tmp_crtc = encoder->base.crtc;
8680
8681                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8682                 }
8683
8684                 if (encoder->new_crtc)
8685                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8686         }
8687
8688         /* Check for any pipes that will be fully disabled ... */
8689         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8690                             base.head) {
8691                 bool used = false;
8692
8693                 /* Don't try to disable disabled crtcs. */
8694                 if (!intel_crtc->base.enabled)
8695                         continue;
8696
8697                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8698                                     base.head) {
8699                         if (encoder->new_crtc == intel_crtc)
8700                                 used = true;
8701                 }
8702
8703                 if (!used)
8704                         *disable_pipes |= 1 << intel_crtc->pipe;
8705         }
8706
8707
8708         /* set_mode is also used to update properties on life display pipes. */
8709         intel_crtc = to_intel_crtc(crtc);
8710         if (crtc->enabled)
8711                 *prepare_pipes |= 1 << intel_crtc->pipe;
8712
8713         /*
8714          * For simplicity do a full modeset on any pipe where the output routing
8715          * changed. We could be more clever, but that would require us to be
8716          * more careful with calling the relevant encoder->mode_set functions.
8717          */
8718         if (*prepare_pipes)
8719                 *modeset_pipes = *prepare_pipes;
8720
8721         /* ... and mask these out. */
8722         *modeset_pipes &= ~(*disable_pipes);
8723         *prepare_pipes &= ~(*disable_pipes);
8724
8725         /*
8726          * HACK: We don't (yet) fully support global modesets. intel_set_config
8727          * obies this rule, but the modeset restore mode of
8728          * intel_modeset_setup_hw_state does not.
8729          */
8730         *modeset_pipes &= 1 << intel_crtc->pipe;
8731         *prepare_pipes &= 1 << intel_crtc->pipe;
8732
8733         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8734                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8735 }
8736
8737 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8738 {
8739         struct drm_encoder *encoder;
8740         struct drm_device *dev = crtc->dev;
8741
8742         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8743                 if (encoder->crtc == crtc)
8744                         return true;
8745
8746         return false;
8747 }
8748
8749 static void
8750 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8751 {
8752         struct intel_encoder *intel_encoder;
8753         struct intel_crtc *intel_crtc;
8754         struct drm_connector *connector;
8755
8756         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8757                             base.head) {
8758                 if (!intel_encoder->base.crtc)
8759                         continue;
8760
8761                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8762
8763                 if (prepare_pipes & (1 << intel_crtc->pipe))
8764                         intel_encoder->connectors_active = false;
8765         }
8766
8767         intel_modeset_commit_output_state(dev);
8768
8769         /* Update computed state. */
8770         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8771                             base.head) {
8772                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8773         }
8774
8775         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8776                 if (!connector->encoder || !connector->encoder->crtc)
8777                         continue;
8778
8779                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8780
8781                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8782                         struct drm_property *dpms_property =
8783                                 dev->mode_config.dpms_property;
8784
8785                         connector->dpms = DRM_MODE_DPMS_ON;
8786                         drm_object_property_set_value(&connector->base,
8787                                                          dpms_property,
8788                                                          DRM_MODE_DPMS_ON);
8789
8790                         intel_encoder = to_intel_encoder(connector->encoder);
8791                         intel_encoder->connectors_active = true;
8792                 }
8793         }
8794
8795 }
8796
8797 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8798 {
8799         int diff;
8800
8801         if (clock1 == clock2)
8802                 return true;
8803
8804         if (!clock1 || !clock2)
8805                 return false;
8806
8807         diff = abs(clock1 - clock2);
8808
8809         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8810                 return true;
8811
8812         return false;
8813 }
8814
8815 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8816         list_for_each_entry((intel_crtc), \
8817                             &(dev)->mode_config.crtc_list, \
8818                             base.head) \
8819                 if (mask & (1 <<(intel_crtc)->pipe))
8820
8821 static bool
8822 intel_pipe_config_compare(struct drm_device *dev,
8823                           struct intel_crtc_config *current_config,
8824                           struct intel_crtc_config *pipe_config)
8825 {
8826 #define PIPE_CONF_CHECK_X(name) \
8827         if (current_config->name != pipe_config->name) { \
8828                 DRM_ERROR("mismatch in " #name " " \
8829                           "(expected 0x%08x, found 0x%08x)\n", \
8830                           current_config->name, \
8831                           pipe_config->name); \
8832                 return false; \
8833         }
8834
8835 #define PIPE_CONF_CHECK_I(name) \
8836         if (current_config->name != pipe_config->name) { \
8837                 DRM_ERROR("mismatch in " #name " " \
8838                           "(expected %i, found %i)\n", \
8839                           current_config->name, \
8840                           pipe_config->name); \
8841                 return false; \
8842         }
8843
8844 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8845         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8846                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8847                           "(expected %i, found %i)\n", \
8848                           current_config->name & (mask), \
8849                           pipe_config->name & (mask)); \
8850                 return false; \
8851         }
8852
8853 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8854         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8855                 DRM_ERROR("mismatch in " #name " " \
8856                           "(expected %i, found %i)\n", \
8857                           current_config->name, \
8858                           pipe_config->name); \
8859                 return false; \
8860         }
8861
8862 #define PIPE_CONF_QUIRK(quirk)  \
8863         ((current_config->quirks | pipe_config->quirks) & (quirk))
8864
8865         PIPE_CONF_CHECK_I(cpu_transcoder);
8866
8867         PIPE_CONF_CHECK_I(has_pch_encoder);
8868         PIPE_CONF_CHECK_I(fdi_lanes);
8869         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8870         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8871         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8872         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8873         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8874
8875         PIPE_CONF_CHECK_I(has_dp_encoder);
8876         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8877         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8878         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8879         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8880         PIPE_CONF_CHECK_I(dp_m_n.tu);
8881
8882         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8883         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8884         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8885         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8886         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8887         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8888
8889         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8890         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8891         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8892         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8893         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8894         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8895
8896         PIPE_CONF_CHECK_I(pixel_multiplier);
8897
8898         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8899                               DRM_MODE_FLAG_INTERLACE);
8900
8901         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8902                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8903                                       DRM_MODE_FLAG_PHSYNC);
8904                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8905                                       DRM_MODE_FLAG_NHSYNC);
8906                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8907                                       DRM_MODE_FLAG_PVSYNC);
8908                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8909                                       DRM_MODE_FLAG_NVSYNC);
8910         }
8911
8912         PIPE_CONF_CHECK_I(pipe_src_w);
8913         PIPE_CONF_CHECK_I(pipe_src_h);
8914
8915         PIPE_CONF_CHECK_I(gmch_pfit.control);
8916         /* pfit ratios are autocomputed by the hw on gen4+ */
8917         if (INTEL_INFO(dev)->gen < 4)
8918                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8919         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8920         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8921         if (current_config->pch_pfit.enabled) {
8922                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8923                 PIPE_CONF_CHECK_I(pch_pfit.size);
8924         }
8925
8926         PIPE_CONF_CHECK_I(ips_enabled);
8927
8928         PIPE_CONF_CHECK_I(double_wide);
8929
8930         PIPE_CONF_CHECK_I(shared_dpll);
8931         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8932         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8933         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8934         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8935
8936         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8937                 PIPE_CONF_CHECK_I(pipe_bpp);
8938
8939         if (!IS_HASWELL(dev)) {
8940                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
8941                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8942         }
8943
8944 #undef PIPE_CONF_CHECK_X
8945 #undef PIPE_CONF_CHECK_I
8946 #undef PIPE_CONF_CHECK_FLAGS
8947 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8948 #undef PIPE_CONF_QUIRK
8949
8950         return true;
8951 }
8952
8953 static void
8954 check_connector_state(struct drm_device *dev)
8955 {
8956         struct intel_connector *connector;
8957
8958         list_for_each_entry(connector, &dev->mode_config.connector_list,
8959                             base.head) {
8960                 /* This also checks the encoder/connector hw state with the
8961                  * ->get_hw_state callbacks. */
8962                 intel_connector_check_state(connector);
8963
8964                 WARN(&connector->new_encoder->base != connector->base.encoder,
8965                      "connector's staged encoder doesn't match current encoder\n");
8966         }
8967 }
8968
8969 static void
8970 check_encoder_state(struct drm_device *dev)
8971 {
8972         struct intel_encoder *encoder;
8973         struct intel_connector *connector;
8974
8975         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8976                             base.head) {
8977                 bool enabled = false;
8978                 bool active = false;
8979                 enum pipe pipe, tracked_pipe;
8980
8981                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8982                               encoder->base.base.id,
8983                               drm_get_encoder_name(&encoder->base));
8984
8985                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8986                      "encoder's stage crtc doesn't match current crtc\n");
8987                 WARN(encoder->connectors_active && !encoder->base.crtc,
8988                      "encoder's active_connectors set, but no crtc\n");
8989
8990                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8991                                     base.head) {
8992                         if (connector->base.encoder != &encoder->base)
8993                                 continue;
8994                         enabled = true;
8995                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8996                                 active = true;
8997                 }
8998                 WARN(!!encoder->base.crtc != enabled,
8999                      "encoder's enabled state mismatch "
9000                      "(expected %i, found %i)\n",
9001                      !!encoder->base.crtc, enabled);
9002                 WARN(active && !encoder->base.crtc,
9003                      "active encoder with no crtc\n");
9004
9005                 WARN(encoder->connectors_active != active,
9006                      "encoder's computed active state doesn't match tracked active state "
9007                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9008
9009                 active = encoder->get_hw_state(encoder, &pipe);
9010                 WARN(active != encoder->connectors_active,
9011                      "encoder's hw state doesn't match sw tracking "
9012                      "(expected %i, found %i)\n",
9013                      encoder->connectors_active, active);
9014
9015                 if (!encoder->base.crtc)
9016                         continue;
9017
9018                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9019                 WARN(active && pipe != tracked_pipe,
9020                      "active encoder's pipe doesn't match"
9021                      "(expected %i, found %i)\n",
9022                      tracked_pipe, pipe);
9023
9024         }
9025 }
9026
9027 static void
9028 check_crtc_state(struct drm_device *dev)
9029 {
9030         drm_i915_private_t *dev_priv = dev->dev_private;
9031         struct intel_crtc *crtc;
9032         struct intel_encoder *encoder;
9033         struct intel_crtc_config pipe_config;
9034
9035         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9036                             base.head) {
9037                 bool enabled = false;
9038                 bool active = false;
9039
9040                 memset(&pipe_config, 0, sizeof(pipe_config));
9041
9042                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9043                               crtc->base.base.id);
9044
9045                 WARN(crtc->active && !crtc->base.enabled,
9046                      "active crtc, but not enabled in sw tracking\n");
9047
9048                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9049                                     base.head) {
9050                         if (encoder->base.crtc != &crtc->base)
9051                                 continue;
9052                         enabled = true;
9053                         if (encoder->connectors_active)
9054                                 active = true;
9055                 }
9056
9057                 WARN(active != crtc->active,
9058                      "crtc's computed active state doesn't match tracked active state "
9059                      "(expected %i, found %i)\n", active, crtc->active);
9060                 WARN(enabled != crtc->base.enabled,
9061                      "crtc's computed enabled state doesn't match tracked enabled state "
9062                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9063
9064                 active = dev_priv->display.get_pipe_config(crtc,
9065                                                            &pipe_config);
9066
9067                 /* hw state is inconsistent with the pipe A quirk */
9068                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9069                         active = crtc->active;
9070
9071                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9072                                     base.head) {
9073                         enum pipe pipe;
9074                         if (encoder->base.crtc != &crtc->base)
9075                                 continue;
9076                         if (encoder->get_config &&
9077                             encoder->get_hw_state(encoder, &pipe))
9078                                 encoder->get_config(encoder, &pipe_config);
9079                 }
9080
9081                 WARN(crtc->active != active,
9082                      "crtc active state doesn't match with hw state "
9083                      "(expected %i, found %i)\n", crtc->active, active);
9084
9085                 if (active &&
9086                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9087                         WARN(1, "pipe state doesn't match!\n");
9088                         intel_dump_pipe_config(crtc, &pipe_config,
9089                                                "[hw state]");
9090                         intel_dump_pipe_config(crtc, &crtc->config,
9091                                                "[sw state]");
9092                 }
9093         }
9094 }
9095
9096 static void
9097 check_shared_dpll_state(struct drm_device *dev)
9098 {
9099         drm_i915_private_t *dev_priv = dev->dev_private;
9100         struct intel_crtc *crtc;
9101         struct intel_dpll_hw_state dpll_hw_state;
9102         int i;
9103
9104         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9105                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9106                 int enabled_crtcs = 0, active_crtcs = 0;
9107                 bool active;
9108
9109                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9110
9111                 DRM_DEBUG_KMS("%s\n", pll->name);
9112
9113                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9114
9115                 WARN(pll->active > pll->refcount,
9116                      "more active pll users than references: %i vs %i\n",
9117                      pll->active, pll->refcount);
9118                 WARN(pll->active && !pll->on,
9119                      "pll in active use but not on in sw tracking\n");
9120                 WARN(pll->on && !pll->active,
9121                      "pll in on but not on in use in sw tracking\n");
9122                 WARN(pll->on != active,
9123                      "pll on state mismatch (expected %i, found %i)\n",
9124                      pll->on, active);
9125
9126                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9127                                     base.head) {
9128                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9129                                 enabled_crtcs++;
9130                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9131                                 active_crtcs++;
9132                 }
9133                 WARN(pll->active != active_crtcs,
9134                      "pll active crtcs mismatch (expected %i, found %i)\n",
9135                      pll->active, active_crtcs);
9136                 WARN(pll->refcount != enabled_crtcs,
9137                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9138                      pll->refcount, enabled_crtcs);
9139
9140                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9141                                        sizeof(dpll_hw_state)),
9142                      "pll hw state mismatch\n");
9143         }
9144 }
9145
9146 void
9147 intel_modeset_check_state(struct drm_device *dev)
9148 {
9149         check_connector_state(dev);
9150         check_encoder_state(dev);
9151         check_crtc_state(dev);
9152         check_shared_dpll_state(dev);
9153 }
9154
9155 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9156                                      int dotclock)
9157 {
9158         /*
9159          * FDI already provided one idea for the dotclock.
9160          * Yell if the encoder disagrees.
9161          */
9162         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9163              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9164              pipe_config->adjusted_mode.crtc_clock, dotclock);
9165 }
9166
9167 static int __intel_set_mode(struct drm_crtc *crtc,
9168                             struct drm_display_mode *mode,
9169                             int x, int y, struct drm_framebuffer *fb)
9170 {
9171         struct drm_device *dev = crtc->dev;
9172         drm_i915_private_t *dev_priv = dev->dev_private;
9173         struct drm_display_mode *saved_mode, *saved_hwmode;
9174         struct intel_crtc_config *pipe_config = NULL;
9175         struct intel_crtc *intel_crtc;
9176         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9177         int ret = 0;
9178
9179         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9180         if (!saved_mode)
9181                 return -ENOMEM;
9182         saved_hwmode = saved_mode + 1;
9183
9184         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9185                                      &prepare_pipes, &disable_pipes);
9186
9187         *saved_hwmode = crtc->hwmode;
9188         *saved_mode = crtc->mode;
9189
9190         /* Hack: Because we don't (yet) support global modeset on multiple
9191          * crtcs, we don't keep track of the new mode for more than one crtc.
9192          * Hence simply check whether any bit is set in modeset_pipes in all the
9193          * pieces of code that are not yet converted to deal with mutliple crtcs
9194          * changing their mode at the same time. */
9195         if (modeset_pipes) {
9196                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9197                 if (IS_ERR(pipe_config)) {
9198                         ret = PTR_ERR(pipe_config);
9199                         pipe_config = NULL;
9200
9201                         goto out;
9202                 }
9203                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9204                                        "[modeset]");
9205         }
9206
9207         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9208                 intel_crtc_disable(&intel_crtc->base);
9209
9210         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9211                 if (intel_crtc->base.enabled)
9212                         dev_priv->display.crtc_disable(&intel_crtc->base);
9213         }
9214
9215         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9216          * to set it here already despite that we pass it down the callchain.
9217          */
9218         if (modeset_pipes) {
9219                 crtc->mode = *mode;
9220                 /* mode_set/enable/disable functions rely on a correct pipe
9221                  * config. */
9222                 to_intel_crtc(crtc)->config = *pipe_config;
9223         }
9224
9225         /* Only after disabling all output pipelines that will be changed can we
9226          * update the the output configuration. */
9227         intel_modeset_update_state(dev, prepare_pipes);
9228
9229         if (dev_priv->display.modeset_global_resources)
9230                 dev_priv->display.modeset_global_resources(dev);
9231
9232         /* Set up the DPLL and any encoders state that needs to adjust or depend
9233          * on the DPLL.
9234          */
9235         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9236                 ret = intel_crtc_mode_set(&intel_crtc->base,
9237                                           x, y, fb);
9238                 if (ret)
9239                         goto done;
9240         }
9241
9242         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9243         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9244                 dev_priv->display.crtc_enable(&intel_crtc->base);
9245
9246         if (modeset_pipes) {
9247                 /* Store real post-adjustment hardware mode. */
9248                 crtc->hwmode = pipe_config->adjusted_mode;
9249
9250                 /* Calculate and store various constants which
9251                  * are later needed by vblank and swap-completion
9252                  * timestamping. They are derived from true hwmode.
9253                  */
9254                 drm_calc_timestamping_constants(crtc);
9255         }
9256
9257         /* FIXME: add subpixel order */
9258 done:
9259         if (ret && crtc->enabled) {
9260                 crtc->hwmode = *saved_hwmode;
9261                 crtc->mode = *saved_mode;
9262         }
9263
9264 out:
9265         kfree(pipe_config);
9266         kfree(saved_mode);
9267         return ret;
9268 }
9269
9270 static int intel_set_mode(struct drm_crtc *crtc,
9271                           struct drm_display_mode *mode,
9272                           int x, int y, struct drm_framebuffer *fb)
9273 {
9274         int ret;
9275
9276         ret = __intel_set_mode(crtc, mode, x, y, fb);
9277
9278         if (ret == 0)
9279                 intel_modeset_check_state(crtc->dev);
9280
9281         return ret;
9282 }
9283
9284 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9285 {
9286         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9287 }
9288
9289 #undef for_each_intel_crtc_masked
9290
9291 static void intel_set_config_free(struct intel_set_config *config)
9292 {
9293         if (!config)
9294                 return;
9295
9296         kfree(config->save_connector_encoders);
9297         kfree(config->save_encoder_crtcs);
9298         kfree(config);
9299 }
9300
9301 static int intel_set_config_save_state(struct drm_device *dev,
9302                                        struct intel_set_config *config)
9303 {
9304         struct drm_encoder *encoder;
9305         struct drm_connector *connector;
9306         int count;
9307
9308         config->save_encoder_crtcs =
9309                 kcalloc(dev->mode_config.num_encoder,
9310                         sizeof(struct drm_crtc *), GFP_KERNEL);
9311         if (!config->save_encoder_crtcs)
9312                 return -ENOMEM;
9313
9314         config->save_connector_encoders =
9315                 kcalloc(dev->mode_config.num_connector,
9316                         sizeof(struct drm_encoder *), GFP_KERNEL);
9317         if (!config->save_connector_encoders)
9318                 return -ENOMEM;
9319
9320         /* Copy data. Note that driver private data is not affected.
9321          * Should anything bad happen only the expected state is
9322          * restored, not the drivers personal bookkeeping.
9323          */
9324         count = 0;
9325         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9326                 config->save_encoder_crtcs[count++] = encoder->crtc;
9327         }
9328
9329         count = 0;
9330         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9331                 config->save_connector_encoders[count++] = connector->encoder;
9332         }
9333
9334         return 0;
9335 }
9336
9337 static void intel_set_config_restore_state(struct drm_device *dev,
9338                                            struct intel_set_config *config)
9339 {
9340         struct intel_encoder *encoder;
9341         struct intel_connector *connector;
9342         int count;
9343
9344         count = 0;
9345         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9346                 encoder->new_crtc =
9347                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9348         }
9349
9350         count = 0;
9351         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9352                 connector->new_encoder =
9353                         to_intel_encoder(config->save_connector_encoders[count++]);
9354         }
9355 }
9356
9357 static bool
9358 is_crtc_connector_off(struct drm_mode_set *set)
9359 {
9360         int i;
9361
9362         if (set->num_connectors == 0)
9363                 return false;
9364
9365         if (WARN_ON(set->connectors == NULL))
9366                 return false;
9367
9368         for (i = 0; i < set->num_connectors; i++)
9369                 if (set->connectors[i]->encoder &&
9370                     set->connectors[i]->encoder->crtc == set->crtc &&
9371                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9372                         return true;
9373
9374         return false;
9375 }
9376
9377 static void
9378 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9379                                       struct intel_set_config *config)
9380 {
9381
9382         /* We should be able to check here if the fb has the same properties
9383          * and then just flip_or_move it */
9384         if (is_crtc_connector_off(set)) {
9385                 config->mode_changed = true;
9386         } else if (set->crtc->fb != set->fb) {
9387                 /* If we have no fb then treat it as a full mode set */
9388                 if (set->crtc->fb == NULL) {
9389                         struct intel_crtc *intel_crtc =
9390                                 to_intel_crtc(set->crtc);
9391
9392                         if (intel_crtc->active && i915_fastboot) {
9393                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9394                                 config->fb_changed = true;
9395                         } else {
9396                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9397                                 config->mode_changed = true;
9398                         }
9399                 } else if (set->fb == NULL) {
9400                         config->mode_changed = true;
9401                 } else if (set->fb->pixel_format !=
9402                            set->crtc->fb->pixel_format) {
9403                         config->mode_changed = true;
9404                 } else {
9405                         config->fb_changed = true;
9406                 }
9407         }
9408
9409         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9410                 config->fb_changed = true;
9411
9412         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9413                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9414                 drm_mode_debug_printmodeline(&set->crtc->mode);
9415                 drm_mode_debug_printmodeline(set->mode);
9416                 config->mode_changed = true;
9417         }
9418
9419         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9420                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9421 }
9422
9423 static int
9424 intel_modeset_stage_output_state(struct drm_device *dev,
9425                                  struct drm_mode_set *set,
9426                                  struct intel_set_config *config)
9427 {
9428         struct drm_crtc *new_crtc;
9429         struct intel_connector *connector;
9430         struct intel_encoder *encoder;
9431         int ro;
9432
9433         /* The upper layers ensure that we either disable a crtc or have a list
9434          * of connectors. For paranoia, double-check this. */
9435         WARN_ON(!set->fb && (set->num_connectors != 0));
9436         WARN_ON(set->fb && (set->num_connectors == 0));
9437
9438         list_for_each_entry(connector, &dev->mode_config.connector_list,
9439                             base.head) {
9440                 /* Otherwise traverse passed in connector list and get encoders
9441                  * for them. */
9442                 for (ro = 0; ro < set->num_connectors; ro++) {
9443                         if (set->connectors[ro] == &connector->base) {
9444                                 connector->new_encoder = connector->encoder;
9445                                 break;
9446                         }
9447                 }
9448
9449                 /* If we disable the crtc, disable all its connectors. Also, if
9450                  * the connector is on the changing crtc but not on the new
9451                  * connector list, disable it. */
9452                 if ((!set->fb || ro == set->num_connectors) &&
9453                     connector->base.encoder &&
9454                     connector->base.encoder->crtc == set->crtc) {
9455                         connector->new_encoder = NULL;
9456
9457                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9458                                 connector->base.base.id,
9459                                 drm_get_connector_name(&connector->base));
9460                 }
9461
9462
9463                 if (&connector->new_encoder->base != connector->base.encoder) {
9464                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9465                         config->mode_changed = true;
9466                 }
9467         }
9468         /* connector->new_encoder is now updated for all connectors. */
9469
9470         /* Update crtc of enabled connectors. */
9471         list_for_each_entry(connector, &dev->mode_config.connector_list,
9472                             base.head) {
9473                 if (!connector->new_encoder)
9474                         continue;
9475
9476                 new_crtc = connector->new_encoder->base.crtc;
9477
9478                 for (ro = 0; ro < set->num_connectors; ro++) {
9479                         if (set->connectors[ro] == &connector->base)
9480                                 new_crtc = set->crtc;
9481                 }
9482
9483                 /* Make sure the new CRTC will work with the encoder */
9484                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9485                                            new_crtc)) {
9486                         return -EINVAL;
9487                 }
9488                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9489
9490                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9491                         connector->base.base.id,
9492                         drm_get_connector_name(&connector->base),
9493                         new_crtc->base.id);
9494         }
9495
9496         /* Check for any encoders that needs to be disabled. */
9497         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9498                             base.head) {
9499                 list_for_each_entry(connector,
9500                                     &dev->mode_config.connector_list,
9501                                     base.head) {
9502                         if (connector->new_encoder == encoder) {
9503                                 WARN_ON(!connector->new_encoder->new_crtc);
9504
9505                                 goto next_encoder;
9506                         }
9507                 }
9508                 encoder->new_crtc = NULL;
9509 next_encoder:
9510                 /* Only now check for crtc changes so we don't miss encoders
9511                  * that will be disabled. */
9512                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9513                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9514                         config->mode_changed = true;
9515                 }
9516         }
9517         /* Now we've also updated encoder->new_crtc for all encoders. */
9518
9519         return 0;
9520 }
9521
9522 static int intel_crtc_set_config(struct drm_mode_set *set)
9523 {
9524         struct drm_device *dev;
9525         struct drm_mode_set save_set;
9526         struct intel_set_config *config;
9527         int ret;
9528
9529         BUG_ON(!set);
9530         BUG_ON(!set->crtc);
9531         BUG_ON(!set->crtc->helper_private);
9532
9533         /* Enforce sane interface api - has been abused by the fb helper. */
9534         BUG_ON(!set->mode && set->fb);
9535         BUG_ON(set->fb && set->num_connectors == 0);
9536
9537         if (set->fb) {
9538                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9539                                 set->crtc->base.id, set->fb->base.id,
9540                                 (int)set->num_connectors, set->x, set->y);
9541         } else {
9542                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9543         }
9544
9545         dev = set->crtc->dev;
9546
9547         ret = -ENOMEM;
9548         config = kzalloc(sizeof(*config), GFP_KERNEL);
9549         if (!config)
9550                 goto out_config;
9551
9552         ret = intel_set_config_save_state(dev, config);
9553         if (ret)
9554                 goto out_config;
9555
9556         save_set.crtc = set->crtc;
9557         save_set.mode = &set->crtc->mode;
9558         save_set.x = set->crtc->x;
9559         save_set.y = set->crtc->y;
9560         save_set.fb = set->crtc->fb;
9561
9562         /* Compute whether we need a full modeset, only an fb base update or no
9563          * change at all. In the future we might also check whether only the
9564          * mode changed, e.g. for LVDS where we only change the panel fitter in
9565          * such cases. */
9566         intel_set_config_compute_mode_changes(set, config);
9567
9568         ret = intel_modeset_stage_output_state(dev, set, config);
9569         if (ret)
9570                 goto fail;
9571
9572         if (config->mode_changed) {
9573                 ret = intel_set_mode(set->crtc, set->mode,
9574                                      set->x, set->y, set->fb);
9575         } else if (config->fb_changed) {
9576                 intel_crtc_wait_for_pending_flips(set->crtc);
9577
9578                 ret = intel_pipe_set_base(set->crtc,
9579                                           set->x, set->y, set->fb);
9580         }
9581
9582         if (ret) {
9583                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9584                               set->crtc->base.id, ret);
9585 fail:
9586                 intel_set_config_restore_state(dev, config);
9587
9588                 /* Try to restore the config */
9589                 if (config->mode_changed &&
9590                     intel_set_mode(save_set.crtc, save_set.mode,
9591                                    save_set.x, save_set.y, save_set.fb))
9592                         DRM_ERROR("failed to restore config after modeset failure\n");
9593         }
9594
9595 out_config:
9596         intel_set_config_free(config);
9597         return ret;
9598 }
9599
9600 static const struct drm_crtc_funcs intel_crtc_funcs = {
9601         .cursor_set = intel_crtc_cursor_set,
9602         .cursor_move = intel_crtc_cursor_move,
9603         .gamma_set = intel_crtc_gamma_set,
9604         .set_config = intel_crtc_set_config,
9605         .destroy = intel_crtc_destroy,
9606         .page_flip = intel_crtc_page_flip,
9607 };
9608
9609 static void intel_cpu_pll_init(struct drm_device *dev)
9610 {
9611         if (HAS_DDI(dev))
9612                 intel_ddi_pll_init(dev);
9613 }
9614
9615 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9616                                       struct intel_shared_dpll *pll,
9617                                       struct intel_dpll_hw_state *hw_state)
9618 {
9619         uint32_t val;
9620
9621         val = I915_READ(PCH_DPLL(pll->id));
9622         hw_state->dpll = val;
9623         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9624         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9625
9626         return val & DPLL_VCO_ENABLE;
9627 }
9628
9629 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9630                                   struct intel_shared_dpll *pll)
9631 {
9632         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9633         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9634 }
9635
9636 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9637                                 struct intel_shared_dpll *pll)
9638 {
9639         /* PCH refclock must be enabled first */
9640         assert_pch_refclk_enabled(dev_priv);
9641
9642         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9643
9644         /* Wait for the clocks to stabilize. */
9645         POSTING_READ(PCH_DPLL(pll->id));
9646         udelay(150);
9647
9648         /* The pixel multiplier can only be updated once the
9649          * DPLL is enabled and the clocks are stable.
9650          *
9651          * So write it again.
9652          */
9653         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9654         POSTING_READ(PCH_DPLL(pll->id));
9655         udelay(200);
9656 }
9657
9658 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9659                                  struct intel_shared_dpll *pll)
9660 {
9661         struct drm_device *dev = dev_priv->dev;
9662         struct intel_crtc *crtc;
9663
9664         /* Make sure no transcoder isn't still depending on us. */
9665         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9666                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9667                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9668         }
9669
9670         I915_WRITE(PCH_DPLL(pll->id), 0);
9671         POSTING_READ(PCH_DPLL(pll->id));
9672         udelay(200);
9673 }
9674
9675 static char *ibx_pch_dpll_names[] = {
9676         "PCH DPLL A",
9677         "PCH DPLL B",
9678 };
9679
9680 static void ibx_pch_dpll_init(struct drm_device *dev)
9681 {
9682         struct drm_i915_private *dev_priv = dev->dev_private;
9683         int i;
9684
9685         dev_priv->num_shared_dpll = 2;
9686
9687         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9688                 dev_priv->shared_dplls[i].id = i;
9689                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9690                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9691                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9692                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9693                 dev_priv->shared_dplls[i].get_hw_state =
9694                         ibx_pch_dpll_get_hw_state;
9695         }
9696 }
9697
9698 static void intel_shared_dpll_init(struct drm_device *dev)
9699 {
9700         struct drm_i915_private *dev_priv = dev->dev_private;
9701
9702         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9703                 ibx_pch_dpll_init(dev);
9704         else
9705                 dev_priv->num_shared_dpll = 0;
9706
9707         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9708         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9709                       dev_priv->num_shared_dpll);
9710 }
9711
9712 static void intel_crtc_init(struct drm_device *dev, int pipe)
9713 {
9714         drm_i915_private_t *dev_priv = dev->dev_private;
9715         struct intel_crtc *intel_crtc;
9716         int i;
9717
9718         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9719         if (intel_crtc == NULL)
9720                 return;
9721
9722         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9723
9724         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9725         for (i = 0; i < 256; i++) {
9726                 intel_crtc->lut_r[i] = i;
9727                 intel_crtc->lut_g[i] = i;
9728                 intel_crtc->lut_b[i] = i;
9729         }
9730
9731         /* Swap pipes & planes for FBC on pre-965 */
9732         intel_crtc->pipe = pipe;
9733         intel_crtc->plane = pipe;
9734         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9735                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9736                 intel_crtc->plane = !pipe;
9737         }
9738
9739         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9740                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9741         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9742         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9743
9744         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9745 }
9746
9747 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9748                                 struct drm_file *file)
9749 {
9750         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9751         struct drm_mode_object *drmmode_obj;
9752         struct intel_crtc *crtc;
9753
9754         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9755                 return -ENODEV;
9756
9757         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9758                         DRM_MODE_OBJECT_CRTC);
9759
9760         if (!drmmode_obj) {
9761                 DRM_ERROR("no such CRTC id\n");
9762                 return -EINVAL;
9763         }
9764
9765         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9766         pipe_from_crtc_id->pipe = crtc->pipe;
9767
9768         return 0;
9769 }
9770
9771 static int intel_encoder_clones(struct intel_encoder *encoder)
9772 {
9773         struct drm_device *dev = encoder->base.dev;
9774         struct intel_encoder *source_encoder;
9775         int index_mask = 0;
9776         int entry = 0;
9777
9778         list_for_each_entry(source_encoder,
9779                             &dev->mode_config.encoder_list, base.head) {
9780
9781                 if (encoder == source_encoder)
9782                         index_mask |= (1 << entry);
9783
9784                 /* Intel hw has only one MUX where enocoders could be cloned. */
9785                 if (encoder->cloneable && source_encoder->cloneable)
9786                         index_mask |= (1 << entry);
9787
9788                 entry++;
9789         }
9790
9791         return index_mask;
9792 }
9793
9794 static bool has_edp_a(struct drm_device *dev)
9795 {
9796         struct drm_i915_private *dev_priv = dev->dev_private;
9797
9798         if (!IS_MOBILE(dev))
9799                 return false;
9800
9801         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9802                 return false;
9803
9804         if (IS_GEN5(dev) &&
9805             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9806                 return false;
9807
9808         return true;
9809 }
9810
9811 static void intel_setup_outputs(struct drm_device *dev)
9812 {
9813         struct drm_i915_private *dev_priv = dev->dev_private;
9814         struct intel_encoder *encoder;
9815         bool dpd_is_edp = false;
9816
9817         intel_lvds_init(dev);
9818
9819         if (!IS_ULT(dev))
9820                 intel_crt_init(dev);
9821
9822         if (HAS_DDI(dev)) {
9823                 int found;
9824
9825                 /* Haswell uses DDI functions to detect digital outputs */
9826                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9827                 /* DDI A only supports eDP */
9828                 if (found)
9829                         intel_ddi_init(dev, PORT_A);
9830
9831                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9832                  * register */
9833                 found = I915_READ(SFUSE_STRAP);
9834
9835                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9836                         intel_ddi_init(dev, PORT_B);
9837                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9838                         intel_ddi_init(dev, PORT_C);
9839                 if (found & SFUSE_STRAP_DDID_DETECTED)
9840                         intel_ddi_init(dev, PORT_D);
9841         } else if (HAS_PCH_SPLIT(dev)) {
9842                 int found;
9843                 dpd_is_edp = intel_dpd_is_edp(dev);
9844
9845                 if (has_edp_a(dev))
9846                         intel_dp_init(dev, DP_A, PORT_A);
9847
9848                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9849                         /* PCH SDVOB multiplex with HDMIB */
9850                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9851                         if (!found)
9852                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9853                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9854                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9855                 }
9856
9857                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9858                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9859
9860                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9861                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9862
9863                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9864                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9865
9866                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9867                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9868         } else if (IS_VALLEYVIEW(dev)) {
9869                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9870                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9871                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9872                                         PORT_C);
9873                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9874                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9875                                               PORT_C);
9876                 }
9877
9878                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9879                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9880                                         PORT_B);
9881                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9882                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9883                 }
9884
9885                 intel_dsi_init(dev);
9886         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9887                 bool found = false;
9888
9889                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9890                         DRM_DEBUG_KMS("probing SDVOB\n");
9891                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9892                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9893                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9894                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9895                         }
9896
9897                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9898                                 intel_dp_init(dev, DP_B, PORT_B);
9899                 }
9900
9901                 /* Before G4X SDVOC doesn't have its own detect register */
9902
9903                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9904                         DRM_DEBUG_KMS("probing SDVOC\n");
9905                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9906                 }
9907
9908                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9909
9910                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9911                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9912                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9913                         }
9914                         if (SUPPORTS_INTEGRATED_DP(dev))
9915                                 intel_dp_init(dev, DP_C, PORT_C);
9916                 }
9917
9918                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9919                     (I915_READ(DP_D) & DP_DETECTED))
9920                         intel_dp_init(dev, DP_D, PORT_D);
9921         } else if (IS_GEN2(dev))
9922                 intel_dvo_init(dev);
9923
9924         if (SUPPORTS_TV(dev))
9925                 intel_tv_init(dev);
9926
9927         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9928                 encoder->base.possible_crtcs = encoder->crtc_mask;
9929                 encoder->base.possible_clones =
9930                         intel_encoder_clones(encoder);
9931         }
9932
9933         intel_init_pch_refclk(dev);
9934
9935         drm_helper_move_panel_connectors_to_head(dev);
9936 }
9937
9938 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9939 {
9940         drm_framebuffer_cleanup(&fb->base);
9941         drm_gem_object_unreference_unlocked(&fb->obj->base);
9942 }
9943
9944 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9945 {
9946         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9947
9948         intel_framebuffer_fini(intel_fb);
9949         kfree(intel_fb);
9950 }
9951
9952 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9953                                                 struct drm_file *file,
9954                                                 unsigned int *handle)
9955 {
9956         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9957         struct drm_i915_gem_object *obj = intel_fb->obj;
9958
9959         return drm_gem_handle_create(file, &obj->base, handle);
9960 }
9961
9962 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9963         .destroy = intel_user_framebuffer_destroy,
9964         .create_handle = intel_user_framebuffer_create_handle,
9965 };
9966
9967 int intel_framebuffer_init(struct drm_device *dev,
9968                            struct intel_framebuffer *intel_fb,
9969                            struct drm_mode_fb_cmd2 *mode_cmd,
9970                            struct drm_i915_gem_object *obj)
9971 {
9972         int pitch_limit;
9973         int ret;
9974
9975         if (obj->tiling_mode == I915_TILING_Y) {
9976                 DRM_DEBUG("hardware does not support tiling Y\n");
9977                 return -EINVAL;
9978         }
9979
9980         if (mode_cmd->pitches[0] & 63) {
9981                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9982                           mode_cmd->pitches[0]);
9983                 return -EINVAL;
9984         }
9985
9986         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9987                 pitch_limit = 32*1024;
9988         } else if (INTEL_INFO(dev)->gen >= 4) {
9989                 if (obj->tiling_mode)
9990                         pitch_limit = 16*1024;
9991                 else
9992                         pitch_limit = 32*1024;
9993         } else if (INTEL_INFO(dev)->gen >= 3) {
9994                 if (obj->tiling_mode)
9995                         pitch_limit = 8*1024;
9996                 else
9997                         pitch_limit = 16*1024;
9998         } else
9999                 /* XXX DSPC is limited to 4k tiled */
10000                 pitch_limit = 8*1024;
10001
10002         if (mode_cmd->pitches[0] > pitch_limit) {
10003                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10004                           obj->tiling_mode ? "tiled" : "linear",
10005                           mode_cmd->pitches[0], pitch_limit);
10006                 return -EINVAL;
10007         }
10008
10009         if (obj->tiling_mode != I915_TILING_NONE &&
10010             mode_cmd->pitches[0] != obj->stride) {
10011                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10012                           mode_cmd->pitches[0], obj->stride);
10013                 return -EINVAL;
10014         }
10015
10016         /* Reject formats not supported by any plane early. */
10017         switch (mode_cmd->pixel_format) {
10018         case DRM_FORMAT_C8:
10019         case DRM_FORMAT_RGB565:
10020         case DRM_FORMAT_XRGB8888:
10021         case DRM_FORMAT_ARGB8888:
10022                 break;
10023         case DRM_FORMAT_XRGB1555:
10024         case DRM_FORMAT_ARGB1555:
10025                 if (INTEL_INFO(dev)->gen > 3) {
10026                         DRM_DEBUG("unsupported pixel format: %s\n",
10027                                   drm_get_format_name(mode_cmd->pixel_format));
10028                         return -EINVAL;
10029                 }
10030                 break;
10031         case DRM_FORMAT_XBGR8888:
10032         case DRM_FORMAT_ABGR8888:
10033         case DRM_FORMAT_XRGB2101010:
10034         case DRM_FORMAT_ARGB2101010:
10035         case DRM_FORMAT_XBGR2101010:
10036         case DRM_FORMAT_ABGR2101010:
10037                 if (INTEL_INFO(dev)->gen < 4) {
10038                         DRM_DEBUG("unsupported pixel format: %s\n",
10039                                   drm_get_format_name(mode_cmd->pixel_format));
10040                         return -EINVAL;
10041                 }
10042                 break;
10043         case DRM_FORMAT_YUYV:
10044         case DRM_FORMAT_UYVY:
10045         case DRM_FORMAT_YVYU:
10046         case DRM_FORMAT_VYUY:
10047                 if (INTEL_INFO(dev)->gen < 5) {
10048                         DRM_DEBUG("unsupported pixel format: %s\n",
10049                                   drm_get_format_name(mode_cmd->pixel_format));
10050                         return -EINVAL;
10051                 }
10052                 break;
10053         default:
10054                 DRM_DEBUG("unsupported pixel format: %s\n",
10055                           drm_get_format_name(mode_cmd->pixel_format));
10056                 return -EINVAL;
10057         }
10058
10059         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10060         if (mode_cmd->offsets[0] != 0)
10061                 return -EINVAL;
10062
10063         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10064         intel_fb->obj = obj;
10065
10066         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10067         if (ret) {
10068                 DRM_ERROR("framebuffer init failed %d\n", ret);
10069                 return ret;
10070         }
10071
10072         return 0;
10073 }
10074
10075 static struct drm_framebuffer *
10076 intel_user_framebuffer_create(struct drm_device *dev,
10077                               struct drm_file *filp,
10078                               struct drm_mode_fb_cmd2 *mode_cmd)
10079 {
10080         struct drm_i915_gem_object *obj;
10081
10082         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10083                                                 mode_cmd->handles[0]));
10084         if (&obj->base == NULL)
10085                 return ERR_PTR(-ENOENT);
10086
10087         return intel_framebuffer_create(dev, mode_cmd, obj);
10088 }
10089
10090 static const struct drm_mode_config_funcs intel_mode_funcs = {
10091         .fb_create = intel_user_framebuffer_create,
10092         .output_poll_changed = intel_fb_output_poll_changed,
10093 };
10094
10095 /* Set up chip specific display functions */
10096 static void intel_init_display(struct drm_device *dev)
10097 {
10098         struct drm_i915_private *dev_priv = dev->dev_private;
10099
10100         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10101                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10102         else if (IS_VALLEYVIEW(dev))
10103                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10104         else if (IS_PINEVIEW(dev))
10105                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10106         else
10107                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10108
10109         if (HAS_DDI(dev)) {
10110                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10111                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10112                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10113                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10114                 dev_priv->display.off = haswell_crtc_off;
10115                 dev_priv->display.update_plane = ironlake_update_plane;
10116         } else if (HAS_PCH_SPLIT(dev)) {
10117                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10118                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10119                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10120                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10121                 dev_priv->display.off = ironlake_crtc_off;
10122                 dev_priv->display.update_plane = ironlake_update_plane;
10123         } else if (IS_VALLEYVIEW(dev)) {
10124                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10125                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10126                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10127                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10128                 dev_priv->display.off = i9xx_crtc_off;
10129                 dev_priv->display.update_plane = i9xx_update_plane;
10130         } else {
10131                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10132                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10133                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10134                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10135                 dev_priv->display.off = i9xx_crtc_off;
10136                 dev_priv->display.update_plane = i9xx_update_plane;
10137         }
10138
10139         /* Returns the core display clock speed */
10140         if (IS_VALLEYVIEW(dev))
10141                 dev_priv->display.get_display_clock_speed =
10142                         valleyview_get_display_clock_speed;
10143         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10144                 dev_priv->display.get_display_clock_speed =
10145                         i945_get_display_clock_speed;
10146         else if (IS_I915G(dev))
10147                 dev_priv->display.get_display_clock_speed =
10148                         i915_get_display_clock_speed;
10149         else if (IS_I945GM(dev) || IS_845G(dev))
10150                 dev_priv->display.get_display_clock_speed =
10151                         i9xx_misc_get_display_clock_speed;
10152         else if (IS_PINEVIEW(dev))
10153                 dev_priv->display.get_display_clock_speed =
10154                         pnv_get_display_clock_speed;
10155         else if (IS_I915GM(dev))
10156                 dev_priv->display.get_display_clock_speed =
10157                         i915gm_get_display_clock_speed;
10158         else if (IS_I865G(dev))
10159                 dev_priv->display.get_display_clock_speed =
10160                         i865_get_display_clock_speed;
10161         else if (IS_I85X(dev))
10162                 dev_priv->display.get_display_clock_speed =
10163                         i855_get_display_clock_speed;
10164         else /* 852, 830 */
10165                 dev_priv->display.get_display_clock_speed =
10166                         i830_get_display_clock_speed;
10167
10168         if (HAS_PCH_SPLIT(dev)) {
10169                 if (IS_GEN5(dev)) {
10170                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10171                         dev_priv->display.write_eld = ironlake_write_eld;
10172                 } else if (IS_GEN6(dev)) {
10173                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10174                         dev_priv->display.write_eld = ironlake_write_eld;
10175                 } else if (IS_IVYBRIDGE(dev)) {
10176                         /* FIXME: detect B0+ stepping and use auto training */
10177                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10178                         dev_priv->display.write_eld = ironlake_write_eld;
10179                         dev_priv->display.modeset_global_resources =
10180                                 ivb_modeset_global_resources;
10181                 } else if (IS_HASWELL(dev)) {
10182                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10183                         dev_priv->display.write_eld = haswell_write_eld;
10184                         dev_priv->display.modeset_global_resources =
10185                                 haswell_modeset_global_resources;
10186                 }
10187         } else if (IS_G4X(dev)) {
10188                 dev_priv->display.write_eld = g4x_write_eld;
10189         }
10190
10191         /* Default just returns -ENODEV to indicate unsupported */
10192         dev_priv->display.queue_flip = intel_default_queue_flip;
10193
10194         switch (INTEL_INFO(dev)->gen) {
10195         case 2:
10196                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10197                 break;
10198
10199         case 3:
10200                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10201                 break;
10202
10203         case 4:
10204         case 5:
10205                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10206                 break;
10207
10208         case 6:
10209                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10210                 break;
10211         case 7:
10212                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10213                 break;
10214         }
10215 }
10216
10217 /*
10218  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10219  * resume, or other times.  This quirk makes sure that's the case for
10220  * affected systems.
10221  */
10222 static void quirk_pipea_force(struct drm_device *dev)
10223 {
10224         struct drm_i915_private *dev_priv = dev->dev_private;
10225
10226         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10227         DRM_INFO("applying pipe a force quirk\n");
10228 }
10229
10230 /*
10231  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10232  */
10233 static void quirk_ssc_force_disable(struct drm_device *dev)
10234 {
10235         struct drm_i915_private *dev_priv = dev->dev_private;
10236         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10237         DRM_INFO("applying lvds SSC disable quirk\n");
10238 }
10239
10240 /*
10241  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10242  * brightness value
10243  */
10244 static void quirk_invert_brightness(struct drm_device *dev)
10245 {
10246         struct drm_i915_private *dev_priv = dev->dev_private;
10247         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10248         DRM_INFO("applying inverted panel brightness quirk\n");
10249 }
10250
10251 /*
10252  * Some machines (Dell XPS13) suffer broken backlight controls if
10253  * BLM_PCH_PWM_ENABLE is set.
10254  */
10255 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10256 {
10257         struct drm_i915_private *dev_priv = dev->dev_private;
10258         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10259         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10260 }
10261
10262 struct intel_quirk {
10263         int device;
10264         int subsystem_vendor;
10265         int subsystem_device;
10266         void (*hook)(struct drm_device *dev);
10267 };
10268
10269 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10270 struct intel_dmi_quirk {
10271         void (*hook)(struct drm_device *dev);
10272         const struct dmi_system_id (*dmi_id_list)[];
10273 };
10274
10275 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10276 {
10277         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10278         return 1;
10279 }
10280
10281 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10282         {
10283                 .dmi_id_list = &(const struct dmi_system_id[]) {
10284                         {
10285                                 .callback = intel_dmi_reverse_brightness,
10286                                 .ident = "NCR Corporation",
10287                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10288                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10289                                 },
10290                         },
10291                         { }  /* terminating entry */
10292                 },
10293                 .hook = quirk_invert_brightness,
10294         },
10295 };
10296
10297 static struct intel_quirk intel_quirks[] = {
10298         /* HP Mini needs pipe A force quirk (LP: #322104) */
10299         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10300
10301         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10302         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10303
10304         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10305         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10306
10307         /* 830/845 need to leave pipe A & dpll A up */
10308         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10309         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10310
10311         /* Lenovo U160 cannot use SSC on LVDS */
10312         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10313
10314         /* Sony Vaio Y cannot use SSC on LVDS */
10315         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10316
10317         /*
10318          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10319          * seem to use inverted backlight PWM.
10320          */
10321         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10322
10323         /* Dell XPS13 HD Sandy Bridge */
10324         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10325         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10326         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10327 };
10328
10329 static void intel_init_quirks(struct drm_device *dev)
10330 {
10331         struct pci_dev *d = dev->pdev;
10332         int i;
10333
10334         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10335                 struct intel_quirk *q = &intel_quirks[i];
10336
10337                 if (d->device == q->device &&
10338                     (d->subsystem_vendor == q->subsystem_vendor ||
10339                      q->subsystem_vendor == PCI_ANY_ID) &&
10340                     (d->subsystem_device == q->subsystem_device ||
10341                      q->subsystem_device == PCI_ANY_ID))
10342                         q->hook(dev);
10343         }
10344         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10345                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10346                         intel_dmi_quirks[i].hook(dev);
10347         }
10348 }
10349
10350 /* Disable the VGA plane that we never use */
10351 static void i915_disable_vga(struct drm_device *dev)
10352 {
10353         struct drm_i915_private *dev_priv = dev->dev_private;
10354         u8 sr1;
10355         u32 vga_reg = i915_vgacntrl_reg(dev);
10356
10357         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10358         outb(SR01, VGA_SR_INDEX);
10359         sr1 = inb(VGA_SR_DATA);
10360         outb(sr1 | 1<<5, VGA_SR_DATA);
10361         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10362         udelay(300);
10363
10364         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10365         POSTING_READ(vga_reg);
10366 }
10367
10368 static void i915_enable_vga_mem(struct drm_device *dev)
10369 {
10370         /* Enable VGA memory on Intel HD */
10371         if (HAS_PCH_SPLIT(dev)) {
10372                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10373                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10374                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10375                                                    VGA_RSRC_LEGACY_MEM |
10376                                                    VGA_RSRC_NORMAL_IO |
10377                                                    VGA_RSRC_NORMAL_MEM);
10378                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10379         }
10380 }
10381
10382 void i915_disable_vga_mem(struct drm_device *dev)
10383 {
10384         /* Disable VGA memory on Intel HD */
10385         if (HAS_PCH_SPLIT(dev)) {
10386                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10387                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10388                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10389                                                    VGA_RSRC_NORMAL_IO |
10390                                                    VGA_RSRC_NORMAL_MEM);
10391                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10392         }
10393 }
10394
10395 void intel_modeset_init_hw(struct drm_device *dev)
10396 {
10397         struct drm_i915_private *dev_priv = dev->dev_private;
10398
10399         intel_prepare_ddi(dev);
10400
10401         intel_init_clock_gating(dev);
10402
10403         /* Enable the CRI clock source so we can get at the display */
10404         if (IS_VALLEYVIEW(dev))
10405                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10406                            DPLL_INTEGRATED_CRI_CLK_VLV);
10407
10408         intel_init_dpio(dev);
10409
10410         mutex_lock(&dev->struct_mutex);
10411         intel_enable_gt_powersave(dev);
10412         mutex_unlock(&dev->struct_mutex);
10413 }
10414
10415 void intel_modeset_suspend_hw(struct drm_device *dev)
10416 {
10417         intel_suspend_hw(dev);
10418 }
10419
10420 void intel_modeset_init(struct drm_device *dev)
10421 {
10422         struct drm_i915_private *dev_priv = dev->dev_private;
10423         int i, j, ret;
10424
10425         drm_mode_config_init(dev);
10426
10427         dev->mode_config.min_width = 0;
10428         dev->mode_config.min_height = 0;
10429
10430         dev->mode_config.preferred_depth = 24;
10431         dev->mode_config.prefer_shadow = 1;
10432
10433         dev->mode_config.funcs = &intel_mode_funcs;
10434
10435         intel_init_quirks(dev);
10436
10437         intel_init_pm(dev);
10438
10439         if (INTEL_INFO(dev)->num_pipes == 0)
10440                 return;
10441
10442         intel_init_display(dev);
10443
10444         if (IS_GEN2(dev)) {
10445                 dev->mode_config.max_width = 2048;
10446                 dev->mode_config.max_height = 2048;
10447         } else if (IS_GEN3(dev)) {
10448                 dev->mode_config.max_width = 4096;
10449                 dev->mode_config.max_height = 4096;
10450         } else {
10451                 dev->mode_config.max_width = 8192;
10452                 dev->mode_config.max_height = 8192;
10453         }
10454         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10455
10456         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10457                       INTEL_INFO(dev)->num_pipes,
10458                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10459
10460         for_each_pipe(i) {
10461                 intel_crtc_init(dev, i);
10462                 for (j = 0; j < dev_priv->num_plane; j++) {
10463                         ret = intel_plane_init(dev, i, j);
10464                         if (ret)
10465                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10466                                               pipe_name(i), sprite_name(i, j), ret);
10467                 }
10468         }
10469
10470         intel_cpu_pll_init(dev);
10471         intel_shared_dpll_init(dev);
10472
10473         /* Just disable it once at startup */
10474         i915_disable_vga(dev);
10475         intel_setup_outputs(dev);
10476
10477         /* Just in case the BIOS is doing something questionable. */
10478         intel_disable_fbc(dev);
10479 }
10480
10481 static void
10482 intel_connector_break_all_links(struct intel_connector *connector)
10483 {
10484         connector->base.dpms = DRM_MODE_DPMS_OFF;
10485         connector->base.encoder = NULL;
10486         connector->encoder->connectors_active = false;
10487         connector->encoder->base.crtc = NULL;
10488 }
10489
10490 static void intel_enable_pipe_a(struct drm_device *dev)
10491 {
10492         struct intel_connector *connector;
10493         struct drm_connector *crt = NULL;
10494         struct intel_load_detect_pipe load_detect_temp;
10495
10496         /* We can't just switch on the pipe A, we need to set things up with a
10497          * proper mode and output configuration. As a gross hack, enable pipe A
10498          * by enabling the load detect pipe once. */
10499         list_for_each_entry(connector,
10500                             &dev->mode_config.connector_list,
10501                             base.head) {
10502                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10503                         crt = &connector->base;
10504                         break;
10505                 }
10506         }
10507
10508         if (!crt)
10509                 return;
10510
10511         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10512                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10513
10514
10515 }
10516
10517 static bool
10518 intel_check_plane_mapping(struct intel_crtc *crtc)
10519 {
10520         struct drm_device *dev = crtc->base.dev;
10521         struct drm_i915_private *dev_priv = dev->dev_private;
10522         u32 reg, val;
10523
10524         if (INTEL_INFO(dev)->num_pipes == 1)
10525                 return true;
10526
10527         reg = DSPCNTR(!crtc->plane);
10528         val = I915_READ(reg);
10529
10530         if ((val & DISPLAY_PLANE_ENABLE) &&
10531             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10532                 return false;
10533
10534         return true;
10535 }
10536
10537 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10538 {
10539         struct drm_device *dev = crtc->base.dev;
10540         struct drm_i915_private *dev_priv = dev->dev_private;
10541         u32 reg;
10542
10543         /* Clear any frame start delays used for debugging left by the BIOS */
10544         reg = PIPECONF(crtc->config.cpu_transcoder);
10545         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10546
10547         /* We need to sanitize the plane -> pipe mapping first because this will
10548          * disable the crtc (and hence change the state) if it is wrong. Note
10549          * that gen4+ has a fixed plane -> pipe mapping.  */
10550         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10551                 struct intel_connector *connector;
10552                 bool plane;
10553
10554                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10555                               crtc->base.base.id);
10556
10557                 /* Pipe has the wrong plane attached and the plane is active.
10558                  * Temporarily change the plane mapping and disable everything
10559                  * ...  */
10560                 plane = crtc->plane;
10561                 crtc->plane = !plane;
10562                 dev_priv->display.crtc_disable(&crtc->base);
10563                 crtc->plane = plane;
10564
10565                 /* ... and break all links. */
10566                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10567                                     base.head) {
10568                         if (connector->encoder->base.crtc != &crtc->base)
10569                                 continue;
10570
10571                         intel_connector_break_all_links(connector);
10572                 }
10573
10574                 WARN_ON(crtc->active);
10575                 crtc->base.enabled = false;
10576         }
10577
10578         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10579             crtc->pipe == PIPE_A && !crtc->active) {
10580                 /* BIOS forgot to enable pipe A, this mostly happens after
10581                  * resume. Force-enable the pipe to fix this, the update_dpms
10582                  * call below we restore the pipe to the right state, but leave
10583                  * the required bits on. */
10584                 intel_enable_pipe_a(dev);
10585         }
10586
10587         /* Adjust the state of the output pipe according to whether we
10588          * have active connectors/encoders. */
10589         intel_crtc_update_dpms(&crtc->base);
10590
10591         if (crtc->active != crtc->base.enabled) {
10592                 struct intel_encoder *encoder;
10593
10594                 /* This can happen either due to bugs in the get_hw_state
10595                  * functions or because the pipe is force-enabled due to the
10596                  * pipe A quirk. */
10597                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10598                               crtc->base.base.id,
10599                               crtc->base.enabled ? "enabled" : "disabled",
10600                               crtc->active ? "enabled" : "disabled");
10601
10602                 crtc->base.enabled = crtc->active;
10603
10604                 /* Because we only establish the connector -> encoder ->
10605                  * crtc links if something is active, this means the
10606                  * crtc is now deactivated. Break the links. connector
10607                  * -> encoder links are only establish when things are
10608                  *  actually up, hence no need to break them. */
10609                 WARN_ON(crtc->active);
10610
10611                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10612                         WARN_ON(encoder->connectors_active);
10613                         encoder->base.crtc = NULL;
10614                 }
10615         }
10616 }
10617
10618 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10619 {
10620         struct intel_connector *connector;
10621         struct drm_device *dev = encoder->base.dev;
10622
10623         /* We need to check both for a crtc link (meaning that the
10624          * encoder is active and trying to read from a pipe) and the
10625          * pipe itself being active. */
10626         bool has_active_crtc = encoder->base.crtc &&
10627                 to_intel_crtc(encoder->base.crtc)->active;
10628
10629         if (encoder->connectors_active && !has_active_crtc) {
10630                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10631                               encoder->base.base.id,
10632                               drm_get_encoder_name(&encoder->base));
10633
10634                 /* Connector is active, but has no active pipe. This is
10635                  * fallout from our resume register restoring. Disable
10636                  * the encoder manually again. */
10637                 if (encoder->base.crtc) {
10638                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10639                                       encoder->base.base.id,
10640                                       drm_get_encoder_name(&encoder->base));
10641                         encoder->disable(encoder);
10642                 }
10643
10644                 /* Inconsistent output/port/pipe state happens presumably due to
10645                  * a bug in one of the get_hw_state functions. Or someplace else
10646                  * in our code, like the register restore mess on resume. Clamp
10647                  * things to off as a safer default. */
10648                 list_for_each_entry(connector,
10649                                     &dev->mode_config.connector_list,
10650                                     base.head) {
10651                         if (connector->encoder != encoder)
10652                                 continue;
10653
10654                         intel_connector_break_all_links(connector);
10655                 }
10656         }
10657         /* Enabled encoders without active connectors will be fixed in
10658          * the crtc fixup. */
10659 }
10660
10661 void i915_redisable_vga(struct drm_device *dev)
10662 {
10663         struct drm_i915_private *dev_priv = dev->dev_private;
10664         u32 vga_reg = i915_vgacntrl_reg(dev);
10665
10666         /* This function can be called both from intel_modeset_setup_hw_state or
10667          * at a very early point in our resume sequence, where the power well
10668          * structures are not yet restored. Since this function is at a very
10669          * paranoid "someone might have enabled VGA while we were not looking"
10670          * level, just check if the power well is enabled instead of trying to
10671          * follow the "don't touch the power well if we don't need it" policy
10672          * the rest of the driver uses. */
10673         if (HAS_POWER_WELL(dev) &&
10674             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10675                 return;
10676
10677         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10678                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10679                 i915_disable_vga(dev);
10680                 i915_disable_vga_mem(dev);
10681         }
10682 }
10683
10684 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10685 {
10686         struct drm_i915_private *dev_priv = dev->dev_private;
10687         enum pipe pipe;
10688         struct intel_crtc *crtc;
10689         struct intel_encoder *encoder;
10690         struct intel_connector *connector;
10691         int i;
10692
10693         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10694                             base.head) {
10695                 memset(&crtc->config, 0, sizeof(crtc->config));
10696
10697                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10698                                                                  &crtc->config);
10699
10700                 crtc->base.enabled = crtc->active;
10701
10702                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10703                               crtc->base.base.id,
10704                               crtc->active ? "enabled" : "disabled");
10705         }
10706
10707         /* FIXME: Smash this into the new shared dpll infrastructure. */
10708         if (HAS_DDI(dev))
10709                 intel_ddi_setup_hw_pll_state(dev);
10710
10711         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10712                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10713
10714                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10715                 pll->active = 0;
10716                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10717                                     base.head) {
10718                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10719                                 pll->active++;
10720                 }
10721                 pll->refcount = pll->active;
10722
10723                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10724                               pll->name, pll->refcount, pll->on);
10725         }
10726
10727         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10728                             base.head) {
10729                 pipe = 0;
10730
10731                 if (encoder->get_hw_state(encoder, &pipe)) {
10732                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10733                         encoder->base.crtc = &crtc->base;
10734                         if (encoder->get_config)
10735                                 encoder->get_config(encoder, &crtc->config);
10736                 } else {
10737                         encoder->base.crtc = NULL;
10738                 }
10739
10740                 encoder->connectors_active = false;
10741                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10742                               encoder->base.base.id,
10743                               drm_get_encoder_name(&encoder->base),
10744                               encoder->base.crtc ? "enabled" : "disabled",
10745                               pipe);
10746         }
10747
10748         list_for_each_entry(connector, &dev->mode_config.connector_list,
10749                             base.head) {
10750                 if (connector->get_hw_state(connector)) {
10751                         connector->base.dpms = DRM_MODE_DPMS_ON;
10752                         connector->encoder->connectors_active = true;
10753                         connector->base.encoder = &connector->encoder->base;
10754                 } else {
10755                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10756                         connector->base.encoder = NULL;
10757                 }
10758                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10759                               connector->base.base.id,
10760                               drm_get_connector_name(&connector->base),
10761                               connector->base.encoder ? "enabled" : "disabled");
10762         }
10763 }
10764
10765 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10766  * and i915 state tracking structures. */
10767 void intel_modeset_setup_hw_state(struct drm_device *dev,
10768                                   bool force_restore)
10769 {
10770         struct drm_i915_private *dev_priv = dev->dev_private;
10771         enum pipe pipe;
10772         struct intel_crtc *crtc;
10773         struct intel_encoder *encoder;
10774         int i;
10775
10776         intel_modeset_readout_hw_state(dev);
10777
10778         /*
10779          * Now that we have the config, copy it to each CRTC struct
10780          * Note that this could go away if we move to using crtc_config
10781          * checking everywhere.
10782          */
10783         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10784                             base.head) {
10785                 if (crtc->active && i915_fastboot) {
10786                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10787
10788                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10789                                       crtc->base.base.id);
10790                         drm_mode_debug_printmodeline(&crtc->base.mode);
10791                 }
10792         }
10793
10794         /* HW state is read out, now we need to sanitize this mess. */
10795         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10796                             base.head) {
10797                 intel_sanitize_encoder(encoder);
10798         }
10799
10800         for_each_pipe(pipe) {
10801                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10802                 intel_sanitize_crtc(crtc);
10803                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10804         }
10805
10806         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10807                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10808
10809                 if (!pll->on || pll->active)
10810                         continue;
10811
10812                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10813
10814                 pll->disable(dev_priv, pll);
10815                 pll->on = false;
10816         }
10817
10818         if (force_restore) {
10819                 i915_redisable_vga(dev);
10820
10821                 /*
10822                  * We need to use raw interfaces for restoring state to avoid
10823                  * checking (bogus) intermediate states.
10824                  */
10825                 for_each_pipe(pipe) {
10826                         struct drm_crtc *crtc =
10827                                 dev_priv->pipe_to_crtc_mapping[pipe];
10828
10829                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10830                                          crtc->fb);
10831                 }
10832         } else {
10833                 intel_modeset_update_staged_output_state(dev);
10834         }
10835
10836         intel_modeset_check_state(dev);
10837
10838         drm_mode_config_reset(dev);
10839 }
10840
10841 void intel_modeset_gem_init(struct drm_device *dev)
10842 {
10843         intel_modeset_init_hw(dev);
10844
10845         intel_setup_overlay(dev);
10846
10847         intel_modeset_setup_hw_state(dev, false);
10848 }
10849
10850 void intel_modeset_cleanup(struct drm_device *dev)
10851 {
10852         struct drm_i915_private *dev_priv = dev->dev_private;
10853         struct drm_crtc *crtc;
10854         struct drm_connector *connector;
10855
10856         /*
10857          * Interrupts and polling as the first thing to avoid creating havoc.
10858          * Too much stuff here (turning of rps, connectors, ...) would
10859          * experience fancy races otherwise.
10860          */
10861         drm_irq_uninstall(dev);
10862         cancel_work_sync(&dev_priv->hotplug_work);
10863         /*
10864          * Due to the hpd irq storm handling the hotplug work can re-arm the
10865          * poll handlers. Hence disable polling after hpd handling is shut down.
10866          */
10867         drm_kms_helper_poll_fini(dev);
10868
10869         mutex_lock(&dev->struct_mutex);
10870
10871         intel_unregister_dsm_handler();
10872
10873         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10874                 /* Skip inactive CRTCs */
10875                 if (!crtc->fb)
10876                         continue;
10877
10878                 intel_increase_pllclock(crtc);
10879         }
10880
10881         intel_disable_fbc(dev);
10882
10883         i915_enable_vga_mem(dev);
10884
10885         intel_disable_gt_powersave(dev);
10886
10887         ironlake_teardown_rc6(dev);
10888
10889         mutex_unlock(&dev->struct_mutex);
10890
10891         /* flush any delayed tasks or pending work */
10892         flush_scheduled_work();
10893
10894         /* destroy backlight, if any, before the connectors */
10895         intel_panel_destroy_backlight(dev);
10896
10897         /* destroy the sysfs files before encoders/connectors */
10898         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10899                 drm_sysfs_connector_remove(connector);
10900
10901         drm_mode_config_cleanup(dev);
10902
10903         intel_cleanup_overlay(dev);
10904 }
10905
10906 /*
10907  * Return which encoder is currently attached for connector.
10908  */
10909 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10910 {
10911         return &intel_attached_encoder(connector)->base;
10912 }
10913
10914 void intel_connector_attach_encoder(struct intel_connector *connector,
10915                                     struct intel_encoder *encoder)
10916 {
10917         connector->encoder = encoder;
10918         drm_mode_connector_attach_encoder(&connector->base,
10919                                           &encoder->base);
10920 }
10921
10922 /*
10923  * set vga decode state - true == enable VGA decode
10924  */
10925 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10926 {
10927         struct drm_i915_private *dev_priv = dev->dev_private;
10928         u16 gmch_ctrl;
10929
10930         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10931         if (state)
10932                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10933         else
10934                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10935         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10936         return 0;
10937 }
10938
10939 struct intel_display_error_state {
10940
10941         u32 power_well_driver;
10942
10943         int num_transcoders;
10944
10945         struct intel_cursor_error_state {
10946                 u32 control;
10947                 u32 position;
10948                 u32 base;
10949                 u32 size;
10950         } cursor[I915_MAX_PIPES];
10951
10952         struct intel_pipe_error_state {
10953                 u32 source;
10954         } pipe[I915_MAX_PIPES];
10955
10956         struct intel_plane_error_state {
10957                 u32 control;
10958                 u32 stride;
10959                 u32 size;
10960                 u32 pos;
10961                 u32 addr;
10962                 u32 surface;
10963                 u32 tile_offset;
10964         } plane[I915_MAX_PIPES];
10965
10966         struct intel_transcoder_error_state {
10967                 enum transcoder cpu_transcoder;
10968
10969                 u32 conf;
10970
10971                 u32 htotal;
10972                 u32 hblank;
10973                 u32 hsync;
10974                 u32 vtotal;
10975                 u32 vblank;
10976                 u32 vsync;
10977         } transcoder[4];
10978 };
10979
10980 struct intel_display_error_state *
10981 intel_display_capture_error_state(struct drm_device *dev)
10982 {
10983         drm_i915_private_t *dev_priv = dev->dev_private;
10984         struct intel_display_error_state *error;
10985         int transcoders[] = {
10986                 TRANSCODER_A,
10987                 TRANSCODER_B,
10988                 TRANSCODER_C,
10989                 TRANSCODER_EDP,
10990         };
10991         int i;
10992
10993         if (INTEL_INFO(dev)->num_pipes == 0)
10994                 return NULL;
10995
10996         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10997         if (error == NULL)
10998                 return NULL;
10999
11000         if (HAS_POWER_WELL(dev))
11001                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11002
11003         for_each_pipe(i) {
11004                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11005                         error->cursor[i].control = I915_READ(CURCNTR(i));
11006                         error->cursor[i].position = I915_READ(CURPOS(i));
11007                         error->cursor[i].base = I915_READ(CURBASE(i));
11008                 } else {
11009                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11010                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11011                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11012                 }
11013
11014                 error->plane[i].control = I915_READ(DSPCNTR(i));
11015                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11016                 if (INTEL_INFO(dev)->gen <= 3) {
11017                         error->plane[i].size = I915_READ(DSPSIZE(i));
11018                         error->plane[i].pos = I915_READ(DSPPOS(i));
11019                 }
11020                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11021                         error->plane[i].addr = I915_READ(DSPADDR(i));
11022                 if (INTEL_INFO(dev)->gen >= 4) {
11023                         error->plane[i].surface = I915_READ(DSPSURF(i));
11024                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11025                 }
11026
11027                 error->pipe[i].source = I915_READ(PIPESRC(i));
11028         }
11029
11030         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11031         if (HAS_DDI(dev_priv->dev))
11032                 error->num_transcoders++; /* Account for eDP. */
11033
11034         for (i = 0; i < error->num_transcoders; i++) {
11035                 enum transcoder cpu_transcoder = transcoders[i];
11036
11037                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11038
11039                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11040                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11041                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11042                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11043                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11044                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11045                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11046         }
11047
11048         /* In the code above we read the registers without checking if the power
11049          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11050          * prevent the next I915_WRITE from detecting it and printing an error
11051          * message. */
11052         intel_uncore_clear_errors(dev);
11053
11054         return error;
11055 }
11056
11057 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11058
11059 void
11060 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11061                                 struct drm_device *dev,
11062                                 struct intel_display_error_state *error)
11063 {
11064         int i;
11065
11066         if (!error)
11067                 return;
11068
11069         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11070         if (HAS_POWER_WELL(dev))
11071                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11072                            error->power_well_driver);
11073         for_each_pipe(i) {
11074                 err_printf(m, "Pipe [%d]:\n", i);
11075                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11076
11077                 err_printf(m, "Plane [%d]:\n", i);
11078                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11079                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11080                 if (INTEL_INFO(dev)->gen <= 3) {
11081                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11082                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11083                 }
11084                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11085                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11086                 if (INTEL_INFO(dev)->gen >= 4) {
11087                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11088                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11089                 }
11090
11091                 err_printf(m, "Cursor [%d]:\n", i);
11092                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11093                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11094                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11095         }
11096
11097         for (i = 0; i < error->num_transcoders; i++) {
11098                 err_printf(m, "  CPU transcoder: %c\n",
11099                            transcoder_name(error->transcoder[i].cpu_transcoder));
11100                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11101                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11102                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11103                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11104                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11105                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11106                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11107         }
11108 }