drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include "drmP.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "drm_dp_helper.h"
  40
  41 #include "drm_crtc_helper.h"
  42
  43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  44
  45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  46 static void intel_update_watermarks(struct drm_device *dev);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51     /* given values */
  52     int n;
  53     int m1, m2;
  54     int p1, p2;
  55     /* derived values */
  56     int dot;
  57     int vco;
  58     int m;
  59     int p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63     int min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67     int dot_limit;
  68     int p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75     intel_p2_t      p2;
  76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                       int, int, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *best_clock);
  86 static bool
  87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  88                         int target, int refclk, intel_clock_t *best_clock);
  89
  90 static bool
  91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  92                       int target, int refclk, intel_clock_t *best_clock);
  93 static bool
  94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                            int target, int refclk, intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2,.max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2,.max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 359                                                 int refclk)
 360 {
 361         struct drm_device *dev = crtc->dev;
 362         struct drm_i915_private *dev_priv = dev->dev_private;
 363         const intel_limit_t *limit;
 364
 365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 367                     LVDS_CLKB_POWER_UP) {
 368                         /* LVDS dual channel */
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_dual_lvds;
 373                 } else {
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_single_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_single_lvds;
 378                 }
 379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 380                         HAS_eDP)
 381                 limit = &intel_limits_ironlake_display_port;
 382         else
 383                 limit = &intel_limits_ironlake_dac;
 384
 385         return limit;
 386 }
 387
 388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 389 {
 390         struct drm_device *dev = crtc->dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         const intel_limit_t *limit;
 393
 394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 396                     LVDS_CLKB_POWER_UP)
 397                         /* LVDS with dual channel */
 398                         limit = &intel_limits_g4x_dual_channel_lvds;
 399                 else
 400                         /* LVDS with dual channel */
 401                         limit = &intel_limits_g4x_single_channel_lvds;
 402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 404                 limit = &intel_limits_g4x_hdmi;
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 406                 limit = &intel_limits_g4x_sdvo;
 407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 408                 limit = &intel_limits_g4x_display_port;
 409         } else /* The option is for other outputs */
 410                 limit = &intel_limits_i9xx_sdvo;
 411
 412         return limit;
 413 }
 414
 415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 416 {
 417         struct drm_device *dev = crtc->dev;
 418         const intel_limit_t *limit;
 419
 420         if (HAS_PCH_SPLIT(dev))
 421                 limit = intel_ironlake_limit(crtc, refclk);
 422         else if (IS_G4X(dev)) {
 423                 limit = intel_g4x_limit(crtc);
 424         } else if (IS_PINEVIEW(dev)) {
 425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 426                         limit = &intel_limits_pineview_lvds;
 427                 else
 428                         limit = &intel_limits_pineview_sdvo;
 429         } else if (!IS_GEN2(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_i9xx_lvds;
 432                 else
 433                         limit = &intel_limits_i9xx_sdvo;
 434         } else {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i8xx_lvds;
 437                 else
 438                         limit = &intel_limits_i8xx_dvo;
 439         }
 440         return limit;
 441 }
 442
 443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 444 static void pineview_clock(int refclk, intel_clock_t *clock)
 445 {
 446         clock->m = clock->m2 + 2;
 447         clock->p = clock->p1 * clock->p2;
 448         clock->vco = refclk * clock->m / clock->n;
 449         clock->dot = clock->vco / clock->p;
 450 }
 451
 452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 453 {
 454         if (IS_PINEVIEW(dev)) {
 455                 pineview_clock(refclk, clock);
 456                 return;
 457         }
 458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 459         clock->p = clock->p1 * clock->p2;
 460         clock->vco = refclk * clock->m / (clock->n + 2);
 461         clock->dot = clock->vco / clock->p;
 462 }
 463
 464 /**
 465  * Returns whether any output on the specified pipe is of the specified type
 466  */
 467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_mode_config *mode_config = &dev->mode_config;
 471         struct intel_encoder *encoder;
 472
 473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 474                 if (encoder->base.crtc == crtc && encoder->type == type)
 475                         return true;
 476
 477         return false;
 478 }
 479
 480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 481 /**
 482  * Returns whether the given set of divisors are valid for a given refclk with
 483  * the given connectors.
 484  */
 485
 486 static bool intel_PLL_is_valid(struct drm_device *dev,
 487                                const intel_limit_t *limit,
 488                                const intel_clock_t *clock)
 489 {
 490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 491                 INTELPllInvalid ("p1 out of range\n");
 492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 493                 INTELPllInvalid ("p out of range\n");
 494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 495                 INTELPllInvalid ("m2 out of range\n");
 496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 497                 INTELPllInvalid ("m1 out of range\n");
 498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 499                 INTELPllInvalid ("m1 <= m2\n");
 500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 501                 INTELPllInvalid ("m out of range\n");
 502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 503                 INTELPllInvalid ("n out of range\n");
 504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 505                 INTELPllInvalid ("vco out of range\n");
 506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 507          * connector, etc., rather than just a single range.
 508          */
 509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 510                 INTELPllInvalid ("dot out of range\n");
 511
 512         return true;
 513 }
 514
 515 static bool
 516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 517                     int target, int refclk, intel_clock_t *best_clock)
 518
 519 {
 520         struct drm_device *dev = crtc->dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         intel_clock_t clock;
 523         int err = target;
 524
 525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 526             (I915_READ(LVDS)) != 0) {
 527                 /*
 528                  * For LVDS, if the panel is on, just rely on its current
 529                  * settings for dual-channel.  We haven't figured out how to
 530                  * reliably set up different single/dual channel state, if we
 531                  * even can.
 532                  */
 533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 534                     LVDS_CLKB_POWER_UP)
 535                         clock.p2 = limit->p2.p2_fast;
 536                 else
 537                         clock.p2 = limit->p2.p2_slow;
 538         } else {
 539                 if (target < limit->p2.dot_limit)
 540                         clock.p2 = limit->p2.p2_slow;
 541                 else
 542                         clock.p2 = limit->p2.p2_fast;
 543         }
 544
 545         memset (best_clock, 0, sizeof (*best_clock));
 546
 547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 548              clock.m1++) {
 549                 for (clock.m2 = limit->m2.min;
 550                      clock.m2 <= limit->m2.max; clock.m2++) {
 551                         /* m1 is always 0 in Pineview */
 552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 553                                 break;
 554                         for (clock.n = limit->n.min;
 555                              clock.n <= limit->n.max; clock.n++) {
 556                                 for (clock.p1 = limit->p1.min;
 557                                         clock.p1 <= limit->p1.max; clock.p1++) {
 558                                         int this_err;
 559
 560                                         intel_clock(dev, refclk, &clock);
 561                                         if (!intel_PLL_is_valid(dev, limit,
 562                                                                 &clock))
 563                                                 continue;
 564
 565                                         this_err = abs(clock.dot - target);
 566                                         if (this_err < err) {
 567                                                 *best_clock = clock;
 568                                                 err = this_err;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573         }
 574
 575         return (err != target);
 576 }
 577
 578 static bool
 579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                         int target, int refclk, intel_clock_t *best_clock)
 581 {
 582         struct drm_device *dev = crtc->dev;
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         intel_clock_t clock;
 585         int max_n;
 586         bool found;
 587         /* approximately equals target * 0.00585 */
 588         int err_most = (target >> 8) + (target >> 9);
 589         found = false;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 int lvds_reg;
 593
 594                 if (HAS_PCH_SPLIT(dev))
 595                         lvds_reg = PCH_LVDS;
 596                 else
 597                         lvds_reg = LVDS;
 598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 599                     LVDS_CLKB_POWER_UP)
 600                         clock.p2 = limit->p2.p2_fast;
 601                 else
 602                         clock.p2 = limit->p2.p2_slow;
 603         } else {
 604                 if (target < limit->p2.dot_limit)
 605                         clock.p2 = limit->p2.p2_slow;
 606                 else
 607                         clock.p2 = limit->p2.p2_fast;
 608         }
 609
 610         memset(best_clock, 0, sizeof(*best_clock));
 611         max_n = limit->n.max;
 612         /* based on hardware requirement, prefer smaller n to precision */
 613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 614                 /* based on hardware requirement, prefere larger m1,m2 */
 615                 for (clock.m1 = limit->m1.max;
 616                      clock.m1 >= limit->m1.min; clock.m1--) {
 617                         for (clock.m2 = limit->m2.max;
 618                              clock.m2 >= limit->m2.min; clock.m2--) {
 619                                 for (clock.p1 = limit->p1.max;
 620                                      clock.p1 >= limit->p1.min; clock.p1--) {
 621                                         int this_err;
 622
 623                                         intel_clock(dev, refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err_most) {
 630                                                 *best_clock = clock;
 631                                                 err_most = this_err;
 632                                                 max_n = clock.n;
 633                                                 found = true;
 634                                         }
 635                                 }
 636                         }
 637                 }
 638         }
 639         return found;
 640 }
 641
 642 static bool
 643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 644                            int target, int refclk, intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         intel_clock_t clock;
 648
 649         if (target < 200000) {
 650                 clock.n = 1;
 651                 clock.p1 = 2;
 652                 clock.p2 = 10;
 653                 clock.m1 = 12;
 654                 clock.m2 = 9;
 655         } else {
 656                 clock.n = 2;
 657                 clock.p1 = 1;
 658                 clock.p2 = 10;
 659                 clock.m1 = 14;
 660                 clock.m2 = 8;
 661         }
 662         intel_clock(dev, refclk, &clock);
 663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 664         return true;
 665 }
 666
 667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 668 static bool
 669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                       int target, int refclk, intel_clock_t *best_clock)
 671 {
 672         intel_clock_t clock;
 673         if (target < 200000) {
 674                 clock.p1 = 2;
 675                 clock.p2 = 10;
 676                 clock.n = 2;
 677                 clock.m1 = 23;
 678                 clock.m2 = 8;
 679         } else {
 680                 clock.p1 = 1;
 681                 clock.p2 = 10;
 682                 clock.n = 1;
 683                 clock.m1 = 14;
 684                 clock.m2 = 2;
 685         }
 686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 687         clock.p = (clock.p1 * clock.p2);
 688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 689         clock.vco = 0;
 690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 691         return true;
 692 }
 693
 694 /**
 695  * intel_wait_for_vblank - wait for vblank on a given pipe
 696  * @dev: drm device
 697  * @pipe: pipe to wait for
 698  *
 699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 700  * mode setting code.
 701  */
 702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 703 {
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         int pipestat_reg = PIPESTAT(pipe);
 706
 707         /* Clear existing vblank status. Note this will clear any other
 708          * sticky status fields as well.
 709          *
 710          * This races with i915_driver_irq_handler() with the result
 711          * that either function could miss a vblank event.  Here it is not
 712          * fatal, as we will either wait upon the next vblank interrupt or
 713          * timeout.  Generally speaking intel_wait_for_vblank() is only
 714          * called during modeset at which time the GPU should be idle and
 715          * should *not* be performing page flips and thus not waiting on
 716          * vblanks...
 717          * Currently, the result of us stealing a vblank from the irq
 718          * handler is that a single frame will be skipped during swapbuffers.
 719          */
 720         I915_WRITE(pipestat_reg,
 721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 722
 723         /* Wait for vblank interrupt bit to set */
 724         if (wait_for(I915_READ(pipestat_reg) &
 725                      PIPE_VBLANK_INTERRUPT_STATUS,
 726                      50))
 727                 DRM_DEBUG_KMS("vblank wait timed out\n");
 728 }
 729
 730 /*
 731  * intel_wait_for_pipe_off - wait for pipe to turn off
 732  * @dev: drm device
 733  * @pipe: pipe to wait for
 734  *
 735  * After disabling a pipe, we can't wait for vblank in the usual way,
 736  * spinning on the vblank interrupt status bit, since we won't actually
 737  * see an interrupt when the pipe is disabled.
 738  *
 739  * On Gen4 and above:
 740  *   wait for the pipe register state bit to turn off
 741  *
 742  * Otherwise:
 743  *   wait for the display line value to settle (it usually
 744  *   ends up stopping at the start of the next frame).
 745  *
 746  */
 747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750
 751         if (INTEL_INFO(dev)->gen >= 4) {
 752                 int reg = PIPECONF(pipe);
 753
 754                 /* Wait for the Pipe State to go off */
 755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 756                              100))
 757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 758         } else {
 759                 u32 last_line;
 760                 int reg = PIPEDSL(pipe);
 761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 762
 763                 /* Wait for the display line to settle */
 764                 do {
 765                         last_line = I915_READ(reg) & DSL_LINEMASK;
 766                         mdelay(5);
 767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 768                          time_after(timeout, jiffies));
 769                 if (time_after(jiffies, timeout))
 770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 771         }
 772 }
 773
 774 static const char *state_string(bool enabled)
 775 {
 776         return enabled ? "on" : "off";
 777 }
 778
 779 /* Only for pre-ILK configs */
 780 static void assert_pll(struct drm_i915_private *dev_priv,
 781                        enum pipe pipe, bool state)
 782 {
 783         int reg;
 784         u32 val;
 785         bool cur_state;
 786
 787         reg = DPLL(pipe);
 788         val = I915_READ(reg);
 789         cur_state = !!(val & DPLL_VCO_ENABLE);
 790         WARN(cur_state != state,
 791              "PLL state assertion failure (expected %s, current %s)\n",
 792              state_string(state), state_string(cur_state));
 793 }
 794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 796
 797 /* For ILK+ */
 798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 799                            enum pipe pipe, bool state)
 800 {
 801         int reg;
 802         u32 val;
 803         bool cur_state;
 804
 805         reg = PCH_DPLL(pipe);
 806         val = I915_READ(reg);
 807         cur_state = !!(val & DPLL_VCO_ENABLE);
 808         WARN(cur_state != state,
 809              "PCH PLL state assertion failure (expected %s, current %s)\n",
 810              state_string(state), state_string(cur_state));
 811 }
 812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 814
 815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 816                           enum pipe pipe, bool state)
 817 {
 818         int reg;
 819         u32 val;
 820         bool cur_state;
 821
 822         reg = FDI_TX_CTL(pipe);
 823         val = I915_READ(reg);
 824         cur_state = !!(val & FDI_TX_ENABLE);
 825         WARN(cur_state != state,
 826              "FDI TX state assertion failure (expected %s, current %s)\n",
 827              state_string(state), state_string(cur_state));
 828 }
 829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 831
 832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 833                           enum pipe pipe, bool state)
 834 {
 835         int reg;
 836         u32 val;
 837         bool cur_state;
 838
 839         reg = FDI_RX_CTL(pipe);
 840         val = I915_READ(reg);
 841         cur_state = !!(val & FDI_RX_ENABLE);
 842         WARN(cur_state != state,
 843              "FDI RX state assertion failure (expected %s, current %s)\n",
 844              state_string(state), state_string(cur_state));
 845 }
 846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 848
 849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 850                                       enum pipe pipe)
 851 {
 852         int reg;
 853         u32 val;
 854
 855         /* ILK FDI PLL is always enabled */
 856         if (dev_priv->info->gen == 5)
 857                 return;
 858
 859         reg = FDI_TX_CTL(pipe);
 860         val = I915_READ(reg);
 861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 862 }
 863
 864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 865                                       enum pipe pipe)
 866 {
 867         int reg;
 868         u32 val;
 869
 870         reg = FDI_RX_CTL(pipe);
 871         val = I915_READ(reg);
 872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 873 }
 874
 875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 876                                   enum pipe pipe)
 877 {
 878         int pp_reg, lvds_reg;
 879         u32 val;
 880         enum pipe panel_pipe = PIPE_A;
 881         bool locked = locked;
 882
 883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 884                 pp_reg = PCH_PP_CONTROL;
 885                 lvds_reg = PCH_LVDS;
 886         } else {
 887                 pp_reg = PP_CONTROL;
 888                 lvds_reg = LVDS;
 889         }
 890
 891         val = I915_READ(pp_reg);
 892         if (!(val & PANEL_POWER_ON) ||
 893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 894                 locked = false;
 895
 896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 897                 panel_pipe = PIPE_B;
 898
 899         WARN(panel_pipe == pipe && locked,
 900              "panel assertion failure, pipe %c regs locked\n",
 901              pipe_name(pipe));
 902 }
 903
 904 static void assert_pipe(struct drm_i915_private *dev_priv,
 905                         enum pipe pipe, bool state)
 906 {
 907         int reg;
 908         u32 val;
 909         bool cur_state;
 910
 911         reg = PIPECONF(pipe);
 912         val = I915_READ(reg);
 913         cur_state = !!(val & PIPECONF_ENABLE);
 914         WARN(cur_state != state,
 915              "pipe %c assertion failure (expected %s, current %s)\n",
 916              pipe_name(pipe), state_string(state), state_string(cur_state));
 917 }
 918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 920
 921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 922                                  enum plane plane)
 923 {
 924         int reg;
 925         u32 val;
 926
 927         reg = DSPCNTR(plane);
 928         val = I915_READ(reg);
 929         WARN(!(val & DISPLAY_PLANE_ENABLE),
 930              "plane %c assertion failure, should be active but is disabled\n",
 931              plane_name(plane));
 932 }
 933
 934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 935                                    enum pipe pipe)
 936 {
 937         int reg, i;
 938         u32 val;
 939         int cur_pipe;
 940
 941         /* Planes are fixed to pipes on ILK+ */
 942         if (HAS_PCH_SPLIT(dev_priv->dev))
 943                 return;
 944
 945         /* Need to check both planes against the pipe */
 946         for (i = 0; i < 2; i++) {
 947                 reg = DSPCNTR(i);
 948                 val = I915_READ(reg);
 949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 950                         DISPPLANE_SEL_PIPE_SHIFT;
 951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 953                      plane_name(i), pipe_name(pipe));
 954         }
 955 }
 956
 957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 958 {
 959         u32 val;
 960         bool enabled;
 961
 962         val = I915_READ(PCH_DREF_CONTROL);
 963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 964                             DREF_SUPERSPREAD_SOURCE_MASK));
 965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 966 }
 967
 968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 969                                        enum pipe pipe)
 970 {
 971         int reg;
 972         u32 val;
 973         bool enabled;
 974
 975         reg = TRANSCONF(pipe);
 976         val = I915_READ(reg);
 977         enabled = !!(val & TRANS_ENABLE);
 978         WARN(enabled,
 979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 980              pipe_name(pipe));
 981 }
 982
 983 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 984                                    enum pipe pipe, int reg)
 985 {
 986         u32 val = I915_READ(reg);
 987         WARN(DP_PIPE_ENABLED(val, pipe),
 988              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 989              reg, pipe_name(pipe));
 990 }
 991
 992 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 993                                      enum pipe pipe, int reg)
 994 {
 995         u32 val = I915_READ(reg);
 996         WARN(HDMI_PIPE_ENABLED(val, pipe),
 997              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 998              reg, pipe_name(pipe));
 999 }
1000
1001 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011         reg = PCH_ADPA;
1012         val = I915_READ(reg);
1013         WARN(ADPA_PIPE_ENABLED(val, pipe),
1014              "PCH VGA enabled on transcoder %c, should be disabled\n",
1015              pipe_name(pipe));
1016
1017         reg = PCH_LVDS;
1018         val = I915_READ(reg);
1019         WARN(LVDS_PIPE_ENABLED(val, pipe),
1020              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1021              pipe_name(pipe));
1022
1023         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026 }
1027
1028 /**
1029  * intel_enable_pll - enable a PLL
1030  * @dev_priv: i915 private structure
1031  * @pipe: pipe PLL to enable
1032  *
1033  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1034  * make sure the PLL reg is writable first though, since the panel write
1035  * protect mechanism may be enabled.
1036  *
1037  * Note!  This is for pre-ILK only.
1038  */
1039 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040 {
1041         int reg;
1042         u32 val;
1043
1044         /* No really, not for ILK+ */
1045         BUG_ON(dev_priv->info->gen >= 5);
1046
1047         /* PLL is protected by panel, make sure we can write it */
1048         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049                 assert_panel_unlocked(dev_priv, pipe);
1050
1051         reg = DPLL(pipe);
1052         val = I915_READ(reg);
1053         val |= DPLL_VCO_ENABLE;
1054
1055         /* We do this three times for luck */
1056         I915_WRITE(reg, val);
1057         POSTING_READ(reg);
1058         udelay(150); /* wait for warmup */
1059         I915_WRITE(reg, val);
1060         POSTING_READ(reg);
1061         udelay(150); /* wait for warmup */
1062         I915_WRITE(reg, val);
1063         POSTING_READ(reg);
1064         udelay(150); /* wait for warmup */
1065 }
1066
1067 /**
1068  * intel_disable_pll - disable a PLL
1069  * @dev_priv: i915 private structure
1070  * @pipe: pipe PLL to disable
1071  *
1072  * Disable the PLL for @pipe, making sure the pipe is off first.
1073  *
1074  * Note!  This is for pre-ILK only.
1075  */
1076 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077 {
1078         int reg;
1079         u32 val;
1080
1081         /* Don't disable pipe A or pipe A PLLs if needed */
1082         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083                 return;
1084
1085         /* Make sure the pipe isn't still relying on us */
1086         assert_pipe_disabled(dev_priv, pipe);
1087
1088         reg = DPLL(pipe);
1089         val = I915_READ(reg);
1090         val &= ~DPLL_VCO_ENABLE;
1091         I915_WRITE(reg, val);
1092         POSTING_READ(reg);
1093 }
1094
1095 /**
1096  * intel_enable_pch_pll - enable PCH PLL
1097  * @dev_priv: i915 private structure
1098  * @pipe: pipe PLL to enable
1099  *
1100  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101  * drives the transcoder clock.
1102  */
1103 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104                                  enum pipe pipe)
1105 {
1106         int reg;
1107         u32 val;
1108
1109         /* PCH only available on ILK+ */
1110         BUG_ON(dev_priv->info->gen < 5);
1111
1112         /* PCH refclock must be enabled first */
1113         assert_pch_refclk_enabled(dev_priv);
1114
1115         reg = PCH_DPLL(pipe);
1116         val = I915_READ(reg);
1117         val |= DPLL_VCO_ENABLE;
1118         I915_WRITE(reg, val);
1119         POSTING_READ(reg);
1120         udelay(200);
1121 }
1122
1123 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124                                   enum pipe pipe)
1125 {
1126         int reg;
1127         u32 val;
1128
1129         /* PCH only available on ILK+ */
1130         BUG_ON(dev_priv->info->gen < 5);
1131
1132         /* Make sure transcoder isn't still depending on us */
1133         assert_transcoder_disabled(dev_priv, pipe);
1134
1135         reg = PCH_DPLL(pipe);
1136         val = I915_READ(reg);
1137         val &= ~DPLL_VCO_ENABLE;
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(200);
1141 }
1142
1143 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144                                     enum pipe pipe)
1145 {
1146         int reg;
1147         u32 val;
1148
1149         /* PCH only available on ILK+ */
1150         BUG_ON(dev_priv->info->gen < 5);
1151
1152         /* Make sure PCH DPLL is enabled */
1153         assert_pch_pll_enabled(dev_priv, pipe);
1154
1155         /* FDI must be feeding us bits for PCH ports */
1156         assert_fdi_tx_enabled(dev_priv, pipe);
1157         assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159         reg = TRANSCONF(pipe);
1160         val = I915_READ(reg);
1161
1162         if (HAS_PCH_IBX(dev_priv->dev)) {
1163                 /*
1164                  * make the BPC in transcoder be consistent with
1165                  * that in pipeconf reg.
1166                  */
1167                 val &= ~PIPE_BPC_MASK;
1168                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169         }
1170         I915_WRITE(reg, val | TRANS_ENABLE);
1171         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173 }
1174
1175 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176                                      enum pipe pipe)
1177 {
1178         int reg;
1179         u32 val;
1180
1181         /* FDI relies on the transcoder */
1182         assert_fdi_tx_disabled(dev_priv, pipe);
1183         assert_fdi_rx_disabled(dev_priv, pipe);
1184
1185         /* Ports must be off as well */
1186         assert_pch_ports_disabled(dev_priv, pipe);
1187
1188         reg = TRANSCONF(pipe);
1189         val = I915_READ(reg);
1190         val &= ~TRANS_ENABLE;
1191         I915_WRITE(reg, val);
1192         /* wait for PCH transcoder off, transcoder state */
1193         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194                 DRM_ERROR("failed to disable transcoder\n");
1195 }
1196
1197 /**
1198  * intel_enable_pipe - enable a pipe, asserting requirements
1199  * @dev_priv: i915 private structure
1200  * @pipe: pipe to enable
1201  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1202  *
1203  * Enable @pipe, making sure that various hardware specific requirements
1204  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205  *
1206  * @pipe should be %PIPE_A or %PIPE_B.
1207  *
1208  * Will wait until the pipe is actually running (i.e. first vblank) before
1209  * returning.
1210  */
1211 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212                               bool pch_port)
1213 {
1214         int reg;
1215         u32 val;
1216
1217         /*
1218          * A pipe without a PLL won't actually be able to drive bits from
1219          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1220          * need the check.
1221          */
1222         if (!HAS_PCH_SPLIT(dev_priv->dev))
1223                 assert_pll_enabled(dev_priv, pipe);
1224         else {
1225                 if (pch_port) {
1226                         /* if driving the PCH, we need FDI enabled */
1227                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229                 }
1230                 /* FIXME: assert CPU port conditions for SNB+ */
1231         }
1232
1233         reg = PIPECONF(pipe);
1234         val = I915_READ(reg);
1235         if (val & PIPECONF_ENABLE)
1236                 return;
1237
1238         I915_WRITE(reg, val | PIPECONF_ENABLE);
1239         intel_wait_for_vblank(dev_priv->dev, pipe);
1240 }
1241
1242 /**
1243  * intel_disable_pipe - disable a pipe, asserting requirements
1244  * @dev_priv: i915 private structure
1245  * @pipe: pipe to disable
1246  *
1247  * Disable @pipe, making sure that various hardware specific requirements
1248  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249  *
1250  * @pipe should be %PIPE_A or %PIPE_B.
1251  *
1252  * Will wait until the pipe has shut down before returning.
1253  */
1254 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255                                enum pipe pipe)
1256 {
1257         int reg;
1258         u32 val;
1259
1260         /*
1261          * Make sure planes won't keep trying to pump pixels to us,
1262          * or we might hang the display.
1263          */
1264         assert_planes_disabled(dev_priv, pipe);
1265
1266         /* Don't disable pipe A or pipe A PLLs if needed */
1267         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268                 return;
1269
1270         reg = PIPECONF(pipe);
1271         val = I915_READ(reg);
1272         if ((val & PIPECONF_ENABLE) == 0)
1273                 return;
1274
1275         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1276         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277 }
1278
1279 /**
1280  * intel_enable_plane - enable a display plane on a given pipe
1281  * @dev_priv: i915 private structure
1282  * @plane: plane to enable
1283  * @pipe: pipe being fed
1284  *
1285  * Enable @plane on @pipe, making sure that @pipe is running first.
1286  */
1287 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288                                enum plane plane, enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val;
1292
1293         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294         assert_pipe_enabled(dev_priv, pipe);
1295
1296         reg = DSPCNTR(plane);
1297         val = I915_READ(reg);
1298         if (val & DISPLAY_PLANE_ENABLE)
1299                 return;
1300
1301         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1302         intel_wait_for_vblank(dev_priv->dev, pipe);
1303 }
1304
1305 /*
1306  * Plane regs are double buffered, going from enabled->disabled needs a
1307  * trigger in order to latch.  The display address reg provides this.
1308  */
1309 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310                                       enum plane plane)
1311 {
1312         u32 reg = DSPADDR(plane);
1313         I915_WRITE(reg, I915_READ(reg));
1314 }
1315
1316 /**
1317  * intel_disable_plane - disable a display plane
1318  * @dev_priv: i915 private structure
1319  * @plane: plane to disable
1320  * @pipe: pipe consuming the data
1321  *
1322  * Disable @plane; should be an independent operation.
1323  */
1324 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325                                 enum plane plane, enum pipe pipe)
1326 {
1327         int reg;
1328         u32 val;
1329
1330         reg = DSPCNTR(plane);
1331         val = I915_READ(reg);
1332         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333                 return;
1334
1335         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1336         intel_flush_display_plane(dev_priv, plane);
1337         intel_wait_for_vblank(dev_priv->dev, pipe);
1338 }
1339
1340 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341                            enum pipe pipe, int reg)
1342 {
1343         u32 val = I915_READ(reg);
1344         if (DP_PIPE_ENABLED(val, pipe))
1345                 I915_WRITE(reg, val & ~DP_PORT_EN);
1346 }
1347
1348 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349                              enum pipe pipe, int reg)
1350 {
1351         u32 val = I915_READ(reg);
1352         if (HDMI_PIPE_ENABLED(val, pipe))
1353                 I915_WRITE(reg, val & ~PORT_ENABLE);
1354 }
1355
1356 /* Disable any ports connected to this transcoder */
1357 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358                                     enum pipe pipe)
1359 {
1360         u32 reg, val;
1361
1362         val = I915_READ(PCH_PP_CONTROL);
1363         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369         reg = PCH_ADPA;
1370         val = I915_READ(reg);
1371         if (ADPA_PIPE_ENABLED(val, pipe))
1372                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374         reg = PCH_LVDS;
1375         val = I915_READ(reg);
1376         if (LVDS_PIPE_ENABLED(val, pipe)) {
1377                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378                 POSTING_READ(reg);
1379                 udelay(100);
1380         }
1381
1382         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384         disable_pch_hdmi(dev_priv, pipe, HDMID);
1385 }
1386
1387 static void i8xx_disable_fbc(struct drm_device *dev)
1388 {
1389         struct drm_i915_private *dev_priv = dev->dev_private;
1390         u32 fbc_ctl;
1391
1392         /* Disable compression */
1393         fbc_ctl = I915_READ(FBC_CONTROL);
1394         if ((fbc_ctl & FBC_CTL_EN) == 0)
1395                 return;
1396
1397         fbc_ctl &= ~FBC_CTL_EN;
1398         I915_WRITE(FBC_CONTROL, fbc_ctl);
1399
1400         /* Wait for compressing bit to clear */
1401         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402                 DRM_DEBUG_KMS("FBC idle timed out\n");
1403                 return;
1404         }
1405
1406         DRM_DEBUG_KMS("disabled FBC\n");
1407 }
1408
1409 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1410 {
1411         struct drm_device *dev = crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_framebuffer *fb = crtc->fb;
1414         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1415         struct drm_i915_gem_object *obj = intel_fb->obj;
1416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1417         int cfb_pitch;
1418         int plane, i;
1419         u32 fbc_ctl, fbc_ctl2;
1420
1421         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1422         if (fb->pitch < cfb_pitch)
1423                 cfb_pitch = fb->pitch;
1424
1425         /* FBC_CTL wants 64B units */
1426         cfb_pitch = (cfb_pitch / 64) - 1;
1427         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1428
1429         /* Clear old tags */
1430         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1431                 I915_WRITE(FBC_TAG + (i * 4), 0);
1432
1433         /* Set it up... */
1434         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1435         fbc_ctl2 |= plane;
1436         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1437         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1438
1439         /* enable it... */
1440         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1441         if (IS_I945GM(dev))
1442                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1443         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1444         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1445         fbc_ctl |= obj->fence_reg;
1446         I915_WRITE(FBC_CONTROL, fbc_ctl);
1447
1448         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1449                       cfb_pitch, crtc->y, intel_crtc->plane);
1450 }
1451
1452 static bool i8xx_fbc_enabled(struct drm_device *dev)
1453 {
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455
1456         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1457 }
1458
1459 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1460 {
1461         struct drm_device *dev = crtc->dev;
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463         struct drm_framebuffer *fb = crtc->fb;
1464         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1465         struct drm_i915_gem_object *obj = intel_fb->obj;
1466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1467         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1468         unsigned long stall_watermark = 200;
1469         u32 dpfc_ctl;
1470
1471         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1472         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1473         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1474
1475         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1476                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1477                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1478         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1479
1480         /* enable it... */
1481         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1482
1483         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1484 }
1485
1486 static void g4x_disable_fbc(struct drm_device *dev)
1487 {
1488         struct drm_i915_private *dev_priv = dev->dev_private;
1489         u32 dpfc_ctl;
1490
1491         /* Disable compression */
1492         dpfc_ctl = I915_READ(DPFC_CONTROL);
1493         if (dpfc_ctl & DPFC_CTL_EN) {
1494                 dpfc_ctl &= ~DPFC_CTL_EN;
1495                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1496
1497                 DRM_DEBUG_KMS("disabled FBC\n");
1498         }
1499 }
1500
1501 static bool g4x_fbc_enabled(struct drm_device *dev)
1502 {
1503         struct drm_i915_private *dev_priv = dev->dev_private;
1504
1505         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1506 }
1507
1508 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1509 {
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         u32 blt_ecoskpd;
1512
1513         /* Make sure blitter notifies FBC of writes */
1514         gen6_gt_force_wake_get(dev_priv);
1515         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1516         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1517                 GEN6_BLITTER_LOCK_SHIFT;
1518         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1519         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1520         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1521         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1522                          GEN6_BLITTER_LOCK_SHIFT);
1523         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1524         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1525         gen6_gt_force_wake_put(dev_priv);
1526 }
1527
1528 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1529 {
1530         struct drm_device *dev = crtc->dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct drm_framebuffer *fb = crtc->fb;
1533         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1534         struct drm_i915_gem_object *obj = intel_fb->obj;
1535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1536         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1537         unsigned long stall_watermark = 200;
1538         u32 dpfc_ctl;
1539
1540         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1541         dpfc_ctl &= DPFC_RESERVED;
1542         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1543         /* Set persistent mode for front-buffer rendering, ala X. */
1544         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1545         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1546         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1547
1548         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1549                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1550                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1551         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1552         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1553         /* enable it... */
1554         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1555
1556         if (IS_GEN6(dev)) {
1557                 I915_WRITE(SNB_DPFC_CTL_SA,
1558                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1559                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1560                 sandybridge_blit_fbc_update(dev);
1561         }
1562
1563         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1564 }
1565
1566 static void ironlake_disable_fbc(struct drm_device *dev)
1567 {
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         u32 dpfc_ctl;
1570
1571         /* Disable compression */
1572         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1573         if (dpfc_ctl & DPFC_CTL_EN) {
1574                 dpfc_ctl &= ~DPFC_CTL_EN;
1575                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1576
1577                 DRM_DEBUG_KMS("disabled FBC\n");
1578         }
1579 }
1580
1581 static bool ironlake_fbc_enabled(struct drm_device *dev)
1582 {
1583         struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1586 }
1587
1588 bool intel_fbc_enabled(struct drm_device *dev)
1589 {
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592         if (!dev_priv->display.fbc_enabled)
1593                 return false;
1594
1595         return dev_priv->display.fbc_enabled(dev);
1596 }
1597
1598 static void intel_fbc_work_fn(struct work_struct *__work)
1599 {
1600         struct intel_fbc_work *work =
1601                 container_of(to_delayed_work(__work),
1602                              struct intel_fbc_work, work);
1603         struct drm_device *dev = work->crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605
1606         mutex_lock(&dev->struct_mutex);
1607         if (work == dev_priv->fbc_work) {
1608                 /* Double check that we haven't switched fb without cancelling
1609                  * the prior work.
1610                  */
1611                 if (work->crtc->fb == work->fb) {
1612                         dev_priv->display.enable_fbc(work->crtc,
1613                                                      work->interval);
1614
1615                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1616                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1617                         dev_priv->cfb_y = work->crtc->y;
1618                 }
1619
1620                 dev_priv->fbc_work = NULL;
1621         }
1622         mutex_unlock(&dev->struct_mutex);
1623
1624         kfree(work);
1625 }
1626
1627 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1628 {
1629         if (dev_priv->fbc_work == NULL)
1630                 return;
1631
1632         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1633
1634         /* Synchronisation is provided by struct_mutex and checking of
1635          * dev_priv->fbc_work, so we can perform the cancellation
1636          * entirely asynchronously.
1637          */
1638         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1639                 /* tasklet was killed before being run, clean up */
1640                 kfree(dev_priv->fbc_work);
1641
1642         /* Mark the work as no longer wanted so that if it does
1643          * wake-up (because the work was already running and waiting
1644          * for our mutex), it will discover that is no longer
1645          * necessary to run.
1646          */
1647         dev_priv->fbc_work = NULL;
1648 }
1649
1650 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1651 {
1652         struct intel_fbc_work *work;
1653         struct drm_device *dev = crtc->dev;
1654         struct drm_i915_private *dev_priv = dev->dev_private;
1655
1656         if (!dev_priv->display.enable_fbc)
1657                 return;
1658
1659         intel_cancel_fbc_work(dev_priv);
1660
1661         work = kzalloc(sizeof *work, GFP_KERNEL);
1662         if (work == NULL) {
1663                 dev_priv->display.enable_fbc(crtc, interval);
1664                 return;
1665         }
1666
1667         work->crtc = crtc;
1668         work->fb = crtc->fb;
1669         work->interval = interval;
1670         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1671
1672         dev_priv->fbc_work = work;
1673
1674         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1675
1676         /* Delay the actual enabling to let pageflipping cease and the
1677          * display to settle before starting the compression. Note that
1678          * this delay also serves a second purpose: it allows for a
1679          * vblank to pass after disabling the FBC before we attempt
1680          * to modify the control registers.
1681          *
1682          * A more complicated solution would involve tracking vblanks
1683          * following the termination of the page-flipping sequence
1684          * and indeed performing the enable as a co-routine and not
1685          * waiting synchronously upon the vblank.
1686          */
1687         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1688 }
1689
1690 void intel_disable_fbc(struct drm_device *dev)
1691 {
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693
1694         intel_cancel_fbc_work(dev_priv);
1695
1696         if (!dev_priv->display.disable_fbc)
1697                 return;
1698
1699         dev_priv->display.disable_fbc(dev);
1700         dev_priv->cfb_plane = -1;
1701 }
1702
1703 /**
1704  * intel_update_fbc - enable/disable FBC as needed
1705  * @dev: the drm_device
1706  *
1707  * Set up the framebuffer compression hardware at mode set time.  We
1708  * enable it if possible:
1709  *   - plane A only (on pre-965)
1710  *   - no pixel mulitply/line duplication
1711  *   - no alpha buffer discard
1712  *   - no dual wide
1713  *   - framebuffer <= 2048 in width, 1536 in height
1714  *
1715  * We can't assume that any compression will take place (worst case),
1716  * so the compressed buffer has to be the same size as the uncompressed
1717  * one.  It also must reside (along with the line length buffer) in
1718  * stolen memory.
1719  *
1720  * We need to enable/disable FBC on a global basis.
1721  */
1722 static void intel_update_fbc(struct drm_device *dev)
1723 {
1724         struct drm_i915_private *dev_priv = dev->dev_private;
1725         struct drm_crtc *crtc = NULL, *tmp_crtc;
1726         struct intel_crtc *intel_crtc;
1727         struct drm_framebuffer *fb;
1728         struct intel_framebuffer *intel_fb;
1729         struct drm_i915_gem_object *obj;
1730
1731         DRM_DEBUG_KMS("\n");
1732
1733         if (!i915_powersave)
1734                 return;
1735
1736         if (!I915_HAS_FBC(dev))
1737                 return;
1738
1739         /*
1740          * If FBC is already on, we just have to verify that we can
1741          * keep it that way...
1742          * Need to disable if:
1743          *   - more than one pipe is active
1744          *   - changing FBC params (stride, fence, mode)
1745          *   - new fb is too large to fit in compressed buffer
1746          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1747          */
1748         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1749                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1750                         if (crtc) {
1751                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1752                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1753                                 goto out_disable;
1754                         }
1755                         crtc = tmp_crtc;
1756                 }
1757         }
1758
1759         if (!crtc || crtc->fb == NULL) {
1760                 DRM_DEBUG_KMS("no output, disabling\n");
1761                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1762                 goto out_disable;
1763         }
1764
1765         intel_crtc = to_intel_crtc(crtc);
1766         fb = crtc->fb;
1767         intel_fb = to_intel_framebuffer(fb);
1768         obj = intel_fb->obj;
1769
1770         if (!i915_enable_fbc) {
1771                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1772                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1773                 goto out_disable;
1774         }
1775         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1776                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1777                               "compression\n");
1778                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1779                 goto out_disable;
1780         }
1781         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1782             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1783                 DRM_DEBUG_KMS("mode incompatible with compression, "
1784                               "disabling\n");
1785                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1786                 goto out_disable;
1787         }
1788         if ((crtc->mode.hdisplay > 2048) ||
1789             (crtc->mode.vdisplay > 1536)) {
1790                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1791                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1792                 goto out_disable;
1793         }
1794         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1795                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1796                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1797                 goto out_disable;
1798         }
1799
1800         /* The use of a CPU fence is mandatory in order to detect writes
1801          * by the CPU to the scanout and trigger updates to the FBC.
1802          */
1803         if (obj->tiling_mode != I915_TILING_X ||
1804             obj->fence_reg == I915_FENCE_REG_NONE) {
1805                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1806                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1807                 goto out_disable;
1808         }
1809
1810         /* If the kernel debugger is active, always disable compression */
1811         if (in_dbg_master())
1812                 goto out_disable;
1813
1814         /* If the scanout has not changed, don't modify the FBC settings.
1815          * Note that we make the fundamental assumption that the fb->obj
1816          * cannot be unpinned (and have its GTT offset and fence revoked)
1817          * without first being decoupled from the scanout and FBC disabled.
1818          */
1819         if (dev_priv->cfb_plane == intel_crtc->plane &&
1820             dev_priv->cfb_fb == fb->base.id &&
1821             dev_priv->cfb_y == crtc->y)
1822                 return;
1823
1824         if (intel_fbc_enabled(dev)) {
1825                 /* We update FBC along two paths, after changing fb/crtc
1826                  * configuration (modeswitching) and after page-flipping
1827                  * finishes. For the latter, we know that not only did
1828                  * we disable the FBC at the start of the page-flip
1829                  * sequence, but also more than one vblank has passed.
1830                  *
1831                  * For the former case of modeswitching, it is possible
1832                  * to switch between two FBC valid configurations
1833                  * instantaneously so we do need to disable the FBC
1834                  * before we can modify its control registers. We also
1835                  * have to wait for the next vblank for that to take
1836                  * effect. However, since we delay enabling FBC we can
1837                  * assume that a vblank has passed since disabling and
1838                  * that we can safely alter the registers in the deferred
1839                  * callback.
1840                  *
1841                  * In the scenario that we go from a valid to invalid
1842                  * and then back to valid FBC configuration we have
1843                  * no strict enforcement that a vblank occurred since
1844                  * disabling the FBC. However, along all current pipe
1845                  * disabling paths we do need to wait for a vblank at
1846                  * some point. And we wait before enabling FBC anyway.
1847                  */
1848                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1849                 intel_disable_fbc(dev);
1850         }
1851
1852         intel_enable_fbc(crtc, 500);
1853         return;
1854
1855 out_disable:
1856         /* Multiple disables should be harmless */
1857         if (intel_fbc_enabled(dev)) {
1858                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1859                 intel_disable_fbc(dev);
1860         }
1861 }
1862
1863 int
1864 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1865                            struct drm_i915_gem_object *obj,
1866                            struct intel_ring_buffer *pipelined)
1867 {
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         u32 alignment;
1870         int ret;
1871
1872         switch (obj->tiling_mode) {
1873         case I915_TILING_NONE:
1874                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1875                         alignment = 128 * 1024;
1876                 else if (INTEL_INFO(dev)->gen >= 4)
1877                         alignment = 4 * 1024;
1878                 else
1879                         alignment = 64 * 1024;
1880                 break;
1881         case I915_TILING_X:
1882                 /* pin() will align the object as required by fence */
1883                 alignment = 0;
1884                 break;
1885         case I915_TILING_Y:
1886                 /* FIXME: Is this true? */
1887                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1888                 return -EINVAL;
1889         default:
1890                 BUG();
1891         }
1892
1893         dev_priv->mm.interruptible = false;
1894         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1895         if (ret)
1896                 goto err_interruptible;
1897
1898         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1899          * fence, whereas 965+ only requires a fence if using
1900          * framebuffer compression.  For simplicity, we always install
1901          * a fence as the cost is not that onerous.
1902          */
1903         if (obj->tiling_mode != I915_TILING_NONE) {
1904                 ret = i915_gem_object_get_fence(obj, pipelined);
1905                 if (ret)
1906                         goto err_unpin;
1907         }
1908
1909         dev_priv->mm.interruptible = true;
1910         return 0;
1911
1912 err_unpin:
1913         i915_gem_object_unpin(obj);
1914 err_interruptible:
1915         dev_priv->mm.interruptible = true;
1916         return ret;
1917 }
1918
1919 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1920                              int x, int y)
1921 {
1922         struct drm_device *dev = crtc->dev;
1923         struct drm_i915_private *dev_priv = dev->dev_private;
1924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1925         struct intel_framebuffer *intel_fb;
1926         struct drm_i915_gem_object *obj;
1927         int plane = intel_crtc->plane;
1928         unsigned long Start, Offset;
1929         u32 dspcntr;
1930         u32 reg;
1931
1932         switch (plane) {
1933         case 0:
1934         case 1:
1935                 break;
1936         default:
1937                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1938                 return -EINVAL;
1939         }
1940
1941         intel_fb = to_intel_framebuffer(fb);
1942         obj = intel_fb->obj;
1943
1944         reg = DSPCNTR(plane);
1945         dspcntr = I915_READ(reg);
1946         /* Mask out pixel format bits in case we change it */
1947         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1948         switch (fb->bits_per_pixel) {
1949         case 8:
1950                 dspcntr |= DISPPLANE_8BPP;
1951                 break;
1952         case 16:
1953                 if (fb->depth == 15)
1954                         dspcntr |= DISPPLANE_15_16BPP;
1955                 else
1956                         dspcntr |= DISPPLANE_16BPP;
1957                 break;
1958         case 24:
1959         case 32:
1960                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1961                 break;
1962         default:
1963                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1964                 return -EINVAL;
1965         }
1966         if (INTEL_INFO(dev)->gen >= 4) {
1967                 if (obj->tiling_mode != I915_TILING_NONE)
1968                         dspcntr |= DISPPLANE_TILED;
1969                 else
1970                         dspcntr &= ~DISPPLANE_TILED;
1971         }
1972
1973         I915_WRITE(reg, dspcntr);
1974
1975         Start = obj->gtt_offset;
1976         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1977
1978         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1979                       Start, Offset, x, y, fb->pitch);
1980         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1981         if (INTEL_INFO(dev)->gen >= 4) {
1982                 I915_WRITE(DSPSURF(plane), Start);
1983                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1984                 I915_WRITE(DSPADDR(plane), Offset);
1985         } else
1986                 I915_WRITE(DSPADDR(plane), Start + Offset);
1987         POSTING_READ(reg);
1988
1989         return 0;
1990 }
1991
1992 static int ironlake_update_plane(struct drm_crtc *crtc,
1993                                  struct drm_framebuffer *fb, int x, int y)
1994 {
1995         struct drm_device *dev = crtc->dev;
1996         struct drm_i915_private *dev_priv = dev->dev_private;
1997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998         struct intel_framebuffer *intel_fb;
1999         struct drm_i915_gem_object *obj;
2000         int plane = intel_crtc->plane;
2001         unsigned long Start, Offset;
2002         u32 dspcntr;
2003         u32 reg;
2004
2005         switch (plane) {
2006         case 0:
2007         case 1:
2008                 break;
2009         default:
2010                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011                 return -EINVAL;
2012         }
2013
2014         intel_fb = to_intel_framebuffer(fb);
2015         obj = intel_fb->obj;
2016
2017         reg = DSPCNTR(plane);
2018         dspcntr = I915_READ(reg);
2019         /* Mask out pixel format bits in case we change it */
2020         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021         switch (fb->bits_per_pixel) {
2022         case 8:
2023                 dspcntr |= DISPPLANE_8BPP;
2024                 break;
2025         case 16:
2026                 if (fb->depth != 16)
2027                         return -EINVAL;
2028
2029                 dspcntr |= DISPPLANE_16BPP;
2030                 break;
2031         case 24:
2032         case 32:
2033                 if (fb->depth == 24)
2034                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2035                 else if (fb->depth == 30)
2036                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2037                 else
2038                         return -EINVAL;
2039                 break;
2040         default:
2041                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2042                 return -EINVAL;
2043         }
2044
2045         if (obj->tiling_mode != I915_TILING_NONE)
2046                 dspcntr |= DISPPLANE_TILED;
2047         else
2048                 dspcntr &= ~DISPPLANE_TILED;
2049
2050         /* must disable */
2051         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2052
2053         I915_WRITE(reg, dspcntr);
2054
2055         Start = obj->gtt_offset;
2056         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2057
2058         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059                       Start, Offset, x, y, fb->pitch);
2060         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2061         I915_WRITE(DSPSURF(plane), Start);
2062         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2063         I915_WRITE(DSPADDR(plane), Offset);
2064         POSTING_READ(reg);
2065
2066         return 0;
2067 }
2068
2069 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2070 static int
2071 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2072                            int x, int y, enum mode_set_atomic state)
2073 {
2074         struct drm_device *dev = crtc->dev;
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         int ret;
2077
2078         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2079         if (ret)
2080                 return ret;
2081
2082         intel_update_fbc(dev);
2083         intel_increase_pllclock(crtc);
2084
2085         return 0;
2086 }
2087
2088 static int
2089 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2090                     struct drm_framebuffer *old_fb)
2091 {
2092         struct drm_device *dev = crtc->dev;
2093         struct drm_i915_master_private *master_priv;
2094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095         int ret;
2096
2097         /* no fb bound */
2098         if (!crtc->fb) {
2099                 DRM_DEBUG_KMS("No FB bound\n");
2100                 return 0;
2101         }
2102
2103         switch (intel_crtc->plane) {
2104         case 0:
2105         case 1:
2106                 break;
2107         default:
2108                 return -EINVAL;
2109         }
2110
2111         mutex_lock(&dev->struct_mutex);
2112         ret = intel_pin_and_fence_fb_obj(dev,
2113                                          to_intel_framebuffer(crtc->fb)->obj,
2114                                          NULL);
2115         if (ret != 0) {
2116                 mutex_unlock(&dev->struct_mutex);
2117                 return ret;
2118         }
2119
2120         if (old_fb) {
2121                 struct drm_i915_private *dev_priv = dev->dev_private;
2122                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2123
2124                 wait_event(dev_priv->pending_flip_queue,
2125                            atomic_read(&dev_priv->mm.wedged) ||
2126                            atomic_read(&obj->pending_flip) == 0);
2127
2128                 /* Big Hammer, we also need to ensure that any pending
2129                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2130                  * current scanout is retired before unpinning the old
2131                  * framebuffer.
2132                  *
2133                  * This should only fail upon a hung GPU, in which case we
2134                  * can safely continue.
2135                  */
2136                 ret = i915_gem_object_finish_gpu(obj);
2137                 (void) ret;
2138         }
2139
2140         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2141                                          LEAVE_ATOMIC_MODE_SET);
2142         if (ret) {
2143                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2144                 mutex_unlock(&dev->struct_mutex);
2145                 return ret;
2146         }
2147
2148         if (old_fb) {
2149                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2150                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2151         }
2152
2153         mutex_unlock(&dev->struct_mutex);
2154
2155         if (!dev->primary->master)
2156                 return 0;
2157
2158         master_priv = dev->primary->master->driver_priv;
2159         if (!master_priv->sarea_priv)
2160                 return 0;
2161
2162         if (intel_crtc->pipe) {
2163                 master_priv->sarea_priv->pipeB_x = x;
2164                 master_priv->sarea_priv->pipeB_y = y;
2165         } else {
2166                 master_priv->sarea_priv->pipeA_x = x;
2167                 master_priv->sarea_priv->pipeA_y = y;
2168         }
2169
2170         return 0;
2171 }
2172
2173 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         u32 dpa_ctl;
2178
2179         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2180         dpa_ctl = I915_READ(DP_A);
2181         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2182
2183         if (clock < 200000) {
2184                 u32 temp;
2185                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2186                 /* workaround for 160Mhz:
2187                    1) program 0x4600c bits 15:0 = 0x8124
2188                    2) program 0x46010 bit 0 = 1
2189                    3) program 0x46034 bit 24 = 1
2190                    4) program 0x64000 bit 14 = 1
2191                    */
2192                 temp = I915_READ(0x4600c);
2193                 temp &= 0xffff0000;
2194                 I915_WRITE(0x4600c, temp | 0x8124);
2195
2196                 temp = I915_READ(0x46010);
2197                 I915_WRITE(0x46010, temp | 1);
2198
2199                 temp = I915_READ(0x46034);
2200                 I915_WRITE(0x46034, temp | (1 << 24));
2201         } else {
2202                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2203         }
2204         I915_WRITE(DP_A, dpa_ctl);
2205
2206         POSTING_READ(DP_A);
2207         udelay(500);
2208 }
2209
2210 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2211 {
2212         struct drm_device *dev = crtc->dev;
2213         struct drm_i915_private *dev_priv = dev->dev_private;
2214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215         int pipe = intel_crtc->pipe;
2216         u32 reg, temp;
2217
2218         /* enable normal train */
2219         reg = FDI_TX_CTL(pipe);
2220         temp = I915_READ(reg);
2221         if (IS_IVYBRIDGE(dev)) {
2222                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2223                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2224         } else {
2225                 temp &= ~FDI_LINK_TRAIN_NONE;
2226                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2227         }
2228         I915_WRITE(reg, temp);
2229
2230         reg = FDI_RX_CTL(pipe);
2231         temp = I915_READ(reg);
2232         if (HAS_PCH_CPT(dev)) {
2233                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2234                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2235         } else {
2236                 temp &= ~FDI_LINK_TRAIN_NONE;
2237                 temp |= FDI_LINK_TRAIN_NONE;
2238         }
2239         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2240
2241         /* wait one idle pattern time */
2242         POSTING_READ(reg);
2243         udelay(1000);
2244
2245         /* IVB wants error correction enabled */
2246         if (IS_IVYBRIDGE(dev))
2247                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2248                            FDI_FE_ERRC_ENABLE);
2249 }
2250
2251 /* The FDI link training functions for ILK/Ibexpeak. */
2252 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2253 {
2254         struct drm_device *dev = crtc->dev;
2255         struct drm_i915_private *dev_priv = dev->dev_private;
2256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257         int pipe = intel_crtc->pipe;
2258         int plane = intel_crtc->plane;
2259         u32 reg, temp, tries;
2260
2261         /* FDI needs bits from pipe & plane first */
2262         assert_pipe_enabled(dev_priv, pipe);
2263         assert_plane_enabled(dev_priv, plane);
2264
2265         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2266            for train result */
2267         reg = FDI_RX_IMR(pipe);
2268         temp = I915_READ(reg);
2269         temp &= ~FDI_RX_SYMBOL_LOCK;
2270         temp &= ~FDI_RX_BIT_LOCK;
2271         I915_WRITE(reg, temp);
2272         I915_READ(reg);
2273         udelay(150);
2274
2275         /* enable CPU FDI TX and PCH FDI RX */
2276         reg = FDI_TX_CTL(pipe);
2277         temp = I915_READ(reg);
2278         temp &= ~(7 << 19);
2279         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2280         temp &= ~FDI_LINK_TRAIN_NONE;
2281         temp |= FDI_LINK_TRAIN_PATTERN_1;
2282         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2283
2284         reg = FDI_RX_CTL(pipe);
2285         temp = I915_READ(reg);
2286         temp &= ~FDI_LINK_TRAIN_NONE;
2287         temp |= FDI_LINK_TRAIN_PATTERN_1;
2288         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2289
2290         POSTING_READ(reg);
2291         udelay(150);
2292
2293         /* Ironlake workaround, enable clock pointer after FDI enable*/
2294         if (HAS_PCH_IBX(dev)) {
2295                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2296                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2297                            FDI_RX_PHASE_SYNC_POINTER_EN);
2298         }
2299
2300         reg = FDI_RX_IIR(pipe);
2301         for (tries = 0; tries < 5; tries++) {
2302                 temp = I915_READ(reg);
2303                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2304
2305                 if ((temp & FDI_RX_BIT_LOCK)) {
2306                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2307                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2308                         break;
2309                 }
2310         }
2311         if (tries == 5)
2312                 DRM_ERROR("FDI train 1 fail!\n");
2313
2314         /* Train 2 */
2315         reg = FDI_TX_CTL(pipe);
2316         temp = I915_READ(reg);
2317         temp &= ~FDI_LINK_TRAIN_NONE;
2318         temp |= FDI_LINK_TRAIN_PATTERN_2;
2319         I915_WRITE(reg, temp);
2320
2321         reg = FDI_RX_CTL(pipe);
2322         temp = I915_READ(reg);
2323         temp &= ~FDI_LINK_TRAIN_NONE;
2324         temp |= FDI_LINK_TRAIN_PATTERN_2;
2325         I915_WRITE(reg, temp);
2326
2327         POSTING_READ(reg);
2328         udelay(150);
2329
2330         reg = FDI_RX_IIR(pipe);
2331         for (tries = 0; tries < 5; tries++) {
2332                 temp = I915_READ(reg);
2333                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2334
2335                 if (temp & FDI_RX_SYMBOL_LOCK) {
2336                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2337                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2338                         break;
2339                 }
2340         }
2341         if (tries == 5)
2342                 DRM_ERROR("FDI train 2 fail!\n");
2343
2344         DRM_DEBUG_KMS("FDI train done\n");
2345
2346 }
2347
2348 static const int snb_b_fdi_train_param [] = {
2349         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2350         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2351         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2352         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2353 };
2354
2355 /* The FDI link training functions for SNB/Cougarpoint. */
2356 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2357 {
2358         struct drm_device *dev = crtc->dev;
2359         struct drm_i915_private *dev_priv = dev->dev_private;
2360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2361         int pipe = intel_crtc->pipe;
2362         u32 reg, temp, i;
2363
2364         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2365            for train result */
2366         reg = FDI_RX_IMR(pipe);
2367         temp = I915_READ(reg);
2368         temp &= ~FDI_RX_SYMBOL_LOCK;
2369         temp &= ~FDI_RX_BIT_LOCK;
2370         I915_WRITE(reg, temp);
2371
2372         POSTING_READ(reg);
2373         udelay(150);
2374
2375         /* enable CPU FDI TX and PCH FDI RX */
2376         reg = FDI_TX_CTL(pipe);
2377         temp = I915_READ(reg);
2378         temp &= ~(7 << 19);
2379         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2380         temp &= ~FDI_LINK_TRAIN_NONE;
2381         temp |= FDI_LINK_TRAIN_PATTERN_1;
2382         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2383         /* SNB-B */
2384         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2385         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2386
2387         reg = FDI_RX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         if (HAS_PCH_CPT(dev)) {
2390                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2392         } else {
2393                 temp &= ~FDI_LINK_TRAIN_NONE;
2394                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2395         }
2396         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2397
2398         POSTING_READ(reg);
2399         udelay(150);
2400
2401         for (i = 0; i < 4; i++ ) {
2402                 reg = FDI_TX_CTL(pipe);
2403                 temp = I915_READ(reg);
2404                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2405                 temp |= snb_b_fdi_train_param[i];
2406                 I915_WRITE(reg, temp);
2407
2408                 POSTING_READ(reg);
2409                 udelay(500);
2410
2411                 reg = FDI_RX_IIR(pipe);
2412                 temp = I915_READ(reg);
2413                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2414
2415                 if (temp & FDI_RX_BIT_LOCK) {
2416                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2417                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2418                         break;
2419                 }
2420         }
2421         if (i == 4)
2422                 DRM_ERROR("FDI train 1 fail!\n");
2423
2424         /* Train 2 */
2425         reg = FDI_TX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_LINK_TRAIN_NONE;
2428         temp |= FDI_LINK_TRAIN_PATTERN_2;
2429         if (IS_GEN6(dev)) {
2430                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2431                 /* SNB-B */
2432                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2433         }
2434         I915_WRITE(reg, temp);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         if (HAS_PCH_CPT(dev)) {
2439                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2440                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2441         } else {
2442                 temp &= ~FDI_LINK_TRAIN_NONE;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2444         }
2445         I915_WRITE(reg, temp);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         for (i = 0; i < 4; i++ ) {
2451                 reg = FDI_TX_CTL(pipe);
2452                 temp = I915_READ(reg);
2453                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2454                 temp |= snb_b_fdi_train_param[i];
2455                 I915_WRITE(reg, temp);
2456
2457                 POSTING_READ(reg);
2458                 udelay(500);
2459
2460                 reg = FDI_RX_IIR(pipe);
2461                 temp = I915_READ(reg);
2462                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2463
2464                 if (temp & FDI_RX_SYMBOL_LOCK) {
2465                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2466                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2467                         break;
2468                 }
2469         }
2470         if (i == 4)
2471                 DRM_ERROR("FDI train 2 fail!\n");
2472
2473         DRM_DEBUG_KMS("FDI train done.\n");
2474 }
2475
2476 /* Manual link training for Ivy Bridge A0 parts */
2477 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2478 {
2479         struct drm_device *dev = crtc->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482         int pipe = intel_crtc->pipe;
2483         u32 reg, temp, i;
2484
2485         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2486            for train result */
2487         reg = FDI_RX_IMR(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~FDI_RX_SYMBOL_LOCK;
2490         temp &= ~FDI_RX_BIT_LOCK;
2491         I915_WRITE(reg, temp);
2492
2493         POSTING_READ(reg);
2494         udelay(150);
2495
2496         /* enable CPU FDI TX and PCH FDI RX */
2497         reg = FDI_TX_CTL(pipe);
2498         temp = I915_READ(reg);
2499         temp &= ~(7 << 19);
2500         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2501         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2502         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2503         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2506
2507         reg = FDI_RX_CTL(pipe);
2508         temp = I915_READ(reg);
2509         temp &= ~FDI_LINK_TRAIN_AUTO;
2510         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2513
2514         POSTING_READ(reg);
2515         udelay(150);
2516
2517         for (i = 0; i < 4; i++ ) {
2518                 reg = FDI_TX_CTL(pipe);
2519                 temp = I915_READ(reg);
2520                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2521                 temp |= snb_b_fdi_train_param[i];
2522                 I915_WRITE(reg, temp);
2523
2524                 POSTING_READ(reg);
2525                 udelay(500);
2526
2527                 reg = FDI_RX_IIR(pipe);
2528                 temp = I915_READ(reg);
2529                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2530
2531                 if (temp & FDI_RX_BIT_LOCK ||
2532                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2533                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2534                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2535                         break;
2536                 }
2537         }
2538         if (i == 4)
2539                 DRM_ERROR("FDI train 1 fail!\n");
2540
2541         /* Train 2 */
2542         reg = FDI_TX_CTL(pipe);
2543         temp = I915_READ(reg);
2544         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2545         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2546         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2548         I915_WRITE(reg, temp);
2549
2550         reg = FDI_RX_CTL(pipe);
2551         temp = I915_READ(reg);
2552         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2554         I915_WRITE(reg, temp);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         for (i = 0; i < 4; i++ ) {
2560                 reg = FDI_TX_CTL(pipe);
2561                 temp = I915_READ(reg);
2562                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563                 temp |= snb_b_fdi_train_param[i];
2564                 I915_WRITE(reg, temp);
2565
2566                 POSTING_READ(reg);
2567                 udelay(500);
2568
2569                 reg = FDI_RX_IIR(pipe);
2570                 temp = I915_READ(reg);
2571                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573                 if (temp & FDI_RX_SYMBOL_LOCK) {
2574                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2576                         break;
2577                 }
2578         }
2579         if (i == 4)
2580                 DRM_ERROR("FDI train 2 fail!\n");
2581
2582         DRM_DEBUG_KMS("FDI train done.\n");
2583 }
2584
2585 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2586 {
2587         struct drm_device *dev = crtc->dev;
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2590         int pipe = intel_crtc->pipe;
2591         u32 reg, temp;
2592
2593         /* Write the TU size bits so error detection works */
2594         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2595                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2596
2597         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2598         reg = FDI_RX_CTL(pipe);
2599         temp = I915_READ(reg);
2600         temp &= ~((0x7 << 19) | (0x7 << 16));
2601         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2602         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2603         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2604
2605         POSTING_READ(reg);
2606         udelay(200);
2607
2608         /* Switch from Rawclk to PCDclk */
2609         temp = I915_READ(reg);
2610         I915_WRITE(reg, temp | FDI_PCDCLK);
2611
2612         POSTING_READ(reg);
2613         udelay(200);
2614
2615         /* Enable CPU FDI TX PLL, always on for Ironlake */
2616         reg = FDI_TX_CTL(pipe);
2617         temp = I915_READ(reg);
2618         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2619                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2620
2621                 POSTING_READ(reg);
2622                 udelay(100);
2623         }
2624 }
2625
2626 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2627 {
2628         struct drm_device *dev = crtc->dev;
2629         struct drm_i915_private *dev_priv = dev->dev_private;
2630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2631         int pipe = intel_crtc->pipe;
2632         u32 reg, temp;
2633
2634         /* disable CPU FDI tx and PCH FDI rx */
2635         reg = FDI_TX_CTL(pipe);
2636         temp = I915_READ(reg);
2637         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2638         POSTING_READ(reg);
2639
2640         reg = FDI_RX_CTL(pipe);
2641         temp = I915_READ(reg);
2642         temp &= ~(0x7 << 16);
2643         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2644         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2645
2646         POSTING_READ(reg);
2647         udelay(100);
2648
2649         /* Ironlake workaround, disable clock pointer after downing FDI */
2650         if (HAS_PCH_IBX(dev)) {
2651                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2652                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2653                            I915_READ(FDI_RX_CHICKEN(pipe) &
2654                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2655         }
2656
2657         /* still set train pattern 1 */
2658         reg = FDI_TX_CTL(pipe);
2659         temp = I915_READ(reg);
2660         temp &= ~FDI_LINK_TRAIN_NONE;
2661         temp |= FDI_LINK_TRAIN_PATTERN_1;
2662         I915_WRITE(reg, temp);
2663
2664         reg = FDI_RX_CTL(pipe);
2665         temp = I915_READ(reg);
2666         if (HAS_PCH_CPT(dev)) {
2667                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2669         } else {
2670                 temp &= ~FDI_LINK_TRAIN_NONE;
2671                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2672         }
2673         /* BPC in FDI rx is consistent with that in PIPECONF */
2674         temp &= ~(0x07 << 16);
2675         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2676         I915_WRITE(reg, temp);
2677
2678         POSTING_READ(reg);
2679         udelay(100);
2680 }
2681
2682 /*
2683  * When we disable a pipe, we need to clear any pending scanline wait events
2684  * to avoid hanging the ring, which we assume we are waiting on.
2685  */
2686 static void intel_clear_scanline_wait(struct drm_device *dev)
2687 {
2688         struct drm_i915_private *dev_priv = dev->dev_private;
2689         struct intel_ring_buffer *ring;
2690         u32 tmp;
2691
2692         if (IS_GEN2(dev))
2693                 /* Can't break the hang on i8xx */
2694                 return;
2695
2696         ring = LP_RING(dev_priv);
2697         tmp = I915_READ_CTL(ring);
2698         if (tmp & RING_WAIT)
2699                 I915_WRITE_CTL(ring, tmp);
2700 }
2701
2702 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2703 {
2704         struct drm_i915_gem_object *obj;
2705         struct drm_i915_private *dev_priv;
2706
2707         if (crtc->fb == NULL)
2708                 return;
2709
2710         obj = to_intel_framebuffer(crtc->fb)->obj;
2711         dev_priv = crtc->dev->dev_private;
2712         wait_event(dev_priv->pending_flip_queue,
2713                    atomic_read(&obj->pending_flip) == 0);
2714 }
2715
2716 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2717 {
2718         struct drm_device *dev = crtc->dev;
2719         struct drm_mode_config *mode_config = &dev->mode_config;
2720         struct intel_encoder *encoder;
2721
2722         /*
2723          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2724          * must be driven by its own crtc; no sharing is possible.
2725          */
2726         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2727                 if (encoder->base.crtc != crtc)
2728                         continue;
2729
2730                 switch (encoder->type) {
2731                 case INTEL_OUTPUT_EDP:
2732                         if (!intel_encoder_is_pch_edp(&encoder->base))
2733                                 return false;
2734                         continue;
2735                 }
2736         }
2737
2738         return true;
2739 }
2740
2741 /*
2742  * Enable PCH resources required for PCH ports:
2743  *   - PCH PLLs
2744  *   - FDI training & RX/TX
2745  *   - update transcoder timings
2746  *   - DP transcoding bits
2747  *   - transcoder
2748  */
2749 static void ironlake_pch_enable(struct drm_crtc *crtc)
2750 {
2751         struct drm_device *dev = crtc->dev;
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754         int pipe = intel_crtc->pipe;
2755         u32 reg, temp;
2756
2757         /* For PCH output, training FDI link */
2758         dev_priv->display.fdi_link_train(crtc);
2759
2760         intel_enable_pch_pll(dev_priv, pipe);
2761
2762         if (HAS_PCH_CPT(dev)) {
2763                 /* Be sure PCH DPLL SEL is set */
2764                 temp = I915_READ(PCH_DPLL_SEL);
2765                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2766                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2767                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2768                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2769                 I915_WRITE(PCH_DPLL_SEL, temp);
2770         }
2771
2772         /* set transcoder timing, panel must allow it */
2773         assert_panel_unlocked(dev_priv, pipe);
2774         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2775         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2776         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2777
2778         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2779         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2780         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2781
2782         intel_fdi_normal_train(crtc);
2783
2784         /* For PCH DP, enable TRANS_DP_CTL */
2785         if (HAS_PCH_CPT(dev) &&
2786             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2787                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2788                 reg = TRANS_DP_CTL(pipe);
2789                 temp = I915_READ(reg);
2790                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2791                           TRANS_DP_SYNC_MASK |
2792                           TRANS_DP_BPC_MASK);
2793                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2794                          TRANS_DP_ENH_FRAMING);
2795                 temp |= bpc << 9; /* same format but at 11:9 */
2796
2797                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2798                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2799                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2800                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2801
2802                 switch (intel_trans_dp_port_sel(crtc)) {
2803                 case PCH_DP_B:
2804                         temp |= TRANS_DP_PORT_SEL_B;
2805                         break;
2806                 case PCH_DP_C:
2807                         temp |= TRANS_DP_PORT_SEL_C;
2808                         break;
2809                 case PCH_DP_D:
2810                         temp |= TRANS_DP_PORT_SEL_D;
2811                         break;
2812                 default:
2813                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2814                         temp |= TRANS_DP_PORT_SEL_B;
2815                         break;
2816                 }
2817
2818                 I915_WRITE(reg, temp);
2819         }
2820
2821         intel_enable_transcoder(dev_priv, pipe);
2822 }
2823
2824 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2825 {
2826         struct drm_device *dev = crtc->dev;
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2829         int pipe = intel_crtc->pipe;
2830         int plane = intel_crtc->plane;
2831         u32 temp;
2832         bool is_pch_port;
2833
2834         if (intel_crtc->active)
2835                 return;
2836
2837         intel_crtc->active = true;
2838         intel_update_watermarks(dev);
2839
2840         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2841                 temp = I915_READ(PCH_LVDS);
2842                 if ((temp & LVDS_PORT_EN) == 0)
2843                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2844         }
2845
2846         is_pch_port = intel_crtc_driving_pch(crtc);
2847
2848         if (is_pch_port)
2849                 ironlake_fdi_pll_enable(crtc);
2850         else
2851                 ironlake_fdi_disable(crtc);
2852
2853         /* Enable panel fitting for LVDS */
2854         if (dev_priv->pch_pf_size &&
2855             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2856                 /* Force use of hard-coded filter coefficients
2857                  * as some pre-programmed values are broken,
2858                  * e.g. x201.
2859                  */
2860                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2861                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2862                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2863         }
2864
2865         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2866         intel_enable_plane(dev_priv, plane, pipe);
2867
2868         if (is_pch_port)
2869                 ironlake_pch_enable(crtc);
2870
2871         intel_crtc_load_lut(crtc);
2872
2873         mutex_lock(&dev->struct_mutex);
2874         intel_update_fbc(dev);
2875         mutex_unlock(&dev->struct_mutex);
2876
2877         intel_crtc_update_cursor(crtc, true);
2878 }
2879
2880 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2881 {
2882         struct drm_device *dev = crtc->dev;
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885         int pipe = intel_crtc->pipe;
2886         int plane = intel_crtc->plane;
2887         u32 reg, temp;
2888
2889         if (!intel_crtc->active)
2890                 return;
2891
2892         intel_crtc_wait_for_pending_flips(crtc);
2893         drm_vblank_off(dev, pipe);
2894         intel_crtc_update_cursor(crtc, false);
2895
2896         intel_disable_plane(dev_priv, plane, pipe);
2897
2898         if (dev_priv->cfb_plane == plane)
2899                 intel_disable_fbc(dev);
2900
2901         intel_disable_pipe(dev_priv, pipe);
2902
2903         /* Disable PF */
2904         I915_WRITE(PF_CTL(pipe), 0);
2905         I915_WRITE(PF_WIN_SZ(pipe), 0);
2906
2907         ironlake_fdi_disable(crtc);
2908
2909         /* This is a horrible layering violation; we should be doing this in
2910          * the connector/encoder ->prepare instead, but we don't always have
2911          * enough information there about the config to know whether it will
2912          * actually be necessary or just cause undesired flicker.
2913          */
2914         intel_disable_pch_ports(dev_priv, pipe);
2915
2916         intel_disable_transcoder(dev_priv, pipe);
2917
2918         if (HAS_PCH_CPT(dev)) {
2919                 /* disable TRANS_DP_CTL */
2920                 reg = TRANS_DP_CTL(pipe);
2921                 temp = I915_READ(reg);
2922                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2923                 temp |= TRANS_DP_PORT_SEL_NONE;
2924                 I915_WRITE(reg, temp);
2925
2926                 /* disable DPLL_SEL */
2927                 temp = I915_READ(PCH_DPLL_SEL);
2928                 switch (pipe) {
2929                 case 0:
2930                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2931                         break;
2932                 case 1:
2933                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2934                         break;
2935                 case 2:
2936                         /* FIXME: manage transcoder PLLs? */
2937                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2938                         break;
2939                 default:
2940                         BUG(); /* wtf */
2941                 }
2942                 I915_WRITE(PCH_DPLL_SEL, temp);
2943         }
2944
2945         /* disable PCH DPLL */
2946         intel_disable_pch_pll(dev_priv, pipe);
2947
2948         /* Switch from PCDclk to Rawclk */
2949         reg = FDI_RX_CTL(pipe);
2950         temp = I915_READ(reg);
2951         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2952
2953         /* Disable CPU FDI TX PLL */
2954         reg = FDI_TX_CTL(pipe);
2955         temp = I915_READ(reg);
2956         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2957
2958         POSTING_READ(reg);
2959         udelay(100);
2960
2961         reg = FDI_RX_CTL(pipe);
2962         temp = I915_READ(reg);
2963         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2964
2965         /* Wait for the clocks to turn off. */
2966         POSTING_READ(reg);
2967         udelay(100);
2968
2969         intel_crtc->active = false;
2970         intel_update_watermarks(dev);
2971
2972         mutex_lock(&dev->struct_mutex);
2973         intel_update_fbc(dev);
2974         intel_clear_scanline_wait(dev);
2975         mutex_unlock(&dev->struct_mutex);
2976 }
2977
2978 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2979 {
2980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2981         int pipe = intel_crtc->pipe;
2982         int plane = intel_crtc->plane;
2983
2984         /* XXX: When our outputs are all unaware of DPMS modes other than off
2985          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2986          */
2987         switch (mode) {
2988         case DRM_MODE_DPMS_ON:
2989         case DRM_MODE_DPMS_STANDBY:
2990         case DRM_MODE_DPMS_SUSPEND:
2991                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2992                 ironlake_crtc_enable(crtc);
2993                 break;
2994
2995         case DRM_MODE_DPMS_OFF:
2996                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2997                 ironlake_crtc_disable(crtc);
2998                 break;
2999         }
3000 }
3001
3002 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3003 {
3004         if (!enable && intel_crtc->overlay) {
3005                 struct drm_device *dev = intel_crtc->base.dev;
3006                 struct drm_i915_private *dev_priv = dev->dev_private;
3007
3008                 mutex_lock(&dev->struct_mutex);
3009                 dev_priv->mm.interruptible = false;
3010                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3011                 dev_priv->mm.interruptible = true;
3012                 mutex_unlock(&dev->struct_mutex);
3013         }
3014
3015         /* Let userspace switch the overlay on again. In most cases userspace
3016          * has to recompute where to put it anyway.
3017          */
3018 }
3019
3020 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3021 {
3022         struct drm_device *dev = crtc->dev;
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3025         int pipe = intel_crtc->pipe;
3026         int plane = intel_crtc->plane;
3027
3028         if (intel_crtc->active)
3029                 return;
3030
3031         intel_crtc->active = true;
3032         intel_update_watermarks(dev);
3033
3034         intel_enable_pll(dev_priv, pipe);
3035         intel_enable_pipe(dev_priv, pipe, false);
3036         intel_enable_plane(dev_priv, plane, pipe);
3037
3038         intel_crtc_load_lut(crtc);
3039         intel_update_fbc(dev);
3040
3041         /* Give the overlay scaler a chance to enable if it's on this pipe */
3042         intel_crtc_dpms_overlay(intel_crtc, true);
3043         intel_crtc_update_cursor(crtc, true);
3044 }
3045
3046 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3047 {
3048         struct drm_device *dev = crtc->dev;
3049         struct drm_i915_private *dev_priv = dev->dev_private;
3050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3051         int pipe = intel_crtc->pipe;
3052         int plane = intel_crtc->plane;
3053
3054         if (!intel_crtc->active)
3055                 return;
3056
3057         /* Give the overlay scaler a chance to disable if it's on this pipe */
3058         intel_crtc_wait_for_pending_flips(crtc);
3059         drm_vblank_off(dev, pipe);
3060         intel_crtc_dpms_overlay(intel_crtc, false);
3061         intel_crtc_update_cursor(crtc, false);
3062
3063         if (dev_priv->cfb_plane == plane)
3064                 intel_disable_fbc(dev);
3065
3066         intel_disable_plane(dev_priv, plane, pipe);
3067         intel_disable_pipe(dev_priv, pipe);
3068         intel_disable_pll(dev_priv, pipe);
3069
3070         intel_crtc->active = false;
3071         intel_update_fbc(dev);
3072         intel_update_watermarks(dev);
3073         intel_clear_scanline_wait(dev);
3074 }
3075
3076 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3077 {
3078         /* XXX: When our outputs are all unaware of DPMS modes other than off
3079          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3080          */
3081         switch (mode) {
3082         case DRM_MODE_DPMS_ON:
3083         case DRM_MODE_DPMS_STANDBY:
3084         case DRM_MODE_DPMS_SUSPEND:
3085                 i9xx_crtc_enable(crtc);
3086                 break;
3087         case DRM_MODE_DPMS_OFF:
3088                 i9xx_crtc_disable(crtc);
3089                 break;
3090         }
3091 }
3092
3093 /**
3094  * Sets the power management mode of the pipe and plane.
3095  */
3096 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3097 {
3098         struct drm_device *dev = crtc->dev;
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100         struct drm_i915_master_private *master_priv;
3101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102         int pipe = intel_crtc->pipe;
3103         bool enabled;
3104
3105         if (intel_crtc->dpms_mode == mode)
3106                 return;
3107
3108         intel_crtc->dpms_mode = mode;
3109
3110         dev_priv->display.dpms(crtc, mode);
3111
3112         if (!dev->primary->master)
3113                 return;
3114
3115         master_priv = dev->primary->master->driver_priv;
3116         if (!master_priv->sarea_priv)
3117                 return;
3118
3119         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3120
3121         switch (pipe) {
3122         case 0:
3123                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3124                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3125                 break;
3126         case 1:
3127                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3128                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3129                 break;
3130         default:
3131                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3132                 break;
3133         }
3134 }
3135
3136 static void intel_crtc_disable(struct drm_crtc *crtc)
3137 {
3138         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3139         struct drm_device *dev = crtc->dev;
3140
3141         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3142
3143         if (crtc->fb) {
3144                 mutex_lock(&dev->struct_mutex);
3145                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3146                 mutex_unlock(&dev->struct_mutex);
3147         }
3148 }
3149
3150 /* Prepare for a mode set.
3151  *
3152  * Note we could be a lot smarter here.  We need to figure out which outputs
3153  * will be enabled, which disabled (in short, how the config will changes)
3154  * and perform the minimum necessary steps to accomplish that, e.g. updating
3155  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3156  * panel fitting is in the proper state, etc.
3157  */
3158 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3159 {
3160         i9xx_crtc_disable(crtc);
3161 }
3162
3163 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3164 {
3165         i9xx_crtc_enable(crtc);
3166 }
3167
3168 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3169 {
3170         ironlake_crtc_disable(crtc);
3171 }
3172
3173 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3174 {
3175         ironlake_crtc_enable(crtc);
3176 }
3177
3178 void intel_encoder_prepare (struct drm_encoder *encoder)
3179 {
3180         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3181         /* lvds has its own version of prepare see intel_lvds_prepare */
3182         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3183 }
3184
3185 void intel_encoder_commit (struct drm_encoder *encoder)
3186 {
3187         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3188         /* lvds has its own version of commit see intel_lvds_commit */
3189         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3190 }
3191
3192 void intel_encoder_destroy(struct drm_encoder *encoder)
3193 {
3194         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3195
3196         drm_encoder_cleanup(encoder);
3197         kfree(intel_encoder);
3198 }
3199
3200 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3201                                   struct drm_display_mode *mode,
3202                                   struct drm_display_mode *adjusted_mode)
3203 {
3204         struct drm_device *dev = crtc->dev;
3205
3206         if (HAS_PCH_SPLIT(dev)) {
3207                 /* FDI link clock is fixed at 2.7G */
3208                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3209                         return false;
3210         }
3211
3212         /* XXX some encoders set the crtcinfo, others don't.
3213          * Obviously we need some form of conflict resolution here...
3214          */
3215         if (adjusted_mode->crtc_htotal == 0)
3216                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3217
3218         return true;
3219 }
3220
3221 static int i945_get_display_clock_speed(struct drm_device *dev)
3222 {
3223         return 400000;
3224 }
3225
3226 static int i915_get_display_clock_speed(struct drm_device *dev)
3227 {
3228         return 333000;
3229 }
3230
3231 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3232 {
3233         return 200000;
3234 }
3235
3236 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3237 {
3238         u16 gcfgc = 0;
3239
3240         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3241
3242         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3243                 return 133000;
3244         else {
3245                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3246                 case GC_DISPLAY_CLOCK_333_MHZ:
3247                         return 333000;
3248                 default:
3249                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3250                         return 190000;
3251                 }
3252         }
3253 }
3254
3255 static int i865_get_display_clock_speed(struct drm_device *dev)
3256 {
3257         return 266000;
3258 }
3259
3260 static int i855_get_display_clock_speed(struct drm_device *dev)
3261 {
3262         u16 hpllcc = 0;
3263         /* Assume that the hardware is in the high speed state.  This
3264          * should be the default.
3265          */
3266         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3267         case GC_CLOCK_133_200:
3268         case GC_CLOCK_100_200:
3269                 return 200000;
3270         case GC_CLOCK_166_250:
3271                 return 250000;
3272         case GC_CLOCK_100_133:
3273                 return 133000;
3274         }
3275
3276         /* Shouldn't happen */
3277         return 0;
3278 }
3279
3280 static int i830_get_display_clock_speed(struct drm_device *dev)
3281 {
3282         return 133000;
3283 }
3284
3285 struct fdi_m_n {
3286         u32        tu;
3287         u32        gmch_m;
3288         u32        gmch_n;
3289         u32        link_m;
3290         u32        link_n;
3291 };
3292
3293 static void
3294 fdi_reduce_ratio(u32 *num, u32 *den)
3295 {
3296         while (*num > 0xffffff || *den > 0xffffff) {
3297                 *num >>= 1;
3298                 *den >>= 1;
3299         }
3300 }
3301
3302 static void
3303 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3304                      int link_clock, struct fdi_m_n *m_n)
3305 {
3306         m_n->tu = 64; /* default size */
3307
3308         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3309         m_n->gmch_m = bits_per_pixel * pixel_clock;
3310         m_n->gmch_n = link_clock * nlanes * 8;
3311         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3312
3313         m_n->link_m = pixel_clock;
3314         m_n->link_n = link_clock;
3315         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3316 }
3317
3318
3319 struct intel_watermark_params {
3320         unsigned long fifo_size;
3321         unsigned long max_wm;
3322         unsigned long default_wm;
3323         unsigned long guard_size;
3324         unsigned long cacheline_size;
3325 };
3326
3327 /* Pineview has different values for various configs */
3328 static const struct intel_watermark_params pineview_display_wm = {
3329         PINEVIEW_DISPLAY_FIFO,
3330         PINEVIEW_MAX_WM,
3331         PINEVIEW_DFT_WM,
3332         PINEVIEW_GUARD_WM,
3333         PINEVIEW_FIFO_LINE_SIZE
3334 };
3335 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3336         PINEVIEW_DISPLAY_FIFO,
3337         PINEVIEW_MAX_WM,
3338         PINEVIEW_DFT_HPLLOFF_WM,
3339         PINEVIEW_GUARD_WM,
3340         PINEVIEW_FIFO_LINE_SIZE
3341 };
3342 static const struct intel_watermark_params pineview_cursor_wm = {
3343         PINEVIEW_CURSOR_FIFO,
3344         PINEVIEW_CURSOR_MAX_WM,
3345         PINEVIEW_CURSOR_DFT_WM,
3346         PINEVIEW_CURSOR_GUARD_WM,
3347         PINEVIEW_FIFO_LINE_SIZE,
3348 };
3349 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3350         PINEVIEW_CURSOR_FIFO,
3351         PINEVIEW_CURSOR_MAX_WM,
3352         PINEVIEW_CURSOR_DFT_WM,
3353         PINEVIEW_CURSOR_GUARD_WM,
3354         PINEVIEW_FIFO_LINE_SIZE
3355 };
3356 static const struct intel_watermark_params g4x_wm_info = {
3357         G4X_FIFO_SIZE,
3358         G4X_MAX_WM,
3359         G4X_MAX_WM,
3360         2,
3361         G4X_FIFO_LINE_SIZE,
3362 };
3363 static const struct intel_watermark_params g4x_cursor_wm_info = {
3364         I965_CURSOR_FIFO,
3365         I965_CURSOR_MAX_WM,
3366         I965_CURSOR_DFT_WM,
3367         2,
3368         G4X_FIFO_LINE_SIZE,
3369 };
3370 static const struct intel_watermark_params i965_cursor_wm_info = {
3371         I965_CURSOR_FIFO,
3372         I965_CURSOR_MAX_WM,
3373         I965_CURSOR_DFT_WM,
3374         2,
3375         I915_FIFO_LINE_SIZE,
3376 };
3377 static const struct intel_watermark_params i945_wm_info = {
3378         I945_FIFO_SIZE,
3379         I915_MAX_WM,
3380         1,
3381         2,
3382         I915_FIFO_LINE_SIZE
3383 };
3384 static const struct intel_watermark_params i915_wm_info = {
3385         I915_FIFO_SIZE,
3386         I915_MAX_WM,
3387         1,
3388         2,
3389         I915_FIFO_LINE_SIZE
3390 };
3391 static const struct intel_watermark_params i855_wm_info = {
3392         I855GM_FIFO_SIZE,
3393         I915_MAX_WM,
3394         1,
3395         2,
3396         I830_FIFO_LINE_SIZE
3397 };
3398 static const struct intel_watermark_params i830_wm_info = {
3399         I830_FIFO_SIZE,
3400         I915_MAX_WM,
3401         1,
3402         2,
3403         I830_FIFO_LINE_SIZE
3404 };
3405
3406 static const struct intel_watermark_params ironlake_display_wm_info = {
3407         ILK_DISPLAY_FIFO,
3408         ILK_DISPLAY_MAXWM,
3409         ILK_DISPLAY_DFTWM,
3410         2,
3411         ILK_FIFO_LINE_SIZE
3412 };
3413 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3414         ILK_CURSOR_FIFO,
3415         ILK_CURSOR_MAXWM,
3416         ILK_CURSOR_DFTWM,
3417         2,
3418         ILK_FIFO_LINE_SIZE
3419 };
3420 static const struct intel_watermark_params ironlake_display_srwm_info = {
3421         ILK_DISPLAY_SR_FIFO,
3422         ILK_DISPLAY_MAX_SRWM,
3423         ILK_DISPLAY_DFT_SRWM,
3424         2,
3425         ILK_FIFO_LINE_SIZE
3426 };
3427 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3428         ILK_CURSOR_SR_FIFO,
3429         ILK_CURSOR_MAX_SRWM,
3430         ILK_CURSOR_DFT_SRWM,
3431         2,
3432         ILK_FIFO_LINE_SIZE
3433 };
3434
3435 static const struct intel_watermark_params sandybridge_display_wm_info = {
3436         SNB_DISPLAY_FIFO,
3437         SNB_DISPLAY_MAXWM,
3438         SNB_DISPLAY_DFTWM,
3439         2,
3440         SNB_FIFO_LINE_SIZE
3441 };
3442 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3443         SNB_CURSOR_FIFO,
3444         SNB_CURSOR_MAXWM,
3445         SNB_CURSOR_DFTWM,
3446         2,
3447         SNB_FIFO_LINE_SIZE
3448 };
3449 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3450         SNB_DISPLAY_SR_FIFO,
3451         SNB_DISPLAY_MAX_SRWM,
3452         SNB_DISPLAY_DFT_SRWM,
3453         2,
3454         SNB_FIFO_LINE_SIZE
3455 };
3456 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3457         SNB_CURSOR_SR_FIFO,
3458         SNB_CURSOR_MAX_SRWM,
3459         SNB_CURSOR_DFT_SRWM,
3460         2,
3461         SNB_FIFO_LINE_SIZE
3462 };
3463
3464
3465 /**
3466  * intel_calculate_wm - calculate watermark level
3467  * @clock_in_khz: pixel clock
3468  * @wm: chip FIFO params
3469  * @pixel_size: display pixel size
3470  * @latency_ns: memory latency for the platform
3471  *
3472  * Calculate the watermark level (the level at which the display plane will
3473  * start fetching from memory again).  Each chip has a different display
3474  * FIFO size and allocation, so the caller needs to figure that out and pass
3475  * in the correct intel_watermark_params structure.
3476  *
3477  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3478  * on the pixel size.  When it reaches the watermark level, it'll start
3479  * fetching FIFO line sized based chunks from memory until the FIFO fills
3480  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3481  * will occur, and a display engine hang could result.
3482  */
3483 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3484                                         const struct intel_watermark_params *wm,
3485                                         int fifo_size,
3486                                         int pixel_size,
3487                                         unsigned long latency_ns)
3488 {
3489         long entries_required, wm_size;
3490
3491         /*
3492          * Note: we need to make sure we don't overflow for various clock &
3493          * latency values.
3494          * clocks go from a few thousand to several hundred thousand.
3495          * latency is usually a few thousand
3496          */
3497         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3498                 1000;
3499         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3500
3501         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3502
3503         wm_size = fifo_size - (entries_required + wm->guard_size);
3504
3505         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3506
3507         /* Don't promote wm_size to unsigned... */
3508         if (wm_size > (long)wm->max_wm)
3509                 wm_size = wm->max_wm;
3510         if (wm_size <= 0)
3511                 wm_size = wm->default_wm;
3512         return wm_size;
3513 }
3514
3515 struct cxsr_latency {
3516         int is_desktop;
3517         int is_ddr3;
3518         unsigned long fsb_freq;
3519         unsigned long mem_freq;
3520         unsigned long display_sr;
3521         unsigned long display_hpll_disable;
3522         unsigned long cursor_sr;
3523         unsigned long cursor_hpll_disable;
3524 };
3525
3526 static const struct cxsr_latency cxsr_latency_table[] = {
3527         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3528         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3529         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3530         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3531         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3532
3533         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3534         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3535         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3536         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3537         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3538
3539         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3540         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3541         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3542         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3543         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3544
3545         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3546         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3547         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3548         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3549         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3550
3551         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3552         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3553         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3554         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3555         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3556
3557         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3558         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3559         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3560         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3561         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3562 };
3563
3564 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3565                                                          int is_ddr3,
3566                                                          int fsb,
3567                                                          int mem)
3568 {
3569         const struct cxsr_latency *latency;
3570         int i;
3571
3572         if (fsb == 0 || mem == 0)
3573                 return NULL;
3574
3575         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3576                 latency = &cxsr_latency_table[i];
3577                 if (is_desktop == latency->is_desktop &&
3578                     is_ddr3 == latency->is_ddr3 &&
3579                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3580                         return latency;
3581         }
3582
3583         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3584
3585         return NULL;
3586 }
3587
3588 static void pineview_disable_cxsr(struct drm_device *dev)
3589 {
3590         struct drm_i915_private *dev_priv = dev->dev_private;
3591
3592         /* deactivate cxsr */
3593         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3594 }
3595
3596 /*
3597  * Latency for FIFO fetches is dependent on several factors:
3598  *   - memory configuration (speed, channels)
3599  *   - chipset
3600  *   - current MCH state
3601  * It can be fairly high in some situations, so here we assume a fairly
3602  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3603  * set this value too high, the FIFO will fetch frequently to stay full)
3604  * and power consumption (set it too low to save power and we might see
3605  * FIFO underruns and display "flicker").
3606  *
3607  * A value of 5us seems to be a good balance; safe for very low end
3608  * platforms but not overly aggressive on lower latency configs.
3609  */
3610 static const int latency_ns = 5000;
3611
3612 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3613 {
3614         struct drm_i915_private *dev_priv = dev->dev_private;
3615         uint32_t dsparb = I915_READ(DSPARB);
3616         int size;
3617
3618         size = dsparb & 0x7f;
3619         if (plane)
3620                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3621
3622         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3623                       plane ? "B" : "A", size);
3624
3625         return size;
3626 }
3627
3628 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3629 {
3630         struct drm_i915_private *dev_priv = dev->dev_private;
3631         uint32_t dsparb = I915_READ(DSPARB);
3632         int size;
3633
3634         size = dsparb & 0x1ff;
3635         if (plane)
3636                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3637         size >>= 1; /* Convert to cachelines */
3638
3639         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3640                       plane ? "B" : "A", size);
3641
3642         return size;
3643 }
3644
3645 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3646 {
3647         struct drm_i915_private *dev_priv = dev->dev_private;
3648         uint32_t dsparb = I915_READ(DSPARB);
3649         int size;
3650
3651         size = dsparb & 0x7f;
3652         size >>= 2; /* Convert to cachelines */
3653
3654         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3655                       plane ? "B" : "A",
3656                       size);
3657
3658         return size;
3659 }
3660
3661 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3662 {
3663         struct drm_i915_private *dev_priv = dev->dev_private;
3664         uint32_t dsparb = I915_READ(DSPARB);
3665         int size;
3666
3667         size = dsparb & 0x7f;
3668         size >>= 1; /* Convert to cachelines */
3669
3670         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3671                       plane ? "B" : "A", size);
3672
3673         return size;
3674 }
3675
3676 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3677 {
3678         struct drm_crtc *crtc, *enabled = NULL;
3679
3680         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3681                 if (crtc->enabled && crtc->fb) {
3682                         if (enabled)
3683                                 return NULL;
3684                         enabled = crtc;
3685                 }
3686         }
3687
3688         return enabled;
3689 }
3690
3691 static void pineview_update_wm(struct drm_device *dev)
3692 {
3693         struct drm_i915_private *dev_priv = dev->dev_private;
3694         struct drm_crtc *crtc;
3695         const struct cxsr_latency *latency;
3696         u32 reg;
3697         unsigned long wm;
3698
3699         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3700                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3701         if (!latency) {
3702                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3703                 pineview_disable_cxsr(dev);
3704                 return;
3705         }
3706
3707         crtc = single_enabled_crtc(dev);
3708         if (crtc) {
3709                 int clock = crtc->mode.clock;
3710                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3711
3712                 /* Display SR */
3713                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3714                                         pineview_display_wm.fifo_size,
3715                                         pixel_size, latency->display_sr);
3716                 reg = I915_READ(DSPFW1);
3717                 reg &= ~DSPFW_SR_MASK;
3718                 reg |= wm << DSPFW_SR_SHIFT;
3719                 I915_WRITE(DSPFW1, reg);
3720                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3721
3722                 /* cursor SR */
3723                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3724                                         pineview_display_wm.fifo_size,
3725                                         pixel_size, latency->cursor_sr);
3726                 reg = I915_READ(DSPFW3);
3727                 reg &= ~DSPFW_CURSOR_SR_MASK;
3728                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3729                 I915_WRITE(DSPFW3, reg);
3730
3731                 /* Display HPLL off SR */
3732                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3733                                         pineview_display_hplloff_wm.fifo_size,
3734                                         pixel_size, latency->display_hpll_disable);
3735                 reg = I915_READ(DSPFW3);
3736                 reg &= ~DSPFW_HPLL_SR_MASK;
3737                 reg |= wm & DSPFW_HPLL_SR_MASK;
3738                 I915_WRITE(DSPFW3, reg);
3739
3740                 /* cursor HPLL off SR */
3741                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3742                                         pineview_display_hplloff_wm.fifo_size,
3743                                         pixel_size, latency->cursor_hpll_disable);
3744                 reg = I915_READ(DSPFW3);
3745                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3746                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3747                 I915_WRITE(DSPFW3, reg);
3748                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3749
3750                 /* activate cxsr */
3751                 I915_WRITE(DSPFW3,
3752                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3753                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3754         } else {
3755                 pineview_disable_cxsr(dev);
3756                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3757         }
3758 }
3759
3760 static bool g4x_compute_wm0(struct drm_device *dev,
3761                             int plane,
3762                             const struct intel_watermark_params *display,
3763                             int display_latency_ns,
3764                             const struct intel_watermark_params *cursor,
3765                             int cursor_latency_ns,
3766                             int *plane_wm,
3767                             int *cursor_wm)
3768 {
3769         struct drm_crtc *crtc;
3770         int htotal, hdisplay, clock, pixel_size;
3771         int line_time_us, line_count;
3772         int entries, tlb_miss;
3773
3774         crtc = intel_get_crtc_for_plane(dev, plane);
3775         if (crtc->fb == NULL || !crtc->enabled) {
3776                 *cursor_wm = cursor->guard_size;
3777                 *plane_wm = display->guard_size;
3778                 return false;
3779         }
3780
3781         htotal = crtc->mode.htotal;
3782         hdisplay = crtc->mode.hdisplay;
3783         clock = crtc->mode.clock;
3784         pixel_size = crtc->fb->bits_per_pixel / 8;
3785
3786         /* Use the small buffer method to calculate plane watermark */
3787         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3788         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3789         if (tlb_miss > 0)
3790                 entries += tlb_miss;
3791         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3792         *plane_wm = entries + display->guard_size;
3793         if (*plane_wm > (int)display->max_wm)
3794                 *plane_wm = display->max_wm;
3795
3796         /* Use the large buffer method to calculate cursor watermark */
3797         line_time_us = ((htotal * 1000) / clock);
3798         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3799         entries = line_count * 64 * pixel_size;
3800         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3801         if (tlb_miss > 0)
3802                 entries += tlb_miss;
3803         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3804         *cursor_wm = entries + cursor->guard_size;
3805         if (*cursor_wm > (int)cursor->max_wm)
3806                 *cursor_wm = (int)cursor->max_wm;
3807
3808         return true;
3809 }
3810
3811 /*
3812  * Check the wm result.
3813  *
3814  * If any calculated watermark values is larger than the maximum value that
3815  * can be programmed into the associated watermark register, that watermark
3816  * must be disabled.
3817  */
3818 static bool g4x_check_srwm(struct drm_device *dev,
3819                            int display_wm, int cursor_wm,
3820                            const struct intel_watermark_params *display,
3821                            const struct intel_watermark_params *cursor)
3822 {
3823         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3824                       display_wm, cursor_wm);
3825
3826         if (display_wm > display->max_wm) {
3827                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3828                               display_wm, display->max_wm);
3829                 return false;
3830         }
3831
3832         if (cursor_wm > cursor->max_wm) {
3833                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3834                               cursor_wm, cursor->max_wm);
3835                 return false;
3836         }
3837
3838         if (!(display_wm || cursor_wm)) {
3839                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3840                 return false;
3841         }
3842
3843         return true;
3844 }
3845
3846 static bool g4x_compute_srwm(struct drm_device *dev,
3847                              int plane,
3848                              int latency_ns,
3849                              const struct intel_watermark_params *display,
3850                              const struct intel_watermark_params *cursor,
3851                              int *display_wm, int *cursor_wm)
3852 {
3853         struct drm_crtc *crtc;
3854         int hdisplay, htotal, pixel_size, clock;
3855         unsigned long line_time_us;
3856         int line_count, line_size;
3857         int small, large;
3858         int entries;
3859
3860         if (!latency_ns) {
3861                 *display_wm = *cursor_wm = 0;
3862                 return false;
3863         }
3864
3865         crtc = intel_get_crtc_for_plane(dev, plane);
3866         hdisplay = crtc->mode.hdisplay;
3867         htotal = crtc->mode.htotal;
3868         clock = crtc->mode.clock;
3869         pixel_size = crtc->fb->bits_per_pixel / 8;
3870
3871         line_time_us = (htotal * 1000) / clock;
3872         line_count = (latency_ns / line_time_us + 1000) / 1000;
3873         line_size = hdisplay * pixel_size;
3874
3875         /* Use the minimum of the small and large buffer method for primary */
3876         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3877         large = line_count * line_size;
3878
3879         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3880         *display_wm = entries + display->guard_size;
3881
3882         /* calculate the self-refresh watermark for display cursor */
3883         entries = line_count * pixel_size * 64;
3884         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3885         *cursor_wm = entries + cursor->guard_size;
3886
3887         return g4x_check_srwm(dev,
3888                               *display_wm, *cursor_wm,
3889                               display, cursor);
3890 }
3891
3892 #define single_plane_enabled(mask) is_power_of_2(mask)
3893
3894 static void g4x_update_wm(struct drm_device *dev)
3895 {
3896         static const int sr_latency_ns = 12000;
3897         struct drm_i915_private *dev_priv = dev->dev_private;
3898         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3899         int plane_sr, cursor_sr;
3900         unsigned int enabled = 0;
3901
3902         if (g4x_compute_wm0(dev, 0,
3903                             &g4x_wm_info, latency_ns,
3904                             &g4x_cursor_wm_info, latency_ns,
3905                             &planea_wm, &cursora_wm))
3906                 enabled |= 1;
3907
3908         if (g4x_compute_wm0(dev, 1,
3909                             &g4x_wm_info, latency_ns,
3910                             &g4x_cursor_wm_info, latency_ns,
3911                             &planeb_wm, &cursorb_wm))
3912                 enabled |= 2;
3913
3914         plane_sr = cursor_sr = 0;
3915         if (single_plane_enabled(enabled) &&
3916             g4x_compute_srwm(dev, ffs(enabled) - 1,
3917                              sr_latency_ns,
3918                              &g4x_wm_info,
3919                              &g4x_cursor_wm_info,
3920                              &plane_sr, &cursor_sr))
3921                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3922         else
3923                 I915_WRITE(FW_BLC_SELF,
3924                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3925
3926         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3927                       planea_wm, cursora_wm,
3928                       planeb_wm, cursorb_wm,
3929                       plane_sr, cursor_sr);
3930
3931         I915_WRITE(DSPFW1,
3932                    (plane_sr << DSPFW_SR_SHIFT) |
3933                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3934                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3935                    planea_wm);
3936         I915_WRITE(DSPFW2,
3937                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3938                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3939         /* HPLL off in SR has some issues on G4x... disable it */
3940         I915_WRITE(DSPFW3,
3941                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3942                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3943 }
3944
3945 static void i965_update_wm(struct drm_device *dev)
3946 {
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948         struct drm_crtc *crtc;
3949         int srwm = 1;
3950         int cursor_sr = 16;
3951
3952         /* Calc sr entries for one plane configs */
3953         crtc = single_enabled_crtc(dev);
3954         if (crtc) {
3955                 /* self-refresh has much higher latency */
3956                 static const int sr_latency_ns = 12000;
3957                 int clock = crtc->mode.clock;
3958                 int htotal = crtc->mode.htotal;
3959                 int hdisplay = crtc->mode.hdisplay;
3960                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3961                 unsigned long line_time_us;
3962                 int entries;
3963
3964                 line_time_us = ((htotal * 1000) / clock);
3965
3966                 /* Use ns/us then divide to preserve precision */
3967                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3968                         pixel_size * hdisplay;
3969                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3970                 srwm = I965_FIFO_SIZE - entries;
3971                 if (srwm < 0)
3972                         srwm = 1;
3973                 srwm &= 0x1ff;
3974                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3975                               entries, srwm);
3976
3977                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3978                         pixel_size * 64;
3979                 entries = DIV_ROUND_UP(entries,
3980                                           i965_cursor_wm_info.cacheline_size);
3981                 cursor_sr = i965_cursor_wm_info.fifo_size -
3982                         (entries + i965_cursor_wm_info.guard_size);
3983
3984                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3985                         cursor_sr = i965_cursor_wm_info.max_wm;
3986
3987                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3988                               "cursor %d\n", srwm, cursor_sr);
3989
3990                 if (IS_CRESTLINE(dev))
3991                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3992         } else {
3993                 /* Turn off self refresh if both pipes are enabled */
3994                 if (IS_CRESTLINE(dev))
3995                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3996                                    & ~FW_BLC_SELF_EN);
3997         }
3998
3999         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4000                       srwm);
4001
4002         /* 965 has limitations... */
4003         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4004                    (8 << 16) | (8 << 8) | (8 << 0));
4005         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4006         /* update cursor SR watermark */
4007         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4008 }
4009
4010 static void i9xx_update_wm(struct drm_device *dev)
4011 {
4012         struct drm_i915_private *dev_priv = dev->dev_private;
4013         const struct intel_watermark_params *wm_info;
4014         uint32_t fwater_lo;
4015         uint32_t fwater_hi;
4016         int cwm, srwm = 1;
4017         int fifo_size;
4018         int planea_wm, planeb_wm;
4019         struct drm_crtc *crtc, *enabled = NULL;
4020
4021         if (IS_I945GM(dev))
4022                 wm_info = &i945_wm_info;
4023         else if (!IS_GEN2(dev))
4024                 wm_info = &i915_wm_info;
4025         else
4026                 wm_info = &i855_wm_info;
4027
4028         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4029         crtc = intel_get_crtc_for_plane(dev, 0);
4030         if (crtc->enabled && crtc->fb) {
4031                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4032                                                wm_info, fifo_size,
4033                                                crtc->fb->bits_per_pixel / 8,
4034                                                latency_ns);
4035                 enabled = crtc;
4036         } else
4037                 planea_wm = fifo_size - wm_info->guard_size;
4038
4039         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4040         crtc = intel_get_crtc_for_plane(dev, 1);
4041         if (crtc->enabled && crtc->fb) {
4042                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4043                                                wm_info, fifo_size,
4044                                                crtc->fb->bits_per_pixel / 8,
4045                                                latency_ns);
4046                 if (enabled == NULL)
4047                         enabled = crtc;
4048                 else
4049                         enabled = NULL;
4050         } else
4051                 planeb_wm = fifo_size - wm_info->guard_size;
4052
4053         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4054
4055         /*
4056          * Overlay gets an aggressive default since video jitter is bad.
4057          */
4058         cwm = 2;
4059
4060         /* Play safe and disable self-refresh before adjusting watermarks. */
4061         if (IS_I945G(dev) || IS_I945GM(dev))
4062                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4063         else if (IS_I915GM(dev))
4064                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4065
4066         /* Calc sr entries for one plane configs */
4067         if (HAS_FW_BLC(dev) && enabled) {
4068                 /* self-refresh has much higher latency */
4069                 static const int sr_latency_ns = 6000;
4070                 int clock = enabled->mode.clock;
4071                 int htotal = enabled->mode.htotal;
4072                 int hdisplay = enabled->mode.hdisplay;
4073                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4074                 unsigned long line_time_us;
4075                 int entries;
4076
4077                 line_time_us = (htotal * 1000) / clock;
4078
4079                 /* Use ns/us then divide to preserve precision */
4080                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4081                         pixel_size * hdisplay;
4082                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4083                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4084                 srwm = wm_info->fifo_size - entries;
4085                 if (srwm < 0)
4086                         srwm = 1;
4087
4088                 if (IS_I945G(dev) || IS_I945GM(dev))
4089                         I915_WRITE(FW_BLC_SELF,
4090                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4091                 else if (IS_I915GM(dev))
4092                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4093         }
4094
4095         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4096                       planea_wm, planeb_wm, cwm, srwm);
4097
4098         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4099         fwater_hi = (cwm & 0x1f);
4100
4101         /* Set request length to 8 cachelines per fetch */
4102         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4103         fwater_hi = fwater_hi | (1 << 8);
4104
4105         I915_WRITE(FW_BLC, fwater_lo);
4106         I915_WRITE(FW_BLC2, fwater_hi);
4107
4108         if (HAS_FW_BLC(dev)) {
4109                 if (enabled) {
4110                         if (IS_I945G(dev) || IS_I945GM(dev))
4111                                 I915_WRITE(FW_BLC_SELF,
4112                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4113                         else if (IS_I915GM(dev))
4114                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4115                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4116                 } else
4117                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4118         }
4119 }
4120
4121 static void i830_update_wm(struct drm_device *dev)
4122 {
4123         struct drm_i915_private *dev_priv = dev->dev_private;
4124         struct drm_crtc *crtc;
4125         uint32_t fwater_lo;
4126         int planea_wm;
4127
4128         crtc = single_enabled_crtc(dev);
4129         if (crtc == NULL)
4130                 return;
4131
4132         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4133                                        dev_priv->display.get_fifo_size(dev, 0),
4134                                        crtc->fb->bits_per_pixel / 8,
4135                                        latency_ns);
4136         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4137         fwater_lo |= (3<<8) | planea_wm;
4138
4139         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4140
4141         I915_WRITE(FW_BLC, fwater_lo);
4142 }
4143
4144 #define ILK_LP0_PLANE_LATENCY           700
4145 #define ILK_LP0_CURSOR_LATENCY          1300
4146
4147 /*
4148  * Check the wm result.
4149  *
4150  * If any calculated watermark values is larger than the maximum value that
4151  * can be programmed into the associated watermark register, that watermark
4152  * must be disabled.
4153  */
4154 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4155                                 int fbc_wm, int display_wm, int cursor_wm,
4156                                 const struct intel_watermark_params *display,
4157                                 const struct intel_watermark_params *cursor)
4158 {
4159         struct drm_i915_private *dev_priv = dev->dev_private;
4160
4161         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4162                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4163
4164         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4165                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4166                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4167
4168                 /* fbc has it's own way to disable FBC WM */
4169                 I915_WRITE(DISP_ARB_CTL,
4170                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4171                 return false;
4172         }
4173
4174         if (display_wm > display->max_wm) {
4175                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4176                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4177                 return false;
4178         }
4179
4180         if (cursor_wm > cursor->max_wm) {
4181                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4182                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4183                 return false;
4184         }
4185
4186         if (!(fbc_wm || display_wm || cursor_wm)) {
4187                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4188                 return false;
4189         }
4190
4191         return true;
4192 }
4193
4194 /*
4195  * Compute watermark values of WM[1-3],
4196  */
4197 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4198                                   int latency_ns,
4199                                   const struct intel_watermark_params *display,
4200                                   const struct intel_watermark_params *cursor,
4201                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4202 {
4203         struct drm_crtc *crtc;
4204         unsigned long line_time_us;
4205         int hdisplay, htotal, pixel_size, clock;
4206         int line_count, line_size;
4207         int small, large;
4208         int entries;
4209
4210         if (!latency_ns) {
4211                 *fbc_wm = *display_wm = *cursor_wm = 0;
4212                 return false;
4213         }
4214
4215         crtc = intel_get_crtc_for_plane(dev, plane);
4216         hdisplay = crtc->mode.hdisplay;
4217         htotal = crtc->mode.htotal;
4218         clock = crtc->mode.clock;
4219         pixel_size = crtc->fb->bits_per_pixel / 8;
4220
4221         line_time_us = (htotal * 1000) / clock;
4222         line_count = (latency_ns / line_time_us + 1000) / 1000;
4223         line_size = hdisplay * pixel_size;
4224
4225         /* Use the minimum of the small and large buffer method for primary */
4226         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4227         large = line_count * line_size;
4228
4229         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4230         *display_wm = entries + display->guard_size;
4231
4232         /*
4233          * Spec says:
4234          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4235          */
4236         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4237
4238         /* calculate the self-refresh watermark for display cursor */
4239         entries = line_count * pixel_size * 64;
4240         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4241         *cursor_wm = entries + cursor->guard_size;
4242
4243         return ironlake_check_srwm(dev, level,
4244                                    *fbc_wm, *display_wm, *cursor_wm,
4245                                    display, cursor);
4246 }
4247
4248 static void ironlake_update_wm(struct drm_device *dev)
4249 {
4250         struct drm_i915_private *dev_priv = dev->dev_private;
4251         int fbc_wm, plane_wm, cursor_wm;
4252         unsigned int enabled;
4253
4254         enabled = 0;
4255         if (g4x_compute_wm0(dev, 0,
4256                             &ironlake_display_wm_info,
4257                             ILK_LP0_PLANE_LATENCY,
4258                             &ironlake_cursor_wm_info,
4259                             ILK_LP0_CURSOR_LATENCY,
4260                             &plane_wm, &cursor_wm)) {
4261                 I915_WRITE(WM0_PIPEA_ILK,
4262                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4263                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4264                               " plane %d, " "cursor: %d\n",
4265                               plane_wm, cursor_wm);
4266                 enabled |= 1;
4267         }
4268
4269         if (g4x_compute_wm0(dev, 1,
4270                             &ironlake_display_wm_info,
4271                             ILK_LP0_PLANE_LATENCY,
4272                             &ironlake_cursor_wm_info,
4273                             ILK_LP0_CURSOR_LATENCY,
4274                             &plane_wm, &cursor_wm)) {
4275                 I915_WRITE(WM0_PIPEB_ILK,
4276                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4277                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4278                               " plane %d, cursor: %d\n",
4279                               plane_wm, cursor_wm);
4280                 enabled |= 2;
4281         }
4282
4283         /*
4284          * Calculate and update the self-refresh watermark only when one
4285          * display plane is used.
4286          */
4287         I915_WRITE(WM3_LP_ILK, 0);
4288         I915_WRITE(WM2_LP_ILK, 0);
4289         I915_WRITE(WM1_LP_ILK, 0);
4290
4291         if (!single_plane_enabled(enabled))
4292                 return;
4293         enabled = ffs(enabled) - 1;
4294
4295         /* WM1 */
4296         if (!ironlake_compute_srwm(dev, 1, enabled,
4297                                    ILK_READ_WM1_LATENCY() * 500,
4298                                    &ironlake_display_srwm_info,
4299                                    &ironlake_cursor_srwm_info,
4300                                    &fbc_wm, &plane_wm, &cursor_wm))
4301                 return;
4302
4303         I915_WRITE(WM1_LP_ILK,
4304                    WM1_LP_SR_EN |
4305                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4306                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4307                    (plane_wm << WM1_LP_SR_SHIFT) |
4308                    cursor_wm);
4309
4310         /* WM2 */
4311         if (!ironlake_compute_srwm(dev, 2, enabled,
4312                                    ILK_READ_WM2_LATENCY() * 500,
4313                                    &ironlake_display_srwm_info,
4314                                    &ironlake_cursor_srwm_info,
4315                                    &fbc_wm, &plane_wm, &cursor_wm))
4316                 return;
4317
4318         I915_WRITE(WM2_LP_ILK,
4319                    WM2_LP_EN |
4320                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4321                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4322                    (plane_wm << WM1_LP_SR_SHIFT) |
4323                    cursor_wm);
4324
4325         /*
4326          * WM3 is unsupported on ILK, probably because we don't have latency
4327          * data for that power state
4328          */
4329 }
4330
4331 static void sandybridge_update_wm(struct drm_device *dev)
4332 {
4333         struct drm_i915_private *dev_priv = dev->dev_private;
4334         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4335         int fbc_wm, plane_wm, cursor_wm;
4336         unsigned int enabled;
4337
4338         enabled = 0;
4339         if (g4x_compute_wm0(dev, 0,
4340                             &sandybridge_display_wm_info, latency,
4341                             &sandybridge_cursor_wm_info, latency,
4342                             &plane_wm, &cursor_wm)) {
4343                 I915_WRITE(WM0_PIPEA_ILK,
4344                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4345                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4346                               " plane %d, " "cursor: %d\n",
4347                               plane_wm, cursor_wm);
4348                 enabled |= 1;
4349         }
4350
4351         if (g4x_compute_wm0(dev, 1,
4352                             &sandybridge_display_wm_info, latency,
4353                             &sandybridge_cursor_wm_info, latency,
4354                             &plane_wm, &cursor_wm)) {
4355                 I915_WRITE(WM0_PIPEB_ILK,
4356                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4357                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4358                               " plane %d, cursor: %d\n",
4359                               plane_wm, cursor_wm);
4360                 enabled |= 2;
4361         }
4362
4363         /*
4364          * Calculate and update the self-refresh watermark only when one
4365          * display plane is used.
4366          *
4367          * SNB support 3 levels of watermark.
4368          *
4369          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4370          * and disabled in the descending order
4371          *
4372          */
4373         I915_WRITE(WM3_LP_ILK, 0);
4374         I915_WRITE(WM2_LP_ILK, 0);
4375         I915_WRITE(WM1_LP_ILK, 0);
4376
4377         if (!single_plane_enabled(enabled))
4378                 return;
4379         enabled = ffs(enabled) - 1;
4380
4381         /* WM1 */
4382         if (!ironlake_compute_srwm(dev, 1, enabled,
4383                                    SNB_READ_WM1_LATENCY() * 500,
4384                                    &sandybridge_display_srwm_info,
4385                                    &sandybridge_cursor_srwm_info,
4386                                    &fbc_wm, &plane_wm, &cursor_wm))
4387                 return;
4388
4389         I915_WRITE(WM1_LP_ILK,
4390                    WM1_LP_SR_EN |
4391                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4392                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4393                    (plane_wm << WM1_LP_SR_SHIFT) |
4394                    cursor_wm);
4395
4396         /* WM2 */
4397         if (!ironlake_compute_srwm(dev, 2, enabled,
4398                                    SNB_READ_WM2_LATENCY() * 500,
4399                                    &sandybridge_display_srwm_info,
4400                                    &sandybridge_cursor_srwm_info,
4401                                    &fbc_wm, &plane_wm, &cursor_wm))
4402                 return;
4403
4404         I915_WRITE(WM2_LP_ILK,
4405                    WM2_LP_EN |
4406                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4407                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4408                    (plane_wm << WM1_LP_SR_SHIFT) |
4409                    cursor_wm);
4410
4411         /* WM3 */
4412         if (!ironlake_compute_srwm(dev, 3, enabled,
4413                                    SNB_READ_WM3_LATENCY() * 500,
4414                                    &sandybridge_display_srwm_info,
4415                                    &sandybridge_cursor_srwm_info,
4416                                    &fbc_wm, &plane_wm, &cursor_wm))
4417                 return;
4418
4419         I915_WRITE(WM3_LP_ILK,
4420                    WM3_LP_EN |
4421                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4422                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4423                    (plane_wm << WM1_LP_SR_SHIFT) |
4424                    cursor_wm);
4425 }
4426
4427 /**
4428  * intel_update_watermarks - update FIFO watermark values based on current modes
4429  *
4430  * Calculate watermark values for the various WM regs based on current mode
4431  * and plane configuration.
4432  *
4433  * There are several cases to deal with here:
4434  *   - normal (i.e. non-self-refresh)
4435  *   - self-refresh (SR) mode
4436  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4437  *   - lines are small relative to FIFO size (buffer can hold more than 2
4438  *     lines), so need to account for TLB latency
4439  *
4440  *   The normal calculation is:
4441  *     watermark = dotclock * bytes per pixel * latency
4442  *   where latency is platform & configuration dependent (we assume pessimal
4443  *   values here).
4444  *
4445  *   The SR calculation is:
4446  *     watermark = (trunc(latency/line time)+1) * surface width *
4447  *       bytes per pixel
4448  *   where
4449  *     line time = htotal / dotclock
4450  *     surface width = hdisplay for normal plane and 64 for cursor
4451  *   and latency is assumed to be high, as above.
4452  *
4453  * The final value programmed to the register should always be rounded up,
4454  * and include an extra 2 entries to account for clock crossings.
4455  *
4456  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4457  * to set the non-SR watermarks to 8.
4458  */
4459 static void intel_update_watermarks(struct drm_device *dev)
4460 {
4461         struct drm_i915_private *dev_priv = dev->dev_private;
4462
4463         if (dev_priv->display.update_wm)
4464                 dev_priv->display.update_wm(dev);
4465 }
4466
4467 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4468 {
4469         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4470 }
4471
4472 /**
4473  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4474  * @crtc: CRTC structure
4475  *
4476  * A pipe may be connected to one or more outputs.  Based on the depth of the
4477  * attached framebuffer, choose a good color depth to use on the pipe.
4478  *
4479  * If possible, match the pipe depth to the fb depth.  In some cases, this
4480  * isn't ideal, because the connected output supports a lesser or restricted
4481  * set of depths.  Resolve that here:
4482  *    LVDS typically supports only 6bpc, so clamp down in that case
4483  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4484  *    Displays may support a restricted set as well, check EDID and clamp as
4485  *      appropriate.
4486  *
4487  * RETURNS:
4488  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4489  * true if they don't match).
4490  */
4491 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4492                                          unsigned int *pipe_bpp)
4493 {
4494         struct drm_device *dev = crtc->dev;
4495         struct drm_i915_private *dev_priv = dev->dev_private;
4496         struct drm_encoder *encoder;
4497         struct drm_connector *connector;
4498         unsigned int display_bpc = UINT_MAX, bpc;
4499
4500         /* Walk the encoders & connectors on this crtc, get min bpc */
4501         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4502                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4503
4504                 if (encoder->crtc != crtc)
4505                         continue;
4506
4507                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4508                         unsigned int lvds_bpc;
4509
4510                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4511                             LVDS_A3_POWER_UP)
4512                                 lvds_bpc = 8;
4513                         else
4514                                 lvds_bpc = 6;
4515
4516                         if (lvds_bpc < display_bpc) {
4517                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4518                                 display_bpc = lvds_bpc;
4519                         }
4520                         continue;
4521                 }
4522
4523                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4524                         /* Use VBT settings if we have an eDP panel */
4525                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4526
4527                         if (edp_bpc < display_bpc) {
4528                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4529                                 display_bpc = edp_bpc;
4530                         }
4531                         continue;
4532                 }
4533
4534                 /* Not one of the known troublemakers, check the EDID */
4535                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4536                                     head) {
4537                         if (connector->encoder != encoder)
4538                                 continue;
4539
4540                         if (connector->display_info.bpc < display_bpc) {
4541                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4542                                 display_bpc = connector->display_info.bpc;
4543                         }
4544                 }
4545
4546                 /*
4547                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4548                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4549                  */
4550                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4551                         if (display_bpc > 8 && display_bpc < 12) {
4552                                 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4553                                 display_bpc = 12;
4554                         } else {
4555                                 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4556                                 display_bpc = 8;
4557                         }
4558                 }
4559         }
4560
4561         /*
4562          * We could just drive the pipe at the highest bpc all the time and
4563          * enable dithering as needed, but that costs bandwidth.  So choose
4564          * the minimum value that expresses the full color range of the fb but
4565          * also stays within the max display bpc discovered above.
4566          */
4567
4568         switch (crtc->fb->depth) {
4569         case 8:
4570                 bpc = 8; /* since we go through a colormap */
4571                 break;
4572         case 15:
4573         case 16:
4574                 bpc = 6; /* min is 18bpp */
4575                 break;
4576         case 24:
4577                 bpc = min((unsigned int)8, display_bpc);
4578                 break;
4579         case 30:
4580                 bpc = min((unsigned int)10, display_bpc);
4581                 break;
4582         case 48:
4583                 bpc = min((unsigned int)12, display_bpc);
4584                 break;
4585         default:
4586                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4587                 bpc = min((unsigned int)8, display_bpc);
4588                 break;
4589         }
4590
4591         DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4592                          bpc, display_bpc);
4593
4594         *pipe_bpp = bpc * 3;
4595
4596         return display_bpc != bpc;
4597 }
4598
4599 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4600                               struct drm_display_mode *mode,
4601                               struct drm_display_mode *adjusted_mode,
4602                               int x, int y,
4603                               struct drm_framebuffer *old_fb)
4604 {
4605         struct drm_device *dev = crtc->dev;
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4608         int pipe = intel_crtc->pipe;
4609         int plane = intel_crtc->plane;
4610         int refclk, num_connectors = 0;
4611         intel_clock_t clock, reduced_clock;
4612         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4613         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4614         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4615         struct drm_mode_config *mode_config = &dev->mode_config;
4616         struct intel_encoder *encoder;
4617         const intel_limit_t *limit;
4618         int ret;
4619         u32 temp;
4620         u32 lvds_sync = 0;
4621
4622         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4623                 if (encoder->base.crtc != crtc)
4624                         continue;
4625
4626                 switch (encoder->type) {
4627                 case INTEL_OUTPUT_LVDS:
4628                         is_lvds = true;
4629                         break;
4630                 case INTEL_OUTPUT_SDVO:
4631                 case INTEL_OUTPUT_HDMI:
4632                         is_sdvo = true;
4633                         if (encoder->needs_tv_clock)
4634                                 is_tv = true;
4635                         break;
4636                 case INTEL_OUTPUT_DVO:
4637                         is_dvo = true;
4638                         break;
4639                 case INTEL_OUTPUT_TVOUT:
4640                         is_tv = true;
4641                         break;
4642                 case INTEL_OUTPUT_ANALOG:
4643                         is_crt = true;
4644                         break;
4645                 case INTEL_OUTPUT_DISPLAYPORT:
4646                         is_dp = true;
4647                         break;
4648                 }
4649
4650                 num_connectors++;
4651         }
4652
4653         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4654                 refclk = dev_priv->lvds_ssc_freq * 1000;
4655                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4656                               refclk / 1000);
4657         } else if (!IS_GEN2(dev)) {
4658                 refclk = 96000;
4659         } else {
4660                 refclk = 48000;
4661         }
4662
4663         /*
4664          * Returns a set of divisors for the desired target clock with the given
4665          * refclk, or FALSE.  The returned values represent the clock equation:
4666          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4667          */
4668         limit = intel_limit(crtc, refclk);
4669         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4670         if (!ok) {
4671                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4672                 return -EINVAL;
4673         }
4674
4675         /* Ensure that the cursor is valid for the new mode before changing... */
4676         intel_crtc_update_cursor(crtc, true);
4677
4678         if (is_lvds && dev_priv->lvds_downclock_avail) {
4679                 has_reduced_clock = limit->find_pll(limit, crtc,
4680                                                     dev_priv->lvds_downclock,
4681                                                     refclk,
4682                                                     &reduced_clock);
4683                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4684                         /*
4685                          * If the different P is found, it means that we can't
4686                          * switch the display clock by using the FP0/FP1.
4687                          * In such case we will disable the LVDS downclock
4688                          * feature.
4689                          */
4690                         DRM_DEBUG_KMS("Different P is found for "
4691                                       "LVDS clock/downclock\n");
4692                         has_reduced_clock = 0;
4693                 }
4694         }
4695         /* SDVO TV has fixed PLL values depend on its clock range,
4696            this mirrors vbios setting. */
4697         if (is_sdvo && is_tv) {
4698                 if (adjusted_mode->clock >= 100000
4699                     && adjusted_mode->clock < 140500) {
4700                         clock.p1 = 2;
4701                         clock.p2 = 10;
4702                         clock.n = 3;
4703                         clock.m1 = 16;
4704                         clock.m2 = 8;
4705                 } else if (adjusted_mode->clock >= 140500
4706                            && adjusted_mode->clock <= 200000) {
4707                         clock.p1 = 1;
4708                         clock.p2 = 10;
4709                         clock.n = 6;
4710                         clock.m1 = 12;
4711                         clock.m2 = 8;
4712                 }
4713         }
4714
4715         if (IS_PINEVIEW(dev)) {
4716                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4717                 if (has_reduced_clock)
4718                         fp2 = (1 << reduced_clock.n) << 16 |
4719                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4720         } else {
4721                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4722                 if (has_reduced_clock)
4723                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4724                                 reduced_clock.m2;
4725         }
4726
4727         dpll = DPLL_VGA_MODE_DIS;
4728
4729         if (!IS_GEN2(dev)) {
4730                 if (is_lvds)
4731                         dpll |= DPLLB_MODE_LVDS;
4732                 else
4733                         dpll |= DPLLB_MODE_DAC_SERIAL;
4734                 if (is_sdvo) {
4735                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4736                         if (pixel_multiplier > 1) {
4737                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4738                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4739                         }
4740                         dpll |= DPLL_DVO_HIGH_SPEED;
4741                 }
4742                 if (is_dp)
4743                         dpll |= DPLL_DVO_HIGH_SPEED;
4744
4745                 /* compute bitmask from p1 value */
4746                 if (IS_PINEVIEW(dev))
4747                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4748                 else {
4749                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4750                         if (IS_G4X(dev) && has_reduced_clock)
4751                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4752                 }
4753                 switch (clock.p2) {
4754                 case 5:
4755                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4756                         break;
4757                 case 7:
4758                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4759                         break;
4760                 case 10:
4761                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4762                         break;
4763                 case 14:
4764                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4765                         break;
4766                 }
4767                 if (INTEL_INFO(dev)->gen >= 4)
4768                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4769         } else {
4770                 if (is_lvds) {
4771                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4772                 } else {
4773                         if (clock.p1 == 2)
4774                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4775                         else
4776                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4777                         if (clock.p2 == 4)
4778                                 dpll |= PLL_P2_DIVIDE_BY_4;
4779                 }
4780         }
4781
4782         if (is_sdvo && is_tv)
4783                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4784         else if (is_tv)
4785                 /* XXX: just matching BIOS for now */
4786                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4787                 dpll |= 3;
4788         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4789                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4790         else
4791                 dpll |= PLL_REF_INPUT_DREFCLK;
4792
4793         /* setup pipeconf */
4794         pipeconf = I915_READ(PIPECONF(pipe));
4795
4796         /* Set up the display plane register */
4797         dspcntr = DISPPLANE_GAMMA_ENABLE;
4798
4799         /* Ironlake's plane is forced to pipe, bit 24 is to
4800            enable color space conversion */
4801         if (pipe == 0)
4802                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4803         else
4804                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4805
4806         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4807                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4808                  * core speed.
4809                  *
4810                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4811                  * pipe == 0 check?
4812                  */
4813                 if (mode->clock >
4814                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4815                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4816                 else
4817                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4818         }
4819
4820         dpll |= DPLL_VCO_ENABLE;
4821
4822         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4823         drm_mode_debug_printmodeline(mode);
4824
4825         I915_WRITE(FP0(pipe), fp);
4826         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4827
4828         POSTING_READ(DPLL(pipe));
4829         udelay(150);
4830
4831         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4832          * This is an exception to the general rule that mode_set doesn't turn
4833          * things on.
4834          */
4835         if (is_lvds) {
4836                 temp = I915_READ(LVDS);
4837                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4838                 if (pipe == 1) {
4839                         temp |= LVDS_PIPEB_SELECT;
4840                 } else {
4841                         temp &= ~LVDS_PIPEB_SELECT;
4842                 }
4843                 /* set the corresponsding LVDS_BORDER bit */
4844                 temp |= dev_priv->lvds_border_bits;
4845                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4846                  * set the DPLLs for dual-channel mode or not.
4847                  */
4848                 if (clock.p2 == 7)
4849                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4850                 else
4851                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4852
4853                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4854                  * appropriately here, but we need to look more thoroughly into how
4855                  * panels behave in the two modes.
4856                  */
4857                 /* set the dithering flag on LVDS as needed */
4858                 if (INTEL_INFO(dev)->gen >= 4) {
4859                         if (dev_priv->lvds_dither)
4860                                 temp |= LVDS_ENABLE_DITHER;
4861                         else
4862                                 temp &= ~LVDS_ENABLE_DITHER;
4863                 }
4864                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4865                         lvds_sync |= LVDS_HSYNC_POLARITY;
4866                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4867                         lvds_sync |= LVDS_VSYNC_POLARITY;
4868                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4869                     != lvds_sync) {
4870                         char flags[2] = "-+";
4871                         DRM_INFO("Changing LVDS panel from "
4872                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4873                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4874                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4875                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4876                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4877                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4878                         temp |= lvds_sync;
4879                 }
4880                 I915_WRITE(LVDS, temp);
4881         }
4882
4883         if (is_dp) {
4884                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4885         }
4886
4887         I915_WRITE(DPLL(pipe), dpll);
4888
4889         /* Wait for the clocks to stabilize. */
4890         POSTING_READ(DPLL(pipe));
4891         udelay(150);
4892
4893         if (INTEL_INFO(dev)->gen >= 4) {
4894                 temp = 0;
4895                 if (is_sdvo) {
4896                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4897                         if (temp > 1)
4898                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4899                         else
4900                                 temp = 0;
4901                 }
4902                 I915_WRITE(DPLL_MD(pipe), temp);
4903         } else {
4904                 /* The pixel multiplier can only be updated once the
4905                  * DPLL is enabled and the clocks are stable.
4906                  *
4907                  * So write it again.
4908                  */
4909                 I915_WRITE(DPLL(pipe), dpll);
4910         }
4911
4912         intel_crtc->lowfreq_avail = false;
4913         if (is_lvds && has_reduced_clock && i915_powersave) {
4914                 I915_WRITE(FP1(pipe), fp2);
4915                 intel_crtc->lowfreq_avail = true;
4916                 if (HAS_PIPE_CXSR(dev)) {
4917                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4918                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4919                 }
4920         } else {
4921                 I915_WRITE(FP1(pipe), fp);
4922                 if (HAS_PIPE_CXSR(dev)) {
4923                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4924                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4925                 }
4926         }
4927
4928         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4929                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4930                 /* the chip adds 2 halflines automatically */
4931                 adjusted_mode->crtc_vdisplay -= 1;
4932                 adjusted_mode->crtc_vtotal -= 1;
4933                 adjusted_mode->crtc_vblank_start -= 1;
4934                 adjusted_mode->crtc_vblank_end -= 1;
4935                 adjusted_mode->crtc_vsync_end -= 1;
4936                 adjusted_mode->crtc_vsync_start -= 1;
4937         } else
4938                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4939
4940         I915_WRITE(HTOTAL(pipe),
4941                    (adjusted_mode->crtc_hdisplay - 1) |
4942                    ((adjusted_mode->crtc_htotal - 1) << 16));
4943         I915_WRITE(HBLANK(pipe),
4944                    (adjusted_mode->crtc_hblank_start - 1) |
4945                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4946         I915_WRITE(HSYNC(pipe),
4947                    (adjusted_mode->crtc_hsync_start - 1) |
4948                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4949
4950         I915_WRITE(VTOTAL(pipe),
4951                    (adjusted_mode->crtc_vdisplay - 1) |
4952                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4953         I915_WRITE(VBLANK(pipe),
4954                    (adjusted_mode->crtc_vblank_start - 1) |
4955                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4956         I915_WRITE(VSYNC(pipe),
4957                    (adjusted_mode->crtc_vsync_start - 1) |
4958                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4959
4960         /* pipesrc and dspsize control the size that is scaled from,
4961          * which should always be the user's requested size.
4962          */
4963         I915_WRITE(DSPSIZE(plane),
4964                    ((mode->vdisplay - 1) << 16) |
4965                    (mode->hdisplay - 1));
4966         I915_WRITE(DSPPOS(plane), 0);
4967         I915_WRITE(PIPESRC(pipe),
4968                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4969
4970         I915_WRITE(PIPECONF(pipe), pipeconf);
4971         POSTING_READ(PIPECONF(pipe));
4972         intel_enable_pipe(dev_priv, pipe, false);
4973
4974         intel_wait_for_vblank(dev, pipe);
4975
4976         I915_WRITE(DSPCNTR(plane), dspcntr);
4977         POSTING_READ(DSPCNTR(plane));
4978         intel_enable_plane(dev_priv, plane, pipe);
4979
4980         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4981
4982         intel_update_watermarks(dev);
4983
4984         return ret;
4985 }
4986
4987 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4988                                   struct drm_display_mode *mode,
4989                                   struct drm_display_mode *adjusted_mode,
4990                                   int x, int y,
4991                                   struct drm_framebuffer *old_fb)
4992 {
4993         struct drm_device *dev = crtc->dev;
4994         struct drm_i915_private *dev_priv = dev->dev_private;
4995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4996         int pipe = intel_crtc->pipe;
4997         int plane = intel_crtc->plane;
4998         int refclk, num_connectors = 0;
4999         intel_clock_t clock, reduced_clock;
5000         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5001         bool ok, has_reduced_clock = false, is_sdvo = false;
5002         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5003         struct intel_encoder *has_edp_encoder = NULL;
5004         struct drm_mode_config *mode_config = &dev->mode_config;
5005         struct intel_encoder *encoder;
5006         const intel_limit_t *limit;
5007         int ret;
5008         struct fdi_m_n m_n = {0};
5009         u32 temp;
5010         u32 lvds_sync = 0;
5011         int target_clock, pixel_multiplier, lane, link_bw, factor;
5012         unsigned int pipe_bpp;
5013         bool dither;
5014
5015         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5016                 if (encoder->base.crtc != crtc)
5017                         continue;
5018
5019                 switch (encoder->type) {
5020                 case INTEL_OUTPUT_LVDS:
5021                         is_lvds = true;
5022                         break;
5023                 case INTEL_OUTPUT_SDVO:
5024                 case INTEL_OUTPUT_HDMI:
5025                         is_sdvo = true;
5026                         if (encoder->needs_tv_clock)
5027                                 is_tv = true;
5028                         break;
5029                 case INTEL_OUTPUT_TVOUT:
5030                         is_tv = true;
5031                         break;
5032                 case INTEL_OUTPUT_ANALOG:
5033                         is_crt = true;
5034                         break;
5035                 case INTEL_OUTPUT_DISPLAYPORT:
5036                         is_dp = true;
5037                         break;
5038                 case INTEL_OUTPUT_EDP:
5039                         has_edp_encoder = encoder;
5040                         break;
5041                 }
5042
5043                 num_connectors++;
5044         }
5045
5046         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5047                 refclk = dev_priv->lvds_ssc_freq * 1000;
5048                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5049                               refclk / 1000);
5050         } else {
5051                 refclk = 96000;
5052                 if (!has_edp_encoder ||
5053                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
5054                         refclk = 120000; /* 120Mhz refclk */
5055         }
5056
5057         /*
5058          * Returns a set of divisors for the desired target clock with the given
5059          * refclk, or FALSE.  The returned values represent the clock equation:
5060          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5061          */
5062         limit = intel_limit(crtc, refclk);
5063         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5064         if (!ok) {
5065                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5066                 return -EINVAL;
5067         }
5068
5069         /* Ensure that the cursor is valid for the new mode before changing... */
5070         intel_crtc_update_cursor(crtc, true);
5071
5072         if (is_lvds && dev_priv->lvds_downclock_avail) {
5073                 has_reduced_clock = limit->find_pll(limit, crtc,
5074                                                     dev_priv->lvds_downclock,
5075                                                     refclk,
5076                                                     &reduced_clock);
5077                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5078                         /*
5079                          * If the different P is found, it means that we can't
5080                          * switch the display clock by using the FP0/FP1.
5081                          * In such case we will disable the LVDS downclock
5082                          * feature.
5083                          */
5084                         DRM_DEBUG_KMS("Different P is found for "
5085                                       "LVDS clock/downclock\n");
5086                         has_reduced_clock = 0;
5087                 }
5088         }
5089         /* SDVO TV has fixed PLL values depend on its clock range,
5090            this mirrors vbios setting. */
5091         if (is_sdvo && is_tv) {
5092                 if (adjusted_mode->clock >= 100000
5093                     && adjusted_mode->clock < 140500) {
5094                         clock.p1 = 2;
5095                         clock.p2 = 10;
5096                         clock.n = 3;
5097                         clock.m1 = 16;
5098                         clock.m2 = 8;
5099                 } else if (adjusted_mode->clock >= 140500
5100                            && adjusted_mode->clock <= 200000) {
5101                         clock.p1 = 1;
5102                         clock.p2 = 10;
5103                         clock.n = 6;
5104                         clock.m1 = 12;
5105                         clock.m2 = 8;
5106                 }
5107         }
5108
5109         /* FDI link */
5110         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5111         lane = 0;
5112         /* CPU eDP doesn't require FDI link, so just set DP M/N
5113            according to current link config */
5114         if (has_edp_encoder &&
5115             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5116                 target_clock = mode->clock;
5117                 intel_edp_link_config(has_edp_encoder,
5118                                       &lane, &link_bw);
5119         } else {
5120                 /* [e]DP over FDI requires target mode clock
5121                    instead of link clock */
5122                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5123                         target_clock = mode->clock;
5124                 else
5125                         target_clock = adjusted_mode->clock;
5126
5127                 /* FDI is a binary signal running at ~2.7GHz, encoding
5128                  * each output octet as 10 bits. The actual frequency
5129                  * is stored as a divider into a 100MHz clock, and the
5130                  * mode pixel clock is stored in units of 1KHz.
5131                  * Hence the bw of each lane in terms of the mode signal
5132                  * is:
5133                  */
5134                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5135         }
5136
5137         /* determine panel color depth */
5138         temp = I915_READ(PIPECONF(pipe));
5139         temp &= ~PIPE_BPC_MASK;
5140         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5141         switch (pipe_bpp) {
5142         case 18:
5143                 temp |= PIPE_6BPC;
5144                 break;
5145         case 24:
5146                 temp |= PIPE_8BPC;
5147                 break;
5148         case 30:
5149                 temp |= PIPE_10BPC;
5150                 break;
5151         case 36:
5152                 temp |= PIPE_12BPC;
5153                 break;
5154         default:
5155                 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5156                 temp |= PIPE_8BPC;
5157                 pipe_bpp = 24;
5158                 break;
5159         }
5160
5161         intel_crtc->bpp = pipe_bpp;
5162         I915_WRITE(PIPECONF(pipe), temp);
5163
5164         if (!lane) {
5165                 /*
5166                  * Account for spread spectrum to avoid
5167                  * oversubscribing the link. Max center spread
5168                  * is 2.5%; use 5% for safety's sake.
5169                  */
5170                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5171                 lane = bps / (link_bw * 8) + 1;
5172         }
5173
5174         intel_crtc->fdi_lanes = lane;
5175
5176         if (pixel_multiplier > 1)
5177                 link_bw *= pixel_multiplier;
5178         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5179                              &m_n);
5180
5181         /* Ironlake: try to setup display ref clock before DPLL
5182          * enabling. This is only under driver's control after
5183          * PCH B stepping, previous chipset stepping should be
5184          * ignoring this setting.
5185          */
5186         temp = I915_READ(PCH_DREF_CONTROL);
5187         /* Always enable nonspread source */
5188         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5189         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5190         temp &= ~DREF_SSC_SOURCE_MASK;
5191         temp |= DREF_SSC_SOURCE_ENABLE;
5192         I915_WRITE(PCH_DREF_CONTROL, temp);
5193
5194         POSTING_READ(PCH_DREF_CONTROL);
5195         udelay(200);
5196
5197         if (has_edp_encoder) {
5198                 if (intel_panel_use_ssc(dev_priv)) {
5199                         temp |= DREF_SSC1_ENABLE;
5200                         I915_WRITE(PCH_DREF_CONTROL, temp);
5201
5202                         POSTING_READ(PCH_DREF_CONTROL);
5203                         udelay(200);
5204                 }
5205                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5206
5207                 /* Enable CPU source on CPU attached eDP */
5208                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5209                         if (intel_panel_use_ssc(dev_priv))
5210                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5211                         else
5212                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5213                 } else {
5214                         /* Enable SSC on PCH eDP if needed */
5215                         if (intel_panel_use_ssc(dev_priv)) {
5216                                 DRM_ERROR("enabling SSC on PCH\n");
5217                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5218                         }
5219                 }
5220                 I915_WRITE(PCH_DREF_CONTROL, temp);
5221                 POSTING_READ(PCH_DREF_CONTROL);
5222                 udelay(200);
5223         }
5224
5225         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5226         if (has_reduced_clock)
5227                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5228                         reduced_clock.m2;
5229
5230         /* Enable autotuning of the PLL clock (if permissible) */
5231         factor = 21;
5232         if (is_lvds) {
5233                 if ((intel_panel_use_ssc(dev_priv) &&
5234                      dev_priv->lvds_ssc_freq == 100) ||
5235                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5236                         factor = 25;
5237         } else if (is_sdvo && is_tv)
5238                 factor = 20;
5239
5240         if (clock.m1 < factor * clock.n)
5241                 fp |= FP_CB_TUNE;
5242
5243         dpll = 0;
5244
5245         if (is_lvds)
5246                 dpll |= DPLLB_MODE_LVDS;
5247         else
5248                 dpll |= DPLLB_MODE_DAC_SERIAL;
5249         if (is_sdvo) {
5250                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5251                 if (pixel_multiplier > 1) {
5252                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5253                 }
5254                 dpll |= DPLL_DVO_HIGH_SPEED;
5255         }
5256         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5257                 dpll |= DPLL_DVO_HIGH_SPEED;
5258
5259         /* compute bitmask from p1 value */
5260         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5261         /* also FPA1 */
5262         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5263
5264         switch (clock.p2) {
5265         case 5:
5266                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5267                 break;
5268         case 7:
5269                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5270                 break;
5271         case 10:
5272                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5273                 break;
5274         case 14:
5275                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5276                 break;
5277         }
5278
5279         if (is_sdvo && is_tv)
5280                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5281         else if (is_tv)
5282                 /* XXX: just matching BIOS for now */
5283                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5284                 dpll |= 3;
5285         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5286                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5287         else
5288                 dpll |= PLL_REF_INPUT_DREFCLK;
5289
5290         /* setup pipeconf */
5291         pipeconf = I915_READ(PIPECONF(pipe));
5292
5293         /* Set up the display plane register */
5294         dspcntr = DISPPLANE_GAMMA_ENABLE;
5295
5296         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5297         drm_mode_debug_printmodeline(mode);
5298
5299         /* PCH eDP needs FDI, but CPU eDP does not */
5300         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5301                 I915_WRITE(PCH_FP0(pipe), fp);
5302                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5303
5304                 POSTING_READ(PCH_DPLL(pipe));
5305                 udelay(150);
5306         }
5307
5308         /* enable transcoder DPLL */
5309         if (HAS_PCH_CPT(dev)) {
5310                 temp = I915_READ(PCH_DPLL_SEL);
5311                 switch (pipe) {
5312                 case 0:
5313                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5314                         break;
5315                 case 1:
5316                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5317                         break;
5318                 case 2:
5319                         /* FIXME: manage transcoder PLLs? */
5320                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5321                         break;
5322                 default:
5323                         BUG();
5324                 }
5325                 I915_WRITE(PCH_DPLL_SEL, temp);
5326
5327                 POSTING_READ(PCH_DPLL_SEL);
5328                 udelay(150);
5329         }
5330
5331         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5332          * This is an exception to the general rule that mode_set doesn't turn
5333          * things on.
5334          */
5335         if (is_lvds) {
5336                 temp = I915_READ(PCH_LVDS);
5337                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5338                 if (pipe == 1) {
5339                         if (HAS_PCH_CPT(dev))
5340                                 temp |= PORT_TRANS_B_SEL_CPT;
5341                         else
5342                                 temp |= LVDS_PIPEB_SELECT;
5343                 } else {
5344                         if (HAS_PCH_CPT(dev))
5345                                 temp &= ~PORT_TRANS_SEL_MASK;
5346                         else
5347                                 temp &= ~LVDS_PIPEB_SELECT;
5348                 }
5349                 /* set the corresponsding LVDS_BORDER bit */
5350                 temp |= dev_priv->lvds_border_bits;
5351                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5352                  * set the DPLLs for dual-channel mode or not.
5353                  */
5354                 if (clock.p2 == 7)
5355                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5356                 else
5357                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5358
5359                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5360                  * appropriately here, but we need to look more thoroughly into how
5361                  * panels behave in the two modes.
5362                  */
5363                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5364                         lvds_sync |= LVDS_HSYNC_POLARITY;
5365                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5366                         lvds_sync |= LVDS_VSYNC_POLARITY;
5367                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5368                     != lvds_sync) {
5369                         char flags[2] = "-+";
5370                         DRM_INFO("Changing LVDS panel from "
5371                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5372                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5373                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5374                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5375                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5376                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5377                         temp |= lvds_sync;
5378                 }
5379                 I915_WRITE(PCH_LVDS, temp);
5380         }
5381
5382         pipeconf &= ~PIPECONF_DITHER_EN;
5383         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5384         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5385                 pipeconf |= PIPECONF_DITHER_EN;
5386                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5387         }
5388         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5389                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5390         } else {
5391                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5392                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5393                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5394                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5395                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5396         }
5397
5398         if (!has_edp_encoder ||
5399             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5400                 I915_WRITE(PCH_DPLL(pipe), dpll);
5401
5402                 /* Wait for the clocks to stabilize. */
5403                 POSTING_READ(PCH_DPLL(pipe));
5404                 udelay(150);
5405
5406                 /* The pixel multiplier can only be updated once the
5407                  * DPLL is enabled and the clocks are stable.
5408                  *
5409                  * So write it again.
5410                  */
5411                 I915_WRITE(PCH_DPLL(pipe), dpll);
5412         }
5413
5414         intel_crtc->lowfreq_avail = false;
5415         if (is_lvds && has_reduced_clock && i915_powersave) {
5416                 I915_WRITE(PCH_FP1(pipe), fp2);
5417                 intel_crtc->lowfreq_avail = true;
5418                 if (HAS_PIPE_CXSR(dev)) {
5419                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5420                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5421                 }
5422         } else {
5423                 I915_WRITE(PCH_FP1(pipe), fp);
5424                 if (HAS_PIPE_CXSR(dev)) {
5425                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5426                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5427                 }
5428         }
5429
5430         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5431                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5432                 /* the chip adds 2 halflines automatically */
5433                 adjusted_mode->crtc_vdisplay -= 1;
5434                 adjusted_mode->crtc_vtotal -= 1;
5435                 adjusted_mode->crtc_vblank_start -= 1;
5436                 adjusted_mode->crtc_vblank_end -= 1;
5437                 adjusted_mode->crtc_vsync_end -= 1;
5438                 adjusted_mode->crtc_vsync_start -= 1;
5439         } else
5440                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5441
5442         I915_WRITE(HTOTAL(pipe),
5443                    (adjusted_mode->crtc_hdisplay - 1) |
5444                    ((adjusted_mode->crtc_htotal - 1) << 16));
5445         I915_WRITE(HBLANK(pipe),
5446                    (adjusted_mode->crtc_hblank_start - 1) |
5447                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5448         I915_WRITE(HSYNC(pipe),
5449                    (adjusted_mode->crtc_hsync_start - 1) |
5450                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5451
5452         I915_WRITE(VTOTAL(pipe),
5453                    (adjusted_mode->crtc_vdisplay - 1) |
5454                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5455         I915_WRITE(VBLANK(pipe),
5456                    (adjusted_mode->crtc_vblank_start - 1) |
5457                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5458         I915_WRITE(VSYNC(pipe),
5459                    (adjusted_mode->crtc_vsync_start - 1) |
5460                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5461
5462         /* pipesrc controls the size that is scaled from, which should
5463          * always be the user's requested size.
5464          */
5465         I915_WRITE(PIPESRC(pipe),
5466                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5467
5468         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5469         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5470         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5471         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5472
5473         if (has_edp_encoder &&
5474             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5475                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5476         }
5477
5478         I915_WRITE(PIPECONF(pipe), pipeconf);
5479         POSTING_READ(PIPECONF(pipe));
5480
5481         intel_wait_for_vblank(dev, pipe);
5482
5483         if (IS_GEN5(dev)) {
5484                 /* enable address swizzle for tiling buffer */
5485                 temp = I915_READ(DISP_ARB_CTL);
5486                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5487         }
5488
5489         I915_WRITE(DSPCNTR(plane), dspcntr);
5490         POSTING_READ(DSPCNTR(plane));
5491
5492         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5493
5494         intel_update_watermarks(dev);
5495
5496         return ret;
5497 }
5498
5499 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5500                                struct drm_display_mode *mode,
5501                                struct drm_display_mode *adjusted_mode,
5502                                int x, int y,
5503                                struct drm_framebuffer *old_fb)
5504 {
5505         struct drm_device *dev = crtc->dev;
5506         struct drm_i915_private *dev_priv = dev->dev_private;
5507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508         int pipe = intel_crtc->pipe;
5509         int ret;
5510
5511         drm_vblank_pre_modeset(dev, pipe);
5512
5513         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5514                                               x, y, old_fb);
5515
5516         drm_vblank_post_modeset(dev, pipe);
5517
5518         return ret;
5519 }
5520
5521 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5522 void intel_crtc_load_lut(struct drm_crtc *crtc)
5523 {
5524         struct drm_device *dev = crtc->dev;
5525         struct drm_i915_private *dev_priv = dev->dev_private;
5526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5527         int palreg = PALETTE(intel_crtc->pipe);
5528         int i;
5529
5530         /* The clocks have to be on to load the palette. */
5531         if (!crtc->enabled)
5532                 return;
5533
5534         /* use legacy palette for Ironlake */
5535         if (HAS_PCH_SPLIT(dev))
5536                 palreg = LGC_PALETTE(intel_crtc->pipe);
5537
5538         for (i = 0; i < 256; i++) {
5539                 I915_WRITE(palreg + 4 * i,
5540                            (intel_crtc->lut_r[i] << 16) |
5541                            (intel_crtc->lut_g[i] << 8) |
5542                            intel_crtc->lut_b[i]);
5543         }
5544 }
5545
5546 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5547 {
5548         struct drm_device *dev = crtc->dev;
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5551         bool visible = base != 0;
5552         u32 cntl;
5553
5554         if (intel_crtc->cursor_visible == visible)
5555                 return;
5556
5557         cntl = I915_READ(_CURACNTR);
5558         if (visible) {
5559                 /* On these chipsets we can only modify the base whilst
5560                  * the cursor is disabled.
5561                  */
5562                 I915_WRITE(_CURABASE, base);
5563
5564                 cntl &= ~(CURSOR_FORMAT_MASK);
5565                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5566                 cntl |= CURSOR_ENABLE |
5567                         CURSOR_GAMMA_ENABLE |
5568                         CURSOR_FORMAT_ARGB;
5569         } else
5570                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5571         I915_WRITE(_CURACNTR, cntl);
5572
5573         intel_crtc->cursor_visible = visible;
5574 }
5575
5576 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5577 {
5578         struct drm_device *dev = crtc->dev;
5579         struct drm_i915_private *dev_priv = dev->dev_private;
5580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5581         int pipe = intel_crtc->pipe;
5582         bool visible = base != 0;
5583
5584         if (intel_crtc->cursor_visible != visible) {
5585                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5586                 if (base) {
5587                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5588                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5589                         cntl |= pipe << 28; /* Connect to correct pipe */
5590                 } else {
5591                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5592                         cntl |= CURSOR_MODE_DISABLE;
5593                 }
5594                 I915_WRITE(CURCNTR(pipe), cntl);
5595
5596                 intel_crtc->cursor_visible = visible;
5597         }
5598         /* and commit changes on next vblank */
5599         I915_WRITE(CURBASE(pipe), base);
5600 }
5601
5602 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5603 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5604                                      bool on)
5605 {
5606         struct drm_device *dev = crtc->dev;
5607         struct drm_i915_private *dev_priv = dev->dev_private;
5608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5609         int pipe = intel_crtc->pipe;
5610         int x = intel_crtc->cursor_x;
5611         int y = intel_crtc->cursor_y;
5612         u32 base, pos;
5613         bool visible;
5614
5615         pos = 0;
5616
5617         if (on && crtc->enabled && crtc->fb) {
5618                 base = intel_crtc->cursor_addr;
5619                 if (x > (int) crtc->fb->width)
5620                         base = 0;
5621
5622                 if (y > (int) crtc->fb->height)
5623                         base = 0;
5624         } else
5625                 base = 0;
5626
5627         if (x < 0) {
5628                 if (x + intel_crtc->cursor_width < 0)
5629                         base = 0;
5630
5631                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5632                 x = -x;
5633         }
5634         pos |= x << CURSOR_X_SHIFT;
5635
5636         if (y < 0) {
5637                 if (y + intel_crtc->cursor_height < 0)
5638                         base = 0;
5639
5640                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5641                 y = -y;
5642         }
5643         pos |= y << CURSOR_Y_SHIFT;
5644
5645         visible = base != 0;
5646         if (!visible && !intel_crtc->cursor_visible)
5647                 return;
5648
5649         I915_WRITE(CURPOS(pipe), pos);
5650         if (IS_845G(dev) || IS_I865G(dev))
5651                 i845_update_cursor(crtc, base);
5652         else
5653                 i9xx_update_cursor(crtc, base);
5654
5655         if (visible)
5656                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5657 }
5658
5659 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5660                                  struct drm_file *file,
5661                                  uint32_t handle,
5662                                  uint32_t width, uint32_t height)
5663 {
5664         struct drm_device *dev = crtc->dev;
5665         struct drm_i915_private *dev_priv = dev->dev_private;
5666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5667         struct drm_i915_gem_object *obj;
5668         uint32_t addr;
5669         int ret;
5670
5671         DRM_DEBUG_KMS("\n");
5672
5673         /* if we want to turn off the cursor ignore width and height */
5674         if (!handle) {
5675                 DRM_DEBUG_KMS("cursor off\n");
5676                 addr = 0;
5677                 obj = NULL;
5678                 mutex_lock(&dev->struct_mutex);
5679                 goto finish;
5680         }
5681
5682         /* Currently we only support 64x64 cursors */
5683         if (width != 64 || height != 64) {
5684                 DRM_ERROR("we currently only support 64x64 cursors\n");
5685                 return -EINVAL;
5686         }
5687
5688         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5689         if (&obj->base == NULL)
5690                 return -ENOENT;
5691
5692         if (obj->base.size < width * height * 4) {
5693                 DRM_ERROR("buffer is to small\n");
5694                 ret = -ENOMEM;
5695                 goto fail;
5696         }
5697
5698         /* we only need to pin inside GTT if cursor is non-phy */
5699         mutex_lock(&dev->struct_mutex);
5700         if (!dev_priv->info->cursor_needs_physical) {
5701                 if (obj->tiling_mode) {
5702                         DRM_ERROR("cursor cannot be tiled\n");
5703                         ret = -EINVAL;
5704                         goto fail_locked;
5705                 }
5706
5707                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5708                 if (ret) {
5709                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5710                         goto fail_locked;
5711                 }
5712
5713                 ret = i915_gem_object_put_fence(obj);
5714                 if (ret) {
5715                         DRM_ERROR("failed to release fence for cursor");
5716                         goto fail_unpin;
5717                 }
5718
5719                 addr = obj->gtt_offset;
5720         } else {
5721                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5722                 ret = i915_gem_attach_phys_object(dev, obj,
5723                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5724                                                   align);
5725                 if (ret) {
5726                         DRM_ERROR("failed to attach phys object\n");
5727                         goto fail_locked;
5728                 }
5729                 addr = obj->phys_obj->handle->busaddr;
5730         }
5731
5732         if (IS_GEN2(dev))
5733                 I915_WRITE(CURSIZE, (height << 12) | width);
5734
5735  finish:
5736         if (intel_crtc->cursor_bo) {
5737                 if (dev_priv->info->cursor_needs_physical) {
5738                         if (intel_crtc->cursor_bo != obj)
5739                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5740                 } else
5741                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5742                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5743         }
5744
5745         mutex_unlock(&dev->struct_mutex);
5746
5747         intel_crtc->cursor_addr = addr;
5748         intel_crtc->cursor_bo = obj;
5749         intel_crtc->cursor_width = width;
5750         intel_crtc->cursor_height = height;
5751
5752         intel_crtc_update_cursor(crtc, true);
5753
5754         return 0;
5755 fail_unpin:
5756         i915_gem_object_unpin(obj);
5757 fail_locked:
5758         mutex_unlock(&dev->struct_mutex);
5759 fail:
5760         drm_gem_object_unreference_unlocked(&obj->base);
5761         return ret;
5762 }
5763
5764 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5765 {
5766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767
5768         intel_crtc->cursor_x = x;
5769         intel_crtc->cursor_y = y;
5770
5771         intel_crtc_update_cursor(crtc, true);
5772
5773         return 0;
5774 }
5775
5776 /** Sets the color ramps on behalf of RandR */
5777 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5778                                  u16 blue, int regno)
5779 {
5780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5781
5782         intel_crtc->lut_r[regno] = red >> 8;
5783         intel_crtc->lut_g[regno] = green >> 8;
5784         intel_crtc->lut_b[regno] = blue >> 8;
5785 }
5786
5787 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5788                              u16 *blue, int regno)
5789 {
5790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791
5792         *red = intel_crtc->lut_r[regno] << 8;
5793         *green = intel_crtc->lut_g[regno] << 8;
5794         *blue = intel_crtc->lut_b[regno] << 8;
5795 }
5796
5797 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5798                                  u16 *blue, uint32_t start, uint32_t size)
5799 {
5800         int end = (start + size > 256) ? 256 : start + size, i;
5801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5802
5803         for (i = start; i < end; i++) {
5804                 intel_crtc->lut_r[i] = red[i] >> 8;
5805                 intel_crtc->lut_g[i] = green[i] >> 8;
5806                 intel_crtc->lut_b[i] = blue[i] >> 8;
5807         }
5808
5809         intel_crtc_load_lut(crtc);
5810 }
5811
5812 /**
5813  * Get a pipe with a simple mode set on it for doing load-based monitor
5814  * detection.
5815  *
5816  * It will be up to the load-detect code to adjust the pipe as appropriate for
5817  * its requirements.  The pipe will be connected to no other encoders.
5818  *
5819  * Currently this code will only succeed if there is a pipe with no encoders
5820  * configured for it.  In the future, it could choose to temporarily disable
5821  * some outputs to free up a pipe for its use.
5822  *
5823  * \return crtc, or NULL if no pipes are available.
5824  */
5825
5826 /* VESA 640x480x72Hz mode to set on the pipe */
5827 static struct drm_display_mode load_detect_mode = {
5828         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5829                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5830 };
5831
5832 static struct drm_framebuffer *
5833 intel_framebuffer_create(struct drm_device *dev,
5834                          struct drm_mode_fb_cmd *mode_cmd,
5835                          struct drm_i915_gem_object *obj)
5836 {
5837         struct intel_framebuffer *intel_fb;
5838         int ret;
5839
5840         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5841         if (!intel_fb) {
5842                 drm_gem_object_unreference_unlocked(&obj->base);
5843                 return ERR_PTR(-ENOMEM);
5844         }
5845
5846         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5847         if (ret) {
5848                 drm_gem_object_unreference_unlocked(&obj->base);
5849                 kfree(intel_fb);
5850                 return ERR_PTR(ret);
5851         }
5852
5853         return &intel_fb->base;
5854 }
5855
5856 static u32
5857 intel_framebuffer_pitch_for_width(int width, int bpp)
5858 {
5859         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5860         return ALIGN(pitch, 64);
5861 }
5862
5863 static u32
5864 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5865 {
5866         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5867         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5868 }
5869
5870 static struct drm_framebuffer *
5871 intel_framebuffer_create_for_mode(struct drm_device *dev,
5872                                   struct drm_display_mode *mode,
5873                                   int depth, int bpp)
5874 {
5875         struct drm_i915_gem_object *obj;
5876         struct drm_mode_fb_cmd mode_cmd;
5877
5878         obj = i915_gem_alloc_object(dev,
5879                                     intel_framebuffer_size_for_mode(mode, bpp));
5880         if (obj == NULL)
5881                 return ERR_PTR(-ENOMEM);
5882
5883         mode_cmd.width = mode->hdisplay;
5884         mode_cmd.height = mode->vdisplay;
5885         mode_cmd.depth = depth;
5886         mode_cmd.bpp = bpp;
5887         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5888
5889         return intel_framebuffer_create(dev, &mode_cmd, obj);
5890 }
5891
5892 static struct drm_framebuffer *
5893 mode_fits_in_fbdev(struct drm_device *dev,
5894                    struct drm_display_mode *mode)
5895 {
5896         struct drm_i915_private *dev_priv = dev->dev_private;
5897         struct drm_i915_gem_object *obj;
5898         struct drm_framebuffer *fb;
5899
5900         if (dev_priv->fbdev == NULL)
5901                 return NULL;
5902
5903         obj = dev_priv->fbdev->ifb.obj;
5904         if (obj == NULL)
5905                 return NULL;
5906
5907         fb = &dev_priv->fbdev->ifb.base;
5908         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5909                                                           fb->bits_per_pixel))
5910                 return NULL;
5911
5912         if (obj->base.size < mode->vdisplay * fb->pitch)
5913                 return NULL;
5914
5915         return fb;
5916 }
5917
5918 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5919                                 struct drm_connector *connector,
5920                                 struct drm_display_mode *mode,
5921                                 struct intel_load_detect_pipe *old)
5922 {
5923         struct intel_crtc *intel_crtc;
5924         struct drm_crtc *possible_crtc;
5925         struct drm_encoder *encoder = &intel_encoder->base;
5926         struct drm_crtc *crtc = NULL;
5927         struct drm_device *dev = encoder->dev;
5928         struct drm_framebuffer *old_fb;
5929         int i = -1;
5930
5931         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5932                       connector->base.id, drm_get_connector_name(connector),
5933                       encoder->base.id, drm_get_encoder_name(encoder));
5934
5935         /*
5936          * Algorithm gets a little messy:
5937          *
5938          *   - if the connector already has an assigned crtc, use it (but make
5939          *     sure it's on first)
5940          *
5941          *   - try to find the first unused crtc that can drive this connector,
5942          *     and use that if we find one
5943          */
5944
5945         /* See if we already have a CRTC for this connector */
5946         if (encoder->crtc) {
5947                 crtc = encoder->crtc;
5948
5949                 intel_crtc = to_intel_crtc(crtc);
5950                 old->dpms_mode = intel_crtc->dpms_mode;
5951                 old->load_detect_temp = false;
5952
5953                 /* Make sure the crtc and connector are running */
5954                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5955                         struct drm_encoder_helper_funcs *encoder_funcs;
5956                         struct drm_crtc_helper_funcs *crtc_funcs;
5957
5958                         crtc_funcs = crtc->helper_private;
5959                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5960
5961                         encoder_funcs = encoder->helper_private;
5962                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5963                 }
5964
5965                 return true;
5966         }
5967
5968         /* Find an unused one (if possible) */
5969         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5970                 i++;
5971                 if (!(encoder->possible_crtcs & (1 << i)))
5972                         continue;
5973                 if (!possible_crtc->enabled) {
5974                         crtc = possible_crtc;
5975                         break;
5976                 }
5977         }
5978
5979         /*
5980          * If we didn't find an unused CRTC, don't use any.
5981          */
5982         if (!crtc) {
5983                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5984                 return false;
5985         }
5986
5987         encoder->crtc = crtc;
5988         connector->encoder = encoder;
5989
5990         intel_crtc = to_intel_crtc(crtc);
5991         old->dpms_mode = intel_crtc->dpms_mode;
5992         old->load_detect_temp = true;
5993         old->release_fb = NULL;
5994
5995         if (!mode)
5996                 mode = &load_detect_mode;
5997
5998         old_fb = crtc->fb;
5999
6000         /* We need a framebuffer large enough to accommodate all accesses
6001          * that the plane may generate whilst we perform load detection.
6002          * We can not rely on the fbcon either being present (we get called
6003          * during its initialisation to detect all boot displays, or it may
6004          * not even exist) or that it is large enough to satisfy the
6005          * requested mode.
6006          */
6007         crtc->fb = mode_fits_in_fbdev(dev, mode);
6008         if (crtc->fb == NULL) {
6009                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6010                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6011                 old->release_fb = crtc->fb;
6012         } else
6013                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6014         if (IS_ERR(crtc->fb)) {
6015                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6016                 crtc->fb = old_fb;
6017                 return false;
6018         }
6019
6020         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6021                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6022                 if (old->release_fb)
6023                         old->release_fb->funcs->destroy(old->release_fb);
6024                 crtc->fb = old_fb;
6025                 return false;
6026         }
6027
6028         /* let the connector get through one full cycle before testing */
6029         intel_wait_for_vblank(dev, intel_crtc->pipe);
6030
6031         return true;
6032 }
6033
6034 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6035                                     struct drm_connector *connector,
6036                                     struct intel_load_detect_pipe *old)
6037 {
6038         struct drm_encoder *encoder = &intel_encoder->base;
6039         struct drm_device *dev = encoder->dev;
6040         struct drm_crtc *crtc = encoder->crtc;
6041         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6042         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6043
6044         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6045                       connector->base.id, drm_get_connector_name(connector),
6046                       encoder->base.id, drm_get_encoder_name(encoder));
6047
6048         if (old->load_detect_temp) {
6049                 connector->encoder = NULL;
6050                 drm_helper_disable_unused_functions(dev);
6051
6052                 if (old->release_fb)
6053                         old->release_fb->funcs->destroy(old->release_fb);
6054
6055                 return;
6056         }
6057
6058         /* Switch crtc and encoder back off if necessary */
6059         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6060                 encoder_funcs->dpms(encoder, old->dpms_mode);
6061                 crtc_funcs->dpms(crtc, old->dpms_mode);
6062         }
6063 }
6064
6065 /* Returns the clock of the currently programmed mode of the given pipe. */
6066 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6067 {
6068         struct drm_i915_private *dev_priv = dev->dev_private;
6069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070         int pipe = intel_crtc->pipe;
6071         u32 dpll = I915_READ(DPLL(pipe));
6072         u32 fp;
6073         intel_clock_t clock;
6074
6075         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6076                 fp = I915_READ(FP0(pipe));
6077         else
6078                 fp = I915_READ(FP1(pipe));
6079
6080         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6081         if (IS_PINEVIEW(dev)) {
6082                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6083                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6084         } else {
6085                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6086                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6087         }
6088
6089         if (!IS_GEN2(dev)) {
6090                 if (IS_PINEVIEW(dev))
6091                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6092                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6093                 else
6094                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6095                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6096
6097                 switch (dpll & DPLL_MODE_MASK) {
6098                 case DPLLB_MODE_DAC_SERIAL:
6099                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6100                                 5 : 10;
6101                         break;
6102                 case DPLLB_MODE_LVDS:
6103                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6104                                 7 : 14;
6105                         break;
6106                 default:
6107                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6108                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6109                         return 0;
6110                 }
6111
6112                 /* XXX: Handle the 100Mhz refclk */
6113                 intel_clock(dev, 96000, &clock);
6114         } else {
6115                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6116
6117                 if (is_lvds) {
6118                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6119                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6120                         clock.p2 = 14;
6121
6122                         if ((dpll & PLL_REF_INPUT_MASK) ==
6123                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6124                                 /* XXX: might not be 66MHz */
6125                                 intel_clock(dev, 66000, &clock);
6126                         } else
6127                                 intel_clock(dev, 48000, &clock);
6128                 } else {
6129                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6130                                 clock.p1 = 2;
6131                         else {
6132                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6133                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6134                         }
6135                         if (dpll & PLL_P2_DIVIDE_BY_4)
6136                                 clock.p2 = 4;
6137                         else
6138                                 clock.p2 = 2;
6139
6140                         intel_clock(dev, 48000, &clock);
6141                 }
6142         }
6143
6144         /* XXX: It would be nice to validate the clocks, but we can't reuse
6145          * i830PllIsValid() because it relies on the xf86_config connector
6146          * configuration being accurate, which it isn't necessarily.
6147          */
6148
6149         return clock.dot;
6150 }
6151
6152 /** Returns the currently programmed mode of the given pipe. */
6153 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6154                                              struct drm_crtc *crtc)
6155 {
6156         struct drm_i915_private *dev_priv = dev->dev_private;
6157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6158         int pipe = intel_crtc->pipe;
6159         struct drm_display_mode *mode;
6160         int htot = I915_READ(HTOTAL(pipe));
6161         int hsync = I915_READ(HSYNC(pipe));
6162         int vtot = I915_READ(VTOTAL(pipe));
6163         int vsync = I915_READ(VSYNC(pipe));
6164
6165         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6166         if (!mode)
6167                 return NULL;
6168
6169         mode->clock = intel_crtc_clock_get(dev, crtc);
6170         mode->hdisplay = (htot & 0xffff) + 1;
6171         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6172         mode->hsync_start = (hsync & 0xffff) + 1;
6173         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6174         mode->vdisplay = (vtot & 0xffff) + 1;
6175         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6176         mode->vsync_start = (vsync & 0xffff) + 1;
6177         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6178
6179         drm_mode_set_name(mode);
6180         drm_mode_set_crtcinfo(mode, 0);
6181
6182         return mode;
6183 }
6184
6185 #define GPU_IDLE_TIMEOUT 500 /* ms */
6186
6187 /* When this timer fires, we've been idle for awhile */
6188 static void intel_gpu_idle_timer(unsigned long arg)
6189 {
6190         struct drm_device *dev = (struct drm_device *)arg;
6191         drm_i915_private_t *dev_priv = dev->dev_private;
6192
6193         if (!list_empty(&dev_priv->mm.active_list)) {
6194                 /* Still processing requests, so just re-arm the timer. */
6195                 mod_timer(&dev_priv->idle_timer, jiffies +
6196                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6197                 return;
6198         }
6199
6200         dev_priv->busy = false;
6201         queue_work(dev_priv->wq, &dev_priv->idle_work);
6202 }
6203
6204 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6205
6206 static void intel_crtc_idle_timer(unsigned long arg)
6207 {
6208         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6209         struct drm_crtc *crtc = &intel_crtc->base;
6210         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6211         struct intel_framebuffer *intel_fb;
6212
6213         intel_fb = to_intel_framebuffer(crtc->fb);
6214         if (intel_fb && intel_fb->obj->active) {
6215                 /* The framebuffer is still being accessed by the GPU. */
6216                 mod_timer(&intel_crtc->idle_timer, jiffies +
6217                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6218                 return;
6219         }
6220
6221         intel_crtc->busy = false;
6222         queue_work(dev_priv->wq, &dev_priv->idle_work);
6223 }
6224
6225 static void intel_increase_pllclock(struct drm_crtc *crtc)
6226 {
6227         struct drm_device *dev = crtc->dev;
6228         drm_i915_private_t *dev_priv = dev->dev_private;
6229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6230         int pipe = intel_crtc->pipe;
6231         int dpll_reg = DPLL(pipe);
6232         int dpll;
6233
6234         if (HAS_PCH_SPLIT(dev))
6235                 return;
6236
6237         if (!dev_priv->lvds_downclock_avail)
6238                 return;
6239
6240         dpll = I915_READ(dpll_reg);
6241         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6242                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6243
6244                 /* Unlock panel regs */
6245                 I915_WRITE(PP_CONTROL,
6246                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6247
6248                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6249                 I915_WRITE(dpll_reg, dpll);
6250                 intel_wait_for_vblank(dev, pipe);
6251
6252                 dpll = I915_READ(dpll_reg);
6253                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6254                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6255
6256                 /* ...and lock them again */
6257                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6258         }
6259
6260         /* Schedule downclock */
6261         mod_timer(&intel_crtc->idle_timer, jiffies +
6262                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6263 }
6264
6265 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6266 {
6267         struct drm_device *dev = crtc->dev;
6268         drm_i915_private_t *dev_priv = dev->dev_private;
6269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270         int pipe = intel_crtc->pipe;
6271         int dpll_reg = DPLL(pipe);
6272         int dpll = I915_READ(dpll_reg);
6273
6274         if (HAS_PCH_SPLIT(dev))
6275                 return;
6276
6277         if (!dev_priv->lvds_downclock_avail)
6278                 return;
6279
6280         /*
6281          * Since this is called by a timer, we should never get here in
6282          * the manual case.
6283          */
6284         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6285                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6286
6287                 /* Unlock panel regs */
6288                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6289                            PANEL_UNLOCK_REGS);
6290
6291                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6292                 I915_WRITE(dpll_reg, dpll);
6293                 intel_wait_for_vblank(dev, pipe);
6294                 dpll = I915_READ(dpll_reg);
6295                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6296                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6297
6298                 /* ...and lock them again */
6299                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6300         }
6301
6302 }
6303
6304 /**
6305  * intel_idle_update - adjust clocks for idleness
6306  * @work: work struct
6307  *
6308  * Either the GPU or display (or both) went idle.  Check the busy status
6309  * here and adjust the CRTC and GPU clocks as necessary.
6310  */
6311 static void intel_idle_update(struct work_struct *work)
6312 {
6313         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6314                                                     idle_work);
6315         struct drm_device *dev = dev_priv->dev;
6316         struct drm_crtc *crtc;
6317         struct intel_crtc *intel_crtc;
6318
6319         if (!i915_powersave)
6320                 return;
6321
6322         mutex_lock(&dev->struct_mutex);
6323
6324         i915_update_gfx_val(dev_priv);
6325
6326         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6327                 /* Skip inactive CRTCs */
6328                 if (!crtc->fb)
6329                         continue;
6330
6331                 intel_crtc = to_intel_crtc(crtc);
6332                 if (!intel_crtc->busy)
6333                         intel_decrease_pllclock(crtc);
6334         }
6335
6336
6337         mutex_unlock(&dev->struct_mutex);
6338 }
6339
6340 /**
6341  * intel_mark_busy - mark the GPU and possibly the display busy
6342  * @dev: drm device
6343  * @obj: object we're operating on
6344  *
6345  * Callers can use this function to indicate that the GPU is busy processing
6346  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6347  * buffer), we'll also mark the display as busy, so we know to increase its
6348  * clock frequency.
6349  */
6350 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6351 {
6352         drm_i915_private_t *dev_priv = dev->dev_private;
6353         struct drm_crtc *crtc = NULL;
6354         struct intel_framebuffer *intel_fb;
6355         struct intel_crtc *intel_crtc;
6356
6357         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6358                 return;
6359
6360         if (!dev_priv->busy)
6361                 dev_priv->busy = true;
6362         else
6363                 mod_timer(&dev_priv->idle_timer, jiffies +
6364                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6365
6366         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6367                 if (!crtc->fb)
6368                         continue;
6369
6370                 intel_crtc = to_intel_crtc(crtc);
6371                 intel_fb = to_intel_framebuffer(crtc->fb);
6372                 if (intel_fb->obj == obj) {
6373                         if (!intel_crtc->busy) {
6374                                 /* Non-busy -> busy, upclock */
6375                                 intel_increase_pllclock(crtc);
6376                                 intel_crtc->busy = true;
6377                         } else {
6378                                 /* Busy -> busy, put off timer */
6379                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6380                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6381                         }
6382                 }
6383         }
6384 }
6385
6386 static void intel_crtc_destroy(struct drm_crtc *crtc)
6387 {
6388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389         struct drm_device *dev = crtc->dev;
6390         struct intel_unpin_work *work;
6391         unsigned long flags;
6392
6393         spin_lock_irqsave(&dev->event_lock, flags);
6394         work = intel_crtc->unpin_work;
6395         intel_crtc->unpin_work = NULL;
6396         spin_unlock_irqrestore(&dev->event_lock, flags);
6397
6398         if (work) {
6399                 cancel_work_sync(&work->work);
6400                 kfree(work);
6401         }
6402
6403         drm_crtc_cleanup(crtc);
6404
6405         kfree(intel_crtc);
6406 }
6407
6408 static void intel_unpin_work_fn(struct work_struct *__work)
6409 {
6410         struct intel_unpin_work *work =
6411                 container_of(__work, struct intel_unpin_work, work);
6412
6413         mutex_lock(&work->dev->struct_mutex);
6414         i915_gem_object_unpin(work->old_fb_obj);
6415         drm_gem_object_unreference(&work->pending_flip_obj->base);
6416         drm_gem_object_unreference(&work->old_fb_obj->base);
6417
6418         intel_update_fbc(work->dev);
6419         mutex_unlock(&work->dev->struct_mutex);
6420         kfree(work);
6421 }
6422
6423 static void do_intel_finish_page_flip(struct drm_device *dev,
6424                                       struct drm_crtc *crtc)
6425 {
6426         drm_i915_private_t *dev_priv = dev->dev_private;
6427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6428         struct intel_unpin_work *work;
6429         struct drm_i915_gem_object *obj;
6430         struct drm_pending_vblank_event *e;
6431         struct timeval tnow, tvbl;
6432         unsigned long flags;
6433
6434         /* Ignore early vblank irqs */
6435         if (intel_crtc == NULL)
6436                 return;
6437
6438         do_gettimeofday(&tnow);
6439
6440         spin_lock_irqsave(&dev->event_lock, flags);
6441         work = intel_crtc->unpin_work;
6442         if (work == NULL || !work->pending) {
6443                 spin_unlock_irqrestore(&dev->event_lock, flags);
6444                 return;
6445         }
6446
6447         intel_crtc->unpin_work = NULL;
6448
6449         if (work->event) {
6450                 e = work->event;
6451                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6452
6453                 /* Called before vblank count and timestamps have
6454                  * been updated for the vblank interval of flip
6455                  * completion? Need to increment vblank count and
6456                  * add one videorefresh duration to returned timestamp
6457                  * to account for this. We assume this happened if we
6458                  * get called over 0.9 frame durations after the last
6459                  * timestamped vblank.
6460                  *
6461                  * This calculation can not be used with vrefresh rates
6462                  * below 5Hz (10Hz to be on the safe side) without
6463                  * promoting to 64 integers.
6464                  */
6465                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6466                     9 * crtc->framedur_ns) {
6467                         e->event.sequence++;
6468                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6469                                              crtc->framedur_ns);
6470                 }
6471
6472                 e->event.tv_sec = tvbl.tv_sec;
6473                 e->event.tv_usec = tvbl.tv_usec;
6474
6475                 list_add_tail(&e->base.link,
6476                               &e->base.file_priv->event_list);
6477                 wake_up_interruptible(&e->base.file_priv->event_wait);
6478         }
6479
6480         drm_vblank_put(dev, intel_crtc->pipe);
6481
6482         spin_unlock_irqrestore(&dev->event_lock, flags);
6483
6484         obj = work->old_fb_obj;
6485
6486         atomic_clear_mask(1 << intel_crtc->plane,
6487                           &obj->pending_flip.counter);
6488         if (atomic_read(&obj->pending_flip) == 0)
6489                 wake_up(&dev_priv->pending_flip_queue);
6490
6491         schedule_work(&work->work);
6492
6493         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6494 }
6495
6496 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6497 {
6498         drm_i915_private_t *dev_priv = dev->dev_private;
6499         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6500
6501         do_intel_finish_page_flip(dev, crtc);
6502 }
6503
6504 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6505 {
6506         drm_i915_private_t *dev_priv = dev->dev_private;
6507         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6508
6509         do_intel_finish_page_flip(dev, crtc);
6510 }
6511
6512 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6513 {
6514         drm_i915_private_t *dev_priv = dev->dev_private;
6515         struct intel_crtc *intel_crtc =
6516                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6517         unsigned long flags;
6518
6519         spin_lock_irqsave(&dev->event_lock, flags);
6520         if (intel_crtc->unpin_work) {
6521                 if ((++intel_crtc->unpin_work->pending) > 1)
6522                         DRM_ERROR("Prepared flip multiple times\n");
6523         } else {
6524                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6525         }
6526         spin_unlock_irqrestore(&dev->event_lock, flags);
6527 }
6528
6529 static int intel_gen2_queue_flip(struct drm_device *dev,
6530                                  struct drm_crtc *crtc,
6531                                  struct drm_framebuffer *fb,
6532                                  struct drm_i915_gem_object *obj)
6533 {
6534         struct drm_i915_private *dev_priv = dev->dev_private;
6535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6536         unsigned long offset;
6537         u32 flip_mask;
6538         int ret;
6539
6540         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6541         if (ret)
6542                 goto out;
6543
6544         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6545         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6546
6547         ret = BEGIN_LP_RING(6);
6548         if (ret)
6549                 goto out;
6550
6551         /* Can't queue multiple flips, so wait for the previous
6552          * one to finish before executing the next.
6553          */
6554         if (intel_crtc->plane)
6555                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6556         else
6557                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6558         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6559         OUT_RING(MI_NOOP);
6560         OUT_RING(MI_DISPLAY_FLIP |
6561                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6562         OUT_RING(fb->pitch);
6563         OUT_RING(obj->gtt_offset + offset);
6564         OUT_RING(MI_NOOP);
6565         ADVANCE_LP_RING();
6566 out:
6567         return ret;
6568 }
6569
6570 static int intel_gen3_queue_flip(struct drm_device *dev,
6571                                  struct drm_crtc *crtc,
6572                                  struct drm_framebuffer *fb,
6573                                  struct drm_i915_gem_object *obj)
6574 {
6575         struct drm_i915_private *dev_priv = dev->dev_private;
6576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6577         unsigned long offset;
6578         u32 flip_mask;
6579         int ret;
6580
6581         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6582         if (ret)
6583                 goto out;
6584
6585         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6586         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6587
6588         ret = BEGIN_LP_RING(6);
6589         if (ret)
6590                 goto out;
6591
6592         if (intel_crtc->plane)
6593                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6594         else
6595                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6596         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6597         OUT_RING(MI_NOOP);
6598         OUT_RING(MI_DISPLAY_FLIP_I915 |
6599                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6600         OUT_RING(fb->pitch);
6601         OUT_RING(obj->gtt_offset + offset);
6602         OUT_RING(MI_NOOP);
6603
6604         ADVANCE_LP_RING();
6605 out:
6606         return ret;
6607 }
6608
6609 static int intel_gen4_queue_flip(struct drm_device *dev,
6610                                  struct drm_crtc *crtc,
6611                                  struct drm_framebuffer *fb,
6612                                  struct drm_i915_gem_object *obj)
6613 {
6614         struct drm_i915_private *dev_priv = dev->dev_private;
6615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6616         uint32_t pf, pipesrc;
6617         int ret;
6618
6619         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6620         if (ret)
6621                 goto out;
6622
6623         ret = BEGIN_LP_RING(4);
6624         if (ret)
6625                 goto out;
6626
6627         /* i965+ uses the linear or tiled offsets from the
6628          * Display Registers (which do not change across a page-flip)
6629          * so we need only reprogram the base address.
6630          */
6631         OUT_RING(MI_DISPLAY_FLIP |
6632                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6633         OUT_RING(fb->pitch);
6634         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6635
6636         /* XXX Enabling the panel-fitter across page-flip is so far
6637          * untested on non-native modes, so ignore it for now.
6638          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6639          */
6640         pf = 0;
6641         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6642         OUT_RING(pf | pipesrc);
6643         ADVANCE_LP_RING();
6644 out:
6645         return ret;
6646 }
6647
6648 static int intel_gen6_queue_flip(struct drm_device *dev,
6649                                  struct drm_crtc *crtc,
6650                                  struct drm_framebuffer *fb,
6651                                  struct drm_i915_gem_object *obj)
6652 {
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6655         uint32_t pf, pipesrc;
6656         int ret;
6657
6658         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6659         if (ret)
6660                 goto out;
6661
6662         ret = BEGIN_LP_RING(4);
6663         if (ret)
6664                 goto out;
6665
6666         OUT_RING(MI_DISPLAY_FLIP |
6667                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6668         OUT_RING(fb->pitch | obj->tiling_mode);
6669         OUT_RING(obj->gtt_offset);
6670
6671         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6672         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6673         OUT_RING(pf | pipesrc);
6674         ADVANCE_LP_RING();
6675 out:
6676         return ret;
6677 }
6678
6679 /*
6680  * On gen7 we currently use the blit ring because (in early silicon at least)
6681  * the render ring doesn't give us interrpts for page flip completion, which
6682  * means clients will hang after the first flip is queued.  Fortunately the
6683  * blit ring generates interrupts properly, so use it instead.
6684  */
6685 static int intel_gen7_queue_flip(struct drm_device *dev,
6686                                  struct drm_crtc *crtc,
6687                                  struct drm_framebuffer *fb,
6688                                  struct drm_i915_gem_object *obj)
6689 {
6690         struct drm_i915_private *dev_priv = dev->dev_private;
6691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6692         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6693         int ret;
6694
6695         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6696         if (ret)
6697                 goto out;
6698
6699         ret = intel_ring_begin(ring, 4);
6700         if (ret)
6701                 goto out;
6702
6703         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6704         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6705         intel_ring_emit(ring, (obj->gtt_offset));
6706         intel_ring_emit(ring, (MI_NOOP));
6707         intel_ring_advance(ring);
6708 out:
6709         return ret;
6710 }
6711
6712 static int intel_default_queue_flip(struct drm_device *dev,
6713                                     struct drm_crtc *crtc,
6714                                     struct drm_framebuffer *fb,
6715                                     struct drm_i915_gem_object *obj)
6716 {
6717         return -ENODEV;
6718 }
6719
6720 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6721                                 struct drm_framebuffer *fb,
6722                                 struct drm_pending_vblank_event *event)
6723 {
6724         struct drm_device *dev = crtc->dev;
6725         struct drm_i915_private *dev_priv = dev->dev_private;
6726         struct intel_framebuffer *intel_fb;
6727         struct drm_i915_gem_object *obj;
6728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6729         struct intel_unpin_work *work;
6730         unsigned long flags;
6731         int ret;
6732
6733         work = kzalloc(sizeof *work, GFP_KERNEL);
6734         if (work == NULL)
6735                 return -ENOMEM;
6736
6737         work->event = event;
6738         work->dev = crtc->dev;
6739         intel_fb = to_intel_framebuffer(crtc->fb);
6740         work->old_fb_obj = intel_fb->obj;
6741         INIT_WORK(&work->work, intel_unpin_work_fn);
6742
6743         /* We borrow the event spin lock for protecting unpin_work */
6744         spin_lock_irqsave(&dev->event_lock, flags);
6745         if (intel_crtc->unpin_work) {
6746                 spin_unlock_irqrestore(&dev->event_lock, flags);
6747                 kfree(work);
6748
6749                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6750                 return -EBUSY;
6751         }
6752         intel_crtc->unpin_work = work;
6753         spin_unlock_irqrestore(&dev->event_lock, flags);
6754
6755         intel_fb = to_intel_framebuffer(fb);
6756         obj = intel_fb->obj;
6757
6758         mutex_lock(&dev->struct_mutex);
6759
6760         /* Reference the objects for the scheduled work. */
6761         drm_gem_object_reference(&work->old_fb_obj->base);
6762         drm_gem_object_reference(&obj->base);
6763
6764         crtc->fb = fb;
6765
6766         ret = drm_vblank_get(dev, intel_crtc->pipe);
6767         if (ret)
6768                 goto cleanup_objs;
6769
6770         work->pending_flip_obj = obj;
6771
6772         work->enable_stall_check = true;
6773
6774         /* Block clients from rendering to the new back buffer until
6775          * the flip occurs and the object is no longer visible.
6776          */
6777         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6778
6779         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6780         if (ret)
6781                 goto cleanup_pending;
6782
6783         intel_disable_fbc(dev);
6784         mutex_unlock(&dev->struct_mutex);
6785
6786         trace_i915_flip_request(intel_crtc->plane, obj);
6787
6788         return 0;
6789
6790 cleanup_pending:
6791         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6792 cleanup_objs:
6793         drm_gem_object_unreference(&work->old_fb_obj->base);
6794         drm_gem_object_unreference(&obj->base);
6795         mutex_unlock(&dev->struct_mutex);
6796
6797         spin_lock_irqsave(&dev->event_lock, flags);
6798         intel_crtc->unpin_work = NULL;
6799         spin_unlock_irqrestore(&dev->event_lock, flags);
6800
6801         kfree(work);
6802
6803         return ret;
6804 }
6805
6806 static void intel_sanitize_modesetting(struct drm_device *dev,
6807                                        int pipe, int plane)
6808 {
6809         struct drm_i915_private *dev_priv = dev->dev_private;
6810         u32 reg, val;
6811
6812         if (HAS_PCH_SPLIT(dev))
6813                 return;
6814
6815         /* Who knows what state these registers were left in by the BIOS or
6816          * grub?
6817          *
6818          * If we leave the registers in a conflicting state (e.g. with the
6819          * display plane reading from the other pipe than the one we intend
6820          * to use) then when we attempt to teardown the active mode, we will
6821          * not disable the pipes and planes in the correct order -- leaving
6822          * a plane reading from a disabled pipe and possibly leading to
6823          * undefined behaviour.
6824          */
6825
6826         reg = DSPCNTR(plane);
6827         val = I915_READ(reg);
6828
6829         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6830                 return;
6831         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6832                 return;
6833
6834         /* This display plane is active and attached to the other CPU pipe. */
6835         pipe = !pipe;
6836
6837         /* Disable the plane and wait for it to stop reading from the pipe. */
6838         intel_disable_plane(dev_priv, plane, pipe);
6839         intel_disable_pipe(dev_priv, pipe);
6840 }
6841
6842 static void intel_crtc_reset(struct drm_crtc *crtc)
6843 {
6844         struct drm_device *dev = crtc->dev;
6845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846
6847         /* Reset flags back to the 'unknown' status so that they
6848          * will be correctly set on the initial modeset.
6849          */
6850         intel_crtc->dpms_mode = -1;
6851
6852         /* We need to fix up any BIOS configuration that conflicts with
6853          * our expectations.
6854          */
6855         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6856 }
6857
6858 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6859         .dpms = intel_crtc_dpms,
6860         .mode_fixup = intel_crtc_mode_fixup,
6861         .mode_set = intel_crtc_mode_set,
6862         .mode_set_base = intel_pipe_set_base,
6863         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6864         .load_lut = intel_crtc_load_lut,
6865         .disable = intel_crtc_disable,
6866 };
6867
6868 static const struct drm_crtc_funcs intel_crtc_funcs = {
6869         .reset = intel_crtc_reset,
6870         .cursor_set = intel_crtc_cursor_set,
6871         .cursor_move = intel_crtc_cursor_move,
6872         .gamma_set = intel_crtc_gamma_set,
6873         .set_config = drm_crtc_helper_set_config,
6874         .destroy = intel_crtc_destroy,
6875         .page_flip = intel_crtc_page_flip,
6876 };
6877
6878 static void intel_crtc_init(struct drm_device *dev, int pipe)
6879 {
6880         drm_i915_private_t *dev_priv = dev->dev_private;
6881         struct intel_crtc *intel_crtc;
6882         int i;
6883
6884         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6885         if (intel_crtc == NULL)
6886                 return;
6887
6888         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6889
6890         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6891         for (i = 0; i < 256; i++) {
6892                 intel_crtc->lut_r[i] = i;
6893                 intel_crtc->lut_g[i] = i;
6894                 intel_crtc->lut_b[i] = i;
6895         }
6896
6897         /* Swap pipes & planes for FBC on pre-965 */
6898         intel_crtc->pipe = pipe;
6899         intel_crtc->plane = pipe;
6900         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6901                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6902                 intel_crtc->plane = !pipe;
6903         }
6904
6905         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6906                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6907         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6908         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6909
6910         intel_crtc_reset(&intel_crtc->base);
6911         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6912         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6913
6914         if (HAS_PCH_SPLIT(dev)) {
6915                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6916                 intel_helper_funcs.commit = ironlake_crtc_commit;
6917         } else {
6918                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6919                 intel_helper_funcs.commit = i9xx_crtc_commit;
6920         }
6921
6922         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6923
6924         intel_crtc->busy = false;
6925
6926         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6927                     (unsigned long)intel_crtc);
6928 }
6929
6930 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6931                                 struct drm_file *file)
6932 {
6933         drm_i915_private_t *dev_priv = dev->dev_private;
6934         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6935         struct drm_mode_object *drmmode_obj;
6936         struct intel_crtc *crtc;
6937
6938         if (!dev_priv) {
6939                 DRM_ERROR("called with no initialization\n");
6940                 return -EINVAL;
6941         }
6942
6943         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6944                         DRM_MODE_OBJECT_CRTC);
6945
6946         if (!drmmode_obj) {
6947                 DRM_ERROR("no such CRTC id\n");
6948                 return -EINVAL;
6949         }
6950
6951         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6952         pipe_from_crtc_id->pipe = crtc->pipe;
6953
6954         return 0;
6955 }
6956
6957 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6958 {
6959         struct intel_encoder *encoder;
6960         int index_mask = 0;
6961         int entry = 0;
6962
6963         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6964                 if (type_mask & encoder->clone_mask)
6965                         index_mask |= (1 << entry);
6966                 entry++;
6967         }
6968
6969         return index_mask;
6970 }
6971
6972 static bool has_edp_a(struct drm_device *dev)
6973 {
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975
6976         if (!IS_MOBILE(dev))
6977                 return false;
6978
6979         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6980                 return false;
6981
6982         if (IS_GEN5(dev) &&
6983             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6984                 return false;
6985
6986         return true;
6987 }
6988
6989 static void intel_setup_outputs(struct drm_device *dev)
6990 {
6991         struct drm_i915_private *dev_priv = dev->dev_private;
6992         struct intel_encoder *encoder;
6993         bool dpd_is_edp = false;
6994         bool has_lvds = false;
6995
6996         if (IS_MOBILE(dev) && !IS_I830(dev))
6997                 has_lvds = intel_lvds_init(dev);
6998         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6999                 /* disable the panel fitter on everything but LVDS */
7000                 I915_WRITE(PFIT_CONTROL, 0);
7001         }
7002
7003         if (HAS_PCH_SPLIT(dev)) {
7004                 dpd_is_edp = intel_dpd_is_edp(dev);
7005
7006                 if (has_edp_a(dev))
7007                         intel_dp_init(dev, DP_A);
7008
7009                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7010                         intel_dp_init(dev, PCH_DP_D);
7011         }
7012
7013         intel_crt_init(dev);
7014
7015         if (HAS_PCH_SPLIT(dev)) {
7016                 int found;
7017
7018                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7019                         /* PCH SDVOB multiplex with HDMIB */
7020                         found = intel_sdvo_init(dev, PCH_SDVOB);
7021                         if (!found)
7022                                 intel_hdmi_init(dev, HDMIB);
7023                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7024                                 intel_dp_init(dev, PCH_DP_B);
7025                 }
7026
7027                 if (I915_READ(HDMIC) & PORT_DETECTED)
7028                         intel_hdmi_init(dev, HDMIC);
7029
7030                 if (I915_READ(HDMID) & PORT_DETECTED)
7031                         intel_hdmi_init(dev, HDMID);
7032
7033                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7034                         intel_dp_init(dev, PCH_DP_C);
7035
7036                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7037                         intel_dp_init(dev, PCH_DP_D);
7038
7039         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7040                 bool found = false;
7041
7042                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7043                         DRM_DEBUG_KMS("probing SDVOB\n");
7044                         found = intel_sdvo_init(dev, SDVOB);
7045                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7046                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7047                                 intel_hdmi_init(dev, SDVOB);
7048                         }
7049
7050                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7051                                 DRM_DEBUG_KMS("probing DP_B\n");
7052                                 intel_dp_init(dev, DP_B);
7053                         }
7054                 }
7055
7056                 /* Before G4X SDVOC doesn't have its own detect register */
7057
7058                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7059                         DRM_DEBUG_KMS("probing SDVOC\n");
7060                         found = intel_sdvo_init(dev, SDVOC);
7061                 }
7062
7063                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7064
7065                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7066                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7067                                 intel_hdmi_init(dev, SDVOC);
7068                         }
7069                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7070                                 DRM_DEBUG_KMS("probing DP_C\n");
7071                                 intel_dp_init(dev, DP_C);
7072                         }
7073                 }
7074
7075                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7076                     (I915_READ(DP_D) & DP_DETECTED)) {
7077                         DRM_DEBUG_KMS("probing DP_D\n");
7078                         intel_dp_init(dev, DP_D);
7079                 }
7080         } else if (IS_GEN2(dev))
7081                 intel_dvo_init(dev);
7082
7083         if (SUPPORTS_TV(dev))
7084                 intel_tv_init(dev);
7085
7086         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7087                 encoder->base.possible_crtcs = encoder->crtc_mask;
7088                 encoder->base.possible_clones =
7089                         intel_encoder_clones(dev, encoder->clone_mask);
7090         }
7091
7092         intel_panel_setup_backlight(dev);
7093
7094         /* disable all the possible outputs/crtcs before entering KMS mode */
7095         drm_helper_disable_unused_functions(dev);
7096 }
7097
7098 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7099 {
7100         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7101
7102         drm_framebuffer_cleanup(fb);
7103         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7104
7105         kfree(intel_fb);
7106 }
7107
7108 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7109                                                 struct drm_file *file,
7110                                                 unsigned int *handle)
7111 {
7112         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7113         struct drm_i915_gem_object *obj = intel_fb->obj;
7114
7115         return drm_gem_handle_create(file, &obj->base, handle);
7116 }
7117
7118 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7119         .destroy = intel_user_framebuffer_destroy,
7120         .create_handle = intel_user_framebuffer_create_handle,
7121 };
7122
7123 int intel_framebuffer_init(struct drm_device *dev,
7124                            struct intel_framebuffer *intel_fb,
7125                            struct drm_mode_fb_cmd *mode_cmd,
7126                            struct drm_i915_gem_object *obj)
7127 {
7128         int ret;
7129
7130         if (obj->tiling_mode == I915_TILING_Y)
7131                 return -EINVAL;
7132
7133         if (mode_cmd->pitch & 63)
7134                 return -EINVAL;
7135
7136         switch (mode_cmd->bpp) {
7137         case 8:
7138         case 16:
7139                 /* Only pre-ILK can handle 5:5:5 */
7140                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7141                         return -EINVAL;
7142                 break;
7143
7144         case 24:
7145         case 32:
7146                 break;
7147         default:
7148                 return -EINVAL;
7149         }
7150
7151         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7152         if (ret) {
7153                 DRM_ERROR("framebuffer init failed %d\n", ret);
7154                 return ret;
7155         }
7156
7157         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7158         intel_fb->obj = obj;
7159         return 0;
7160 }
7161
7162 static struct drm_framebuffer *
7163 intel_user_framebuffer_create(struct drm_device *dev,
7164                               struct drm_file *filp,
7165                               struct drm_mode_fb_cmd *mode_cmd)
7166 {
7167         struct drm_i915_gem_object *obj;
7168
7169         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7170         if (&obj->base == NULL)
7171                 return ERR_PTR(-ENOENT);
7172
7173         return intel_framebuffer_create(dev, mode_cmd, obj);
7174 }
7175
7176 static const struct drm_mode_config_funcs intel_mode_funcs = {
7177         .fb_create = intel_user_framebuffer_create,
7178         .output_poll_changed = intel_fb_output_poll_changed,
7179 };
7180
7181 static struct drm_i915_gem_object *
7182 intel_alloc_context_page(struct drm_device *dev)
7183 {
7184         struct drm_i915_gem_object *ctx;
7185         int ret;
7186
7187         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7188
7189         ctx = i915_gem_alloc_object(dev, 4096);
7190         if (!ctx) {
7191                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7192                 return NULL;
7193         }
7194
7195         ret = i915_gem_object_pin(ctx, 4096, true);
7196         if (ret) {
7197                 DRM_ERROR("failed to pin power context: %d\n", ret);
7198                 goto err_unref;
7199         }
7200
7201         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7202         if (ret) {
7203                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7204                 goto err_unpin;
7205         }
7206
7207         return ctx;
7208
7209 err_unpin:
7210         i915_gem_object_unpin(ctx);
7211 err_unref:
7212         drm_gem_object_unreference(&ctx->base);
7213         mutex_unlock(&dev->struct_mutex);
7214         return NULL;
7215 }
7216
7217 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7218 {
7219         struct drm_i915_private *dev_priv = dev->dev_private;
7220         u16 rgvswctl;
7221
7222         rgvswctl = I915_READ16(MEMSWCTL);
7223         if (rgvswctl & MEMCTL_CMD_STS) {
7224                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7225                 return false; /* still busy with another command */
7226         }
7227
7228         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7229                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7230         I915_WRITE16(MEMSWCTL, rgvswctl);
7231         POSTING_READ16(MEMSWCTL);
7232
7233         rgvswctl |= MEMCTL_CMD_STS;
7234         I915_WRITE16(MEMSWCTL, rgvswctl);
7235
7236         return true;
7237 }
7238
7239 void ironlake_enable_drps(struct drm_device *dev)
7240 {
7241         struct drm_i915_private *dev_priv = dev->dev_private;
7242         u32 rgvmodectl = I915_READ(MEMMODECTL);
7243         u8 fmax, fmin, fstart, vstart;
7244
7245         /* Enable temp reporting */
7246         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7247         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7248
7249         /* 100ms RC evaluation intervals */
7250         I915_WRITE(RCUPEI, 100000);
7251         I915_WRITE(RCDNEI, 100000);
7252
7253         /* Set max/min thresholds to 90ms and 80ms respectively */
7254         I915_WRITE(RCBMAXAVG, 90000);
7255         I915_WRITE(RCBMINAVG, 80000);
7256
7257         I915_WRITE(MEMIHYST, 1);
7258
7259         /* Set up min, max, and cur for interrupt handling */
7260         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7261         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7262         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7263                 MEMMODE_FSTART_SHIFT;
7264
7265         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7266                 PXVFREQ_PX_SHIFT;
7267
7268         dev_priv->fmax = fmax; /* IPS callback will increase this */
7269         dev_priv->fstart = fstart;
7270
7271         dev_priv->max_delay = fstart;
7272         dev_priv->min_delay = fmin;
7273         dev_priv->cur_delay = fstart;
7274
7275         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7276                          fmax, fmin, fstart);
7277
7278         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7279
7280         /*
7281          * Interrupts will be enabled in ironlake_irq_postinstall
7282          */
7283
7284         I915_WRITE(VIDSTART, vstart);
7285         POSTING_READ(VIDSTART);
7286
7287         rgvmodectl |= MEMMODE_SWMODE_EN;
7288         I915_WRITE(MEMMODECTL, rgvmodectl);
7289
7290         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7291                 DRM_ERROR("stuck trying to change perf mode\n");
7292         msleep(1);
7293
7294         ironlake_set_drps(dev, fstart);
7295
7296         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7297                 I915_READ(0x112e0);
7298         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7299         dev_priv->last_count2 = I915_READ(0x112f4);
7300         getrawmonotonic(&dev_priv->last_time2);
7301 }
7302
7303 void ironlake_disable_drps(struct drm_device *dev)
7304 {
7305         struct drm_i915_private *dev_priv = dev->dev_private;
7306         u16 rgvswctl = I915_READ16(MEMSWCTL);
7307
7308         /* Ack interrupts, disable EFC interrupt */
7309         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7310         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7311         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7312         I915_WRITE(DEIIR, DE_PCU_EVENT);
7313         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7314
7315         /* Go back to the starting frequency */
7316         ironlake_set_drps(dev, dev_priv->fstart);
7317         msleep(1);
7318         rgvswctl |= MEMCTL_CMD_STS;
7319         I915_WRITE(MEMSWCTL, rgvswctl);
7320         msleep(1);
7321
7322 }
7323
7324 void gen6_set_rps(struct drm_device *dev, u8 val)
7325 {
7326         struct drm_i915_private *dev_priv = dev->dev_private;
7327         u32 swreq;
7328
7329         swreq = (val & 0x3ff) << 25;
7330         I915_WRITE(GEN6_RPNSWREQ, swreq);
7331 }
7332
7333 void gen6_disable_rps(struct drm_device *dev)
7334 {
7335         struct drm_i915_private *dev_priv = dev->dev_private;
7336
7337         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7338         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7339         I915_WRITE(GEN6_PMIER, 0);
7340
7341         spin_lock_irq(&dev_priv->rps_lock);
7342         dev_priv->pm_iir = 0;
7343         spin_unlock_irq(&dev_priv->rps_lock);
7344
7345         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7346 }
7347
7348 static unsigned long intel_pxfreq(u32 vidfreq)
7349 {
7350         unsigned long freq;
7351         int div = (vidfreq & 0x3f0000) >> 16;
7352         int post = (vidfreq & 0x3000) >> 12;
7353         int pre = (vidfreq & 0x7);
7354
7355         if (!pre)
7356                 return 0;
7357
7358         freq = ((div * 133333) / ((1<<post) * pre));
7359
7360         return freq;
7361 }
7362
7363 void intel_init_emon(struct drm_device *dev)
7364 {
7365         struct drm_i915_private *dev_priv = dev->dev_private;
7366         u32 lcfuse;
7367         u8 pxw[16];
7368         int i;
7369
7370         /* Disable to program */
7371         I915_WRITE(ECR, 0);
7372         POSTING_READ(ECR);
7373
7374         /* Program energy weights for various events */
7375         I915_WRITE(SDEW, 0x15040d00);
7376         I915_WRITE(CSIEW0, 0x007f0000);
7377         I915_WRITE(CSIEW1, 0x1e220004);
7378         I915_WRITE(CSIEW2, 0x04000004);
7379
7380         for (i = 0; i < 5; i++)
7381                 I915_WRITE(PEW + (i * 4), 0);
7382         for (i = 0; i < 3; i++)
7383                 I915_WRITE(DEW + (i * 4), 0);
7384
7385         /* Program P-state weights to account for frequency power adjustment */
7386         for (i = 0; i < 16; i++) {
7387                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7388                 unsigned long freq = intel_pxfreq(pxvidfreq);
7389                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7390                         PXVFREQ_PX_SHIFT;
7391                 unsigned long val;
7392
7393                 val = vid * vid;
7394                 val *= (freq / 1000);
7395                 val *= 255;
7396                 val /= (127*127*900);
7397                 if (val > 0xff)
7398                         DRM_ERROR("bad pxval: %ld\n", val);
7399                 pxw[i] = val;
7400         }
7401         /* Render standby states get 0 weight */
7402         pxw[14] = 0;
7403         pxw[15] = 0;
7404
7405         for (i = 0; i < 4; i++) {
7406                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7407                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7408                 I915_WRITE(PXW + (i * 4), val);
7409         }
7410
7411         /* Adjust magic regs to magic values (more experimental results) */
7412         I915_WRITE(OGW0, 0);
7413         I915_WRITE(OGW1, 0);
7414         I915_WRITE(EG0, 0x00007f00);
7415         I915_WRITE(EG1, 0x0000000e);
7416         I915_WRITE(EG2, 0x000e0000);
7417         I915_WRITE(EG3, 0x68000300);
7418         I915_WRITE(EG4, 0x42000000);
7419         I915_WRITE(EG5, 0x00140031);
7420         I915_WRITE(EG6, 0);
7421         I915_WRITE(EG7, 0);
7422
7423         for (i = 0; i < 8; i++)
7424                 I915_WRITE(PXWL + (i * 4), 0);
7425
7426         /* Enable PMON + select events */
7427         I915_WRITE(ECR, 0x80000019);
7428
7429         lcfuse = I915_READ(LCFUSE02);
7430
7431         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7432 }
7433
7434 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7435 {
7436         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7437         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7438         u32 pcu_mbox, rc6_mask = 0;
7439         int cur_freq, min_freq, max_freq;
7440         int i;
7441
7442         /* Here begins a magic sequence of register writes to enable
7443          * auto-downclocking.
7444          *
7445          * Perhaps there might be some value in exposing these to
7446          * userspace...
7447          */
7448         I915_WRITE(GEN6_RC_STATE, 0);
7449         mutex_lock(&dev_priv->dev->struct_mutex);
7450         gen6_gt_force_wake_get(dev_priv);
7451
7452         /* disable the counters and set deterministic thresholds */
7453         I915_WRITE(GEN6_RC_CONTROL, 0);
7454
7455         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7456         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7457         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7458         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7459         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7460
7461         for (i = 0; i < I915_NUM_RINGS; i++)
7462                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7463
7464         I915_WRITE(GEN6_RC_SLEEP, 0);
7465         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7466         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7467         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7468         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7469
7470         if (i915_enable_rc6)
7471                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7472                         GEN6_RC_CTL_RC6_ENABLE;
7473
7474         I915_WRITE(GEN6_RC_CONTROL,
7475                    rc6_mask |
7476                    GEN6_RC_CTL_EI_MODE(1) |
7477                    GEN6_RC_CTL_HW_ENABLE);
7478
7479         I915_WRITE(GEN6_RPNSWREQ,
7480                    GEN6_FREQUENCY(10) |
7481                    GEN6_OFFSET(0) |
7482                    GEN6_AGGRESSIVE_TURBO);
7483         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7484                    GEN6_FREQUENCY(12));
7485
7486         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7487         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7488                    18 << 24 |
7489                    6 << 16);
7490         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7491         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7492         I915_WRITE(GEN6_RP_UP_EI, 100000);
7493         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7494         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7495         I915_WRITE(GEN6_RP_CONTROL,
7496                    GEN6_RP_MEDIA_TURBO |
7497                    GEN6_RP_USE_NORMAL_FREQ |
7498                    GEN6_RP_MEDIA_IS_GFX |
7499                    GEN6_RP_ENABLE |
7500                    GEN6_RP_UP_BUSY_AVG |
7501                    GEN6_RP_DOWN_IDLE_CONT);
7502
7503         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7504                      500))
7505                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7506
7507         I915_WRITE(GEN6_PCODE_DATA, 0);
7508         I915_WRITE(GEN6_PCODE_MAILBOX,
7509                    GEN6_PCODE_READY |
7510                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7511         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7512                      500))
7513                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7514
7515         min_freq = (rp_state_cap & 0xff0000) >> 16;
7516         max_freq = rp_state_cap & 0xff;
7517         cur_freq = (gt_perf_status & 0xff00) >> 8;
7518
7519         /* Check for overclock support */
7520         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7521                      500))
7522                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7523         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7524         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7525         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7526                      500))
7527                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7528         if (pcu_mbox & (1<<31)) { /* OC supported */
7529                 max_freq = pcu_mbox & 0xff;
7530                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7531         }
7532
7533         /* In units of 100MHz */
7534         dev_priv->max_delay = max_freq;
7535         dev_priv->min_delay = min_freq;
7536         dev_priv->cur_delay = cur_freq;
7537
7538         /* requires MSI enabled */
7539         I915_WRITE(GEN6_PMIER,
7540                    GEN6_PM_MBOX_EVENT |
7541                    GEN6_PM_THERMAL_EVENT |
7542                    GEN6_PM_RP_DOWN_TIMEOUT |
7543                    GEN6_PM_RP_UP_THRESHOLD |
7544                    GEN6_PM_RP_DOWN_THRESHOLD |
7545                    GEN6_PM_RP_UP_EI_EXPIRED |
7546                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7547         spin_lock_irq(&dev_priv->rps_lock);
7548         WARN_ON(dev_priv->pm_iir != 0);
7549         I915_WRITE(GEN6_PMIMR, 0);
7550         spin_unlock_irq(&dev_priv->rps_lock);
7551         /* enable all PM interrupts */
7552         I915_WRITE(GEN6_PMINTRMSK, 0);
7553
7554         gen6_gt_force_wake_put(dev_priv);
7555         mutex_unlock(&dev_priv->dev->struct_mutex);
7556 }
7557
7558 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7559 {
7560         int min_freq = 15;
7561         int gpu_freq, ia_freq, max_ia_freq;
7562         int scaling_factor = 180;
7563
7564         max_ia_freq = cpufreq_quick_get_max(0);
7565         /*
7566          * Default to measured freq if none found, PCU will ensure we don't go
7567          * over
7568          */
7569         if (!max_ia_freq)
7570                 max_ia_freq = tsc_khz;
7571
7572         /* Convert from kHz to MHz */
7573         max_ia_freq /= 1000;
7574
7575         mutex_lock(&dev_priv->dev->struct_mutex);
7576
7577         /*
7578          * For each potential GPU frequency, load a ring frequency we'd like
7579          * to use for memory access.  We do this by specifying the IA frequency
7580          * the PCU should use as a reference to determine the ring frequency.
7581          */
7582         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7583              gpu_freq--) {
7584                 int diff = dev_priv->max_delay - gpu_freq;
7585
7586                 /*
7587                  * For GPU frequencies less than 750MHz, just use the lowest
7588                  * ring freq.
7589                  */
7590                 if (gpu_freq < min_freq)
7591                         ia_freq = 800;
7592                 else
7593                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7594                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7595
7596                 I915_WRITE(GEN6_PCODE_DATA,
7597                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7598                            gpu_freq);
7599                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7600                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7601                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7602                               GEN6_PCODE_READY) == 0, 10)) {
7603                         DRM_ERROR("pcode write of freq table timed out\n");
7604                         continue;
7605                 }
7606         }
7607
7608         mutex_unlock(&dev_priv->dev->struct_mutex);
7609 }
7610
7611 static void ironlake_init_clock_gating(struct drm_device *dev)
7612 {
7613         struct drm_i915_private *dev_priv = dev->dev_private;
7614         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7615
7616         /* Required for FBC */
7617         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7618                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7619                 DPFDUNIT_CLOCK_GATE_DISABLE;
7620         /* Required for CxSR */
7621         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7622
7623         I915_WRITE(PCH_3DCGDIS0,
7624                    MARIUNIT_CLOCK_GATE_DISABLE |
7625                    SVSMUNIT_CLOCK_GATE_DISABLE);
7626         I915_WRITE(PCH_3DCGDIS1,
7627                    VFMUNIT_CLOCK_GATE_DISABLE);
7628
7629         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7630
7631         /*
7632          * According to the spec the following bits should be set in
7633          * order to enable memory self-refresh
7634          * The bit 22/21 of 0x42004
7635          * The bit 5 of 0x42020
7636          * The bit 15 of 0x45000
7637          */
7638         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7639                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7640                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7641         I915_WRITE(ILK_DSPCLK_GATE,
7642                    (I915_READ(ILK_DSPCLK_GATE) |
7643                     ILK_DPARB_CLK_GATE));
7644         I915_WRITE(DISP_ARB_CTL,
7645                    (I915_READ(DISP_ARB_CTL) |
7646                     DISP_FBC_WM_DIS));
7647         I915_WRITE(WM3_LP_ILK, 0);
7648         I915_WRITE(WM2_LP_ILK, 0);
7649         I915_WRITE(WM1_LP_ILK, 0);
7650
7651         /*
7652          * Based on the document from hardware guys the following bits
7653          * should be set unconditionally in order to enable FBC.
7654          * The bit 22 of 0x42000
7655          * The bit 22 of 0x42004
7656          * The bit 7,8,9 of 0x42020.
7657          */
7658         if (IS_IRONLAKE_M(dev)) {
7659                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7660                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7661                            ILK_FBCQ_DIS);
7662                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7663                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7664                            ILK_DPARB_GATE);
7665                 I915_WRITE(ILK_DSPCLK_GATE,
7666                            I915_READ(ILK_DSPCLK_GATE) |
7667                            ILK_DPFC_DIS1 |
7668                            ILK_DPFC_DIS2 |
7669                            ILK_CLK_FBC);
7670         }
7671
7672         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7673                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7674                    ILK_ELPIN_409_SELECT);
7675         I915_WRITE(_3D_CHICKEN2,
7676                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7677                    _3D_CHICKEN2_WM_READ_PIPELINED);
7678 }
7679
7680 static void gen6_init_clock_gating(struct drm_device *dev)
7681 {
7682         struct drm_i915_private *dev_priv = dev->dev_private;
7683         int pipe;
7684         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7685
7686         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7687
7688         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7689                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7690                    ILK_ELPIN_409_SELECT);
7691
7692         I915_WRITE(WM3_LP_ILK, 0);
7693         I915_WRITE(WM2_LP_ILK, 0);
7694         I915_WRITE(WM1_LP_ILK, 0);
7695
7696         /*
7697          * According to the spec the following bits should be
7698          * set in order to enable memory self-refresh and fbc:
7699          * The bit21 and bit22 of 0x42000
7700          * The bit21 and bit22 of 0x42004
7701          * The bit5 and bit7 of 0x42020
7702          * The bit14 of 0x70180
7703          * The bit14 of 0x71180
7704          */
7705         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7706                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7707                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7708         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7709                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7710                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7711         I915_WRITE(ILK_DSPCLK_GATE,
7712                    I915_READ(ILK_DSPCLK_GATE) |
7713                    ILK_DPARB_CLK_GATE  |
7714                    ILK_DPFD_CLK_GATE);
7715
7716         for_each_pipe(pipe)
7717                 I915_WRITE(DSPCNTR(pipe),
7718                            I915_READ(DSPCNTR(pipe)) |
7719                            DISPPLANE_TRICKLE_FEED_DISABLE);
7720 }
7721
7722 static void ivybridge_init_clock_gating(struct drm_device *dev)
7723 {
7724         struct drm_i915_private *dev_priv = dev->dev_private;
7725         int pipe;
7726         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7727
7728         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7729
7730         I915_WRITE(WM3_LP_ILK, 0);
7731         I915_WRITE(WM2_LP_ILK, 0);
7732         I915_WRITE(WM1_LP_ILK, 0);
7733
7734         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7735
7736         for_each_pipe(pipe)
7737                 I915_WRITE(DSPCNTR(pipe),
7738                            I915_READ(DSPCNTR(pipe)) |
7739                            DISPPLANE_TRICKLE_FEED_DISABLE);
7740 }
7741
7742 static void g4x_init_clock_gating(struct drm_device *dev)
7743 {
7744         struct drm_i915_private *dev_priv = dev->dev_private;
7745         uint32_t dspclk_gate;
7746
7747         I915_WRITE(RENCLK_GATE_D1, 0);
7748         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7749                    GS_UNIT_CLOCK_GATE_DISABLE |
7750                    CL_UNIT_CLOCK_GATE_DISABLE);
7751         I915_WRITE(RAMCLK_GATE_D, 0);
7752         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7753                 OVRUNIT_CLOCK_GATE_DISABLE |
7754                 OVCUNIT_CLOCK_GATE_DISABLE;
7755         if (IS_GM45(dev))
7756                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7757         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7758 }
7759
7760 static void crestline_init_clock_gating(struct drm_device *dev)
7761 {
7762         struct drm_i915_private *dev_priv = dev->dev_private;
7763
7764         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7765         I915_WRITE(RENCLK_GATE_D2, 0);
7766         I915_WRITE(DSPCLK_GATE_D, 0);
7767         I915_WRITE(RAMCLK_GATE_D, 0);
7768         I915_WRITE16(DEUC, 0);
7769 }
7770
7771 static void broadwater_init_clock_gating(struct drm_device *dev)
7772 {
7773         struct drm_i915_private *dev_priv = dev->dev_private;
7774
7775         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7776                    I965_RCC_CLOCK_GATE_DISABLE |
7777                    I965_RCPB_CLOCK_GATE_DISABLE |
7778                    I965_ISC_CLOCK_GATE_DISABLE |
7779                    I965_FBC_CLOCK_GATE_DISABLE);
7780         I915_WRITE(RENCLK_GATE_D2, 0);
7781 }
7782
7783 static void gen3_init_clock_gating(struct drm_device *dev)
7784 {
7785         struct drm_i915_private *dev_priv = dev->dev_private;
7786         u32 dstate = I915_READ(D_STATE);
7787
7788         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7789                 DSTATE_DOT_CLOCK_GATING;
7790         I915_WRITE(D_STATE, dstate);
7791 }
7792
7793 static void i85x_init_clock_gating(struct drm_device *dev)
7794 {
7795         struct drm_i915_private *dev_priv = dev->dev_private;
7796
7797         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7798 }
7799
7800 static void i830_init_clock_gating(struct drm_device *dev)
7801 {
7802         struct drm_i915_private *dev_priv = dev->dev_private;
7803
7804         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7805 }
7806
7807 static void ibx_init_clock_gating(struct drm_device *dev)
7808 {
7809         struct drm_i915_private *dev_priv = dev->dev_private;
7810
7811         /*
7812          * On Ibex Peak and Cougar Point, we need to disable clock
7813          * gating for the panel power sequencer or it will fail to
7814          * start up when no ports are active.
7815          */
7816         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7817 }
7818
7819 static void cpt_init_clock_gating(struct drm_device *dev)
7820 {
7821         struct drm_i915_private *dev_priv = dev->dev_private;
7822
7823         /*
7824          * On Ibex Peak and Cougar Point, we need to disable clock
7825          * gating for the panel power sequencer or it will fail to
7826          * start up when no ports are active.
7827          */
7828         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7829         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7830                    DPLS_EDP_PPS_FIX_DIS);
7831 }
7832
7833 static void ironlake_teardown_rc6(struct drm_device *dev)
7834 {
7835         struct drm_i915_private *dev_priv = dev->dev_private;
7836
7837         if (dev_priv->renderctx) {
7838                 i915_gem_object_unpin(dev_priv->renderctx);
7839                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7840                 dev_priv->renderctx = NULL;
7841         }
7842
7843         if (dev_priv->pwrctx) {
7844                 i915_gem_object_unpin(dev_priv->pwrctx);
7845                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7846                 dev_priv->pwrctx = NULL;
7847         }
7848 }
7849
7850 static void ironlake_disable_rc6(struct drm_device *dev)
7851 {
7852         struct drm_i915_private *dev_priv = dev->dev_private;
7853
7854         if (I915_READ(PWRCTXA)) {
7855                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7856                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7857                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7858                          50);
7859
7860                 I915_WRITE(PWRCTXA, 0);
7861                 POSTING_READ(PWRCTXA);
7862
7863                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7864                 POSTING_READ(RSTDBYCTL);
7865         }
7866
7867         ironlake_teardown_rc6(dev);
7868 }
7869
7870 static int ironlake_setup_rc6(struct drm_device *dev)
7871 {
7872         struct drm_i915_private *dev_priv = dev->dev_private;
7873
7874         if (dev_priv->renderctx == NULL)
7875                 dev_priv->renderctx = intel_alloc_context_page(dev);
7876         if (!dev_priv->renderctx)
7877                 return -ENOMEM;
7878
7879         if (dev_priv->pwrctx == NULL)
7880                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7881         if (!dev_priv->pwrctx) {
7882                 ironlake_teardown_rc6(dev);
7883                 return -ENOMEM;
7884         }
7885
7886         return 0;
7887 }
7888
7889 void ironlake_enable_rc6(struct drm_device *dev)
7890 {
7891         struct drm_i915_private *dev_priv = dev->dev_private;
7892         int ret;
7893
7894         /* rc6 disabled by default due to repeated reports of hanging during
7895          * boot and resume.
7896          */
7897         if (!i915_enable_rc6)
7898                 return;
7899
7900         mutex_lock(&dev->struct_mutex);
7901         ret = ironlake_setup_rc6(dev);
7902         if (ret) {
7903                 mutex_unlock(&dev->struct_mutex);
7904                 return;
7905         }
7906
7907         /*
7908          * GPU can automatically power down the render unit if given a page
7909          * to save state.
7910          */
7911         ret = BEGIN_LP_RING(6);
7912         if (ret) {
7913                 ironlake_teardown_rc6(dev);
7914                 mutex_unlock(&dev->struct_mutex);
7915                 return;
7916         }
7917
7918         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7919         OUT_RING(MI_SET_CONTEXT);
7920         OUT_RING(dev_priv->renderctx->gtt_offset |
7921                  MI_MM_SPACE_GTT |
7922                  MI_SAVE_EXT_STATE_EN |
7923                  MI_RESTORE_EXT_STATE_EN |
7924                  MI_RESTORE_INHIBIT);
7925         OUT_RING(MI_SUSPEND_FLUSH);
7926         OUT_RING(MI_NOOP);
7927         OUT_RING(MI_FLUSH);
7928         ADVANCE_LP_RING();
7929
7930         /*
7931          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7932          * does an implicit flush, combined with MI_FLUSH above, it should be
7933          * safe to assume that renderctx is valid
7934          */
7935         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7936         if (ret) {
7937                 DRM_ERROR("failed to enable ironlake power power savings\n");
7938                 ironlake_teardown_rc6(dev);
7939                 mutex_unlock(&dev->struct_mutex);
7940                 return;
7941         }
7942
7943         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7944         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7945         mutex_unlock(&dev->struct_mutex);
7946 }
7947
7948 void intel_init_clock_gating(struct drm_device *dev)
7949 {
7950         struct drm_i915_private *dev_priv = dev->dev_private;
7951
7952         dev_priv->display.init_clock_gating(dev);
7953
7954         if (dev_priv->display.init_pch_clock_gating)
7955                 dev_priv->display.init_pch_clock_gating(dev);
7956 }
7957
7958 /* Set up chip specific display functions */
7959 static void intel_init_display(struct drm_device *dev)
7960 {
7961         struct drm_i915_private *dev_priv = dev->dev_private;
7962
7963         /* We always want a DPMS function */
7964         if (HAS_PCH_SPLIT(dev)) {
7965                 dev_priv->display.dpms = ironlake_crtc_dpms;
7966                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7967                 dev_priv->display.update_plane = ironlake_update_plane;
7968         } else {
7969                 dev_priv->display.dpms = i9xx_crtc_dpms;
7970                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7971                 dev_priv->display.update_plane = i9xx_update_plane;
7972         }
7973
7974         if (I915_HAS_FBC(dev)) {
7975                 if (HAS_PCH_SPLIT(dev)) {
7976                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7977                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7978                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7979                 } else if (IS_GM45(dev)) {
7980                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7981                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7982                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7983                 } else if (IS_CRESTLINE(dev)) {
7984                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7985                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7986                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7987                 }
7988                 /* 855GM needs testing */
7989         }
7990
7991         /* Returns the core display clock speed */
7992         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7993                 dev_priv->display.get_display_clock_speed =
7994                         i945_get_display_clock_speed;
7995         else if (IS_I915G(dev))
7996                 dev_priv->display.get_display_clock_speed =
7997                         i915_get_display_clock_speed;
7998         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7999                 dev_priv->display.get_display_clock_speed =
8000                         i9xx_misc_get_display_clock_speed;
8001         else if (IS_I915GM(dev))
8002                 dev_priv->display.get_display_clock_speed =
8003                         i915gm_get_display_clock_speed;
8004         else if (IS_I865G(dev))
8005                 dev_priv->display.get_display_clock_speed =
8006                         i865_get_display_clock_speed;
8007         else if (IS_I85X(dev))
8008                 dev_priv->display.get_display_clock_speed =
8009                         i855_get_display_clock_speed;
8010         else /* 852, 830 */
8011                 dev_priv->display.get_display_clock_speed =
8012                         i830_get_display_clock_speed;
8013
8014         /* For FIFO watermark updates */
8015         if (HAS_PCH_SPLIT(dev)) {
8016                 if (HAS_PCH_IBX(dev))
8017                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8018                 else if (HAS_PCH_CPT(dev))
8019                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8020
8021                 if (IS_GEN5(dev)) {
8022                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8023                                 dev_priv->display.update_wm = ironlake_update_wm;
8024                         else {
8025                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8026                                               "Disable CxSR\n");
8027                                 dev_priv->display.update_wm = NULL;
8028                         }
8029                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8030                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8031                 } else if (IS_GEN6(dev)) {
8032                         if (SNB_READ_WM0_LATENCY()) {
8033                                 dev_priv->display.update_wm = sandybridge_update_wm;
8034                         } else {
8035                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8036                                               "Disable CxSR\n");
8037                                 dev_priv->display.update_wm = NULL;
8038                         }
8039                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8040                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8041                 } else if (IS_IVYBRIDGE(dev)) {
8042                         /* FIXME: detect B0+ stepping and use auto training */
8043                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8044                         if (SNB_READ_WM0_LATENCY()) {
8045                                 dev_priv->display.update_wm = sandybridge_update_wm;
8046                         } else {
8047                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8048                                               "Disable CxSR\n");
8049                                 dev_priv->display.update_wm = NULL;
8050                         }
8051                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8052
8053                 } else
8054                         dev_priv->display.update_wm = NULL;
8055         } else if (IS_PINEVIEW(dev)) {
8056                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8057                                             dev_priv->is_ddr3,
8058                                             dev_priv->fsb_freq,
8059                                             dev_priv->mem_freq)) {
8060                         DRM_INFO("failed to find known CxSR latency "
8061                                  "(found ddr%s fsb freq %d, mem freq %d), "
8062                                  "disabling CxSR\n",
8063                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
8064                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8065                         /* Disable CxSR and never update its watermark again */
8066                         pineview_disable_cxsr(dev);
8067                         dev_priv->display.update_wm = NULL;
8068                 } else
8069                         dev_priv->display.update_wm = pineview_update_wm;
8070                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8071         } else if (IS_G4X(dev)) {
8072                 dev_priv->display.update_wm = g4x_update_wm;
8073                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8074         } else if (IS_GEN4(dev)) {
8075                 dev_priv->display.update_wm = i965_update_wm;
8076                 if (IS_CRESTLINE(dev))
8077                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8078                 else if (IS_BROADWATER(dev))
8079                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8080         } else if (IS_GEN3(dev)) {
8081                 dev_priv->display.update_wm = i9xx_update_wm;
8082                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8083                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8084         } else if (IS_I865G(dev)) {
8085                 dev_priv->display.update_wm = i830_update_wm;
8086                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8087                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8088         } else if (IS_I85X(dev)) {
8089                 dev_priv->display.update_wm = i9xx_update_wm;
8090                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8091                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8092         } else {
8093                 dev_priv->display.update_wm = i830_update_wm;
8094                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8095                 if (IS_845G(dev))
8096                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8097                 else
8098                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8099         }
8100
8101         /* Default just returns -ENODEV to indicate unsupported */
8102         dev_priv->display.queue_flip = intel_default_queue_flip;
8103
8104         switch (INTEL_INFO(dev)->gen) {
8105         case 2:
8106                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8107                 break;
8108
8109         case 3:
8110                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8111                 break;
8112
8113         case 4:
8114         case 5:
8115                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8116                 break;
8117
8118         case 6:
8119                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8120                 break;
8121         case 7:
8122                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8123                 break;
8124         }
8125 }
8126
8127 /*
8128  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8129  * resume, or other times.  This quirk makes sure that's the case for
8130  * affected systems.
8131  */
8132 static void quirk_pipea_force (struct drm_device *dev)
8133 {
8134         struct drm_i915_private *dev_priv = dev->dev_private;
8135
8136         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8137         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8138 }
8139
8140 struct intel_quirk {
8141         int device;
8142         int subsystem_vendor;
8143         int subsystem_device;
8144         void (*hook)(struct drm_device *dev);
8145 };
8146
8147 struct intel_quirk intel_quirks[] = {
8148         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8149         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8150         /* HP Mini needs pipe A force quirk (LP: #322104) */
8151         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8152
8153         /* Thinkpad R31 needs pipe A force quirk */
8154         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8155         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8156         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8157
8158         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8159         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8160         /* ThinkPad X40 needs pipe A force quirk */
8161
8162         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8163         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8164
8165         /* 855 & before need to leave pipe A & dpll A up */
8166         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8167         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8168 };
8169
8170 static void intel_init_quirks(struct drm_device *dev)
8171 {
8172         struct pci_dev *d = dev->pdev;
8173         int i;
8174
8175         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8176                 struct intel_quirk *q = &intel_quirks[i];
8177
8178                 if (d->device == q->device &&
8179                     (d->subsystem_vendor == q->subsystem_vendor ||
8180                      q->subsystem_vendor == PCI_ANY_ID) &&
8181                     (d->subsystem_device == q->subsystem_device ||
8182                      q->subsystem_device == PCI_ANY_ID))
8183                         q->hook(dev);
8184         }
8185 }
8186
8187 /* Disable the VGA plane that we never use */
8188 static void i915_disable_vga(struct drm_device *dev)
8189 {
8190         struct drm_i915_private *dev_priv = dev->dev_private;
8191         u8 sr1;
8192         u32 vga_reg;
8193
8194         if (HAS_PCH_SPLIT(dev))
8195                 vga_reg = CPU_VGACNTRL;
8196         else
8197                 vga_reg = VGACNTRL;
8198
8199         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8200         outb(1, VGA_SR_INDEX);
8201         sr1 = inb(VGA_SR_DATA);
8202         outb(sr1 | 1<<5, VGA_SR_DATA);
8203         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8204         udelay(300);
8205
8206         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8207         POSTING_READ(vga_reg);
8208 }
8209
8210 void intel_modeset_init(struct drm_device *dev)
8211 {
8212         struct drm_i915_private *dev_priv = dev->dev_private;
8213         int i;
8214
8215         drm_mode_config_init(dev);
8216
8217         dev->mode_config.min_width = 0;
8218         dev->mode_config.min_height = 0;
8219
8220         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8221
8222         intel_init_quirks(dev);
8223
8224         intel_init_display(dev);
8225
8226         if (IS_GEN2(dev)) {
8227                 dev->mode_config.max_width = 2048;
8228                 dev->mode_config.max_height = 2048;
8229         } else if (IS_GEN3(dev)) {
8230                 dev->mode_config.max_width = 4096;
8231                 dev->mode_config.max_height = 4096;
8232         } else {
8233                 dev->mode_config.max_width = 8192;
8234                 dev->mode_config.max_height = 8192;
8235         }
8236         dev->mode_config.fb_base = dev->agp->base;
8237
8238         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8239                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8240
8241         for (i = 0; i < dev_priv->num_pipe; i++) {
8242                 intel_crtc_init(dev, i);
8243         }
8244
8245         /* Just disable it once at startup */
8246         i915_disable_vga(dev);
8247         intel_setup_outputs(dev);
8248
8249         intel_init_clock_gating(dev);
8250
8251         if (IS_IRONLAKE_M(dev)) {
8252                 ironlake_enable_drps(dev);
8253                 intel_init_emon(dev);
8254         }
8255
8256         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8257                 gen6_enable_rps(dev_priv);
8258                 gen6_update_ring_freq(dev_priv);
8259         }
8260
8261         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8262         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8263                     (unsigned long)dev);
8264 }
8265
8266 void intel_modeset_gem_init(struct drm_device *dev)
8267 {
8268         if (IS_IRONLAKE_M(dev))
8269                 ironlake_enable_rc6(dev);
8270
8271         intel_setup_overlay(dev);
8272 }
8273
8274 void intel_modeset_cleanup(struct drm_device *dev)
8275 {
8276         struct drm_i915_private *dev_priv = dev->dev_private;
8277         struct drm_crtc *crtc;
8278         struct intel_crtc *intel_crtc;
8279
8280         drm_kms_helper_poll_fini(dev);
8281         mutex_lock(&dev->struct_mutex);
8282
8283         intel_unregister_dsm_handler();
8284
8285
8286         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8287                 /* Skip inactive CRTCs */
8288                 if (!crtc->fb)
8289                         continue;
8290
8291                 intel_crtc = to_intel_crtc(crtc);
8292                 intel_increase_pllclock(crtc);
8293         }
8294
8295         intel_disable_fbc(dev);
8296
8297         if (IS_IRONLAKE_M(dev))
8298                 ironlake_disable_drps(dev);
8299         if (IS_GEN6(dev) || IS_GEN7(dev))
8300                 gen6_disable_rps(dev);
8301
8302         if (IS_IRONLAKE_M(dev))
8303                 ironlake_disable_rc6(dev);
8304
8305         mutex_unlock(&dev->struct_mutex);
8306
8307         /* Disable the irq before mode object teardown, for the irq might
8308          * enqueue unpin/hotplug work. */
8309         drm_irq_uninstall(dev);
8310         cancel_work_sync(&dev_priv->hotplug_work);
8311
8312         /* flush any delayed tasks or pending work */
8313         flush_scheduled_work();
8314
8315         /* Shut off idle work before the crtcs get freed. */
8316         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8317                 intel_crtc = to_intel_crtc(crtc);
8318                 del_timer_sync(&intel_crtc->idle_timer);
8319         }
8320         del_timer_sync(&dev_priv->idle_timer);
8321         cancel_work_sync(&dev_priv->idle_work);
8322
8323         drm_mode_config_cleanup(dev);
8324 }
8325
8326 /*
8327  * Return which encoder is currently attached for connector.
8328  */
8329 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8330 {
8331         return &intel_attached_encoder(connector)->base;
8332 }
8333
8334 void intel_connector_attach_encoder(struct intel_connector *connector,
8335                                     struct intel_encoder *encoder)
8336 {
8337         connector->encoder = encoder;
8338         drm_mode_connector_attach_encoder(&connector->base,
8339                                           &encoder->base);
8340 }
8341
8342 /*
8343  * set vga decode state - true == enable VGA decode
8344  */
8345 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8346 {
8347         struct drm_i915_private *dev_priv = dev->dev_private;
8348         u16 gmch_ctrl;
8349
8350         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8351         if (state)
8352                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8353         else
8354                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8355         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8356         return 0;
8357 }
8358
8359 #ifdef CONFIG_DEBUG_FS
8360 #include <linux/seq_file.h>
8361
8362 struct intel_display_error_state {
8363         struct intel_cursor_error_state {
8364                 u32 control;
8365                 u32 position;
8366                 u32 base;
8367                 u32 size;
8368         } cursor[2];
8369
8370         struct intel_pipe_error_state {
8371                 u32 conf;
8372                 u32 source;
8373
8374                 u32 htotal;
8375                 u32 hblank;
8376                 u32 hsync;
8377                 u32 vtotal;
8378                 u32 vblank;
8379                 u32 vsync;
8380         } pipe[2];
8381
8382         struct intel_plane_error_state {
8383                 u32 control;
8384                 u32 stride;
8385                 u32 size;
8386                 u32 pos;
8387                 u32 addr;
8388                 u32 surface;
8389                 u32 tile_offset;
8390         } plane[2];
8391 };
8392
8393 struct intel_display_error_state *
8394 intel_display_capture_error_state(struct drm_device *dev)
8395 {
8396         drm_i915_private_t *dev_priv = dev->dev_private;
8397         struct intel_display_error_state *error;
8398         int i;
8399
8400         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8401         if (error == NULL)
8402                 return NULL;
8403
8404         for (i = 0; i < 2; i++) {
8405                 error->cursor[i].control = I915_READ(CURCNTR(i));
8406                 error->cursor[i].position = I915_READ(CURPOS(i));
8407                 error->cursor[i].base = I915_READ(CURBASE(i));
8408
8409                 error->plane[i].control = I915_READ(DSPCNTR(i));
8410                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8411                 error->plane[i].size = I915_READ(DSPSIZE(i));
8412                 error->plane[i].pos= I915_READ(DSPPOS(i));
8413                 error->plane[i].addr = I915_READ(DSPADDR(i));
8414                 if (INTEL_INFO(dev)->gen >= 4) {
8415                         error->plane[i].surface = I915_READ(DSPSURF(i));
8416                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8417                 }
8418
8419                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8420                 error->pipe[i].source = I915_READ(PIPESRC(i));
8421                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8422                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8423                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8424                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8425                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8426                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8427         }
8428
8429         return error;
8430 }
8431
8432 void
8433 intel_display_print_error_state(struct seq_file *m,
8434                                 struct drm_device *dev,
8435                                 struct intel_display_error_state *error)
8436 {
8437         int i;
8438
8439         for (i = 0; i < 2; i++) {
8440                 seq_printf(m, "Pipe [%d]:\n", i);
8441                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8442                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8443                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8444                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8445                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8446                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8447                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8448                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8449
8450                 seq_printf(m, "Plane [%d]:\n", i);
8451                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8452                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8453                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8454                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8455                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8456                 if (INTEL_INFO(dev)->gen >= 4) {
8457                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8458                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8459                 }
8460
8461                 seq_printf(m, "Cursor [%d]:\n", i);
8462                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8463                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8464                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8465         }
8466 }
8467 #endif