2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
59 return intel_dig_port->base.base.dev;
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
74 switch (max_link_bw) {
79 max_link_bw = DP_LINK_BW_1_62;
86 * The units on the numbers in the next two are... bizarre. Examples will
87 * make it clearer; this one parallels an example in the eDP spec.
89 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
91 * 270000 * 1 * 8 / 10 == 216000
93 * The actual data capacity of that configuration is 2.16Gbit/s, so the
94 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
95 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
96 * 119000. At 18bpp that's 2142000 kilobits per second.
98 * Thus the strange-looking division by 10 in intel_dp_link_required, to
99 * get the result in decakilobits instead of kilobits.
103 intel_dp_link_required(int pixel_clock, int bpp)
105 return (pixel_clock * bpp + 9) / 10;
109 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
111 return (max_link_clock * max_lanes * 8) / 10;
115 intel_dp_mode_valid(struct drm_connector *connector,
116 struct drm_display_mode *mode)
118 struct intel_dp *intel_dp = intel_attached_dp(connector);
119 struct intel_connector *intel_connector = to_intel_connector(connector);
120 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
121 int target_clock = mode->clock;
122 int max_rate, mode_rate, max_lanes, max_link_clock;
124 if (is_edp(intel_dp) && fixed_mode) {
125 if (mode->hdisplay > fixed_mode->hdisplay)
128 if (mode->vdisplay > fixed_mode->vdisplay)
131 target_clock = fixed_mode->clock;
134 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
135 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
137 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
138 mode_rate = intel_dp_link_required(target_clock, 18);
140 if (mode_rate > max_rate)
141 return MODE_CLOCK_HIGH;
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
146 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
147 return MODE_H_ILLEGAL;
153 pack_aux(uint8_t *src, int src_bytes)
160 for (i = 0; i < src_bytes; i++)
161 v |= ((uint32_t) src[i]) << ((3-i) * 8);
166 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
171 for (i = 0; i < dst_bytes; i++)
172 dst[i] = src >> ((3-i) * 8);
175 /* hrawclock is 1/4 the FSB frequency */
177 intel_hrawclk(struct drm_device *dev)
179 struct drm_i915_private *dev_priv = dev->dev_private;
182 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
183 if (IS_VALLEYVIEW(dev))
186 clkcfg = I915_READ(CLKCFG);
187 switch (clkcfg & CLKCFG_FSB_MASK) {
196 case CLKCFG_FSB_1067:
198 case CLKCFG_FSB_1333:
200 /* these two are just a guess; one of them might be right */
201 case CLKCFG_FSB_1600:
202 case CLKCFG_FSB_1600_ALT:
209 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
212 struct drm_i915_private *dev_priv = dev->dev_private;
215 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
216 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
219 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
222 struct drm_i915_private *dev_priv = dev->dev_private;
225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
226 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
230 intel_dp_check_edp(struct intel_dp *intel_dp)
232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
233 struct drm_i915_private *dev_priv = dev->dev_private;
234 u32 pp_stat_reg, pp_ctrl_reg;
236 if (!is_edp(intel_dp))
239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
242 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
243 WARN(1, "eDP powered off while attempting aux channel communication.\n");
244 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
245 I915_READ(pp_stat_reg),
246 I915_READ(pp_ctrl_reg));
251 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
260 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
262 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
263 msecs_to_jiffies_timeout(10));
265 done = wait_for_atomic(C, 10) == 0;
267 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
275 intel_dp_aux_ch(struct intel_dp *intel_dp,
276 uint8_t *send, int send_bytes,
277 uint8_t *recv, int recv_size)
279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
280 struct drm_device *dev = intel_dig_port->base.base.dev;
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
283 uint32_t ch_data = ch_ctl + 4;
284 int i, ret, recv_bytes;
286 uint32_t aux_clock_divider;
288 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
290 /* dp aux is extremely sensitive to irq latency, hence request the
291 * lowest possible wakeup latency and so prevent the cpu from going into
294 pm_qos_update_request(&dev_priv->pm_qos, 0);
296 intel_dp_check_edp(intel_dp);
297 /* The clock divider is based off the hrawclk,
298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
301 * Note that PCH attached eDP panels should use a 125MHz input
304 if (IS_VALLEYVIEW(dev)) {
305 aux_clock_divider = 100;
306 } else if (intel_dig_port->port == PORT_A) {
308 aux_clock_divider = DIV_ROUND_CLOSEST(
309 intel_ddi_get_cdclk_freq(dev_priv), 2000);
310 else if (IS_GEN6(dev) || IS_GEN7(dev))
311 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
313 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
314 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
315 /* Workaround for non-ULT HSW */
316 aux_clock_divider = 74;
317 } else if (HAS_PCH_SPLIT(dev)) {
318 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
320 aux_clock_divider = intel_hrawclk(dev) / 2;
328 /* Try to wait for any previous AUX channel activity */
329 for (try = 0; try < 3; try++) {
330 status = I915_READ_NOTRACE(ch_ctl);
331 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
337 WARN(1, "dp_aux_ch not started status 0x%08x\n",
343 /* Must try at least 3 times according to DP spec */
344 for (try = 0; try < 5; try++) {
345 /* Load the send data into the aux channel data registers */
346 for (i = 0; i < send_bytes; i += 4)
347 I915_WRITE(ch_data + i,
348 pack_aux(send + i, send_bytes - i));
350 /* Send the command and wait for it to complete */
352 DP_AUX_CH_CTL_SEND_BUSY |
353 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
354 DP_AUX_CH_CTL_TIME_OUT_400us |
355 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
356 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
357 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
359 DP_AUX_CH_CTL_TIME_OUT_ERROR |
360 DP_AUX_CH_CTL_RECEIVE_ERROR);
362 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
364 /* Clear done status and any errors */
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
371 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
372 DP_AUX_CH_CTL_RECEIVE_ERROR))
374 if (status & DP_AUX_CH_CTL_DONE)
378 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
379 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
384 /* Check for timeout or receive error.
385 * Timeouts occur when the sink is not connected
387 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
388 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
393 /* Timeouts occur when the device isn't connected, so they're
394 * "normal" -- don't fill the kernel log with these */
395 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
396 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
401 /* Unload any bytes sent back from the other side */
402 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
403 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
404 if (recv_bytes > recv_size)
405 recv_bytes = recv_size;
407 for (i = 0; i < recv_bytes; i += 4)
408 unpack_aux(I915_READ(ch_data + i),
409 recv + i, recv_bytes - i);
413 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
418 /* Write data to the aux channel in native mode */
420 intel_dp_aux_native_write(struct intel_dp *intel_dp,
421 uint16_t address, uint8_t *send, int send_bytes)
428 intel_dp_check_edp(intel_dp);
431 msg[0] = AUX_NATIVE_WRITE << 4;
432 msg[1] = address >> 8;
433 msg[2] = address & 0xff;
434 msg[3] = send_bytes - 1;
435 memcpy(&msg[4], send, send_bytes);
436 msg_bytes = send_bytes + 4;
438 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
441 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
443 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
451 /* Write a single byte to the aux channel in native mode */
453 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
454 uint16_t address, uint8_t byte)
456 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
459 /* read bytes from a native aux channel */
461 intel_dp_aux_native_read(struct intel_dp *intel_dp,
462 uint16_t address, uint8_t *recv, int recv_bytes)
471 intel_dp_check_edp(intel_dp);
472 msg[0] = AUX_NATIVE_READ << 4;
473 msg[1] = address >> 8;
474 msg[2] = address & 0xff;
475 msg[3] = recv_bytes - 1;
478 reply_bytes = recv_bytes + 1;
481 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
488 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
489 memcpy(recv, reply + 1, ret - 1);
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
500 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
501 uint8_t write_byte, uint8_t *read_byte)
503 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
504 struct intel_dp *intel_dp = container_of(adapter,
507 uint16_t address = algo_data->address;
515 intel_dp_check_edp(intel_dp);
516 /* Set up the command byte */
517 if (mode & MODE_I2C_READ)
518 msg[0] = AUX_I2C_READ << 4;
520 msg[0] = AUX_I2C_WRITE << 4;
522 if (!(mode & MODE_I2C_STOP))
523 msg[0] |= AUX_I2C_MOT << 4;
525 msg[1] = address >> 8;
546 for (retry = 0; retry < 5; retry++) {
547 ret = intel_dp_aux_ch(intel_dp,
551 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
555 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
556 case AUX_NATIVE_REPLY_ACK:
557 /* I2C-over-AUX Reply field is only valid
558 * when paired with AUX ACK.
561 case AUX_NATIVE_REPLY_NACK:
562 DRM_DEBUG_KMS("aux_ch native nack\n");
564 case AUX_NATIVE_REPLY_DEFER:
568 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
573 switch (reply[0] & AUX_I2C_REPLY_MASK) {
574 case AUX_I2C_REPLY_ACK:
575 if (mode == MODE_I2C_READ) {
576 *read_byte = reply[1];
578 return reply_bytes - 1;
579 case AUX_I2C_REPLY_NACK:
580 DRM_DEBUG_KMS("aux_i2c nack\n");
582 case AUX_I2C_REPLY_DEFER:
583 DRM_DEBUG_KMS("aux_i2c defer\n");
587 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
592 DRM_ERROR("too many retries, giving up\n");
597 intel_dp_i2c_init(struct intel_dp *intel_dp,
598 struct intel_connector *intel_connector, const char *name)
602 DRM_DEBUG_KMS("i2c_init %s\n", name);
603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
607 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
610 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
615 ironlake_edp_panel_vdd_on(intel_dp);
616 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
617 ironlake_edp_panel_vdd_off(intel_dp, false);
622 intel_dp_set_clock(struct intel_encoder *encoder,
623 struct intel_crtc_config *pipe_config, int link_bw)
625 struct drm_device *dev = encoder->base.dev;
628 if (link_bw == DP_LINK_BW_1_62) {
629 pipe_config->dpll.p1 = 2;
630 pipe_config->dpll.p2 = 10;
631 pipe_config->dpll.n = 2;
632 pipe_config->dpll.m1 = 23;
633 pipe_config->dpll.m2 = 8;
635 pipe_config->dpll.p1 = 1;
636 pipe_config->dpll.p2 = 10;
637 pipe_config->dpll.n = 1;
638 pipe_config->dpll.m1 = 14;
639 pipe_config->dpll.m2 = 2;
641 pipe_config->clock_set = true;
642 } else if (IS_HASWELL(dev)) {
643 /* Haswell has special-purpose DP DDI clocks. */
644 } else if (HAS_PCH_SPLIT(dev)) {
645 if (link_bw == DP_LINK_BW_1_62) {
646 pipe_config->dpll.n = 1;
647 pipe_config->dpll.p1 = 2;
648 pipe_config->dpll.p2 = 10;
649 pipe_config->dpll.m1 = 12;
650 pipe_config->dpll.m2 = 9;
652 pipe_config->dpll.n = 2;
653 pipe_config->dpll.p1 = 1;
654 pipe_config->dpll.p2 = 10;
655 pipe_config->dpll.m1 = 14;
656 pipe_config->dpll.m2 = 8;
658 pipe_config->clock_set = true;
659 } else if (IS_VALLEYVIEW(dev)) {
660 /* FIXME: Need to figure out optimized DP clocks for vlv. */
665 intel_dp_compute_config(struct intel_encoder *encoder,
666 struct intel_crtc_config *pipe_config)
668 struct drm_device *dev = encoder->base.dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
672 enum port port = dp_to_dig_port(intel_dp)->port;
673 struct intel_crtc *intel_crtc = encoder->new_crtc;
674 struct intel_connector *intel_connector = intel_dp->attached_connector;
675 int lane_count, clock;
676 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
680 int link_avail, link_clock;
682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
683 pipe_config->has_pch_encoder = true;
685 pipe_config->has_dp_encoder = true;
687 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
688 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
690 if (!HAS_PCH_SPLIT(dev))
691 intel_gmch_panel_fitting(intel_crtc, pipe_config,
692 intel_connector->panel.fitting_mode);
694 intel_pch_panel_fitting(intel_crtc, pipe_config,
695 intel_connector->panel.fitting_mode);
698 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
701 DRM_DEBUG_KMS("DP link computation with max lane count %i "
702 "max bw %02x pixel clock %iKHz\n",
703 max_lane_count, bws[max_clock], adjusted_mode->clock);
705 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
707 bpp = pipe_config->pipe_bpp;
708 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
709 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
711 for (; bpp >= 6*3; bpp -= 2*3) {
712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
717 link_avail = intel_dp_max_data_rate(link_clock,
720 if (mode_rate <= link_avail) {
730 if (intel_dp->color_range_auto) {
733 * CEA-861-E - 5.1 Default Encoding Parameters
734 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
736 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
737 intel_dp->color_range = DP_COLOR_RANGE_16_235;
739 intel_dp->color_range = 0;
742 if (intel_dp->color_range)
743 pipe_config->limited_color_range = true;
745 intel_dp->link_bw = bws[clock];
746 intel_dp->lane_count = lane_count;
747 pipe_config->pipe_bpp = bpp;
748 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
750 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
751 intel_dp->link_bw, intel_dp->lane_count,
752 pipe_config->port_clock, bpp);
753 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
754 mode_rate, link_avail);
756 intel_link_compute_m_n(bpp, lane_count,
757 adjusted_mode->clock, pipe_config->port_clock,
758 &pipe_config->dp_m_n);
760 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
765 void intel_dp_init_link_config(struct intel_dp *intel_dp)
767 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
768 intel_dp->link_configuration[0] = intel_dp->link_bw;
769 intel_dp->link_configuration[1] = intel_dp->lane_count;
770 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
772 * Check for DPCD version > 1.1 and enhanced framing support
774 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
775 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
776 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
780 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
783 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
784 struct drm_device *dev = crtc->base.dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
788 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
789 dpa_ctl = I915_READ(DP_A);
790 dpa_ctl &= ~DP_PLL_FREQ_MASK;
792 if (crtc->config.port_clock == 162000) {
793 /* For a long time we've carried around a ILK-DevA w/a for the
794 * 160MHz clock. If we're really unlucky, it's still required.
796 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
797 dpa_ctl |= DP_PLL_FREQ_160MHZ;
798 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
800 dpa_ctl |= DP_PLL_FREQ_270MHZ;
801 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
804 I915_WRITE(DP_A, dpa_ctl);
811 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode)
814 struct drm_device *dev = encoder->dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
817 enum port port = dp_to_dig_port(intel_dp)->port;
818 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
821 * There are four kinds of DP registers:
828 * IBX PCH and CPU are the same for almost everything,
829 * except that the CPU DP PLL is configured in this
832 * CPT PCH is quite different, having many bits moved
833 * to the TRANS_DP_CTL register instead. That
834 * configuration happens (oddly) in ironlake_pch_enable
837 /* Preserve the BIOS-computed detected bit. This is
838 * supposed to be read-only.
840 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
842 /* Handle DP bits in common between all three register formats */
843 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
844 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
846 if (intel_dp->has_audio) {
847 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
848 pipe_name(crtc->pipe));
849 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
850 intel_write_eld(encoder, adjusted_mode);
853 intel_dp_init_link_config(intel_dp);
855 /* Split out the IBX/CPU vs CPT settings */
857 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
858 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
859 intel_dp->DP |= DP_SYNC_HS_HIGH;
860 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
861 intel_dp->DP |= DP_SYNC_VS_HIGH;
862 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
864 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
865 intel_dp->DP |= DP_ENHANCED_FRAMING;
867 intel_dp->DP |= crtc->pipe << 29;
868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
869 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
870 intel_dp->DP |= intel_dp->color_range;
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
873 intel_dp->DP |= DP_SYNC_HS_HIGH;
874 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
875 intel_dp->DP |= DP_SYNC_VS_HIGH;
876 intel_dp->DP |= DP_LINK_TRAIN_OFF;
878 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
879 intel_dp->DP |= DP_ENHANCED_FRAMING;
882 intel_dp->DP |= DP_PIPEB_SELECT;
884 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
887 if (port == PORT_A && !IS_VALLEYVIEW(dev))
888 ironlake_set_pll_cpu_edp(intel_dp);
891 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
892 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
894 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
895 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
897 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
898 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
900 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
904 struct drm_device *dev = intel_dp_to_dev(intel_dp);
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 u32 pp_stat_reg, pp_ctrl_reg;
908 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
909 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
911 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
913 I915_READ(pp_stat_reg),
914 I915_READ(pp_ctrl_reg));
916 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
917 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
918 I915_READ(pp_stat_reg),
919 I915_READ(pp_ctrl_reg));
923 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
925 DRM_DEBUG_KMS("Wait for panel power on\n");
926 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
929 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
931 DRM_DEBUG_KMS("Wait for panel power off time\n");
932 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
935 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
937 DRM_DEBUG_KMS("Wait for panel power cycle\n");
938 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
942 /* Read the current pp_control value, unlocking the register if it
946 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
948 struct drm_device *dev = intel_dp_to_dev(intel_dp);
949 struct drm_i915_private *dev_priv = dev->dev_private;
953 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
954 control = I915_READ(pp_ctrl_reg);
956 control &= ~PANEL_UNLOCK_MASK;
957 control |= PANEL_UNLOCK_REGS;
961 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
964 struct drm_i915_private *dev_priv = dev->dev_private;
966 u32 pp_stat_reg, pp_ctrl_reg;
968 if (!is_edp(intel_dp))
970 DRM_DEBUG_KMS("Turn eDP VDD on\n");
972 WARN(intel_dp->want_panel_vdd,
973 "eDP VDD already requested on\n");
975 intel_dp->want_panel_vdd = true;
977 if (ironlake_edp_have_panel_vdd(intel_dp)) {
978 DRM_DEBUG_KMS("eDP VDD already on\n");
982 if (!ironlake_edp_have_panel_power(intel_dp))
983 ironlake_wait_panel_power_cycle(intel_dp);
985 pp = ironlake_get_pp_control(intel_dp);
988 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
989 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
991 I915_WRITE(pp_ctrl_reg, pp);
992 POSTING_READ(pp_ctrl_reg);
993 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
994 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
996 * If the panel wasn't on, delay before accessing aux channel
998 if (!ironlake_edp_have_panel_power(intel_dp)) {
999 DRM_DEBUG_KMS("eDP was not running\n");
1000 msleep(intel_dp->panel_power_up_delay);
1004 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1009 u32 pp_stat_reg, pp_ctrl_reg;
1011 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1013 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1014 pp = ironlake_get_pp_control(intel_dp);
1015 pp &= ~EDP_FORCE_VDD;
1017 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1018 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1020 I915_WRITE(pp_ctrl_reg, pp);
1021 POSTING_READ(pp_ctrl_reg);
1023 /* Make sure sequencer is idle before allowing subsequent activity */
1024 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1025 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1026 msleep(intel_dp->panel_power_down_delay);
1030 static void ironlake_panel_vdd_work(struct work_struct *__work)
1032 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1033 struct intel_dp, panel_vdd_work);
1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1036 mutex_lock(&dev->mode_config.mutex);
1037 ironlake_panel_vdd_off_sync(intel_dp);
1038 mutex_unlock(&dev->mode_config.mutex);
1041 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1043 if (!is_edp(intel_dp))
1046 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1047 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1049 intel_dp->want_panel_vdd = false;
1052 ironlake_panel_vdd_off_sync(intel_dp);
1055 * Queue the timer to fire a long
1056 * time from now (relative to the power down delay)
1057 * to keep the panel power up across a sequence of operations
1059 schedule_delayed_work(&intel_dp->panel_vdd_work,
1060 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1064 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1071 if (!is_edp(intel_dp))
1074 DRM_DEBUG_KMS("Turn eDP power on\n");
1076 if (ironlake_edp_have_panel_power(intel_dp)) {
1077 DRM_DEBUG_KMS("eDP power already on\n");
1081 ironlake_wait_panel_power_cycle(intel_dp);
1083 pp = ironlake_get_pp_control(intel_dp);
1085 /* ILK workaround: disable reset around power sequence */
1086 pp &= ~PANEL_POWER_RESET;
1087 I915_WRITE(PCH_PP_CONTROL, pp);
1088 POSTING_READ(PCH_PP_CONTROL);
1091 pp |= POWER_TARGET_ON;
1093 pp |= PANEL_POWER_RESET;
1095 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1097 I915_WRITE(pp_ctrl_reg, pp);
1098 POSTING_READ(pp_ctrl_reg);
1100 ironlake_wait_panel_on(intel_dp);
1103 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1104 I915_WRITE(PCH_PP_CONTROL, pp);
1105 POSTING_READ(PCH_PP_CONTROL);
1109 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1111 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1116 if (!is_edp(intel_dp))
1119 DRM_DEBUG_KMS("Turn eDP power off\n");
1121 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1123 pp = ironlake_get_pp_control(intel_dp);
1124 /* We need to switch off panel power _and_ force vdd, for otherwise some
1125 * panels get very unhappy and cease to work. */
1126 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1128 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1130 I915_WRITE(pp_ctrl_reg, pp);
1131 POSTING_READ(pp_ctrl_reg);
1133 intel_dp->want_panel_vdd = false;
1135 ironlake_wait_panel_off(intel_dp);
1138 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1140 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1141 struct drm_device *dev = intel_dig_port->base.base.dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1147 if (!is_edp(intel_dp))
1150 DRM_DEBUG_KMS("\n");
1152 * If we enable the backlight right away following a panel power
1153 * on, we may see slight flicker as the panel syncs with the eDP
1154 * link. So delay a bit to make sure the image is solid before
1155 * allowing it to appear.
1157 msleep(intel_dp->backlight_on_delay);
1158 pp = ironlake_get_pp_control(intel_dp);
1159 pp |= EDP_BLC_ENABLE;
1161 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1163 I915_WRITE(pp_ctrl_reg, pp);
1164 POSTING_READ(pp_ctrl_reg);
1166 intel_panel_enable_backlight(dev, pipe);
1169 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1171 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1176 if (!is_edp(intel_dp))
1179 intel_panel_disable_backlight(dev);
1181 DRM_DEBUG_KMS("\n");
1182 pp = ironlake_get_pp_control(intel_dp);
1183 pp &= ~EDP_BLC_ENABLE;
1185 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1187 I915_WRITE(pp_ctrl_reg, pp);
1188 POSTING_READ(pp_ctrl_reg);
1189 msleep(intel_dp->backlight_off_delay);
1192 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1194 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1195 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1196 struct drm_device *dev = crtc->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1200 assert_pipe_disabled(dev_priv,
1201 to_intel_crtc(crtc)->pipe);
1203 DRM_DEBUG_KMS("\n");
1204 dpa_ctl = I915_READ(DP_A);
1205 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1206 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1208 /* We don't adjust intel_dp->DP while tearing down the link, to
1209 * facilitate link retraining (e.g. after hotplug). Hence clear all
1210 * enable bits here to ensure that we don't enable too much. */
1211 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1212 intel_dp->DP |= DP_PLL_ENABLE;
1213 I915_WRITE(DP_A, intel_dp->DP);
1218 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222 struct drm_device *dev = crtc->dev;
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1229 dpa_ctl = I915_READ(DP_A);
1230 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1231 "dp pll off, should be on\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1234 /* We can't rely on the value tracked for the DP register in
1235 * intel_dp->DP because link_down must not change that (otherwise link
1236 * re-training will fail. */
1237 dpa_ctl &= ~DP_PLL_ENABLE;
1238 I915_WRITE(DP_A, dpa_ctl);
1243 /* If the sink supports it, try to set the power state appropriately */
1244 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1248 /* Should have a valid DPCD by this point */
1249 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1252 if (mode != DRM_MODE_DPMS_ON) {
1253 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1256 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1259 * When turning on, we need to retry for 1ms to give the sink
1262 for (i = 0; i < 3; i++) {
1263 ret = intel_dp_aux_native_write_1(intel_dp,
1273 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1276 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1277 enum port port = dp_to_dig_port(intel_dp)->port;
1278 struct drm_device *dev = encoder->base.dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 u32 tmp = I915_READ(intel_dp->output_reg);
1282 if (!(tmp & DP_PORT_EN))
1285 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1286 *pipe = PORT_TO_PIPE_CPT(tmp);
1287 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1288 *pipe = PORT_TO_PIPE(tmp);
1294 switch (intel_dp->output_reg) {
1296 trans_sel = TRANS_DP_PORT_SEL_B;
1299 trans_sel = TRANS_DP_PORT_SEL_C;
1302 trans_sel = TRANS_DP_PORT_SEL_D;
1309 trans_dp = I915_READ(TRANS_DP_CTL(i));
1310 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1316 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1317 intel_dp->output_reg);
1323 static void intel_dp_get_config(struct intel_encoder *encoder,
1324 struct intel_crtc_config *pipe_config)
1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1327 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1330 tmp = I915_READ(intel_dp->output_reg);
1332 if (tmp & DP_SYNC_HS_HIGH)
1333 flags |= DRM_MODE_FLAG_PHSYNC;
1335 flags |= DRM_MODE_FLAG_NHSYNC;
1337 if (tmp & DP_SYNC_VS_HIGH)
1338 flags |= DRM_MODE_FLAG_PVSYNC;
1340 flags |= DRM_MODE_FLAG_NVSYNC;
1342 pipe_config->adjusted_mode.flags |= flags;
1345 static void intel_disable_dp(struct intel_encoder *encoder)
1347 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1348 enum port port = dp_to_dig_port(intel_dp)->port;
1349 struct drm_device *dev = encoder->base.dev;
1351 /* Make sure the panel is off before trying to change the mode. But also
1352 * ensure that we have vdd while we switch off the panel. */
1353 ironlake_edp_panel_vdd_on(intel_dp);
1354 ironlake_edp_backlight_off(intel_dp);
1355 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1356 ironlake_edp_panel_off(intel_dp);
1358 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1359 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1360 intel_dp_link_down(intel_dp);
1363 static void intel_post_disable_dp(struct intel_encoder *encoder)
1365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1366 enum port port = dp_to_dig_port(intel_dp)->port;
1367 struct drm_device *dev = encoder->base.dev;
1369 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1370 intel_dp_link_down(intel_dp);
1371 if (!IS_VALLEYVIEW(dev))
1372 ironlake_edp_pll_off(intel_dp);
1376 static void intel_enable_dp(struct intel_encoder *encoder)
1378 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1383 if (WARN_ON(dp_reg & DP_PORT_EN))
1386 ironlake_edp_panel_vdd_on(intel_dp);
1387 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1388 intel_dp_start_link_train(intel_dp);
1389 ironlake_edp_panel_on(intel_dp);
1390 ironlake_edp_panel_vdd_off(intel_dp, true);
1391 intel_dp_complete_link_train(intel_dp);
1392 intel_dp_stop_link_train(intel_dp);
1393 ironlake_edp_backlight_on(intel_dp);
1395 if (IS_VALLEYVIEW(dev)) {
1396 struct intel_digital_port *dport =
1397 enc_to_dig_port(&encoder->base);
1398 int channel = vlv_dport_to_channel(dport);
1400 vlv_wait_port_ready(dev_priv, channel);
1404 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1406 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1407 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1408 struct drm_device *dev = encoder->base.dev;
1409 struct drm_i915_private *dev_priv = dev->dev_private;
1411 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1412 ironlake_edp_pll_on(intel_dp);
1414 if (IS_VALLEYVIEW(dev)) {
1415 struct intel_crtc *intel_crtc =
1416 to_intel_crtc(encoder->base.crtc);
1417 int port = vlv_dport_to_channel(dport);
1418 int pipe = intel_crtc->pipe;
1421 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1428 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1430 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1432 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1437 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1439 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1440 struct drm_device *dev = encoder->base.dev;
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442 int port = vlv_dport_to_channel(dport);
1444 if (!IS_VALLEYVIEW(dev))
1447 /* Program Tx lane resets to default */
1448 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1449 DPIO_PCS_TX_LANE2_RESET |
1450 DPIO_PCS_TX_LANE1_RESET);
1451 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1452 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1453 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1454 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1455 DPIO_PCS_CLK_SOFT_RESET);
1457 /* Fix up inter-pair skew failure */
1458 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1459 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1460 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1464 * Native read with retry for link status and receiver capability reads for
1465 * cases where the sink may still be asleep.
1468 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1469 uint8_t *recv, int recv_bytes)
1474 * Sinks are *supposed* to come up within 1ms from an off state,
1475 * but we're also supposed to retry 3 times per the spec.
1477 for (i = 0; i < 3; i++) {
1478 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1480 if (ret == recv_bytes)
1489 * Fetch AUX CH registers 0x202 - 0x207 which contain
1490 * link status information
1493 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1495 return intel_dp_aux_native_read_retry(intel_dp,
1498 DP_LINK_STATUS_SIZE);
1502 static char *voltage_names[] = {
1503 "0.4V", "0.6V", "0.8V", "1.2V"
1505 static char *pre_emph_names[] = {
1506 "0dB", "3.5dB", "6dB", "9.5dB"
1508 static char *link_train_names[] = {
1509 "pattern 1", "pattern 2", "idle", "off"
1514 * These are source-specific values; current Intel hardware supports
1515 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1519 intel_dp_voltage_max(struct intel_dp *intel_dp)
1521 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1522 enum port port = dp_to_dig_port(intel_dp)->port;
1524 if (IS_VALLEYVIEW(dev))
1525 return DP_TRAIN_VOLTAGE_SWING_1200;
1526 else if (IS_GEN7(dev) && port == PORT_A)
1527 return DP_TRAIN_VOLTAGE_SWING_800;
1528 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1529 return DP_TRAIN_VOLTAGE_SWING_1200;
1531 return DP_TRAIN_VOLTAGE_SWING_800;
1535 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1537 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1538 enum port port = dp_to_dig_port(intel_dp)->port;
1541 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1542 case DP_TRAIN_VOLTAGE_SWING_400:
1543 return DP_TRAIN_PRE_EMPHASIS_9_5;
1544 case DP_TRAIN_VOLTAGE_SWING_600:
1545 return DP_TRAIN_PRE_EMPHASIS_6;
1546 case DP_TRAIN_VOLTAGE_SWING_800:
1547 return DP_TRAIN_PRE_EMPHASIS_3_5;
1548 case DP_TRAIN_VOLTAGE_SWING_1200:
1550 return DP_TRAIN_PRE_EMPHASIS_0;
1552 } else if (IS_VALLEYVIEW(dev)) {
1553 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1554 case DP_TRAIN_VOLTAGE_SWING_400:
1555 return DP_TRAIN_PRE_EMPHASIS_9_5;
1556 case DP_TRAIN_VOLTAGE_SWING_600:
1557 return DP_TRAIN_PRE_EMPHASIS_6;
1558 case DP_TRAIN_VOLTAGE_SWING_800:
1559 return DP_TRAIN_PRE_EMPHASIS_3_5;
1560 case DP_TRAIN_VOLTAGE_SWING_1200:
1562 return DP_TRAIN_PRE_EMPHASIS_0;
1564 } else if (IS_GEN7(dev) && port == PORT_A) {
1565 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1566 case DP_TRAIN_VOLTAGE_SWING_400:
1567 return DP_TRAIN_PRE_EMPHASIS_6;
1568 case DP_TRAIN_VOLTAGE_SWING_600:
1569 case DP_TRAIN_VOLTAGE_SWING_800:
1570 return DP_TRAIN_PRE_EMPHASIS_3_5;
1572 return DP_TRAIN_PRE_EMPHASIS_0;
1575 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576 case DP_TRAIN_VOLTAGE_SWING_400:
1577 return DP_TRAIN_PRE_EMPHASIS_6;
1578 case DP_TRAIN_VOLTAGE_SWING_600:
1579 return DP_TRAIN_PRE_EMPHASIS_6;
1580 case DP_TRAIN_VOLTAGE_SWING_800:
1581 return DP_TRAIN_PRE_EMPHASIS_3_5;
1582 case DP_TRAIN_VOLTAGE_SWING_1200:
1584 return DP_TRAIN_PRE_EMPHASIS_0;
1589 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1594 unsigned long demph_reg_value, preemph_reg_value,
1595 uniqtranscale_reg_value;
1596 uint8_t train_set = intel_dp->train_set[0];
1597 int port = vlv_dport_to_channel(dport);
1599 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1600 case DP_TRAIN_PRE_EMPHASIS_0:
1601 preemph_reg_value = 0x0004000;
1602 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1603 case DP_TRAIN_VOLTAGE_SWING_400:
1604 demph_reg_value = 0x2B405555;
1605 uniqtranscale_reg_value = 0x552AB83A;
1607 case DP_TRAIN_VOLTAGE_SWING_600:
1608 demph_reg_value = 0x2B404040;
1609 uniqtranscale_reg_value = 0x5548B83A;
1611 case DP_TRAIN_VOLTAGE_SWING_800:
1612 demph_reg_value = 0x2B245555;
1613 uniqtranscale_reg_value = 0x5560B83A;
1615 case DP_TRAIN_VOLTAGE_SWING_1200:
1616 demph_reg_value = 0x2B405555;
1617 uniqtranscale_reg_value = 0x5598DA3A;
1623 case DP_TRAIN_PRE_EMPHASIS_3_5:
1624 preemph_reg_value = 0x0002000;
1625 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1626 case DP_TRAIN_VOLTAGE_SWING_400:
1627 demph_reg_value = 0x2B404040;
1628 uniqtranscale_reg_value = 0x5552B83A;
1630 case DP_TRAIN_VOLTAGE_SWING_600:
1631 demph_reg_value = 0x2B404848;
1632 uniqtranscale_reg_value = 0x5580B83A;
1634 case DP_TRAIN_VOLTAGE_SWING_800:
1635 demph_reg_value = 0x2B404040;
1636 uniqtranscale_reg_value = 0x55ADDA3A;
1642 case DP_TRAIN_PRE_EMPHASIS_6:
1643 preemph_reg_value = 0x0000000;
1644 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1645 case DP_TRAIN_VOLTAGE_SWING_400:
1646 demph_reg_value = 0x2B305555;
1647 uniqtranscale_reg_value = 0x5570B83A;
1649 case DP_TRAIN_VOLTAGE_SWING_600:
1650 demph_reg_value = 0x2B2B4040;
1651 uniqtranscale_reg_value = 0x55ADDA3A;
1657 case DP_TRAIN_PRE_EMPHASIS_9_5:
1658 preemph_reg_value = 0x0006000;
1659 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1660 case DP_TRAIN_VOLTAGE_SWING_400:
1661 demph_reg_value = 0x1B405555;
1662 uniqtranscale_reg_value = 0x55ADDA3A;
1672 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1673 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1674 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1675 uniqtranscale_reg_value);
1676 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1677 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1678 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1679 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1685 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1690 uint8_t voltage_max;
1691 uint8_t preemph_max;
1693 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1694 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1695 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1703 voltage_max = intel_dp_voltage_max(intel_dp);
1704 if (v >= voltage_max)
1705 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1707 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1708 if (p >= preemph_max)
1709 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1711 for (lane = 0; lane < 4; lane++)
1712 intel_dp->train_set[lane] = v | p;
1716 intel_gen4_signal_levels(uint8_t train_set)
1718 uint32_t signal_levels = 0;
1720 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1721 case DP_TRAIN_VOLTAGE_SWING_400:
1723 signal_levels |= DP_VOLTAGE_0_4;
1725 case DP_TRAIN_VOLTAGE_SWING_600:
1726 signal_levels |= DP_VOLTAGE_0_6;
1728 case DP_TRAIN_VOLTAGE_SWING_800:
1729 signal_levels |= DP_VOLTAGE_0_8;
1731 case DP_TRAIN_VOLTAGE_SWING_1200:
1732 signal_levels |= DP_VOLTAGE_1_2;
1735 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1736 case DP_TRAIN_PRE_EMPHASIS_0:
1738 signal_levels |= DP_PRE_EMPHASIS_0;
1740 case DP_TRAIN_PRE_EMPHASIS_3_5:
1741 signal_levels |= DP_PRE_EMPHASIS_3_5;
1743 case DP_TRAIN_PRE_EMPHASIS_6:
1744 signal_levels |= DP_PRE_EMPHASIS_6;
1746 case DP_TRAIN_PRE_EMPHASIS_9_5:
1747 signal_levels |= DP_PRE_EMPHASIS_9_5;
1750 return signal_levels;
1753 /* Gen6's DP voltage swing and pre-emphasis control */
1755 intel_gen6_edp_signal_levels(uint8_t train_set)
1757 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1758 DP_TRAIN_PRE_EMPHASIS_MASK);
1759 switch (signal_levels) {
1760 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1761 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1762 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1763 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1764 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1765 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1766 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1767 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1768 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1769 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1770 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1771 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1772 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1773 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1775 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1776 "0x%x\n", signal_levels);
1777 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1781 /* Gen7's DP voltage swing and pre-emphasis control */
1783 intel_gen7_edp_signal_levels(uint8_t train_set)
1785 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1786 DP_TRAIN_PRE_EMPHASIS_MASK);
1787 switch (signal_levels) {
1788 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1789 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1790 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1791 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1792 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1793 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1795 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1796 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1797 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1798 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1800 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1801 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1802 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1803 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1806 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1807 "0x%x\n", signal_levels);
1808 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1812 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1814 intel_hsw_signal_levels(uint8_t train_set)
1816 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1817 DP_TRAIN_PRE_EMPHASIS_MASK);
1818 switch (signal_levels) {
1819 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1820 return DDI_BUF_EMP_400MV_0DB_HSW;
1821 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1822 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1823 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1824 return DDI_BUF_EMP_400MV_6DB_HSW;
1825 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1826 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1828 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1829 return DDI_BUF_EMP_600MV_0DB_HSW;
1830 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1831 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1832 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1833 return DDI_BUF_EMP_600MV_6DB_HSW;
1835 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1836 return DDI_BUF_EMP_800MV_0DB_HSW;
1837 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1838 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1840 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1841 "0x%x\n", signal_levels);
1842 return DDI_BUF_EMP_400MV_0DB_HSW;
1846 /* Properly updates "DP" with the correct signal levels. */
1848 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1850 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1851 enum port port = intel_dig_port->port;
1852 struct drm_device *dev = intel_dig_port->base.base.dev;
1853 uint32_t signal_levels, mask;
1854 uint8_t train_set = intel_dp->train_set[0];
1857 signal_levels = intel_hsw_signal_levels(train_set);
1858 mask = DDI_BUF_EMP_MASK;
1859 } else if (IS_VALLEYVIEW(dev)) {
1860 signal_levels = intel_vlv_signal_levels(intel_dp);
1862 } else if (IS_GEN7(dev) && port == PORT_A) {
1863 signal_levels = intel_gen7_edp_signal_levels(train_set);
1864 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1865 } else if (IS_GEN6(dev) && port == PORT_A) {
1866 signal_levels = intel_gen6_edp_signal_levels(train_set);
1867 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1869 signal_levels = intel_gen4_signal_levels(train_set);
1870 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1873 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1875 *DP = (*DP & ~mask) | signal_levels;
1879 intel_dp_set_link_train(struct intel_dp *intel_dp,
1880 uint32_t dp_reg_value,
1881 uint8_t dp_train_pat)
1883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1884 struct drm_device *dev = intel_dig_port->base.base.dev;
1885 struct drm_i915_private *dev_priv = dev->dev_private;
1886 enum port port = intel_dig_port->port;
1890 uint32_t temp = I915_READ(DP_TP_CTL(port));
1892 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1893 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1895 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1897 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1898 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1899 case DP_TRAINING_PATTERN_DISABLE:
1900 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1903 case DP_TRAINING_PATTERN_1:
1904 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1906 case DP_TRAINING_PATTERN_2:
1907 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1909 case DP_TRAINING_PATTERN_3:
1910 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1913 I915_WRITE(DP_TP_CTL(port), temp);
1915 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
1916 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1918 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1919 case DP_TRAINING_PATTERN_DISABLE:
1920 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1922 case DP_TRAINING_PATTERN_1:
1923 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1925 case DP_TRAINING_PATTERN_2:
1926 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1928 case DP_TRAINING_PATTERN_3:
1929 DRM_ERROR("DP training pattern 3 not supported\n");
1930 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1935 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1937 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1938 case DP_TRAINING_PATTERN_DISABLE:
1939 dp_reg_value |= DP_LINK_TRAIN_OFF;
1941 case DP_TRAINING_PATTERN_1:
1942 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1944 case DP_TRAINING_PATTERN_2:
1945 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1947 case DP_TRAINING_PATTERN_3:
1948 DRM_ERROR("DP training pattern 3 not supported\n");
1949 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1954 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1955 POSTING_READ(intel_dp->output_reg);
1957 intel_dp_aux_native_write_1(intel_dp,
1958 DP_TRAINING_PATTERN_SET,
1961 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1962 DP_TRAINING_PATTERN_DISABLE) {
1963 ret = intel_dp_aux_native_write(intel_dp,
1964 DP_TRAINING_LANE0_SET,
1965 intel_dp->train_set,
1966 intel_dp->lane_count);
1967 if (ret != intel_dp->lane_count)
1974 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1976 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1977 struct drm_device *dev = intel_dig_port->base.base.dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 enum port port = intel_dig_port->port;
1985 val = I915_READ(DP_TP_CTL(port));
1986 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1987 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1988 I915_WRITE(DP_TP_CTL(port), val);
1991 * On PORT_A we can have only eDP in SST mode. There the only reason
1992 * we need to set idle transmission mode is to work around a HW issue
1993 * where we enable the pipe while not in idle link-training mode.
1994 * In this case there is requirement to wait for a minimum number of
1995 * idle patterns to be sent.
2000 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2002 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2005 /* Enable corresponding port and start training pattern 1 */
2007 intel_dp_start_link_train(struct intel_dp *intel_dp)
2009 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2010 struct drm_device *dev = encoder->dev;
2013 bool clock_recovery = false;
2014 int voltage_tries, loop_tries;
2015 uint32_t DP = intel_dp->DP;
2018 intel_ddi_prepare_link_retrain(encoder);
2020 /* Write the link configuration data */
2021 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2022 intel_dp->link_configuration,
2023 DP_LINK_CONFIGURATION_SIZE);
2027 memset(intel_dp->train_set, 0, 4);
2031 clock_recovery = false;
2033 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2034 uint8_t link_status[DP_LINK_STATUS_SIZE];
2036 intel_dp_set_signal_levels(intel_dp, &DP);
2038 /* Set training pattern 1 */
2039 if (!intel_dp_set_link_train(intel_dp, DP,
2040 DP_TRAINING_PATTERN_1 |
2041 DP_LINK_SCRAMBLING_DISABLE))
2044 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2045 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2046 DRM_ERROR("failed to get link status\n");
2050 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2051 DRM_DEBUG_KMS("clock recovery OK\n");
2052 clock_recovery = true;
2056 /* Check to see if we've tried the max voltage */
2057 for (i = 0; i < intel_dp->lane_count; i++)
2058 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2060 if (i == intel_dp->lane_count) {
2062 if (loop_tries == 5) {
2063 DRM_DEBUG_KMS("too many full retries, give up\n");
2066 memset(intel_dp->train_set, 0, 4);
2071 /* Check to see if we've tried the same voltage 5 times */
2072 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2074 if (voltage_tries == 5) {
2075 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2080 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2082 /* Compute new intel_dp->train_set as requested by target */
2083 intel_get_adjust_train(intel_dp, link_status);
2090 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2092 bool channel_eq = false;
2093 int tries, cr_tries;
2094 uint32_t DP = intel_dp->DP;
2096 /* channel equalization */
2101 uint8_t link_status[DP_LINK_STATUS_SIZE];
2104 DRM_ERROR("failed to train DP, aborting\n");
2105 intel_dp_link_down(intel_dp);
2109 intel_dp_set_signal_levels(intel_dp, &DP);
2111 /* channel eq pattern */
2112 if (!intel_dp_set_link_train(intel_dp, DP,
2113 DP_TRAINING_PATTERN_2 |
2114 DP_LINK_SCRAMBLING_DISABLE))
2117 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2118 if (!intel_dp_get_link_status(intel_dp, link_status))
2121 /* Make sure clock is still ok */
2122 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2123 intel_dp_start_link_train(intel_dp);
2128 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2133 /* Try 5 times, then try clock recovery if that fails */
2135 intel_dp_link_down(intel_dp);
2136 intel_dp_start_link_train(intel_dp);
2142 /* Compute new intel_dp->train_set as requested by target */
2143 intel_get_adjust_train(intel_dp, link_status);
2147 intel_dp_set_idle_link_train(intel_dp);
2152 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2156 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2158 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2159 DP_TRAINING_PATTERN_DISABLE);
2163 intel_dp_link_down(struct intel_dp *intel_dp)
2165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2166 enum port port = intel_dig_port->port;
2167 struct drm_device *dev = intel_dig_port->base.base.dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc =
2170 to_intel_crtc(intel_dig_port->base.base.crtc);
2171 uint32_t DP = intel_dp->DP;
2174 * DDI code has a strict mode set sequence and we should try to respect
2175 * it, otherwise we might hang the machine in many different ways. So we
2176 * really should be disabling the port only on a complete crtc_disable
2177 * sequence. This function is just called under two conditions on DDI
2179 * - Link train failed while doing crtc_enable, and on this case we
2180 * really should respect the mode set sequence and wait for a
2182 * - Someone turned the monitor off and intel_dp_check_link_status
2183 * called us. We don't need to disable the whole port on this case, so
2184 * when someone turns the monitor on again,
2185 * intel_ddi_prepare_link_retrain will take care of redoing the link
2191 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2194 DRM_DEBUG_KMS("\n");
2196 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2197 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2198 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2200 DP &= ~DP_LINK_TRAIN_MASK;
2201 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2203 POSTING_READ(intel_dp->output_reg);
2205 /* We don't really know why we're doing this */
2206 intel_wait_for_vblank(dev, intel_crtc->pipe);
2208 if (HAS_PCH_IBX(dev) &&
2209 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2210 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2212 /* Hardware workaround: leaving our transcoder select
2213 * set to transcoder B while it's off will prevent the
2214 * corresponding HDMI output on transcoder A.
2216 * Combine this with another hardware workaround:
2217 * transcoder select bit can only be cleared while the
2220 DP &= ~DP_PIPEB_SELECT;
2221 I915_WRITE(intel_dp->output_reg, DP);
2223 /* Changes to enable or select take place the vblank
2224 * after being written.
2226 if (WARN_ON(crtc == NULL)) {
2227 /* We should never try to disable a port without a crtc
2228 * attached. For paranoia keep the code around for a
2230 POSTING_READ(intel_dp->output_reg);
2233 intel_wait_for_vblank(dev, intel_crtc->pipe);
2236 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2237 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2238 POSTING_READ(intel_dp->output_reg);
2239 msleep(intel_dp->panel_power_down_delay);
2243 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2245 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2247 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2248 sizeof(intel_dp->dpcd)) == 0)
2249 return false; /* aux transfer failed */
2251 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2252 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2253 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2255 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2256 return false; /* DPCD not present */
2258 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2259 DP_DWN_STRM_PORT_PRESENT))
2260 return true; /* native DP sink */
2262 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2263 return true; /* no per-port downstream info */
2265 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2266 intel_dp->downstream_ports,
2267 DP_MAX_DOWNSTREAM_PORTS) == 0)
2268 return false; /* downstream port status fetch failed */
2274 intel_dp_probe_oui(struct intel_dp *intel_dp)
2278 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2281 ironlake_edp_panel_vdd_on(intel_dp);
2283 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2284 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2285 buf[0], buf[1], buf[2]);
2287 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2288 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2289 buf[0], buf[1], buf[2]);
2291 ironlake_edp_panel_vdd_off(intel_dp, false);
2295 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2299 ret = intel_dp_aux_native_read_retry(intel_dp,
2300 DP_DEVICE_SERVICE_IRQ_VECTOR,
2301 sink_irq_vector, 1);
2309 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2311 /* NAK by default */
2312 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2316 * According to DP spec
2319 * 2. Configure link according to Receiver Capabilities
2320 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2321 * 4. Check link status on receipt of hot-plug interrupt
2325 intel_dp_check_link_status(struct intel_dp *intel_dp)
2327 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2329 u8 link_status[DP_LINK_STATUS_SIZE];
2331 if (!intel_encoder->connectors_active)
2334 if (WARN_ON(!intel_encoder->base.crtc))
2337 /* Try to read receiver status if the link appears to be up */
2338 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2339 intel_dp_link_down(intel_dp);
2343 /* Now read the DPCD to see if it's actually running */
2344 if (!intel_dp_get_dpcd(intel_dp)) {
2345 intel_dp_link_down(intel_dp);
2349 /* Try to read the source of the interrupt */
2350 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2351 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2352 /* Clear interrupt source */
2353 intel_dp_aux_native_write_1(intel_dp,
2354 DP_DEVICE_SERVICE_IRQ_VECTOR,
2357 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2358 intel_dp_handle_test_request(intel_dp);
2359 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2360 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2363 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2364 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2365 drm_get_encoder_name(&intel_encoder->base));
2366 intel_dp_start_link_train(intel_dp);
2367 intel_dp_complete_link_train(intel_dp);
2368 intel_dp_stop_link_train(intel_dp);
2372 /* XXX this is probably wrong for multiple downstream ports */
2373 static enum drm_connector_status
2374 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2376 uint8_t *dpcd = intel_dp->dpcd;
2380 if (!intel_dp_get_dpcd(intel_dp))
2381 return connector_status_disconnected;
2383 /* if there's no downstream port, we're done */
2384 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2385 return connector_status_connected;
2387 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2388 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2391 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2393 return connector_status_unknown;
2394 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2395 : connector_status_disconnected;
2398 /* If no HPD, poke DDC gently */
2399 if (drm_probe_ddc(&intel_dp->adapter))
2400 return connector_status_connected;
2402 /* Well we tried, say unknown for unreliable port types */
2403 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2404 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2405 return connector_status_unknown;
2407 /* Anything else is out of spec, warn and ignore */
2408 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2409 return connector_status_disconnected;
2412 static enum drm_connector_status
2413 ironlake_dp_detect(struct intel_dp *intel_dp)
2415 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2418 enum drm_connector_status status;
2420 /* Can't disconnect eDP, but you can close the lid... */
2421 if (is_edp(intel_dp)) {
2422 status = intel_panel_detect(dev);
2423 if (status == connector_status_unknown)
2424 status = connector_status_connected;
2428 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2429 return connector_status_disconnected;
2431 return intel_dp_detect_dpcd(intel_dp);
2434 static enum drm_connector_status
2435 g4x_dp_detect(struct intel_dp *intel_dp)
2437 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2438 struct drm_i915_private *dev_priv = dev->dev_private;
2439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2442 /* Can't disconnect eDP, but you can close the lid... */
2443 if (is_edp(intel_dp)) {
2444 enum drm_connector_status status;
2446 status = intel_panel_detect(dev);
2447 if (status == connector_status_unknown)
2448 status = connector_status_connected;
2452 switch (intel_dig_port->port) {
2454 bit = PORTB_HOTPLUG_LIVE_STATUS;
2457 bit = PORTC_HOTPLUG_LIVE_STATUS;
2460 bit = PORTD_HOTPLUG_LIVE_STATUS;
2463 return connector_status_unknown;
2466 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2467 return connector_status_disconnected;
2469 return intel_dp_detect_dpcd(intel_dp);
2472 static struct edid *
2473 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2475 struct intel_connector *intel_connector = to_intel_connector(connector);
2477 /* use cached edid if we have one */
2478 if (intel_connector->edid) {
2483 if (IS_ERR(intel_connector->edid))
2486 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2487 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2494 return drm_get_edid(connector, adapter);
2498 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2500 struct intel_connector *intel_connector = to_intel_connector(connector);
2502 /* use cached edid if we have one */
2503 if (intel_connector->edid) {
2505 if (IS_ERR(intel_connector->edid))
2508 return intel_connector_update_modes(connector,
2509 intel_connector->edid);
2512 return intel_ddc_get_modes(connector, adapter);
2515 static enum drm_connector_status
2516 intel_dp_detect(struct drm_connector *connector, bool force)
2518 struct intel_dp *intel_dp = intel_attached_dp(connector);
2519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2520 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2521 struct drm_device *dev = connector->dev;
2522 enum drm_connector_status status;
2523 struct edid *edid = NULL;
2525 intel_dp->has_audio = false;
2527 if (HAS_PCH_SPLIT(dev))
2528 status = ironlake_dp_detect(intel_dp);
2530 status = g4x_dp_detect(intel_dp);
2532 if (status != connector_status_connected)
2535 intel_dp_probe_oui(intel_dp);
2537 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2538 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2540 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2542 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2547 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2548 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2549 return connector_status_connected;
2552 static int intel_dp_get_modes(struct drm_connector *connector)
2554 struct intel_dp *intel_dp = intel_attached_dp(connector);
2555 struct intel_connector *intel_connector = to_intel_connector(connector);
2556 struct drm_device *dev = connector->dev;
2559 /* We should parse the EDID data and find out if it has an audio sink
2562 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2566 /* if eDP has no EDID, fall back to fixed mode */
2567 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2568 struct drm_display_mode *mode;
2569 mode = drm_mode_duplicate(dev,
2570 intel_connector->panel.fixed_mode);
2572 drm_mode_probed_add(connector, mode);
2580 intel_dp_detect_audio(struct drm_connector *connector)
2582 struct intel_dp *intel_dp = intel_attached_dp(connector);
2584 bool has_audio = false;
2586 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2588 has_audio = drm_detect_monitor_audio(edid);
2596 intel_dp_set_property(struct drm_connector *connector,
2597 struct drm_property *property,
2600 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2601 struct intel_connector *intel_connector = to_intel_connector(connector);
2602 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2603 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2606 ret = drm_object_property_set_value(&connector->base, property, val);
2610 if (property == dev_priv->force_audio_property) {
2614 if (i == intel_dp->force_audio)
2617 intel_dp->force_audio = i;
2619 if (i == HDMI_AUDIO_AUTO)
2620 has_audio = intel_dp_detect_audio(connector);
2622 has_audio = (i == HDMI_AUDIO_ON);
2624 if (has_audio == intel_dp->has_audio)
2627 intel_dp->has_audio = has_audio;
2631 if (property == dev_priv->broadcast_rgb_property) {
2632 bool old_auto = intel_dp->color_range_auto;
2633 uint32_t old_range = intel_dp->color_range;
2636 case INTEL_BROADCAST_RGB_AUTO:
2637 intel_dp->color_range_auto = true;
2639 case INTEL_BROADCAST_RGB_FULL:
2640 intel_dp->color_range_auto = false;
2641 intel_dp->color_range = 0;
2643 case INTEL_BROADCAST_RGB_LIMITED:
2644 intel_dp->color_range_auto = false;
2645 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2651 if (old_auto == intel_dp->color_range_auto &&
2652 old_range == intel_dp->color_range)
2658 if (is_edp(intel_dp) &&
2659 property == connector->dev->mode_config.scaling_mode_property) {
2660 if (val == DRM_MODE_SCALE_NONE) {
2661 DRM_DEBUG_KMS("no scaling not supported\n");
2665 if (intel_connector->panel.fitting_mode == val) {
2666 /* the eDP scaling property is not changed */
2669 intel_connector->panel.fitting_mode = val;
2677 if (intel_encoder->base.crtc)
2678 intel_crtc_restore_mode(intel_encoder->base.crtc);
2684 intel_dp_destroy(struct drm_connector *connector)
2686 struct intel_connector *intel_connector = to_intel_connector(connector);
2688 if (!IS_ERR_OR_NULL(intel_connector->edid))
2689 kfree(intel_connector->edid);
2691 /* Can't call is_edp() since the encoder may have been destroyed
2693 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2694 intel_panel_fini(&intel_connector->panel);
2696 drm_sysfs_connector_remove(connector);
2697 drm_connector_cleanup(connector);
2701 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2703 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2704 struct intel_dp *intel_dp = &intel_dig_port->dp;
2705 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2707 i2c_del_adapter(&intel_dp->adapter);
2708 drm_encoder_cleanup(encoder);
2709 if (is_edp(intel_dp)) {
2710 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2711 mutex_lock(&dev->mode_config.mutex);
2712 ironlake_panel_vdd_off_sync(intel_dp);
2713 mutex_unlock(&dev->mode_config.mutex);
2715 kfree(intel_dig_port);
2718 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2719 .mode_set = intel_dp_mode_set,
2722 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2723 .dpms = intel_connector_dpms,
2724 .detect = intel_dp_detect,
2725 .fill_modes = drm_helper_probe_single_connector_modes,
2726 .set_property = intel_dp_set_property,
2727 .destroy = intel_dp_destroy,
2730 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2731 .get_modes = intel_dp_get_modes,
2732 .mode_valid = intel_dp_mode_valid,
2733 .best_encoder = intel_best_encoder,
2736 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2737 .destroy = intel_dp_encoder_destroy,
2741 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2743 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2745 intel_dp_check_link_status(intel_dp);
2748 /* Return which DP Port should be selected for Transcoder DP control */
2750 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2752 struct drm_device *dev = crtc->dev;
2753 struct intel_encoder *intel_encoder;
2754 struct intel_dp *intel_dp;
2756 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2757 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2759 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2760 intel_encoder->type == INTEL_OUTPUT_EDP)
2761 return intel_dp->output_reg;
2767 /* check the VBT to see whether the eDP is on DP-D port */
2768 bool intel_dpd_is_edp(struct drm_device *dev)
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct child_device_config *p_child;
2774 if (!dev_priv->vbt.child_dev_num)
2777 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2778 p_child = dev_priv->vbt.child_dev + i;
2780 if (p_child->dvo_port == PORT_IDPD &&
2781 p_child->device_type == DEVICE_TYPE_eDP)
2788 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2790 struct intel_connector *intel_connector = to_intel_connector(connector);
2792 intel_attach_force_audio_property(connector);
2793 intel_attach_broadcast_rgb_property(connector);
2794 intel_dp->color_range_auto = true;
2796 if (is_edp(intel_dp)) {
2797 drm_mode_create_scaling_mode_property(connector->dev);
2798 drm_object_attach_property(
2800 connector->dev->mode_config.scaling_mode_property,
2801 DRM_MODE_SCALE_ASPECT);
2802 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2807 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2808 struct intel_dp *intel_dp,
2809 struct edp_power_seq *out)
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 struct edp_power_seq cur, vbt, spec, final;
2813 u32 pp_on, pp_off, pp_div, pp;
2814 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2816 if (HAS_PCH_SPLIT(dev)) {
2817 pp_control_reg = PCH_PP_CONTROL;
2818 pp_on_reg = PCH_PP_ON_DELAYS;
2819 pp_off_reg = PCH_PP_OFF_DELAYS;
2820 pp_div_reg = PCH_PP_DIVISOR;
2822 pp_control_reg = PIPEA_PP_CONTROL;
2823 pp_on_reg = PIPEA_PP_ON_DELAYS;
2824 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2825 pp_div_reg = PIPEA_PP_DIVISOR;
2828 /* Workaround: Need to write PP_CONTROL with the unlock key as
2829 * the very first thing. */
2830 pp = ironlake_get_pp_control(intel_dp);
2831 I915_WRITE(pp_control_reg, pp);
2833 pp_on = I915_READ(pp_on_reg);
2834 pp_off = I915_READ(pp_off_reg);
2835 pp_div = I915_READ(pp_div_reg);
2837 /* Pull timing values out of registers */
2838 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2839 PANEL_POWER_UP_DELAY_SHIFT;
2841 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2842 PANEL_LIGHT_ON_DELAY_SHIFT;
2844 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2845 PANEL_LIGHT_OFF_DELAY_SHIFT;
2847 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2848 PANEL_POWER_DOWN_DELAY_SHIFT;
2850 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2851 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2853 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2854 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2856 vbt = dev_priv->vbt.edp_pps;
2858 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2859 * our hw here, which are all in 100usec. */
2860 spec.t1_t3 = 210 * 10;
2861 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2862 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2863 spec.t10 = 500 * 10;
2864 /* This one is special and actually in units of 100ms, but zero
2865 * based in the hw (so we need to add 100 ms). But the sw vbt
2866 * table multiplies it with 1000 to make it in units of 100usec,
2868 spec.t11_t12 = (510 + 100) * 10;
2870 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2871 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2873 /* Use the max of the register settings and vbt. If both are
2874 * unset, fall back to the spec limits. */
2875 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2877 max(cur.field, vbt.field))
2878 assign_final(t1_t3);
2882 assign_final(t11_t12);
2885 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2886 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2887 intel_dp->backlight_on_delay = get_delay(t8);
2888 intel_dp->backlight_off_delay = get_delay(t9);
2889 intel_dp->panel_power_down_delay = get_delay(t10);
2890 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2893 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2894 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2895 intel_dp->panel_power_cycle_delay);
2897 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2898 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2905 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2906 struct intel_dp *intel_dp,
2907 struct edp_power_seq *seq)
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 u32 pp_on, pp_off, pp_div, port_sel = 0;
2911 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2912 int pp_on_reg, pp_off_reg, pp_div_reg;
2914 if (HAS_PCH_SPLIT(dev)) {
2915 pp_on_reg = PCH_PP_ON_DELAYS;
2916 pp_off_reg = PCH_PP_OFF_DELAYS;
2917 pp_div_reg = PCH_PP_DIVISOR;
2919 pp_on_reg = PIPEA_PP_ON_DELAYS;
2920 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2921 pp_div_reg = PIPEA_PP_DIVISOR;
2924 /* And finally store the new values in the power sequencer. */
2925 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2926 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2927 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2928 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2929 /* Compute the divisor for the pp clock, simply match the Bspec
2931 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2932 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2933 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2935 /* Haswell doesn't have any port selection bits for the panel
2936 * power sequencer any more. */
2937 if (IS_VALLEYVIEW(dev)) {
2938 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2939 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2940 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2941 port_sel = PANEL_POWER_PORT_DP_A;
2943 port_sel = PANEL_POWER_PORT_DP_D;
2948 I915_WRITE(pp_on_reg, pp_on);
2949 I915_WRITE(pp_off_reg, pp_off);
2950 I915_WRITE(pp_div_reg, pp_div);
2952 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2953 I915_READ(pp_on_reg),
2954 I915_READ(pp_off_reg),
2955 I915_READ(pp_div_reg));
2958 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
2959 struct intel_connector *intel_connector)
2961 struct drm_connector *connector = &intel_connector->base;
2962 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2963 struct drm_device *dev = intel_dig_port->base.base.dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct drm_display_mode *fixed_mode = NULL;
2966 struct edp_power_seq power_seq = { 0 };
2968 struct drm_display_mode *scan;
2971 if (!is_edp(intel_dp))
2974 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2976 /* Cache DPCD and EDID for edp. */
2977 ironlake_edp_panel_vdd_on(intel_dp);
2978 has_dpcd = intel_dp_get_dpcd(intel_dp);
2979 ironlake_edp_panel_vdd_off(intel_dp, false);
2982 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2983 dev_priv->no_aux_handshake =
2984 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2985 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2987 /* if this fails, presume the device is a ghost */
2988 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2989 intel_dp_encoder_destroy(&intel_dig_port->base.base);
2990 intel_dp_destroy(connector);
2994 /* We now know it's not a ghost, init power sequence regs. */
2995 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2998 ironlake_edp_panel_vdd_on(intel_dp);
2999 edid = drm_get_edid(connector, &intel_dp->adapter);
3001 if (drm_add_edid_modes(connector, edid)) {
3002 drm_mode_connector_update_edid_property(connector,
3004 drm_edid_to_eld(connector, edid);
3007 edid = ERR_PTR(-EINVAL);
3010 edid = ERR_PTR(-ENOENT);
3012 intel_connector->edid = edid;
3014 /* prefer fixed mode from EDID if available */
3015 list_for_each_entry(scan, &connector->probed_modes, head) {
3016 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3017 fixed_mode = drm_mode_duplicate(dev, scan);
3022 /* fallback to VBT if available for eDP */
3023 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3024 fixed_mode = drm_mode_duplicate(dev,
3025 dev_priv->vbt.lfp_lvds_vbt_mode);
3027 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3030 ironlake_edp_panel_vdd_off(intel_dp, false);
3032 intel_panel_init(&intel_connector->panel, fixed_mode);
3033 intel_panel_setup_backlight(connector);
3039 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3040 struct intel_connector *intel_connector)
3042 struct drm_connector *connector = &intel_connector->base;
3043 struct intel_dp *intel_dp = &intel_dig_port->dp;
3044 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3045 struct drm_device *dev = intel_encoder->base.dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 enum port port = intel_dig_port->port;
3048 const char *name = NULL;
3051 /* Preserve the current hw state. */
3052 intel_dp->DP = I915_READ(intel_dp->output_reg);
3053 intel_dp->attached_connector = intel_connector;
3055 type = DRM_MODE_CONNECTOR_DisplayPort;
3057 * FIXME : We need to initialize built-in panels before external panels.
3058 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3062 type = DRM_MODE_CONNECTOR_eDP;
3065 if (IS_VALLEYVIEW(dev))
3066 type = DRM_MODE_CONNECTOR_eDP;
3069 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3070 type = DRM_MODE_CONNECTOR_eDP;
3072 default: /* silence GCC warning */
3077 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3078 * for DP the encoder type can be set by the caller to
3079 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3081 if (type == DRM_MODE_CONNECTOR_eDP)
3082 intel_encoder->type = INTEL_OUTPUT_EDP;
3084 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3085 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3088 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3089 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3091 connector->interlace_allowed = true;
3092 connector->doublescan_allowed = 0;
3094 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3095 ironlake_panel_vdd_work);
3097 intel_connector_attach_encoder(intel_connector, intel_encoder);
3098 drm_sysfs_connector_add(connector);
3101 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3103 intel_connector->get_hw_state = intel_connector_get_hw_state;
3105 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3107 switch (intel_dig_port->port) {
3109 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3112 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3115 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3118 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3125 /* Set up the DDC bus. */
3128 intel_encoder->hpd_pin = HPD_PORT_A;
3132 intel_encoder->hpd_pin = HPD_PORT_B;
3136 intel_encoder->hpd_pin = HPD_PORT_C;
3140 intel_encoder->hpd_pin = HPD_PORT_D;
3147 intel_dp_i2c_init(intel_dp, intel_connector, name);
3149 if (!intel_edp_init_connector(intel_dp, intel_connector))
3152 intel_dp_add_properties(intel_dp, connector);
3154 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3155 * 0xd. Failure to do so will result in spurious interrupts being
3156 * generated on the port when a cable is not attached.
3158 if (IS_G4X(dev) && !IS_GM45(dev)) {
3159 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3160 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3167 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3169 struct intel_digital_port *intel_dig_port;
3170 struct intel_encoder *intel_encoder;
3171 struct drm_encoder *encoder;
3172 struct intel_connector *intel_connector;
3174 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3175 if (!intel_dig_port)
3178 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3179 if (!intel_connector) {
3180 kfree(intel_dig_port);
3184 intel_encoder = &intel_dig_port->base;
3185 encoder = &intel_encoder->base;
3187 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3188 DRM_MODE_ENCODER_TMDS);
3189 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3191 intel_encoder->compute_config = intel_dp_compute_config;
3192 intel_encoder->enable = intel_enable_dp;
3193 intel_encoder->pre_enable = intel_pre_enable_dp;
3194 intel_encoder->disable = intel_disable_dp;
3195 intel_encoder->post_disable = intel_post_disable_dp;
3196 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3197 intel_encoder->get_config = intel_dp_get_config;
3198 if (IS_VALLEYVIEW(dev))
3199 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3201 intel_dig_port->port = port;
3202 intel_dig_port->dp.output_reg = output_reg;
3204 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3205 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3206 intel_encoder->cloneable = false;
3207 intel_encoder->hot_plug = intel_dp_hot_plug;
3209 intel_dp_init_connector(intel_dig_port, intel_connector);