2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp *intel_dp)
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
85 return intel_dig_port->base.base.dev;
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
110 max_link_bw = DP_LINK_BW_1_62;
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
122 * 270000 * 1 * 8 / 10 == 216000
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
134 intel_dp_link_required(int pixel_clock, int bpp)
136 return (pixel_clock * bpp + 9) / 10;
140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
142 return (max_link_clock * max_lanes * 8) / 10;
146 intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
149 struct intel_dp *intel_dp = intel_attached_dp(connector);
150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
159 if (mode->vdisplay > fixed_mode->vdisplay)
162 target_clock = fixed_mode->clock;
165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
171 if (mode_rate > max_rate)
172 return MODE_CLOCK_HIGH;
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
184 pack_aux(uint8_t *src, int src_bytes)
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
206 /* hrawclock is 1/4 the FSB frequency */
208 intel_hrawclk(struct drm_device *dev)
210 struct drm_i915_private *dev_priv = dev->dev_private;
213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
227 case CLKCFG_FSB_1067:
229 case CLKCFG_FSB_1333:
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
259 /* modeset should have pipe */
261 return to_intel_crtc(crtc)->pipe;
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
300 struct drm_i915_private *dev_priv = dev->dev_private;
302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
308 struct drm_i915_private *dev_priv = dev->dev_private;
310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
314 intel_dp_check_edp(struct intel_dp *intel_dp)
316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
317 struct drm_i915_private *dev_priv = dev->dev_private;
319 if (!is_edp(intel_dp))
322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
343 msecs_to_jiffies_timeout(10));
345 done = wait_for_atomic(C, 10) == 0;
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
365 * Note that PCH attached eDP panels should use a 125MHz input
368 if (IS_VALLEYVIEW(dev)) {
369 return index ? 0 : 100;
370 } else if (intel_dig_port->port == PORT_A) {
374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
386 } else if (HAS_PCH_SPLIT(dev)) {
387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 return index ? 0 :intel_hrawclk(dev) / 2;
394 intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
403 uint32_t aux_clock_divider;
404 int i, ret, recv_bytes;
406 int try, precharge, clock = 0;
407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
415 intel_dp_check_edp(intel_dp);
422 intel_aux_display_runtime_get(dev_priv);
424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
426 status = I915_READ_NOTRACE(ch_ctl);
427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
439 /* Only 5 data registers! */
440 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
445 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
446 /* Must try at least 3 times according to DP spec */
447 for (try = 0; try < 5; try++) {
448 /* Load the send data into the aux channel data registers */
449 for (i = 0; i < send_bytes; i += 4)
450 I915_WRITE(ch_data + i,
451 pack_aux(send + i, send_bytes - i));
453 /* Send the command and wait for it to complete */
455 DP_AUX_CH_CTL_SEND_BUSY |
456 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
457 DP_AUX_CH_CTL_TIME_OUT_400us |
458 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
459 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
460 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
462 DP_AUX_CH_CTL_TIME_OUT_ERROR |
463 DP_AUX_CH_CTL_RECEIVE_ERROR);
465 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
467 /* Clear done status and any errors */
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
474 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
475 DP_AUX_CH_CTL_RECEIVE_ERROR))
477 if (status & DP_AUX_CH_CTL_DONE)
480 if (status & DP_AUX_CH_CTL_DONE)
484 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
485 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
490 /* Check for timeout or receive error.
491 * Timeouts occur when the sink is not connected
493 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
494 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
499 /* Timeouts occur when the device isn't connected, so they're
500 * "normal" -- don't fill the kernel log with these */
501 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
502 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
507 /* Unload any bytes sent back from the other side */
508 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
509 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
510 if (recv_bytes > recv_size)
511 recv_bytes = recv_size;
513 for (i = 0; i < recv_bytes; i += 4)
514 unpack_aux(I915_READ(ch_data + i),
515 recv + i, recv_bytes - i);
519 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
520 intel_aux_display_runtime_put(dev_priv);
525 /* Write data to the aux channel in native mode */
527 intel_dp_aux_native_write(struct intel_dp *intel_dp,
528 uint16_t address, uint8_t *send, int send_bytes)
535 if (WARN_ON(send_bytes > 16))
538 intel_dp_check_edp(intel_dp);
539 msg[0] = AUX_NATIVE_WRITE << 4;
540 msg[1] = address >> 8;
541 msg[2] = address & 0xff;
542 msg[3] = send_bytes - 1;
543 memcpy(&msg[4], send, send_bytes);
544 msg_bytes = send_bytes + 4;
546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
551 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
559 /* Write a single byte to the aux channel in native mode */
561 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
562 uint16_t address, uint8_t byte)
564 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
567 /* read bytes from a native aux channel */
569 intel_dp_aux_native_read(struct intel_dp *intel_dp,
570 uint16_t address, uint8_t *recv, int recv_bytes)
579 if (WARN_ON(recv_bytes > 19))
582 intel_dp_check_edp(intel_dp);
583 msg[0] = AUX_NATIVE_READ << 4;
584 msg[1] = address >> 8;
585 msg[2] = address & 0xff;
586 msg[3] = recv_bytes - 1;
589 reply_bytes = recv_bytes + 1;
592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
599 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
600 memcpy(recv, reply + 1, ret - 1);
603 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
611 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
612 uint8_t write_byte, uint8_t *read_byte)
614 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
615 struct intel_dp *intel_dp = container_of(adapter,
618 uint16_t address = algo_data->address;
626 intel_dp_check_edp(intel_dp);
627 /* Set up the command byte */
628 if (mode & MODE_I2C_READ)
629 msg[0] = AUX_I2C_READ << 4;
631 msg[0] = AUX_I2C_WRITE << 4;
633 if (!(mode & MODE_I2C_STOP))
634 msg[0] |= AUX_I2C_MOT << 4;
636 msg[1] = address >> 8;
658 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
659 * required to retry at least seven times upon receiving AUX_DEFER
660 * before giving up the AUX transaction.
662 for (retry = 0; retry < 7; retry++) {
663 ret = intel_dp_aux_ch(intel_dp,
667 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
671 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
672 case AUX_NATIVE_REPLY_ACK:
673 /* I2C-over-AUX Reply field is only valid
674 * when paired with AUX ACK.
677 case AUX_NATIVE_REPLY_NACK:
678 DRM_DEBUG_KMS("aux_ch native nack\n");
680 case AUX_NATIVE_REPLY_DEFER:
682 * For now, just give more slack to branch devices. We
683 * could check the DPCD for I2C bit rate capabilities,
684 * and if available, adjust the interval. We could also
685 * be more careful with DP-to-Legacy adapters where a
686 * long legacy cable may force very low I2C bit rates.
688 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
689 DP_DWN_STRM_PORT_PRESENT)
690 usleep_range(500, 600);
692 usleep_range(300, 400);
695 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
700 switch (reply[0] & AUX_I2C_REPLY_MASK) {
701 case AUX_I2C_REPLY_ACK:
702 if (mode == MODE_I2C_READ) {
703 *read_byte = reply[1];
705 return reply_bytes - 1;
706 case AUX_I2C_REPLY_NACK:
707 DRM_DEBUG_KMS("aux_i2c nack\n");
709 case AUX_I2C_REPLY_DEFER:
710 DRM_DEBUG_KMS("aux_i2c defer\n");
714 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
719 DRM_ERROR("too many retries, giving up\n");
724 intel_dp_i2c_init(struct intel_dp *intel_dp,
725 struct intel_connector *intel_connector, const char *name)
729 DRM_DEBUG_KMS("i2c_init %s\n", name);
730 intel_dp->algo.running = false;
731 intel_dp->algo.address = 0;
732 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
734 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
735 intel_dp->adapter.owner = THIS_MODULE;
736 intel_dp->adapter.class = I2C_CLASS_DDC;
737 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
738 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
739 intel_dp->adapter.algo_data = &intel_dp->algo;
740 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
742 ironlake_edp_panel_vdd_on(intel_dp);
743 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
744 ironlake_edp_panel_vdd_off(intel_dp, false);
749 intel_dp_set_clock(struct intel_encoder *encoder,
750 struct intel_crtc_config *pipe_config, int link_bw)
752 struct drm_device *dev = encoder->base.dev;
753 const struct dp_link_dpll *divisor = NULL;
758 count = ARRAY_SIZE(gen4_dpll);
759 } else if (IS_HASWELL(dev)) {
760 /* Haswell has special-purpose DP DDI clocks. */
761 } else if (HAS_PCH_SPLIT(dev)) {
763 count = ARRAY_SIZE(pch_dpll);
764 } else if (IS_VALLEYVIEW(dev)) {
766 count = ARRAY_SIZE(vlv_dpll);
769 if (divisor && count) {
770 for (i = 0; i < count; i++) {
771 if (link_bw == divisor[i].link_bw) {
772 pipe_config->dpll = divisor[i].dpll;
773 pipe_config->clock_set = true;
781 intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
784 struct drm_device *dev = encoder->base.dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
788 enum port port = dp_to_dig_port(intel_dp)->port;
789 struct intel_crtc *intel_crtc = encoder->new_crtc;
790 struct intel_connector *intel_connector = intel_dp->attached_connector;
791 int lane_count, clock;
792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
793 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
795 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
796 int link_avail, link_clock;
798 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
799 pipe_config->has_pch_encoder = true;
801 pipe_config->has_dp_encoder = true;
803 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
804 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
806 if (!HAS_PCH_SPLIT(dev))
807 intel_gmch_panel_fitting(intel_crtc, pipe_config,
808 intel_connector->panel.fitting_mode);
810 intel_pch_panel_fitting(intel_crtc, pipe_config,
811 intel_connector->panel.fitting_mode);
814 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
817 DRM_DEBUG_KMS("DP link computation with max lane count %i "
818 "max bw %02x pixel clock %iKHz\n",
819 max_lane_count, bws[max_clock],
820 adjusted_mode->crtc_clock);
822 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
824 bpp = pipe_config->pipe_bpp;
825 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
826 dev_priv->vbt.edp_bpp < bpp) {
827 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
828 dev_priv->vbt.edp_bpp);
829 bpp = dev_priv->vbt.edp_bpp;
832 for (; bpp >= 6*3; bpp -= 2*3) {
833 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
836 for (clock = 0; clock <= max_clock; clock++) {
837 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
838 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
839 link_avail = intel_dp_max_data_rate(link_clock,
842 if (mode_rate <= link_avail) {
852 if (intel_dp->color_range_auto) {
855 * CEA-861-E - 5.1 Default Encoding Parameters
856 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
858 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
859 intel_dp->color_range = DP_COLOR_RANGE_16_235;
861 intel_dp->color_range = 0;
864 if (intel_dp->color_range)
865 pipe_config->limited_color_range = true;
867 intel_dp->link_bw = bws[clock];
868 intel_dp->lane_count = lane_count;
869 pipe_config->pipe_bpp = bpp;
870 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
872 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
873 intel_dp->link_bw, intel_dp->lane_count,
874 pipe_config->port_clock, bpp);
875 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
876 mode_rate, link_avail);
878 intel_link_compute_m_n(bpp, lane_count,
879 adjusted_mode->crtc_clock,
880 pipe_config->port_clock,
881 &pipe_config->dp_m_n);
883 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
888 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
890 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
891 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
892 struct drm_device *dev = crtc->base.dev;
893 struct drm_i915_private *dev_priv = dev->dev_private;
896 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
897 dpa_ctl = I915_READ(DP_A);
898 dpa_ctl &= ~DP_PLL_FREQ_MASK;
900 if (crtc->config.port_clock == 162000) {
901 /* For a long time we've carried around a ILK-DevA w/a for the
902 * 160MHz clock. If we're really unlucky, it's still required.
904 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
905 dpa_ctl |= DP_PLL_FREQ_160MHZ;
906 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
908 dpa_ctl |= DP_PLL_FREQ_270MHZ;
909 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
912 I915_WRITE(DP_A, dpa_ctl);
918 static void intel_dp_mode_set(struct intel_encoder *encoder)
920 struct drm_device *dev = encoder->base.dev;
921 struct drm_i915_private *dev_priv = dev->dev_private;
922 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
923 enum port port = dp_to_dig_port(intel_dp)->port;
924 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
925 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
928 * There are four kinds of DP registers:
935 * IBX PCH and CPU are the same for almost everything,
936 * except that the CPU DP PLL is configured in this
939 * CPT PCH is quite different, having many bits moved
940 * to the TRANS_DP_CTL register instead. That
941 * configuration happens (oddly) in ironlake_pch_enable
944 /* Preserve the BIOS-computed detected bit. This is
945 * supposed to be read-only.
947 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
949 /* Handle DP bits in common between all three register formats */
950 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
951 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
953 if (intel_dp->has_audio) {
954 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
955 pipe_name(crtc->pipe));
956 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
957 intel_write_eld(&encoder->base, adjusted_mode);
960 /* Split out the IBX/CPU vs CPT settings */
962 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
963 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
964 intel_dp->DP |= DP_SYNC_HS_HIGH;
965 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
966 intel_dp->DP |= DP_SYNC_VS_HIGH;
967 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
969 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
970 intel_dp->DP |= DP_ENHANCED_FRAMING;
972 intel_dp->DP |= crtc->pipe << 29;
973 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
974 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
975 intel_dp->DP |= intel_dp->color_range;
977 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
978 intel_dp->DP |= DP_SYNC_HS_HIGH;
979 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
980 intel_dp->DP |= DP_SYNC_VS_HIGH;
981 intel_dp->DP |= DP_LINK_TRAIN_OFF;
983 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
984 intel_dp->DP |= DP_ENHANCED_FRAMING;
987 intel_dp->DP |= DP_PIPEB_SELECT;
989 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
992 if (port == PORT_A && !IS_VALLEYVIEW(dev))
993 ironlake_set_pll_cpu_edp(intel_dp);
996 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
997 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
999 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1000 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1002 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1003 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1005 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1009 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 pp_stat_reg, pp_ctrl_reg;
1013 pp_stat_reg = _pp_stat_reg(intel_dp);
1014 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1016 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1018 I915_READ(pp_stat_reg),
1019 I915_READ(pp_ctrl_reg));
1021 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1022 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1023 I915_READ(pp_stat_reg),
1024 I915_READ(pp_ctrl_reg));
1028 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1030 DRM_DEBUG_KMS("Wait for panel power on\n");
1031 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1034 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1036 DRM_DEBUG_KMS("Wait for panel power off time\n");
1037 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1040 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1042 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1043 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1047 /* Read the current pp_control value, unlocking the register if it
1051 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1053 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1057 control = I915_READ(_pp_ctrl_reg(intel_dp));
1058 control &= ~PANEL_UNLOCK_MASK;
1059 control |= PANEL_UNLOCK_REGS;
1063 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1065 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1068 u32 pp_stat_reg, pp_ctrl_reg;
1070 if (!is_edp(intel_dp))
1072 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1074 WARN(intel_dp->want_panel_vdd,
1075 "eDP VDD already requested on\n");
1077 intel_dp->want_panel_vdd = true;
1079 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1080 DRM_DEBUG_KMS("eDP VDD already on\n");
1084 if (!ironlake_edp_have_panel_power(intel_dp))
1085 ironlake_wait_panel_power_cycle(intel_dp);
1087 pp = ironlake_get_pp_control(intel_dp);
1088 pp |= EDP_FORCE_VDD;
1090 pp_stat_reg = _pp_stat_reg(intel_dp);
1091 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1093 I915_WRITE(pp_ctrl_reg, pp);
1094 POSTING_READ(pp_ctrl_reg);
1095 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1096 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1098 * If the panel wasn't on, delay before accessing aux channel
1100 if (!ironlake_edp_have_panel_power(intel_dp)) {
1101 DRM_DEBUG_KMS("eDP was not running\n");
1102 msleep(intel_dp->panel_power_up_delay);
1106 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1108 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1109 struct drm_i915_private *dev_priv = dev->dev_private;
1111 u32 pp_stat_reg, pp_ctrl_reg;
1113 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1115 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1116 pp = ironlake_get_pp_control(intel_dp);
1117 pp &= ~EDP_FORCE_VDD;
1119 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1120 pp_ctrl_reg = _pp_stat_reg(intel_dp);
1122 I915_WRITE(pp_ctrl_reg, pp);
1123 POSTING_READ(pp_ctrl_reg);
1125 /* Make sure sequencer is idle before allowing subsequent activity */
1126 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1127 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1128 msleep(intel_dp->panel_power_down_delay);
1132 static void ironlake_panel_vdd_work(struct work_struct *__work)
1134 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1135 struct intel_dp, panel_vdd_work);
1136 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1138 mutex_lock(&dev->mode_config.mutex);
1139 ironlake_panel_vdd_off_sync(intel_dp);
1140 mutex_unlock(&dev->mode_config.mutex);
1143 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1145 if (!is_edp(intel_dp))
1148 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1149 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1151 intel_dp->want_panel_vdd = false;
1154 ironlake_panel_vdd_off_sync(intel_dp);
1157 * Queue the timer to fire a long
1158 * time from now (relative to the power down delay)
1159 * to keep the panel power up across a sequence of operations
1161 schedule_delayed_work(&intel_dp->panel_vdd_work,
1162 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1166 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1173 if (!is_edp(intel_dp))
1176 DRM_DEBUG_KMS("Turn eDP power on\n");
1178 if (ironlake_edp_have_panel_power(intel_dp)) {
1179 DRM_DEBUG_KMS("eDP power already on\n");
1183 ironlake_wait_panel_power_cycle(intel_dp);
1185 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1186 pp = ironlake_get_pp_control(intel_dp);
1188 /* ILK workaround: disable reset around power sequence */
1189 pp &= ~PANEL_POWER_RESET;
1190 I915_WRITE(pp_ctrl_reg, pp);
1191 POSTING_READ(pp_ctrl_reg);
1194 pp |= POWER_TARGET_ON;
1196 pp |= PANEL_POWER_RESET;
1198 I915_WRITE(pp_ctrl_reg, pp);
1199 POSTING_READ(pp_ctrl_reg);
1201 ironlake_wait_panel_on(intel_dp);
1204 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1205 I915_WRITE(pp_ctrl_reg, pp);
1206 POSTING_READ(pp_ctrl_reg);
1210 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1212 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1217 if (!is_edp(intel_dp))
1220 DRM_DEBUG_KMS("Turn eDP power off\n");
1222 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1224 pp = ironlake_get_pp_control(intel_dp);
1225 /* We need to switch off panel power _and_ force vdd, for otherwise some
1226 * panels get very unhappy and cease to work. */
1227 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1229 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1231 I915_WRITE(pp_ctrl_reg, pp);
1232 POSTING_READ(pp_ctrl_reg);
1234 intel_dp->want_panel_vdd = false;
1236 ironlake_wait_panel_off(intel_dp);
1239 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1241 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1242 struct drm_device *dev = intel_dig_port->base.base.dev;
1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1248 if (!is_edp(intel_dp))
1251 DRM_DEBUG_KMS("\n");
1253 * If we enable the backlight right away following a panel power
1254 * on, we may see slight flicker as the panel syncs with the eDP
1255 * link. So delay a bit to make sure the image is solid before
1256 * allowing it to appear.
1258 msleep(intel_dp->backlight_on_delay);
1259 pp = ironlake_get_pp_control(intel_dp);
1260 pp |= EDP_BLC_ENABLE;
1262 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1264 I915_WRITE(pp_ctrl_reg, pp);
1265 POSTING_READ(pp_ctrl_reg);
1267 intel_panel_enable_backlight(dev, pipe);
1270 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1273 struct drm_i915_private *dev_priv = dev->dev_private;
1277 if (!is_edp(intel_dp))
1280 intel_panel_disable_backlight(dev);
1282 DRM_DEBUG_KMS("\n");
1283 pp = ironlake_get_pp_control(intel_dp);
1284 pp &= ~EDP_BLC_ENABLE;
1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1288 I915_WRITE(pp_ctrl_reg, pp);
1289 POSTING_READ(pp_ctrl_reg);
1290 msleep(intel_dp->backlight_off_delay);
1293 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1296 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1297 struct drm_device *dev = crtc->dev;
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1301 assert_pipe_disabled(dev_priv,
1302 to_intel_crtc(crtc)->pipe);
1304 DRM_DEBUG_KMS("\n");
1305 dpa_ctl = I915_READ(DP_A);
1306 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1307 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1309 /* We don't adjust intel_dp->DP while tearing down the link, to
1310 * facilitate link retraining (e.g. after hotplug). Hence clear all
1311 * enable bits here to ensure that we don't enable too much. */
1312 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1313 intel_dp->DP |= DP_PLL_ENABLE;
1314 I915_WRITE(DP_A, intel_dp->DP);
1319 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1321 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1322 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1323 struct drm_device *dev = crtc->dev;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1327 assert_pipe_disabled(dev_priv,
1328 to_intel_crtc(crtc)->pipe);
1330 dpa_ctl = I915_READ(DP_A);
1331 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1332 "dp pll off, should be on\n");
1333 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1335 /* We can't rely on the value tracked for the DP register in
1336 * intel_dp->DP because link_down must not change that (otherwise link
1337 * re-training will fail. */
1338 dpa_ctl &= ~DP_PLL_ENABLE;
1339 I915_WRITE(DP_A, dpa_ctl);
1344 /* If the sink supports it, try to set the power state appropriately */
1345 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1349 /* Should have a valid DPCD by this point */
1350 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1353 if (mode != DRM_MODE_DPMS_ON) {
1354 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1357 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1360 * When turning on, we need to retry for 1ms to give the sink
1363 for (i = 0; i < 3; i++) {
1364 ret = intel_dp_aux_native_write_1(intel_dp,
1374 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1377 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1378 enum port port = dp_to_dig_port(intel_dp)->port;
1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 u32 tmp = I915_READ(intel_dp->output_reg);
1383 if (!(tmp & DP_PORT_EN))
1386 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1387 *pipe = PORT_TO_PIPE_CPT(tmp);
1388 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1389 *pipe = PORT_TO_PIPE(tmp);
1395 switch (intel_dp->output_reg) {
1397 trans_sel = TRANS_DP_PORT_SEL_B;
1400 trans_sel = TRANS_DP_PORT_SEL_C;
1403 trans_sel = TRANS_DP_PORT_SEL_D;
1410 trans_dp = I915_READ(TRANS_DP_CTL(i));
1411 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1417 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1418 intel_dp->output_reg);
1424 static void intel_dp_get_config(struct intel_encoder *encoder,
1425 struct intel_crtc_config *pipe_config)
1427 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1429 struct drm_device *dev = encoder->base.dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 enum port port = dp_to_dig_port(intel_dp)->port;
1432 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1435 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1436 tmp = I915_READ(intel_dp->output_reg);
1437 if (tmp & DP_SYNC_HS_HIGH)
1438 flags |= DRM_MODE_FLAG_PHSYNC;
1440 flags |= DRM_MODE_FLAG_NHSYNC;
1442 if (tmp & DP_SYNC_VS_HIGH)
1443 flags |= DRM_MODE_FLAG_PVSYNC;
1445 flags |= DRM_MODE_FLAG_NVSYNC;
1447 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1448 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1449 flags |= DRM_MODE_FLAG_PHSYNC;
1451 flags |= DRM_MODE_FLAG_NHSYNC;
1453 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1454 flags |= DRM_MODE_FLAG_PVSYNC;
1456 flags |= DRM_MODE_FLAG_NVSYNC;
1459 pipe_config->adjusted_mode.flags |= flags;
1461 pipe_config->has_dp_encoder = true;
1463 intel_dp_get_m_n(crtc, pipe_config);
1465 if (port == PORT_A) {
1466 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1467 pipe_config->port_clock = 162000;
1469 pipe_config->port_clock = 270000;
1472 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1473 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1475 * This is a big fat ugly hack.
1477 * Some machines in UEFI boot mode provide us a VBT that has 18
1478 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1479 * unknown we fail to light up. Yet the same BIOS boots up with
1480 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1481 * max, not what it tells us to use.
1483 * Note: This will still be broken if the eDP panel is not lit
1484 * up by the BIOS, and thus we can't get the mode at module
1487 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1488 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1489 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1492 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1493 &pipe_config->dp_m_n);
1495 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1496 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1498 pipe_config->adjusted_mode.crtc_clock = dotclock;
1501 static bool is_edp_psr(struct drm_device *dev)
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1505 return dev_priv->psr.sink_support;
1508 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1515 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1518 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1519 struct edp_vsc_psr *vsc_psr)
1521 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1522 struct drm_device *dev = dig_port->base.base.dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1525 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1526 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1527 uint32_t *data = (uint32_t *) vsc_psr;
1530 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1531 the video DIP being updated before program video DIP data buffer
1532 registers for DIP being updated. */
1533 I915_WRITE(ctl_reg, 0);
1534 POSTING_READ(ctl_reg);
1536 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1537 if (i < sizeof(struct edp_vsc_psr))
1538 I915_WRITE(data_reg + i, *data++);
1540 I915_WRITE(data_reg + i, 0);
1543 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1544 POSTING_READ(ctl_reg);
1547 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1549 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 struct edp_vsc_psr psr_vsc;
1553 if (intel_dp->psr_setup_done)
1556 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1557 memset(&psr_vsc, 0, sizeof(psr_vsc));
1558 psr_vsc.sdp_header.HB0 = 0;
1559 psr_vsc.sdp_header.HB1 = 0x7;
1560 psr_vsc.sdp_header.HB2 = 0x2;
1561 psr_vsc.sdp_header.HB3 = 0x8;
1562 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1564 /* Avoid continuous PSR exit by masking memup and hpd */
1565 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1566 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1568 intel_dp->psr_setup_done = true;
1571 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1573 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1576 int precharge = 0x3;
1577 int msg_size = 5; /* Header(4) + Message(1) */
1579 /* Enable PSR in sink */
1580 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1581 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1583 ~DP_PSR_MAIN_LINK_ACTIVE);
1585 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1587 DP_PSR_MAIN_LINK_ACTIVE);
1589 /* Setup AUX registers */
1590 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1591 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1592 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1593 DP_AUX_CH_CTL_TIME_OUT_400us |
1594 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1595 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1596 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1599 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1601 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 uint32_t max_sleep_time = 0x1f;
1604 uint32_t idle_frames = 1;
1607 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1608 val |= EDP_PSR_LINK_STANDBY;
1609 val |= EDP_PSR_TP2_TP3_TIME_0us;
1610 val |= EDP_PSR_TP1_TIME_0us;
1611 val |= EDP_PSR_SKIP_AUX_EXIT;
1613 val |= EDP_PSR_LINK_DISABLE;
1615 I915_WRITE(EDP_PSR_CTL(dev), val |
1616 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1617 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1618 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1622 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1624 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1625 struct drm_device *dev = dig_port->base.base.dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 struct drm_crtc *crtc = dig_port->base.base.crtc;
1628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1629 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1630 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1632 dev_priv->psr.source_ok = false;
1634 if (!HAS_PSR(dev)) {
1635 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1639 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1640 (dig_port->port != PORT_A)) {
1641 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1645 if (!i915_enable_psr) {
1646 DRM_DEBUG_KMS("PSR disable by flag\n");
1650 crtc = dig_port->base.base.crtc;
1652 DRM_DEBUG_KMS("crtc not active for PSR\n");
1656 intel_crtc = to_intel_crtc(crtc);
1657 if (!intel_crtc_active(crtc)) {
1658 DRM_DEBUG_KMS("crtc not active for PSR\n");
1662 obj = to_intel_framebuffer(crtc->fb)->obj;
1663 if (obj->tiling_mode != I915_TILING_X ||
1664 obj->fence_reg == I915_FENCE_REG_NONE) {
1665 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1669 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1670 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1674 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1676 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1680 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1681 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1685 dev_priv->psr.source_ok = true;
1689 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1691 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1693 if (!intel_edp_psr_match_conditions(intel_dp) ||
1694 intel_edp_is_psr_enabled(dev))
1697 /* Setup PSR once */
1698 intel_edp_psr_setup(intel_dp);
1700 /* Enable PSR on the panel */
1701 intel_edp_psr_enable_sink(intel_dp);
1703 /* Enable PSR on the host */
1704 intel_edp_psr_enable_source(intel_dp);
1707 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1709 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1711 if (intel_edp_psr_match_conditions(intel_dp) &&
1712 !intel_edp_is_psr_enabled(dev))
1713 intel_edp_psr_do_enable(intel_dp);
1716 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1721 if (!intel_edp_is_psr_enabled(dev))
1724 I915_WRITE(EDP_PSR_CTL(dev),
1725 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1727 /* Wait till PSR is idle */
1728 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1729 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1730 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1733 void intel_edp_psr_update(struct drm_device *dev)
1735 struct intel_encoder *encoder;
1736 struct intel_dp *intel_dp = NULL;
1738 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1739 if (encoder->type == INTEL_OUTPUT_EDP) {
1740 intel_dp = enc_to_intel_dp(&encoder->base);
1742 if (!is_edp_psr(dev))
1745 if (!intel_edp_psr_match_conditions(intel_dp))
1746 intel_edp_psr_disable(intel_dp);
1748 if (!intel_edp_is_psr_enabled(dev))
1749 intel_edp_psr_do_enable(intel_dp);
1753 static void intel_disable_dp(struct intel_encoder *encoder)
1755 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1756 enum port port = dp_to_dig_port(intel_dp)->port;
1757 struct drm_device *dev = encoder->base.dev;
1759 /* Make sure the panel is off before trying to change the mode. But also
1760 * ensure that we have vdd while we switch off the panel. */
1761 ironlake_edp_panel_vdd_on(intel_dp);
1762 ironlake_edp_backlight_off(intel_dp);
1763 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1764 ironlake_edp_panel_off(intel_dp);
1766 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1767 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1768 intel_dp_link_down(intel_dp);
1771 static void intel_post_disable_dp(struct intel_encoder *encoder)
1773 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1774 enum port port = dp_to_dig_port(intel_dp)->port;
1775 struct drm_device *dev = encoder->base.dev;
1777 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1778 intel_dp_link_down(intel_dp);
1779 if (!IS_VALLEYVIEW(dev))
1780 ironlake_edp_pll_off(intel_dp);
1784 static void intel_enable_dp(struct intel_encoder *encoder)
1786 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1787 struct drm_device *dev = encoder->base.dev;
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1791 if (WARN_ON(dp_reg & DP_PORT_EN))
1794 ironlake_edp_panel_vdd_on(intel_dp);
1795 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1796 intel_dp_start_link_train(intel_dp);
1797 ironlake_edp_panel_on(intel_dp);
1798 ironlake_edp_panel_vdd_off(intel_dp, true);
1799 intel_dp_complete_link_train(intel_dp);
1800 intel_dp_stop_link_train(intel_dp);
1803 static void g4x_enable_dp(struct intel_encoder *encoder)
1805 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1807 intel_enable_dp(encoder);
1808 ironlake_edp_backlight_on(intel_dp);
1811 static void vlv_enable_dp(struct intel_encoder *encoder)
1813 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815 ironlake_edp_backlight_on(intel_dp);
1818 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1820 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1821 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1823 if (dport->port == PORT_A)
1824 ironlake_edp_pll_on(intel_dp);
1827 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1829 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1830 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1831 struct drm_device *dev = encoder->base.dev;
1832 struct drm_i915_private *dev_priv = dev->dev_private;
1833 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1834 int port = vlv_dport_to_channel(dport);
1835 int pipe = intel_crtc->pipe;
1836 struct edp_power_seq power_seq;
1839 mutex_lock(&dev_priv->dpio_lock);
1841 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
1848 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1849 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1850 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1852 mutex_unlock(&dev_priv->dpio_lock);
1854 /* init power sequencer on this pipe and port */
1855 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1856 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1859 intel_enable_dp(encoder);
1861 vlv_wait_port_ready(dev_priv, port);
1864 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1866 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1867 struct drm_device *dev = encoder->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_crtc *intel_crtc =
1870 to_intel_crtc(encoder->base.crtc);
1871 int port = vlv_dport_to_channel(dport);
1872 int pipe = intel_crtc->pipe;
1874 /* Program Tx lane resets to default */
1875 mutex_lock(&dev_priv->dpio_lock);
1876 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
1877 DPIO_PCS_TX_LANE2_RESET |
1878 DPIO_PCS_TX_LANE1_RESET);
1879 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
1880 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1881 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1882 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1883 DPIO_PCS_CLK_SOFT_RESET);
1885 /* Fix up inter-pair skew failure */
1886 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1887 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1888 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
1889 mutex_unlock(&dev_priv->dpio_lock);
1893 * Native read with retry for link status and receiver capability reads for
1894 * cases where the sink may still be asleep.
1897 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1898 uint8_t *recv, int recv_bytes)
1903 * Sinks are *supposed* to come up within 1ms from an off state,
1904 * but we're also supposed to retry 3 times per the spec.
1906 for (i = 0; i < 3; i++) {
1907 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1909 if (ret == recv_bytes)
1918 * Fetch AUX CH registers 0x202 - 0x207 which contain
1919 * link status information
1922 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1924 return intel_dp_aux_native_read_retry(intel_dp,
1927 DP_LINK_STATUS_SIZE);
1931 static char *voltage_names[] = {
1932 "0.4V", "0.6V", "0.8V", "1.2V"
1934 static char *pre_emph_names[] = {
1935 "0dB", "3.5dB", "6dB", "9.5dB"
1937 static char *link_train_names[] = {
1938 "pattern 1", "pattern 2", "idle", "off"
1943 * These are source-specific values; current Intel hardware supports
1944 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1948 intel_dp_voltage_max(struct intel_dp *intel_dp)
1950 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1951 enum port port = dp_to_dig_port(intel_dp)->port;
1953 if (IS_VALLEYVIEW(dev))
1954 return DP_TRAIN_VOLTAGE_SWING_1200;
1955 else if (IS_GEN7(dev) && port == PORT_A)
1956 return DP_TRAIN_VOLTAGE_SWING_800;
1957 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1958 return DP_TRAIN_VOLTAGE_SWING_1200;
1960 return DP_TRAIN_VOLTAGE_SWING_800;
1964 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1966 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1967 enum port port = dp_to_dig_port(intel_dp)->port;
1970 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1971 case DP_TRAIN_VOLTAGE_SWING_400:
1972 return DP_TRAIN_PRE_EMPHASIS_9_5;
1973 case DP_TRAIN_VOLTAGE_SWING_600:
1974 return DP_TRAIN_PRE_EMPHASIS_6;
1975 case DP_TRAIN_VOLTAGE_SWING_800:
1976 return DP_TRAIN_PRE_EMPHASIS_3_5;
1977 case DP_TRAIN_VOLTAGE_SWING_1200:
1979 return DP_TRAIN_PRE_EMPHASIS_0;
1981 } else if (IS_VALLEYVIEW(dev)) {
1982 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1983 case DP_TRAIN_VOLTAGE_SWING_400:
1984 return DP_TRAIN_PRE_EMPHASIS_9_5;
1985 case DP_TRAIN_VOLTAGE_SWING_600:
1986 return DP_TRAIN_PRE_EMPHASIS_6;
1987 case DP_TRAIN_VOLTAGE_SWING_800:
1988 return DP_TRAIN_PRE_EMPHASIS_3_5;
1989 case DP_TRAIN_VOLTAGE_SWING_1200:
1991 return DP_TRAIN_PRE_EMPHASIS_0;
1993 } else if (IS_GEN7(dev) && port == PORT_A) {
1994 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1995 case DP_TRAIN_VOLTAGE_SWING_400:
1996 return DP_TRAIN_PRE_EMPHASIS_6;
1997 case DP_TRAIN_VOLTAGE_SWING_600:
1998 case DP_TRAIN_VOLTAGE_SWING_800:
1999 return DP_TRAIN_PRE_EMPHASIS_3_5;
2001 return DP_TRAIN_PRE_EMPHASIS_0;
2004 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2005 case DP_TRAIN_VOLTAGE_SWING_400:
2006 return DP_TRAIN_PRE_EMPHASIS_6;
2007 case DP_TRAIN_VOLTAGE_SWING_600:
2008 return DP_TRAIN_PRE_EMPHASIS_6;
2009 case DP_TRAIN_VOLTAGE_SWING_800:
2010 return DP_TRAIN_PRE_EMPHASIS_3_5;
2011 case DP_TRAIN_VOLTAGE_SWING_1200:
2013 return DP_TRAIN_PRE_EMPHASIS_0;
2018 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2023 struct intel_crtc *intel_crtc =
2024 to_intel_crtc(dport->base.base.crtc);
2025 unsigned long demph_reg_value, preemph_reg_value,
2026 uniqtranscale_reg_value;
2027 uint8_t train_set = intel_dp->train_set[0];
2028 int port = vlv_dport_to_channel(dport);
2029 int pipe = intel_crtc->pipe;
2031 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2032 case DP_TRAIN_PRE_EMPHASIS_0:
2033 preemph_reg_value = 0x0004000;
2034 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2035 case DP_TRAIN_VOLTAGE_SWING_400:
2036 demph_reg_value = 0x2B405555;
2037 uniqtranscale_reg_value = 0x552AB83A;
2039 case DP_TRAIN_VOLTAGE_SWING_600:
2040 demph_reg_value = 0x2B404040;
2041 uniqtranscale_reg_value = 0x5548B83A;
2043 case DP_TRAIN_VOLTAGE_SWING_800:
2044 demph_reg_value = 0x2B245555;
2045 uniqtranscale_reg_value = 0x5560B83A;
2047 case DP_TRAIN_VOLTAGE_SWING_1200:
2048 demph_reg_value = 0x2B405555;
2049 uniqtranscale_reg_value = 0x5598DA3A;
2055 case DP_TRAIN_PRE_EMPHASIS_3_5:
2056 preemph_reg_value = 0x0002000;
2057 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2058 case DP_TRAIN_VOLTAGE_SWING_400:
2059 demph_reg_value = 0x2B404040;
2060 uniqtranscale_reg_value = 0x5552B83A;
2062 case DP_TRAIN_VOLTAGE_SWING_600:
2063 demph_reg_value = 0x2B404848;
2064 uniqtranscale_reg_value = 0x5580B83A;
2066 case DP_TRAIN_VOLTAGE_SWING_800:
2067 demph_reg_value = 0x2B404040;
2068 uniqtranscale_reg_value = 0x55ADDA3A;
2074 case DP_TRAIN_PRE_EMPHASIS_6:
2075 preemph_reg_value = 0x0000000;
2076 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2077 case DP_TRAIN_VOLTAGE_SWING_400:
2078 demph_reg_value = 0x2B305555;
2079 uniqtranscale_reg_value = 0x5570B83A;
2081 case DP_TRAIN_VOLTAGE_SWING_600:
2082 demph_reg_value = 0x2B2B4040;
2083 uniqtranscale_reg_value = 0x55ADDA3A;
2089 case DP_TRAIN_PRE_EMPHASIS_9_5:
2090 preemph_reg_value = 0x0006000;
2091 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2092 case DP_TRAIN_VOLTAGE_SWING_400:
2093 demph_reg_value = 0x1B405555;
2094 uniqtranscale_reg_value = 0x55ADDA3A;
2104 mutex_lock(&dev_priv->dpio_lock);
2105 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2106 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2107 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
2108 uniqtranscale_reg_value);
2109 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2110 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2111 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2112 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
2113 mutex_unlock(&dev_priv->dpio_lock);
2119 intel_get_adjust_train(struct intel_dp *intel_dp,
2120 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2125 uint8_t voltage_max;
2126 uint8_t preemph_max;
2128 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2129 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2130 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2138 voltage_max = intel_dp_voltage_max(intel_dp);
2139 if (v >= voltage_max)
2140 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2142 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2143 if (p >= preemph_max)
2144 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2146 for (lane = 0; lane < 4; lane++)
2147 intel_dp->train_set[lane] = v | p;
2151 intel_gen4_signal_levels(uint8_t train_set)
2153 uint32_t signal_levels = 0;
2155 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2156 case DP_TRAIN_VOLTAGE_SWING_400:
2158 signal_levels |= DP_VOLTAGE_0_4;
2160 case DP_TRAIN_VOLTAGE_SWING_600:
2161 signal_levels |= DP_VOLTAGE_0_6;
2163 case DP_TRAIN_VOLTAGE_SWING_800:
2164 signal_levels |= DP_VOLTAGE_0_8;
2166 case DP_TRAIN_VOLTAGE_SWING_1200:
2167 signal_levels |= DP_VOLTAGE_1_2;
2170 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2171 case DP_TRAIN_PRE_EMPHASIS_0:
2173 signal_levels |= DP_PRE_EMPHASIS_0;
2175 case DP_TRAIN_PRE_EMPHASIS_3_5:
2176 signal_levels |= DP_PRE_EMPHASIS_3_5;
2178 case DP_TRAIN_PRE_EMPHASIS_6:
2179 signal_levels |= DP_PRE_EMPHASIS_6;
2181 case DP_TRAIN_PRE_EMPHASIS_9_5:
2182 signal_levels |= DP_PRE_EMPHASIS_9_5;
2185 return signal_levels;
2188 /* Gen6's DP voltage swing and pre-emphasis control */
2190 intel_gen6_edp_signal_levels(uint8_t train_set)
2192 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2193 DP_TRAIN_PRE_EMPHASIS_MASK);
2194 switch (signal_levels) {
2195 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2196 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2197 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2198 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2199 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2200 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2201 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2202 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2203 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2204 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2205 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2206 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2207 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2208 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2210 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2211 "0x%x\n", signal_levels);
2212 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2216 /* Gen7's DP voltage swing and pre-emphasis control */
2218 intel_gen7_edp_signal_levels(uint8_t train_set)
2220 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2221 DP_TRAIN_PRE_EMPHASIS_MASK);
2222 switch (signal_levels) {
2223 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2224 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2225 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2226 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2227 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2228 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2230 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2231 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2232 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2233 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2235 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2236 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2237 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2238 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2241 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2242 "0x%x\n", signal_levels);
2243 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2247 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2249 intel_hsw_signal_levels(uint8_t train_set)
2251 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2252 DP_TRAIN_PRE_EMPHASIS_MASK);
2253 switch (signal_levels) {
2254 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2255 return DDI_BUF_EMP_400MV_0DB_HSW;
2256 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2257 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2258 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2259 return DDI_BUF_EMP_400MV_6DB_HSW;
2260 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2261 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2263 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2264 return DDI_BUF_EMP_600MV_0DB_HSW;
2265 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2266 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2267 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2268 return DDI_BUF_EMP_600MV_6DB_HSW;
2270 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2271 return DDI_BUF_EMP_800MV_0DB_HSW;
2272 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2273 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2275 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2276 "0x%x\n", signal_levels);
2277 return DDI_BUF_EMP_400MV_0DB_HSW;
2281 /* Properly updates "DP" with the correct signal levels. */
2283 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2286 enum port port = intel_dig_port->port;
2287 struct drm_device *dev = intel_dig_port->base.base.dev;
2288 uint32_t signal_levels, mask;
2289 uint8_t train_set = intel_dp->train_set[0];
2292 signal_levels = intel_hsw_signal_levels(train_set);
2293 mask = DDI_BUF_EMP_MASK;
2294 } else if (IS_VALLEYVIEW(dev)) {
2295 signal_levels = intel_vlv_signal_levels(intel_dp);
2297 } else if (IS_GEN7(dev) && port == PORT_A) {
2298 signal_levels = intel_gen7_edp_signal_levels(train_set);
2299 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2300 } else if (IS_GEN6(dev) && port == PORT_A) {
2301 signal_levels = intel_gen6_edp_signal_levels(train_set);
2302 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2304 signal_levels = intel_gen4_signal_levels(train_set);
2305 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2308 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2310 *DP = (*DP & ~mask) | signal_levels;
2314 intel_dp_set_link_train(struct intel_dp *intel_dp,
2316 uint8_t dp_train_pat)
2318 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2319 struct drm_device *dev = intel_dig_port->base.base.dev;
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2321 enum port port = intel_dig_port->port;
2322 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2326 uint32_t temp = I915_READ(DP_TP_CTL(port));
2328 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2329 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2331 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2333 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2334 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2335 case DP_TRAINING_PATTERN_DISABLE:
2336 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2339 case DP_TRAINING_PATTERN_1:
2340 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2342 case DP_TRAINING_PATTERN_2:
2343 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2345 case DP_TRAINING_PATTERN_3:
2346 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2349 I915_WRITE(DP_TP_CTL(port), temp);
2351 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2352 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2354 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2355 case DP_TRAINING_PATTERN_DISABLE:
2356 *DP |= DP_LINK_TRAIN_OFF_CPT;
2358 case DP_TRAINING_PATTERN_1:
2359 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2361 case DP_TRAINING_PATTERN_2:
2362 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2364 case DP_TRAINING_PATTERN_3:
2365 DRM_ERROR("DP training pattern 3 not supported\n");
2366 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2371 *DP &= ~DP_LINK_TRAIN_MASK;
2373 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2374 case DP_TRAINING_PATTERN_DISABLE:
2375 *DP |= DP_LINK_TRAIN_OFF;
2377 case DP_TRAINING_PATTERN_1:
2378 *DP |= DP_LINK_TRAIN_PAT_1;
2380 case DP_TRAINING_PATTERN_2:
2381 *DP |= DP_LINK_TRAIN_PAT_2;
2383 case DP_TRAINING_PATTERN_3:
2384 DRM_ERROR("DP training pattern 3 not supported\n");
2385 *DP |= DP_LINK_TRAIN_PAT_2;
2390 I915_WRITE(intel_dp->output_reg, *DP);
2391 POSTING_READ(intel_dp->output_reg);
2393 buf[0] = dp_train_pat;
2394 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2395 DP_TRAINING_PATTERN_DISABLE) {
2396 /* don't write DP_TRAINING_LANEx_SET on disable */
2399 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2400 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2401 len = intel_dp->lane_count + 1;
2404 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2411 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2412 uint8_t dp_train_pat)
2414 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2415 intel_dp_set_signal_levels(intel_dp, DP);
2416 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2420 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2421 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2424 struct drm_device *dev = intel_dig_port->base.base.dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2428 intel_get_adjust_train(intel_dp, link_status);
2429 intel_dp_set_signal_levels(intel_dp, DP);
2431 I915_WRITE(intel_dp->output_reg, *DP);
2432 POSTING_READ(intel_dp->output_reg);
2434 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2435 intel_dp->train_set,
2436 intel_dp->lane_count);
2438 return ret == intel_dp->lane_count;
2441 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2444 struct drm_device *dev = intel_dig_port->base.base.dev;
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2446 enum port port = intel_dig_port->port;
2452 val = I915_READ(DP_TP_CTL(port));
2453 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2454 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2455 I915_WRITE(DP_TP_CTL(port), val);
2458 * On PORT_A we can have only eDP in SST mode. There the only reason
2459 * we need to set idle transmission mode is to work around a HW issue
2460 * where we enable the pipe while not in idle link-training mode.
2461 * In this case there is requirement to wait for a minimum number of
2462 * idle patterns to be sent.
2467 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2469 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2472 /* Enable corresponding port and start training pattern 1 */
2474 intel_dp_start_link_train(struct intel_dp *intel_dp)
2476 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2477 struct drm_device *dev = encoder->dev;
2480 int voltage_tries, loop_tries;
2481 uint32_t DP = intel_dp->DP;
2482 uint8_t link_config[2];
2485 intel_ddi_prepare_link_retrain(encoder);
2487 /* Write the link configuration data */
2488 link_config[0] = intel_dp->link_bw;
2489 link_config[1] = intel_dp->lane_count;
2490 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2491 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2492 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2495 link_config[1] = DP_SET_ANSI_8B10B;
2496 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2500 /* clock recovery */
2501 if (!intel_dp_reset_link_train(intel_dp, &DP,
2502 DP_TRAINING_PATTERN_1 |
2503 DP_LINK_SCRAMBLING_DISABLE)) {
2504 DRM_ERROR("failed to enable link training\n");
2512 uint8_t link_status[DP_LINK_STATUS_SIZE];
2514 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2515 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2516 DRM_ERROR("failed to get link status\n");
2520 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2521 DRM_DEBUG_KMS("clock recovery OK\n");
2525 /* Check to see if we've tried the max voltage */
2526 for (i = 0; i < intel_dp->lane_count; i++)
2527 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2529 if (i == intel_dp->lane_count) {
2531 if (loop_tries == 5) {
2532 DRM_ERROR("too many full retries, give up\n");
2535 intel_dp_reset_link_train(intel_dp, &DP,
2536 DP_TRAINING_PATTERN_1 |
2537 DP_LINK_SCRAMBLING_DISABLE);
2542 /* Check to see if we've tried the same voltage 5 times */
2543 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2545 if (voltage_tries == 5) {
2546 DRM_ERROR("too many voltage retries, give up\n");
2551 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2553 /* Update training set as requested by target */
2554 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2555 DRM_ERROR("failed to update link training\n");
2564 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2566 bool channel_eq = false;
2567 int tries, cr_tries;
2568 uint32_t DP = intel_dp->DP;
2570 /* channel equalization */
2571 if (!intel_dp_set_link_train(intel_dp, &DP,
2572 DP_TRAINING_PATTERN_2 |
2573 DP_LINK_SCRAMBLING_DISABLE)) {
2574 DRM_ERROR("failed to start channel equalization\n");
2582 uint8_t link_status[DP_LINK_STATUS_SIZE];
2585 DRM_ERROR("failed to train DP, aborting\n");
2586 intel_dp_link_down(intel_dp);
2590 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2591 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2592 DRM_ERROR("failed to get link status\n");
2596 /* Make sure clock is still ok */
2597 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2598 intel_dp_start_link_train(intel_dp);
2599 intel_dp_set_link_train(intel_dp, &DP,
2600 DP_TRAINING_PATTERN_2 |
2601 DP_LINK_SCRAMBLING_DISABLE);
2606 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2611 /* Try 5 times, then try clock recovery if that fails */
2613 intel_dp_link_down(intel_dp);
2614 intel_dp_start_link_train(intel_dp);
2615 intel_dp_set_link_train(intel_dp, &DP,
2616 DP_TRAINING_PATTERN_2 |
2617 DP_LINK_SCRAMBLING_DISABLE);
2623 /* Update training set as requested by target */
2624 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2625 DRM_ERROR("failed to update link training\n");
2631 intel_dp_set_idle_link_train(intel_dp);
2636 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2640 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2642 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2643 DP_TRAINING_PATTERN_DISABLE);
2647 intel_dp_link_down(struct intel_dp *intel_dp)
2649 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2650 enum port port = intel_dig_port->port;
2651 struct drm_device *dev = intel_dig_port->base.base.dev;
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 struct intel_crtc *intel_crtc =
2654 to_intel_crtc(intel_dig_port->base.base.crtc);
2655 uint32_t DP = intel_dp->DP;
2658 * DDI code has a strict mode set sequence and we should try to respect
2659 * it, otherwise we might hang the machine in many different ways. So we
2660 * really should be disabling the port only on a complete crtc_disable
2661 * sequence. This function is just called under two conditions on DDI
2663 * - Link train failed while doing crtc_enable, and on this case we
2664 * really should respect the mode set sequence and wait for a
2666 * - Someone turned the monitor off and intel_dp_check_link_status
2667 * called us. We don't need to disable the whole port on this case, so
2668 * when someone turns the monitor on again,
2669 * intel_ddi_prepare_link_retrain will take care of redoing the link
2675 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2678 DRM_DEBUG_KMS("\n");
2680 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2681 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2682 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2684 DP &= ~DP_LINK_TRAIN_MASK;
2685 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2687 POSTING_READ(intel_dp->output_reg);
2689 /* We don't really know why we're doing this */
2690 intel_wait_for_vblank(dev, intel_crtc->pipe);
2692 if (HAS_PCH_IBX(dev) &&
2693 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2694 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2696 /* Hardware workaround: leaving our transcoder select
2697 * set to transcoder B while it's off will prevent the
2698 * corresponding HDMI output on transcoder A.
2700 * Combine this with another hardware workaround:
2701 * transcoder select bit can only be cleared while the
2704 DP &= ~DP_PIPEB_SELECT;
2705 I915_WRITE(intel_dp->output_reg, DP);
2707 /* Changes to enable or select take place the vblank
2708 * after being written.
2710 if (WARN_ON(crtc == NULL)) {
2711 /* We should never try to disable a port without a crtc
2712 * attached. For paranoia keep the code around for a
2714 POSTING_READ(intel_dp->output_reg);
2717 intel_wait_for_vblank(dev, intel_crtc->pipe);
2720 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2721 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2722 POSTING_READ(intel_dp->output_reg);
2723 msleep(intel_dp->panel_power_down_delay);
2727 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2729 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2730 struct drm_device *dev = dig_port->base.base.dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2733 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2735 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2736 sizeof(intel_dp->dpcd)) == 0)
2737 return false; /* aux transfer failed */
2739 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2740 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2741 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2743 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2744 return false; /* DPCD not present */
2746 /* Check if the panel supports PSR */
2747 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2748 if (is_edp(intel_dp)) {
2749 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2751 sizeof(intel_dp->psr_dpcd));
2752 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2753 dev_priv->psr.sink_support = true;
2754 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2758 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2759 DP_DWN_STRM_PORT_PRESENT))
2760 return true; /* native DP sink */
2762 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2763 return true; /* no per-port downstream info */
2765 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2766 intel_dp->downstream_ports,
2767 DP_MAX_DOWNSTREAM_PORTS) == 0)
2768 return false; /* downstream port status fetch failed */
2774 intel_dp_probe_oui(struct intel_dp *intel_dp)
2778 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2781 ironlake_edp_panel_vdd_on(intel_dp);
2783 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2784 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2785 buf[0], buf[1], buf[2]);
2787 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2788 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2789 buf[0], buf[1], buf[2]);
2791 ironlake_edp_panel_vdd_off(intel_dp, false);
2795 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2799 ret = intel_dp_aux_native_read_retry(intel_dp,
2800 DP_DEVICE_SERVICE_IRQ_VECTOR,
2801 sink_irq_vector, 1);
2809 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2811 /* NAK by default */
2812 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2816 * According to DP spec
2819 * 2. Configure link according to Receiver Capabilities
2820 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2821 * 4. Check link status on receipt of hot-plug interrupt
2825 intel_dp_check_link_status(struct intel_dp *intel_dp)
2827 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2829 u8 link_status[DP_LINK_STATUS_SIZE];
2831 if (!intel_encoder->connectors_active)
2834 if (WARN_ON(!intel_encoder->base.crtc))
2837 /* Try to read receiver status if the link appears to be up */
2838 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2839 intel_dp_link_down(intel_dp);
2843 /* Now read the DPCD to see if it's actually running */
2844 if (!intel_dp_get_dpcd(intel_dp)) {
2845 intel_dp_link_down(intel_dp);
2849 /* Try to read the source of the interrupt */
2850 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2851 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2852 /* Clear interrupt source */
2853 intel_dp_aux_native_write_1(intel_dp,
2854 DP_DEVICE_SERVICE_IRQ_VECTOR,
2857 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2858 intel_dp_handle_test_request(intel_dp);
2859 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2860 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2863 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2864 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2865 drm_get_encoder_name(&intel_encoder->base));
2866 intel_dp_start_link_train(intel_dp);
2867 intel_dp_complete_link_train(intel_dp);
2868 intel_dp_stop_link_train(intel_dp);
2872 /* XXX this is probably wrong for multiple downstream ports */
2873 static enum drm_connector_status
2874 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2876 uint8_t *dpcd = intel_dp->dpcd;
2879 if (!intel_dp_get_dpcd(intel_dp))
2880 return connector_status_disconnected;
2882 /* if there's no downstream port, we're done */
2883 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2884 return connector_status_connected;
2886 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2887 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2888 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2890 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2892 return connector_status_unknown;
2893 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2894 : connector_status_disconnected;
2897 /* If no HPD, poke DDC gently */
2898 if (drm_probe_ddc(&intel_dp->adapter))
2899 return connector_status_connected;
2901 /* Well we tried, say unknown for unreliable port types */
2902 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2903 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2904 if (type == DP_DS_PORT_TYPE_VGA ||
2905 type == DP_DS_PORT_TYPE_NON_EDID)
2906 return connector_status_unknown;
2908 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2909 DP_DWN_STRM_PORT_TYPE_MASK;
2910 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2911 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2912 return connector_status_unknown;
2915 /* Anything else is out of spec, warn and ignore */
2916 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2917 return connector_status_disconnected;
2920 static enum drm_connector_status
2921 ironlake_dp_detect(struct intel_dp *intel_dp)
2923 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2926 enum drm_connector_status status;
2928 /* Can't disconnect eDP, but you can close the lid... */
2929 if (is_edp(intel_dp)) {
2930 status = intel_panel_detect(dev);
2931 if (status == connector_status_unknown)
2932 status = connector_status_connected;
2936 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2937 return connector_status_disconnected;
2939 return intel_dp_detect_dpcd(intel_dp);
2942 static enum drm_connector_status
2943 g4x_dp_detect(struct intel_dp *intel_dp)
2945 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2950 /* Can't disconnect eDP, but you can close the lid... */
2951 if (is_edp(intel_dp)) {
2952 enum drm_connector_status status;
2954 status = intel_panel_detect(dev);
2955 if (status == connector_status_unknown)
2956 status = connector_status_connected;
2960 switch (intel_dig_port->port) {
2962 bit = PORTB_HOTPLUG_LIVE_STATUS;
2965 bit = PORTC_HOTPLUG_LIVE_STATUS;
2968 bit = PORTD_HOTPLUG_LIVE_STATUS;
2971 return connector_status_unknown;
2974 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2975 return connector_status_disconnected;
2977 return intel_dp_detect_dpcd(intel_dp);
2980 static struct edid *
2981 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2983 struct intel_connector *intel_connector = to_intel_connector(connector);
2985 /* use cached edid if we have one */
2986 if (intel_connector->edid) {
2988 if (IS_ERR(intel_connector->edid))
2991 return drm_edid_duplicate(intel_connector->edid);
2994 return drm_get_edid(connector, adapter);
2998 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3000 struct intel_connector *intel_connector = to_intel_connector(connector);
3002 /* use cached edid if we have one */
3003 if (intel_connector->edid) {
3005 if (IS_ERR(intel_connector->edid))
3008 return intel_connector_update_modes(connector,
3009 intel_connector->edid);
3012 return intel_ddc_get_modes(connector, adapter);
3015 static enum drm_connector_status
3016 intel_dp_detect(struct drm_connector *connector, bool force)
3018 struct intel_dp *intel_dp = intel_attached_dp(connector);
3019 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3020 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3021 struct drm_device *dev = connector->dev;
3022 enum drm_connector_status status;
3023 struct edid *edid = NULL;
3025 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3026 connector->base.id, drm_get_connector_name(connector));
3028 intel_dp->has_audio = false;
3030 if (HAS_PCH_SPLIT(dev))
3031 status = ironlake_dp_detect(intel_dp);
3033 status = g4x_dp_detect(intel_dp);
3035 if (status != connector_status_connected)
3038 intel_dp_probe_oui(intel_dp);
3040 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3041 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3043 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3045 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3050 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3051 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3052 return connector_status_connected;
3055 static int intel_dp_get_modes(struct drm_connector *connector)
3057 struct intel_dp *intel_dp = intel_attached_dp(connector);
3058 struct intel_connector *intel_connector = to_intel_connector(connector);
3059 struct drm_device *dev = connector->dev;
3062 /* We should parse the EDID data and find out if it has an audio sink
3065 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3069 /* if eDP has no EDID, fall back to fixed mode */
3070 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3071 struct drm_display_mode *mode;
3072 mode = drm_mode_duplicate(dev,
3073 intel_connector->panel.fixed_mode);
3075 drm_mode_probed_add(connector, mode);
3083 intel_dp_detect_audio(struct drm_connector *connector)
3085 struct intel_dp *intel_dp = intel_attached_dp(connector);
3087 bool has_audio = false;
3089 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3091 has_audio = drm_detect_monitor_audio(edid);
3099 intel_dp_set_property(struct drm_connector *connector,
3100 struct drm_property *property,
3103 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3104 struct intel_connector *intel_connector = to_intel_connector(connector);
3105 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3106 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3109 ret = drm_object_property_set_value(&connector->base, property, val);
3113 if (property == dev_priv->force_audio_property) {
3117 if (i == intel_dp->force_audio)
3120 intel_dp->force_audio = i;
3122 if (i == HDMI_AUDIO_AUTO)
3123 has_audio = intel_dp_detect_audio(connector);
3125 has_audio = (i == HDMI_AUDIO_ON);
3127 if (has_audio == intel_dp->has_audio)
3130 intel_dp->has_audio = has_audio;
3134 if (property == dev_priv->broadcast_rgb_property) {
3135 bool old_auto = intel_dp->color_range_auto;
3136 uint32_t old_range = intel_dp->color_range;
3139 case INTEL_BROADCAST_RGB_AUTO:
3140 intel_dp->color_range_auto = true;
3142 case INTEL_BROADCAST_RGB_FULL:
3143 intel_dp->color_range_auto = false;
3144 intel_dp->color_range = 0;
3146 case INTEL_BROADCAST_RGB_LIMITED:
3147 intel_dp->color_range_auto = false;
3148 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3154 if (old_auto == intel_dp->color_range_auto &&
3155 old_range == intel_dp->color_range)
3161 if (is_edp(intel_dp) &&
3162 property == connector->dev->mode_config.scaling_mode_property) {
3163 if (val == DRM_MODE_SCALE_NONE) {
3164 DRM_DEBUG_KMS("no scaling not supported\n");
3168 if (intel_connector->panel.fitting_mode == val) {
3169 /* the eDP scaling property is not changed */
3172 intel_connector->panel.fitting_mode = val;
3180 if (intel_encoder->base.crtc)
3181 intel_crtc_restore_mode(intel_encoder->base.crtc);
3187 intel_dp_connector_destroy(struct drm_connector *connector)
3189 struct intel_connector *intel_connector = to_intel_connector(connector);
3191 if (!IS_ERR_OR_NULL(intel_connector->edid))
3192 kfree(intel_connector->edid);
3194 /* Can't call is_edp() since the encoder may have been destroyed
3196 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3197 intel_panel_fini(&intel_connector->panel);
3199 drm_connector_cleanup(connector);
3203 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3205 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3206 struct intel_dp *intel_dp = &intel_dig_port->dp;
3207 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3209 i2c_del_adapter(&intel_dp->adapter);
3210 drm_encoder_cleanup(encoder);
3211 if (is_edp(intel_dp)) {
3212 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3213 mutex_lock(&dev->mode_config.mutex);
3214 ironlake_panel_vdd_off_sync(intel_dp);
3215 mutex_unlock(&dev->mode_config.mutex);
3217 kfree(intel_dig_port);
3220 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3221 .dpms = intel_connector_dpms,
3222 .detect = intel_dp_detect,
3223 .fill_modes = drm_helper_probe_single_connector_modes,
3224 .set_property = intel_dp_set_property,
3225 .destroy = intel_dp_connector_destroy,
3228 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3229 .get_modes = intel_dp_get_modes,
3230 .mode_valid = intel_dp_mode_valid,
3231 .best_encoder = intel_best_encoder,
3234 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3235 .destroy = intel_dp_encoder_destroy,
3239 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3241 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3243 intel_dp_check_link_status(intel_dp);
3246 /* Return which DP Port should be selected for Transcoder DP control */
3248 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3250 struct drm_device *dev = crtc->dev;
3251 struct intel_encoder *intel_encoder;
3252 struct intel_dp *intel_dp;
3254 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3255 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3257 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3258 intel_encoder->type == INTEL_OUTPUT_EDP)
3259 return intel_dp->output_reg;
3265 /* check the VBT to see whether the eDP is on DP-D port */
3266 bool intel_dpd_is_edp(struct drm_device *dev)
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 union child_device_config *p_child;
3272 if (!dev_priv->vbt.child_dev_num)
3275 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3276 p_child = dev_priv->vbt.child_dev + i;
3278 if (p_child->common.dvo_port == PORT_IDPD &&
3279 p_child->common.device_type == DEVICE_TYPE_eDP)
3286 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3288 struct intel_connector *intel_connector = to_intel_connector(connector);
3290 intel_attach_force_audio_property(connector);
3291 intel_attach_broadcast_rgb_property(connector);
3292 intel_dp->color_range_auto = true;
3294 if (is_edp(intel_dp)) {
3295 drm_mode_create_scaling_mode_property(connector->dev);
3296 drm_object_attach_property(
3298 connector->dev->mode_config.scaling_mode_property,
3299 DRM_MODE_SCALE_ASPECT);
3300 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3305 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3306 struct intel_dp *intel_dp,
3307 struct edp_power_seq *out)
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 struct edp_power_seq cur, vbt, spec, final;
3311 u32 pp_on, pp_off, pp_div, pp;
3312 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3314 if (HAS_PCH_SPLIT(dev)) {
3315 pp_ctrl_reg = PCH_PP_CONTROL;
3316 pp_on_reg = PCH_PP_ON_DELAYS;
3317 pp_off_reg = PCH_PP_OFF_DELAYS;
3318 pp_div_reg = PCH_PP_DIVISOR;
3320 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3322 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3323 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3324 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3325 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3328 /* Workaround: Need to write PP_CONTROL with the unlock key as
3329 * the very first thing. */
3330 pp = ironlake_get_pp_control(intel_dp);
3331 I915_WRITE(pp_ctrl_reg, pp);
3333 pp_on = I915_READ(pp_on_reg);
3334 pp_off = I915_READ(pp_off_reg);
3335 pp_div = I915_READ(pp_div_reg);
3337 /* Pull timing values out of registers */
3338 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3339 PANEL_POWER_UP_DELAY_SHIFT;
3341 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3342 PANEL_LIGHT_ON_DELAY_SHIFT;
3344 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3345 PANEL_LIGHT_OFF_DELAY_SHIFT;
3347 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3348 PANEL_POWER_DOWN_DELAY_SHIFT;
3350 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3351 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3353 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3354 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3356 vbt = dev_priv->vbt.edp_pps;
3358 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3359 * our hw here, which are all in 100usec. */
3360 spec.t1_t3 = 210 * 10;
3361 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3362 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3363 spec.t10 = 500 * 10;
3364 /* This one is special and actually in units of 100ms, but zero
3365 * based in the hw (so we need to add 100 ms). But the sw vbt
3366 * table multiplies it with 1000 to make it in units of 100usec,
3368 spec.t11_t12 = (510 + 100) * 10;
3370 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3371 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3373 /* Use the max of the register settings and vbt. If both are
3374 * unset, fall back to the spec limits. */
3375 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3377 max(cur.field, vbt.field))
3378 assign_final(t1_t3);
3382 assign_final(t11_t12);
3385 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3386 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3387 intel_dp->backlight_on_delay = get_delay(t8);
3388 intel_dp->backlight_off_delay = get_delay(t9);
3389 intel_dp->panel_power_down_delay = get_delay(t10);
3390 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3393 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3394 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3395 intel_dp->panel_power_cycle_delay);
3397 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3398 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3405 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3406 struct intel_dp *intel_dp,
3407 struct edp_power_seq *seq)
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 u32 pp_on, pp_off, pp_div, port_sel = 0;
3411 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3412 int pp_on_reg, pp_off_reg, pp_div_reg;
3414 if (HAS_PCH_SPLIT(dev)) {
3415 pp_on_reg = PCH_PP_ON_DELAYS;
3416 pp_off_reg = PCH_PP_OFF_DELAYS;
3417 pp_div_reg = PCH_PP_DIVISOR;
3419 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3421 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3422 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3423 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3426 /* And finally store the new values in the power sequencer. */
3427 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3428 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3429 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3430 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3431 /* Compute the divisor for the pp clock, simply match the Bspec
3433 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3434 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3435 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3437 /* Haswell doesn't have any port selection bits for the panel
3438 * power sequencer any more. */
3439 if (IS_VALLEYVIEW(dev)) {
3440 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3441 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3443 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3444 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3445 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3446 port_sel = PANEL_PORT_SELECT_DPA;
3448 port_sel = PANEL_PORT_SELECT_DPD;
3453 I915_WRITE(pp_on_reg, pp_on);
3454 I915_WRITE(pp_off_reg, pp_off);
3455 I915_WRITE(pp_div_reg, pp_div);
3457 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3458 I915_READ(pp_on_reg),
3459 I915_READ(pp_off_reg),
3460 I915_READ(pp_div_reg));
3463 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3464 struct intel_connector *intel_connector)
3466 struct drm_connector *connector = &intel_connector->base;
3467 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3468 struct drm_device *dev = intel_dig_port->base.base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 struct drm_display_mode *fixed_mode = NULL;
3471 struct edp_power_seq power_seq = { 0 };
3473 struct drm_display_mode *scan;
3476 if (!is_edp(intel_dp))
3479 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3481 /* Cache DPCD and EDID for edp. */
3482 ironlake_edp_panel_vdd_on(intel_dp);
3483 has_dpcd = intel_dp_get_dpcd(intel_dp);
3484 ironlake_edp_panel_vdd_off(intel_dp, false);
3487 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3488 dev_priv->no_aux_handshake =
3489 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3490 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3492 /* if this fails, presume the device is a ghost */
3493 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3497 /* We now know it's not a ghost, init power sequence regs. */
3498 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3501 ironlake_edp_panel_vdd_on(intel_dp);
3502 edid = drm_get_edid(connector, &intel_dp->adapter);
3504 if (drm_add_edid_modes(connector, edid)) {
3505 drm_mode_connector_update_edid_property(connector,
3507 drm_edid_to_eld(connector, edid);
3510 edid = ERR_PTR(-EINVAL);
3513 edid = ERR_PTR(-ENOENT);
3515 intel_connector->edid = edid;
3517 /* prefer fixed mode from EDID if available */
3518 list_for_each_entry(scan, &connector->probed_modes, head) {
3519 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3520 fixed_mode = drm_mode_duplicate(dev, scan);
3525 /* fallback to VBT if available for eDP */
3526 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3527 fixed_mode = drm_mode_duplicate(dev,
3528 dev_priv->vbt.lfp_lvds_vbt_mode);
3530 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3533 ironlake_edp_panel_vdd_off(intel_dp, false);
3535 intel_panel_init(&intel_connector->panel, fixed_mode);
3536 intel_panel_setup_backlight(connector);
3542 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3543 struct intel_connector *intel_connector)
3545 struct drm_connector *connector = &intel_connector->base;
3546 struct intel_dp *intel_dp = &intel_dig_port->dp;
3547 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3548 struct drm_device *dev = intel_encoder->base.dev;
3549 struct drm_i915_private *dev_priv = dev->dev_private;
3550 enum port port = intel_dig_port->port;
3551 const char *name = NULL;
3554 /* Preserve the current hw state. */
3555 intel_dp->DP = I915_READ(intel_dp->output_reg);
3556 intel_dp->attached_connector = intel_connector;
3558 type = DRM_MODE_CONNECTOR_DisplayPort;
3560 * FIXME : We need to initialize built-in panels before external panels.
3561 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3565 type = DRM_MODE_CONNECTOR_eDP;
3568 if (IS_VALLEYVIEW(dev))
3569 type = DRM_MODE_CONNECTOR_eDP;
3572 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3573 type = DRM_MODE_CONNECTOR_eDP;
3575 default: /* silence GCC warning */
3580 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3581 * for DP the encoder type can be set by the caller to
3582 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3584 if (type == DRM_MODE_CONNECTOR_eDP)
3585 intel_encoder->type = INTEL_OUTPUT_EDP;
3587 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3588 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3591 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3592 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3594 connector->interlace_allowed = true;
3595 connector->doublescan_allowed = 0;
3597 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3598 ironlake_panel_vdd_work);
3600 intel_connector_attach_encoder(intel_connector, intel_encoder);
3601 drm_sysfs_connector_add(connector);
3604 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3606 intel_connector->get_hw_state = intel_connector_get_hw_state;
3608 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3610 switch (intel_dig_port->port) {
3612 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3615 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3618 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3621 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3628 /* Set up the DDC bus. */
3631 intel_encoder->hpd_pin = HPD_PORT_A;
3635 intel_encoder->hpd_pin = HPD_PORT_B;
3639 intel_encoder->hpd_pin = HPD_PORT_C;
3643 intel_encoder->hpd_pin = HPD_PORT_D;
3650 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3651 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3652 error, port_name(port));
3654 intel_dp->psr_setup_done = false;
3656 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3657 i2c_del_adapter(&intel_dp->adapter);
3658 if (is_edp(intel_dp)) {
3659 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3660 mutex_lock(&dev->mode_config.mutex);
3661 ironlake_panel_vdd_off_sync(intel_dp);
3662 mutex_unlock(&dev->mode_config.mutex);
3664 drm_sysfs_connector_remove(connector);
3665 drm_connector_cleanup(connector);
3669 intel_dp_add_properties(intel_dp, connector);
3671 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3672 * 0xd. Failure to do so will result in spurious interrupts being
3673 * generated on the port when a cable is not attached.
3675 if (IS_G4X(dev) && !IS_GM45(dev)) {
3676 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3677 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3684 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3686 struct intel_digital_port *intel_dig_port;
3687 struct intel_encoder *intel_encoder;
3688 struct drm_encoder *encoder;
3689 struct intel_connector *intel_connector;
3691 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3692 if (!intel_dig_port)
3695 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3696 if (!intel_connector) {
3697 kfree(intel_dig_port);
3701 intel_encoder = &intel_dig_port->base;
3702 encoder = &intel_encoder->base;
3704 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3705 DRM_MODE_ENCODER_TMDS);
3707 intel_encoder->compute_config = intel_dp_compute_config;
3708 intel_encoder->mode_set = intel_dp_mode_set;
3709 intel_encoder->disable = intel_disable_dp;
3710 intel_encoder->post_disable = intel_post_disable_dp;
3711 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3712 intel_encoder->get_config = intel_dp_get_config;
3713 if (IS_VALLEYVIEW(dev)) {
3714 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3715 intel_encoder->pre_enable = vlv_pre_enable_dp;
3716 intel_encoder->enable = vlv_enable_dp;
3718 intel_encoder->pre_enable = g4x_pre_enable_dp;
3719 intel_encoder->enable = g4x_enable_dp;
3722 intel_dig_port->port = port;
3723 intel_dig_port->dp.output_reg = output_reg;
3725 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3726 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3727 intel_encoder->cloneable = false;
3728 intel_encoder->hot_plug = intel_dp_hot_plug;
3730 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3731 drm_encoder_cleanup(encoder);
3732 kfree(intel_dig_port);
3733 kfree(intel_connector);