2 * Copyright © 2014-2016 Intel Corporation
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21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
30 * ports. DPIO is the name given to such a display PHY. These PHYs
31 * don't follow the standard programming model using direct MMIO
32 * registers, and instead their registers must be accessed trough IOSF
33 * sideband. VLV has one such PHY for driving ports B and C, and CHV
34 * adds another PHY for driving port D. Each PHY responds to specific
37 * Each display PHY is made up of one or two channels. Each channel
38 * houses a common lane part which contains the PLL and other common
39 * logic. CH0 common lane also contains the IOSF-SB logic for the
40 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
41 * must be running when any DPIO registers are accessed.
43 * In addition to having their own registers, the PHYs are also
44 * controlled through some dedicated signals from the display
45 * controller. These include PLL reference clock enable, PLL enable,
46 * and CRI clock selection, for example.
48 * Eeach channel also has two splines (also called data lanes), and
49 * each spline is made up of one Physical Access Coding Sub-Layer
50 * (PCS) block and two TX lanes. So each channel has two PCS blocks
51 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
52 * data/clock pairs depending on the output type.
54 * Additionally the PHY also contains an AUX lane with AUX blocks
55 * for each channel. This is used for DP AUX communication, but
56 * this fact isn't really relevant for the driver since AUX is
57 * controlled from the display controller side. No DPIO registers
58 * need to be accessed during AUX communication,
60 * Generally on VLV/CHV the common lane corresponds to the pipe and
61 * the spline (PCS/TX) corresponds to the port.
63 * For dual channel PHY (VLV/CHV):
65 * pipe A == CMN/PLL/REF CH0
67 * pipe B == CMN/PLL/REF CH1
69 * port B == PCS/TX CH0
71 * port C == PCS/TX CH1
73 * This is especially important when we cross the streams
74 * ie. drive port B with pipe B, or port C with pipe A.
76 * For single channel PHY (CHV):
78 * pipe C == CMN/PLL/REF CH0
80 * port D == PCS/TX CH0
82 * On BXT the entire PHY channel corresponds to the port. That means
83 * the PLL is also now associated with the port rather than the pipe,
84 * and so the clock needs to be routed to the appropriate transcoder.
85 * Port A PLL is directly connected to transcoder EDP and port B/C
86 * PLLs can be routed to any transcoder A/B/C.
88 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
89 * digital port D (CHV) or port A (BXT). ::
92 * Dual channel PHY (VLV/CHV/BXT)
93 * ---------------------------------
95 * | CMN/PLL/REF | CMN/PLL/REF |
96 * |---------------|---------------| Display PHY
97 * | PCS01 | PCS23 | PCS01 | PCS23 |
98 * |-------|-------|-------|-------|
99 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
100 * ---------------------------------
101 * | DDI0 | DDI1 | DP/HDMI ports
102 * ---------------------------------
104 * Single channel PHY (CHV/BXT)
108 * |---------------| Display PHY
113 * | DDI2 | DP/HDMI port
118 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
120 struct bxt_ddi_phy_info {
122 * @dual_channel: true if this phy has a second channel.
127 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
128 * Otherwise the GRC value will be copied from the phy indicated by
131 enum dpio_phy rcomp_phy;
134 * @reset_delay: delay in us to wait before setting the common reset
135 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
140 * @pwron_mask: Mask with the appropriate bit set that would cause the
141 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
146 * @channel: struct containing per channel information.
150 * @port: which port maps to this channel.
156 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
158 .dual_channel = true,
159 .rcomp_phy = DPIO_PHY1,
160 .pwron_mask = BIT(0),
163 [DPIO_CH0] = { .port = PORT_B },
164 [DPIO_CH1] = { .port = PORT_C },
168 .dual_channel = false,
170 .pwron_mask = BIT(1),
173 [DPIO_CH0] = { .port = PORT_A },
178 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
180 .dual_channel = false,
181 .rcomp_phy = DPIO_PHY1,
182 .pwron_mask = BIT(0),
186 [DPIO_CH0] = { .port = PORT_B },
190 .dual_channel = false,
192 .pwron_mask = BIT(3),
196 [DPIO_CH0] = { .port = PORT_A },
200 .dual_channel = false,
201 .rcomp_phy = DPIO_PHY1,
202 .pwron_mask = BIT(1),
206 [DPIO_CH0] = { .port = PORT_C },
211 static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
213 return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
214 BIT(phy_info->channel[DPIO_CH0].port);
217 static const struct bxt_ddi_phy_info *
218 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
220 if (IS_GEMINILAKE(dev_priv)) {
221 *count = ARRAY_SIZE(glk_ddi_phy_info);
222 return glk_ddi_phy_info;
224 *count = ARRAY_SIZE(bxt_ddi_phy_info);
225 return bxt_ddi_phy_info;
229 static const struct bxt_ddi_phy_info *
230 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
233 const struct bxt_ddi_phy_info *phy_list =
234 bxt_get_phy_list(dev_priv, &count);
236 return &phy_list[phy];
239 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
240 enum dpio_phy *phy, enum dpio_channel *ch)
242 const struct bxt_ddi_phy_info *phy_info, *phys;
245 phys = bxt_get_phy_list(dev_priv, &count);
247 for (i = 0; i < count; i++) {
250 if (port == phy_info->channel[DPIO_CH0].port) {
256 if (phy_info->dual_channel &&
257 port == phy_info->channel[DPIO_CH1].port) {
264 WARN(1, "PHY not found for PORT %c", port_name(port));
269 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
270 enum port port, u32 margin, u32 scale,
271 u32 enable, u32 deemphasis)
275 enum dpio_channel ch;
277 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
280 * While we write to the group register to program all lanes at once we
281 * can read only lane registers and we pick lanes 0/1 for that.
283 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
284 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
285 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
287 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
288 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
289 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
290 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
292 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
293 val &= ~SCALE_DCOMP_METHOD;
295 val |= SCALE_DCOMP_METHOD;
297 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
298 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
300 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
302 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
304 val |= deemphasis << DEEMPH_SHIFT;
305 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
307 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
308 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
309 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
312 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
315 const struct bxt_ddi_phy_info *phy_info;
318 phy_info = bxt_get_phy_info(dev_priv, phy);
320 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
323 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
324 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
325 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
331 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
332 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
338 for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
339 u32 tmp = I915_READ(BXT_PHY_CTL(port));
341 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
342 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
343 "for port %c powered down "
345 phy, port_name(port), tmp);
354 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
356 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
358 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
361 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
364 if (intel_wait_for_register(dev_priv,
365 BXT_PORT_REF_DW3(phy),
368 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
371 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
374 const struct bxt_ddi_phy_info *phy_info;
377 phy_info = bxt_get_phy_info(dev_priv, phy);
379 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
380 /* Still read out the GRC value for state verification */
381 if (phy_info->rcomp_phy != -1)
382 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
384 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
385 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
386 "won't reprogram it\n", phy);
390 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
391 "force reprogramming it\n", phy);
394 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
395 val |= phy_info->pwron_mask;
396 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
399 * The PHY registers start out inaccessible and respond to reads with
400 * all 1s. Eventually they become accessible as they power up, then
401 * the reserved bit will give the default 0. Poll on the reserved bit
402 * becoming 0 to find when the PHY is accessible.
403 * HW team confirmed that the time to reach phypowergood status is
404 * anywhere between 50 us and 100us.
406 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
407 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
408 DRM_ERROR("timeout during PHY%d power on\n", phy);
411 /* Program PLL Rcomp code offset */
412 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
413 val &= ~IREF0RC_OFFSET_MASK;
414 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
415 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
417 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
418 val &= ~IREF1RC_OFFSET_MASK;
419 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
420 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
422 /* Program power gating */
423 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
424 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
426 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
428 if (phy_info->dual_channel) {
429 val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
430 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
431 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
434 if (phy_info->rcomp_phy != -1) {
437 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
440 * PHY0 isn't connected to an RCOMP resistor so copy over
441 * the corresponding calibrated value from PHY1, and disable
442 * the automatic calibration on PHY0.
444 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
445 phy_info->rcomp_phy);
446 grc_code = val << GRC_CODE_FAST_SHIFT |
447 val << GRC_CODE_SLOW_SHIFT |
449 I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
451 val = I915_READ(BXT_PORT_REF_DW8(phy));
452 val |= GRC_DIS | GRC_RDY_OVRD;
453 I915_WRITE(BXT_PORT_REF_DW8(phy), val);
456 if (phy_info->reset_delay)
457 udelay(phy_info->reset_delay);
459 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
460 val |= COMMON_RESET_DIS;
461 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
464 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
466 const struct bxt_ddi_phy_info *phy_info;
469 phy_info = bxt_get_phy_info(dev_priv, phy);
471 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
472 val &= ~COMMON_RESET_DIS;
473 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
475 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
476 val &= ~phy_info->pwron_mask;
477 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
480 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
482 const struct bxt_ddi_phy_info *phy_info =
483 bxt_get_phy_info(dev_priv, phy);
484 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
487 lockdep_assert_held(&dev_priv->power_domains.lock);
489 if (rcomp_phy != -1) {
490 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
493 * We need to copy the GRC calibration value from rcomp_phy,
494 * so make sure it's powered up.
497 _bxt_ddi_phy_init(dev_priv, rcomp_phy);
500 _bxt_ddi_phy_init(dev_priv, phy);
502 if (rcomp_phy != -1 && !was_enabled)
503 bxt_ddi_phy_uninit(dev_priv, phy_info->rcomp_phy);
506 static bool __printf(6, 7)
507 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
508 i915_reg_t reg, u32 mask, u32 expected,
509 const char *reg_fmt, ...)
511 struct va_format vaf;
515 val = I915_READ(reg);
516 if ((val & mask) == expected)
519 va_start(args, reg_fmt);
523 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
524 "current %08x, expected %08x (mask %08x)\n",
525 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
533 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
536 const struct bxt_ddi_phy_info *phy_info;
540 phy_info = bxt_get_phy_info(dev_priv, phy);
542 #define _CHK(reg, mask, exp, fmt, ...) \
543 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
546 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
551 /* PLL Rcomp code offset */
552 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
553 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
554 "BXT_PORT_CL1CM_DW9(%d)", phy);
555 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
556 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
557 "BXT_PORT_CL1CM_DW10(%d)", phy);
560 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
561 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
562 "BXT_PORT_CL1CM_DW28(%d)", phy);
564 if (phy_info->dual_channel)
565 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
566 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
567 "BXT_PORT_CL2CM_DW6(%d)", phy);
569 if (phy_info->rcomp_phy != -1) {
570 u32 grc_code = dev_priv->bxt_phy_grc;
572 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
573 grc_code << GRC_CODE_SLOW_SHIFT |
575 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
577 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
578 "BXT_PORT_REF_DW6(%d)", phy);
580 mask = GRC_DIS | GRC_RDY_OVRD;
581 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
582 "BXT_PORT_REF_DW8(%d)", phy);
590 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
593 switch (lane_count) {
597 return BIT(2) | BIT(0);
599 return BIT(3) | BIT(2) | BIT(0);
601 MISSING_CASE(lane_count);
607 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
608 uint8_t lane_lat_optim_mask)
610 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
611 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
612 enum port port = dport->port;
614 enum dpio_channel ch;
617 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
619 for (lane = 0; lane < 4; lane++) {
620 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
623 * Note that on CHV this flag is called UPAR, but has
626 val &= ~LATENCY_OPTIM;
627 if (lane_lat_optim_mask & BIT(lane))
628 val |= LATENCY_OPTIM;
630 I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
635 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
637 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
638 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
639 enum port port = dport->port;
641 enum dpio_channel ch;
645 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
648 for (lane = 0; lane < 4; lane++) {
649 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
651 if (val & LATENCY_OPTIM)
659 void chv_set_phy_signal_level(struct intel_encoder *encoder,
660 u32 deemph_reg_value, u32 margin_reg_value,
661 bool uniq_trans_scale)
663 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
664 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
665 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
666 enum dpio_channel ch = vlv_dport_to_channel(dport);
667 enum pipe pipe = intel_crtc->pipe;
671 mutex_lock(&dev_priv->sb_lock);
673 /* Clear calc init */
674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
675 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
676 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
677 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
678 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
680 if (intel_crtc->config->lane_count > 2) {
681 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
682 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
683 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
684 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
685 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
688 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
689 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
690 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
691 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
693 if (intel_crtc->config->lane_count > 2) {
694 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
695 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
696 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
697 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
700 /* Program swing deemph */
701 for (i = 0; i < intel_crtc->config->lane_count; i++) {
702 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
703 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
704 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
705 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
708 /* Program swing margin */
709 for (i = 0; i < intel_crtc->config->lane_count; i++) {
710 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
712 val &= ~DPIO_SWING_MARGIN000_MASK;
713 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
716 * Supposedly this value shouldn't matter when unique transition
717 * scale is disabled, but in fact it does matter. Let's just
718 * always program the same value and hope it's OK.
720 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
721 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
723 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
727 * The document said it needs to set bit 27 for ch0 and bit 26
728 * for ch1. Might be a typo in the doc.
729 * For now, for this unique transition scale selection, set bit
730 * 27 for ch0 and ch1.
732 for (i = 0; i < intel_crtc->config->lane_count; i++) {
733 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
734 if (uniq_trans_scale)
735 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
737 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
738 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
741 /* Start swing calculation */
742 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
743 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
744 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
746 if (intel_crtc->config->lane_count > 2) {
747 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
748 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
749 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
752 mutex_unlock(&dev_priv->sb_lock);
756 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
759 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
760 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
761 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
762 enum pipe pipe = crtc->pipe;
765 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
767 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
769 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
770 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
772 if (crtc->config->lane_count > 2) {
773 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
775 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
777 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
778 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
781 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
782 val |= CHV_PCS_REQ_SOFTRESET_EN;
784 val &= ~DPIO_PCS_CLK_SOFT_RESET;
786 val |= DPIO_PCS_CLK_SOFT_RESET;
787 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
789 if (crtc->config->lane_count > 2) {
790 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
791 val |= CHV_PCS_REQ_SOFTRESET_EN;
793 val &= ~DPIO_PCS_CLK_SOFT_RESET;
795 val |= DPIO_PCS_CLK_SOFT_RESET;
796 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
800 void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
802 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
803 struct drm_device *dev = encoder->base.dev;
804 struct drm_i915_private *dev_priv = to_i915(dev);
805 struct intel_crtc *intel_crtc =
806 to_intel_crtc(encoder->base.crtc);
807 enum dpio_channel ch = vlv_dport_to_channel(dport);
808 enum pipe pipe = intel_crtc->pipe;
809 unsigned int lane_mask =
810 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
814 * Must trick the second common lane into life.
815 * Otherwise we can't even access the PLL.
817 if (ch == DPIO_CH0 && pipe == PIPE_B)
818 dport->release_cl2_override =
819 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
821 chv_phy_powergate_lanes(encoder, true, lane_mask);
823 mutex_lock(&dev_priv->sb_lock);
825 /* Assert data lane reset */
826 chv_data_lane_soft_reset(encoder, true);
828 /* program left/right clock distribution */
829 if (pipe != PIPE_B) {
830 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
831 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
833 val |= CHV_BUFLEFTENA1_FORCE;
835 val |= CHV_BUFRIGHTENA1_FORCE;
836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
841 val |= CHV_BUFLEFTENA2_FORCE;
843 val |= CHV_BUFRIGHTENA2_FORCE;
844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
847 /* program clock channel usage */
848 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
849 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
851 val &= ~CHV_PCS_USEDCLKCHANNEL;
853 val |= CHV_PCS_USEDCLKCHANNEL;
854 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
856 if (intel_crtc->config->lane_count > 2) {
857 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
858 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
860 val &= ~CHV_PCS_USEDCLKCHANNEL;
862 val |= CHV_PCS_USEDCLKCHANNEL;
863 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
867 * This a a bit weird since generally CL
868 * matches the pipe, but here we need to
869 * pick the CL based on the port.
871 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
873 val &= ~CHV_CMN_USEDCLKCHANNEL;
875 val |= CHV_CMN_USEDCLKCHANNEL;
876 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
878 mutex_unlock(&dev_priv->sb_lock);
881 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
883 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
884 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
885 struct drm_device *dev = encoder->base.dev;
886 struct drm_i915_private *dev_priv = to_i915(dev);
887 struct intel_crtc *intel_crtc =
888 to_intel_crtc(encoder->base.crtc);
889 enum dpio_channel ch = vlv_dport_to_channel(dport);
890 int pipe = intel_crtc->pipe;
891 int data, i, stagger;
894 mutex_lock(&dev_priv->sb_lock);
896 /* allow hardware to manage TX FIFO reset source */
897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
898 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
899 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
901 if (intel_crtc->config->lane_count > 2) {
902 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
903 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
904 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
907 /* Program Tx lane latency optimal setting*/
908 for (i = 0; i < intel_crtc->config->lane_count; i++) {
909 /* Set the upar bit */
910 if (intel_crtc->config->lane_count == 1)
913 data = (i == 1) ? 0x0 : 0x1;
914 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
915 data << DPIO_UPAR_SHIFT);
918 /* Data lane stagger programming */
919 if (intel_crtc->config->port_clock > 270000)
921 else if (intel_crtc->config->port_clock > 135000)
923 else if (intel_crtc->config->port_clock > 67500)
925 else if (intel_crtc->config->port_clock > 33750)
930 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
931 val |= DPIO_TX2_STAGGER_MASK(0x1f);
932 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
934 if (intel_crtc->config->lane_count > 2) {
935 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
936 val |= DPIO_TX2_STAGGER_MASK(0x1f);
937 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
940 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
941 DPIO_LANESTAGGER_STRAP(stagger) |
942 DPIO_LANESTAGGER_STRAP_OVRD |
943 DPIO_TX1_STAGGER_MASK(0x1f) |
944 DPIO_TX1_STAGGER_MULT(6) |
945 DPIO_TX2_STAGGER_MULT(0));
947 if (intel_crtc->config->lane_count > 2) {
948 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
949 DPIO_LANESTAGGER_STRAP(stagger) |
950 DPIO_LANESTAGGER_STRAP_OVRD |
951 DPIO_TX1_STAGGER_MASK(0x1f) |
952 DPIO_TX1_STAGGER_MULT(7) |
953 DPIO_TX2_STAGGER_MULT(5));
956 /* Deassert data lane reset */
957 chv_data_lane_soft_reset(encoder, false);
959 mutex_unlock(&dev_priv->sb_lock);
962 void chv_phy_release_cl2_override(struct intel_encoder *encoder)
964 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
967 if (dport->release_cl2_override) {
968 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
969 dport->release_cl2_override = false;
973 void chv_phy_post_pll_disable(struct intel_encoder *encoder)
975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
976 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
979 mutex_lock(&dev_priv->sb_lock);
981 /* disable left/right clock distribution */
982 if (pipe != PIPE_B) {
983 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
984 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
985 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
987 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
988 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
989 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
992 mutex_unlock(&dev_priv->sb_lock);
995 * Leave the power down bit cleared for at least one
996 * lane so that chv_powergate_phy_ch() will power
997 * on something when the channel is otherwise unused.
998 * When the port is off and the override is removed
999 * the lanes power down anyway, so otherwise it doesn't
1000 * really matter what the state of power down bits is
1003 chv_phy_powergate_lanes(encoder, false, 0x0);
1006 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
1007 u32 demph_reg_value, u32 preemph_reg_value,
1008 u32 uniqtranscale_reg_value, u32 tx3_demph)
1010 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1011 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1012 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1013 enum dpio_channel port = vlv_dport_to_channel(dport);
1014 int pipe = intel_crtc->pipe;
1016 mutex_lock(&dev_priv->sb_lock);
1017 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
1018 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
1019 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
1020 uniqtranscale_reg_value);
1021 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
1024 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
1026 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1027 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
1028 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1029 mutex_unlock(&dev_priv->sb_lock);
1032 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
1034 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1035 struct drm_device *dev = encoder->base.dev;
1036 struct drm_i915_private *dev_priv = to_i915(dev);
1037 struct intel_crtc *intel_crtc =
1038 to_intel_crtc(encoder->base.crtc);
1039 enum dpio_channel port = vlv_dport_to_channel(dport);
1040 int pipe = intel_crtc->pipe;
1042 /* Program Tx lane resets to default */
1043 mutex_lock(&dev_priv->sb_lock);
1044 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1045 DPIO_PCS_TX_LANE2_RESET |
1046 DPIO_PCS_TX_LANE1_RESET);
1047 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1048 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1049 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1050 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1051 DPIO_PCS_CLK_SOFT_RESET);
1053 /* Fix up inter-pair skew failure */
1054 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1055 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1056 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1057 mutex_unlock(&dev_priv->sb_lock);
1060 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
1062 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1063 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1064 struct drm_device *dev = encoder->base.dev;
1065 struct drm_i915_private *dev_priv = to_i915(dev);
1066 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1067 enum dpio_channel port = vlv_dport_to_channel(dport);
1068 int pipe = intel_crtc->pipe;
1071 mutex_lock(&dev_priv->sb_lock);
1073 /* Enable clock channels for this port */
1074 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1081 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1083 /* Program lane clock */
1084 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1085 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1087 mutex_unlock(&dev_priv->sb_lock);
1090 void vlv_phy_reset_lanes(struct intel_encoder *encoder)
1092 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1093 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1094 struct intel_crtc *intel_crtc =
1095 to_intel_crtc(encoder->base.crtc);
1096 enum dpio_channel port = vlv_dport_to_channel(dport);
1097 int pipe = intel_crtc->pipe;
1099 mutex_lock(&dev_priv->sb_lock);
1100 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1101 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1102 mutex_unlock(&dev_priv->sb_lock);