2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <drm/i915_drm.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_dp_helper.h>
37 * _wait_for - magic (register) wait macro
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
44 #define _wait_for(COND, MS, W) ({ \
45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
48 if (time_after(jiffies, timeout__)) { \
53 if (W && drm_can_sleep()) { \
62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
67 #define KHz(x) (1000*x)
68 #define MHz(x) KHz(1000*x)
71 * Display related stuff
74 /* store information about an Ixxx DVO */
75 /* The i830->i865 use multiple DVOs with multiple i2cs */
76 /* the i915, i945 have a single sDVO i2c bus - which is different */
78 /* maximum connectors per crtcs in the mode set */
79 #define INTELFB_CONN_LIMIT 4
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_UNKNOWN 9
97 #define INTEL_DVO_CHIP_NONE 0
98 #define INTEL_DVO_CHIP_LVDS 1
99 #define INTEL_DVO_CHIP_TMDS 2
100 #define INTEL_DVO_CHIP_TVOUT 4
102 struct intel_framebuffer {
103 struct drm_framebuffer base;
104 struct drm_i915_gem_object *obj;
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
114 struct intel_encoder {
115 struct drm_encoder base;
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
120 struct intel_crtc *new_crtc;
124 * Intel hw has only one MUX where encoders could be clone, hence a
125 * simple flag is enough to compute the possible_clones mask.
128 bool connectors_active;
129 void (*hot_plug)(struct intel_encoder *);
130 bool (*compute_config)(struct intel_encoder *,
131 struct intel_crtc_config *);
132 void (*pre_pll_enable)(struct intel_encoder *);
133 void (*pre_enable)(struct intel_encoder *);
134 void (*enable)(struct intel_encoder *);
135 void (*mode_set)(struct intel_encoder *intel_encoder);
136 void (*disable)(struct intel_encoder *);
137 void (*post_disable)(struct intel_encoder *);
138 /* Read out the current hw state of this connector, returning true if
139 * the encoder is active. If the encoder is enabled it also set the pipe
140 * it is connected to in the pipe parameter. */
141 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
142 /* Reconstructs the equivalent mode flags for the current hardware
143 * state. This must be called _after_ display->get_pipe_config has
144 * pre-filled the pipe config. */
145 void (*get_config)(struct intel_encoder *,
146 struct intel_crtc_config *pipe_config);
148 enum hpd_pin hpd_pin;
152 struct drm_display_mode *fixed_mode;
156 struct intel_connector {
157 struct drm_connector base;
159 * The fixed encoder this connector is connected to.
161 struct intel_encoder *encoder;
164 * The new encoder this connector will be driven. Only differs from
165 * encoder while a modeset is in progress.
167 struct intel_encoder *new_encoder;
169 /* Reads out the current hw, returning true if the connector is enabled
170 * and active (i.e. dpms ON state). */
171 bool (*get_hw_state)(struct intel_connector *);
173 /* Panel info for eDP and LVDS */
174 struct intel_panel panel;
176 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
179 /* since POLL and HPD connectors may use the same HPD line keep the native
180 state of connector->polled in case hotplug storm detection changes it */
184 typedef struct dpll {
196 struct intel_crtc_config {
198 * quirks - bitfield with hw state readout quirks
200 * For various reasons the hw state readout code might not be able to
201 * completely faithfully read out the current state. These cases are
202 * tracked with quirk flags so that fastboot and state checker can act
205 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
206 unsigned long quirks;
208 struct drm_display_mode requested_mode;
209 struct drm_display_mode adjusted_mode;
210 /* This flag must be set by the encoder's compute_config callback if it
211 * changes the crtc timings in the mode to prevent the crtc fixup from
212 * overwriting them. Currently only lvds needs that. */
214 /* Whether to set up the PCH/FDI. Note that we never allow sharing
215 * between pch encoders and cpu encoders. */
216 bool has_pch_encoder;
218 /* CPU Transcoder for the pipe. Currently this can only differ from the
219 * pipe on Haswell (where we have a special eDP transcoder). */
220 enum transcoder cpu_transcoder;
223 * Use reduced/limited/broadcast rbg range, compressing from the full
224 * range fed into the crtcs.
226 bool limited_color_range;
228 /* DP has a bunch of special case unfortunately, so mark the pipe
233 * Enable dithering, used when the selected pipe bpp doesn't match the
238 /* Controls for the clock computation, to override various stages. */
241 /* SDVO TV has a bunch of special case. To make multifunction encoders
242 * work correctly, we need to track this at runtime.*/
246 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
247 * required. This is set in the 2nd loop of calling encoder's
248 * ->compute_config if the first pick doesn't work out.
252 /* Settings for the intel dpll used on pretty much everything but
256 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
257 enum intel_dpll_id shared_dpll;
259 /* Actual register state of the dpll, for shared dpll cross-checking. */
260 struct intel_dpll_hw_state dpll_hw_state;
263 struct intel_link_m_n dp_m_n;
266 * Frequence the dpll for the port should run at. Differs from the
267 * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
271 /* Used by SDVO (and if we ever fix it, HDMI). */
272 unsigned pixel_multiplier;
274 /* Panel fitter controls for gen2-gen4 + VLV */
278 u32 lvds_border_bits;
281 /* Panel fitter placement and size for Ironlake+ */
287 /* FDI configuration, only valid if has_pch_encoder is set. */
289 struct intel_link_m_n fdi_m_n;
295 struct drm_crtc base;
298 u8 lut_r[256], lut_g[256], lut_b[256];
300 * Whether the crtc and the connected output pipeline is active. Implies
301 * that crtc->enabled is set, i.e. the current mode configuration has
302 * some outputs connected to this crtc.
306 bool primary_disabled; /* is the crtc obscured by a plane? */
308 struct intel_overlay *overlay;
309 struct intel_unpin_work *unpin_work;
311 atomic_t unpin_work_count;
313 /* Display surface base address adjustement for pageflips. Note that on
314 * gen4+ this only adjusts up to a tile, offsets within a tile are
315 * handled in the hw itself (with the TILEOFF register). */
316 unsigned long dspaddr_offset;
318 struct drm_i915_gem_object *cursor_bo;
319 uint32_t cursor_addr;
320 int16_t cursor_x, cursor_y;
321 int16_t cursor_width, cursor_height;
324 struct intel_crtc_config config;
326 uint32_t ddi_pll_sel;
328 /* reset counter value when the last flip was submitted */
329 unsigned int reset_counter;
331 /* Access to these should be protected by dev_priv->irq_lock. */
332 bool cpu_fifo_underrun_disabled;
333 bool pch_fifo_underrun_disabled;
337 struct drm_plane base;
340 struct drm_i915_gem_object *obj;
343 u32 lut_r[1024], lut_g[1024], lut_b[1024];
345 unsigned int crtc_w, crtc_h;
346 uint32_t src_x, src_y;
347 uint32_t src_w, src_h;
349 /* Since we need to change the watermarks before/after
350 * enabling/disabling the planes, we need to store the parameters here
351 * as the other pieces of the struct may not reflect the values we want
352 * for the watermark calculations. Currently only Haswell uses this.
356 uint8_t bytes_per_pixel;
357 uint32_t horiz_pixels;
360 void (*update_plane)(struct drm_plane *plane,
361 struct drm_framebuffer *fb,
362 struct drm_i915_gem_object *obj,
363 int crtc_x, int crtc_y,
364 unsigned int crtc_w, unsigned int crtc_h,
365 uint32_t x, uint32_t y,
366 uint32_t src_w, uint32_t src_h);
367 void (*disable_plane)(struct drm_plane *plane);
368 int (*update_colorkey)(struct drm_plane *plane,
369 struct drm_intel_sprite_colorkey *key);
370 void (*get_colorkey)(struct drm_plane *plane,
371 struct drm_intel_sprite_colorkey *key);
374 struct intel_watermark_params {
375 unsigned long fifo_size;
376 unsigned long max_wm;
377 unsigned long default_wm;
378 unsigned long guard_size;
379 unsigned long cacheline_size;
382 struct cxsr_latency {
385 unsigned long fsb_freq;
386 unsigned long mem_freq;
387 unsigned long display_sr;
388 unsigned long display_hpll_disable;
389 unsigned long cursor_sr;
390 unsigned long cursor_hpll_disable;
393 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
394 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
395 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
396 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
397 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
399 #define DIP_HEADER_SIZE 5
401 #define DIP_TYPE_AVI 0x82
402 #define DIP_VERSION_AVI 0x2
403 #define DIP_LEN_AVI 13
404 #define DIP_AVI_PR_1 0
405 #define DIP_AVI_PR_2 1
406 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
407 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
408 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
410 #define DIP_TYPE_SPD 0x83
411 #define DIP_VERSION_SPD 0x1
412 #define DIP_LEN_SPD 25
413 #define DIP_SPD_UNKNOWN 0
414 #define DIP_SPD_DSTB 0x1
415 #define DIP_SPD_DVDP 0x2
416 #define DIP_SPD_DVHS 0x3
417 #define DIP_SPD_HDDVR 0x4
418 #define DIP_SPD_DVC 0x5
419 #define DIP_SPD_DSC 0x6
420 #define DIP_SPD_VCD 0x7
421 #define DIP_SPD_GAME 0x8
422 #define DIP_SPD_PC 0x9
423 #define DIP_SPD_BD 0xa
424 #define DIP_SPD_SCD 0xb
426 struct dip_infoframe {
427 uint8_t type; /* HB0 */
428 uint8_t ver; /* HB1 */
429 uint8_t len; /* HB2 - body len, not including checksum */
430 uint8_t ecc; /* Header ECC */
431 uint8_t checksum; /* PB0 */
434 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
436 /* PB2 - C 7:6, M 5:4, R 3:0 */
438 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
442 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
445 uint16_t top_bar_end;
446 uint16_t bottom_bar_start;
447 uint16_t left_bar_end;
448 uint16_t right_bar_start;
449 } __attribute__ ((packed)) avi;
454 } __attribute__ ((packed)) spd;
456 } __attribute__ ((packed)) body;
457 } __attribute__((packed));
462 uint32_t color_range;
463 bool color_range_auto;
466 enum hdmi_force_audio force_audio;
467 bool rgb_quant_range_selectable;
468 void (*write_infoframe)(struct drm_encoder *encoder,
469 struct dip_infoframe *frame);
470 void (*set_infoframes)(struct drm_encoder *encoder,
471 struct drm_display_mode *adjusted_mode);
474 #define DP_MAX_DOWNSTREAM_PORTS 0x10
475 #define DP_LINK_CONFIGURATION_SIZE 9
479 uint32_t aux_ch_ctl_reg;
481 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
483 enum hdmi_force_audio force_audio;
484 uint32_t color_range;
485 bool color_range_auto;
488 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
489 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
490 struct i2c_adapter adapter;
491 struct i2c_algo_dp_aux_data algo;
492 uint8_t train_set[4];
493 int panel_power_up_delay;
494 int panel_power_down_delay;
495 int panel_power_cycle_delay;
496 int backlight_on_delay;
497 int backlight_off_delay;
498 struct delayed_work panel_vdd_work;
500 struct intel_connector *attached_connector;
503 struct intel_digital_port {
504 struct intel_encoder base;
508 struct intel_hdmi hdmi;
512 vlv_dport_to_channel(struct intel_digital_port *dport)
514 switch (dport->port) {
524 static inline struct drm_crtc *
525 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 return dev_priv->pipe_to_crtc_mapping[pipe];
531 static inline struct drm_crtc *
532 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
534 struct drm_i915_private *dev_priv = dev->dev_private;
535 return dev_priv->plane_to_crtc_mapping[plane];
538 struct intel_unpin_work {
539 struct work_struct work;
540 struct drm_crtc *crtc;
541 struct drm_i915_gem_object *old_fb_obj;
542 struct drm_i915_gem_object *pending_flip_obj;
543 struct drm_pending_vblank_event *event;
545 #define INTEL_FLIP_INACTIVE 0
546 #define INTEL_FLIP_PENDING 1
547 #define INTEL_FLIP_COMPLETE 2
548 bool enable_stall_check;
551 struct intel_fbc_work {
552 struct delayed_work work;
553 struct drm_crtc *crtc;
554 struct drm_framebuffer *fb;
558 int intel_pch_rawclk(struct drm_device *dev);
560 int intel_connector_update_modes(struct drm_connector *connector,
562 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
564 extern void intel_attach_force_audio_property(struct drm_connector *connector);
565 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
567 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
568 extern void intel_crt_init(struct drm_device *dev);
569 extern void intel_hdmi_init(struct drm_device *dev,
570 int hdmi_reg, enum port port);
571 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
572 struct intel_connector *intel_connector);
573 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
574 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
575 struct intel_crtc_config *pipe_config);
576 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
577 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
579 extern void intel_dvo_init(struct drm_device *dev);
580 extern void intel_tv_init(struct drm_device *dev);
581 extern void intel_mark_busy(struct drm_device *dev);
582 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
583 struct intel_ring_buffer *ring);
584 extern void intel_mark_idle(struct drm_device *dev);
585 extern void intel_lvds_init(struct drm_device *dev);
586 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
587 extern void intel_dp_init(struct drm_device *dev, int output_reg,
589 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
590 struct intel_connector *intel_connector);
591 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
592 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
593 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
594 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
595 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
596 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
597 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
598 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
599 struct intel_crtc_config *pipe_config);
600 extern bool intel_dpd_is_edp(struct drm_device *dev);
601 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
602 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
603 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
604 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
605 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
606 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
607 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
608 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
612 extern int intel_panel_init(struct intel_panel *panel,
613 struct drm_display_mode *fixed_mode);
614 extern void intel_panel_fini(struct intel_panel *panel);
616 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
617 struct drm_display_mode *adjusted_mode);
618 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
619 struct intel_crtc_config *pipe_config,
621 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
622 struct intel_crtc_config *pipe_config,
624 extern void intel_panel_set_backlight(struct drm_device *dev,
626 extern int intel_panel_setup_backlight(struct drm_connector *connector);
627 extern void intel_panel_enable_backlight(struct drm_device *dev,
629 extern void intel_panel_disable_backlight(struct drm_device *dev);
630 extern void intel_panel_destroy_backlight(struct drm_device *dev);
631 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
633 struct intel_set_config {
634 struct drm_encoder **save_connector_encoders;
635 struct drm_crtc **save_encoder_crtcs;
641 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
642 int x, int y, struct drm_framebuffer *old_fb);
643 extern void intel_modeset_disable(struct drm_device *dev);
644 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
645 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
646 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
647 extern void intel_encoder_destroy(struct drm_encoder *encoder);
648 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
649 extern void intel_connector_dpms(struct drm_connector *, int mode);
650 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
651 extern void intel_modeset_check_state(struct drm_device *dev);
652 extern void intel_plane_restore(struct drm_plane *plane);
653 extern void intel_plane_disable(struct drm_plane *plane);
656 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
658 return to_intel_connector(connector)->encoder;
661 static inline struct intel_digital_port *
662 enc_to_dig_port(struct drm_encoder *encoder)
664 return container_of(encoder, struct intel_digital_port, base.base);
667 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
669 return &enc_to_dig_port(encoder)->dp;
672 static inline struct intel_digital_port *
673 dp_to_dig_port(struct intel_dp *intel_dp)
675 return container_of(intel_dp, struct intel_digital_port, dp);
678 static inline struct intel_digital_port *
679 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
681 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
684 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
685 struct intel_digital_port *port);
687 extern void intel_connector_attach_encoder(struct intel_connector *connector,
688 struct intel_encoder *encoder);
689 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
691 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
692 struct drm_crtc *crtc);
693 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
694 struct drm_file *file_priv);
695 extern enum transcoder
696 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
698 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
699 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
700 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
701 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
703 struct intel_load_detect_pipe {
704 struct drm_framebuffer *release_fb;
705 bool load_detect_temp;
708 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
709 struct drm_display_mode *mode,
710 struct intel_load_detect_pipe *old);
711 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
712 struct intel_load_detect_pipe *old);
714 extern void intelfb_restore(void);
715 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
716 u16 blue, int regno);
717 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
718 u16 *blue, int regno);
719 extern void intel_enable_clock_gating(struct drm_device *dev);
721 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
722 struct drm_i915_gem_object *obj,
723 struct intel_ring_buffer *pipelined);
724 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
726 extern int intel_framebuffer_init(struct drm_device *dev,
727 struct intel_framebuffer *ifb,
728 struct drm_mode_fb_cmd2 *mode_cmd,
729 struct drm_i915_gem_object *obj);
730 extern int intel_fbdev_init(struct drm_device *dev);
731 extern void intel_fbdev_initial_config(struct drm_device *dev);
732 extern void intel_fbdev_fini(struct drm_device *dev);
733 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
734 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
735 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
736 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
738 extern void intel_setup_overlay(struct drm_device *dev);
739 extern void intel_cleanup_overlay(struct drm_device *dev);
740 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
741 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
742 struct drm_file *file_priv);
743 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
744 struct drm_file *file_priv);
746 extern void intel_fb_output_poll_changed(struct drm_device *dev);
747 extern void intel_fb_restore_mode(struct drm_device *dev);
749 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
751 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
752 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
754 extern void intel_init_clock_gating(struct drm_device *dev);
755 extern void intel_suspend_hw(struct drm_device *dev);
756 extern void intel_write_eld(struct drm_encoder *encoder,
757 struct drm_display_mode *mode);
758 extern void intel_prepare_ddi(struct drm_device *dev);
759 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
760 extern void intel_ddi_init(struct drm_device *dev, enum port port);
762 /* For use by IVB LP watermark workaround in intel_sprite.c */
763 extern void intel_update_watermarks(struct drm_device *dev);
764 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
765 uint32_t sprite_width,
766 int pixel_size, bool enable);
768 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
769 unsigned int tiling_mode,
773 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
774 struct drm_file *file_priv);
775 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
776 struct drm_file *file_priv);
778 /* Power-related functions, located in intel_pm.c */
779 extern void intel_init_pm(struct drm_device *dev);
781 extern bool intel_fbc_enabled(struct drm_device *dev);
782 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
783 extern void intel_update_fbc(struct drm_device *dev);
785 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
786 extern void intel_gpu_ips_teardown(void);
789 extern int i915_init_power_well(struct drm_device *dev);
790 extern void i915_remove_power_well(struct drm_device *dev);
792 extern bool intel_display_power_enabled(struct drm_device *dev,
793 enum intel_display_power_domain domain);
794 extern void intel_init_power_well(struct drm_device *dev);
795 extern void intel_set_power_well(struct drm_device *dev, bool enable);
796 extern void intel_enable_gt_powersave(struct drm_device *dev);
797 extern void intel_disable_gt_powersave(struct drm_device *dev);
798 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
799 extern void ironlake_teardown_rc6(struct drm_device *dev);
801 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
803 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
804 extern void intel_ddi_pll_init(struct drm_device *dev);
805 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
806 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
807 enum transcoder cpu_transcoder);
808 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
809 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
810 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
811 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
812 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
813 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
814 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
816 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
817 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
819 extern void intel_display_handle_reset(struct drm_device *dev);
820 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
823 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
824 enum transcoder pch_transcoder,
827 #endif /* __INTEL_DRV_H__ */