drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33 #include "intel_frontbuffer.h"
  34
  35 /* Limits for overlay size. According to intel doc, the real limits are:
  36  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  37  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  38  * the mininum of both.  */
  39 #define IMAGE_MAX_WIDTH         2048
  40 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  41 /* on 830 and 845 these large limits result in the card hanging */
  42 #define IMAGE_MAX_WIDTH_LEGACY  1024
  43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  44
  45 /* overlay register definitions */
  46 /* OCMD register */
  47 #define OCMD_TILED_SURFACE      (0x1<<19)
  48 #define OCMD_MIRROR_MASK        (0x3<<17)
  49 #define OCMD_MIRROR_MODE        (0x3<<17)
  50 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  51 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  52 #define OCMD_MIRROR_BOTH        (0x3<<17)
  53 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  54 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  55 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  56 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  58 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  60 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  61 #define OCMD_YUV_422_PACKED     (0x8<<10)
  62 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  64 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  65 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  66 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  67 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  68 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  69 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  70 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  71 #define OCMD_TEST_MODE          (0x1<<4)
  72 #define OCMD_BUFFER_SELECT      (0x3<<2)
  73 #define OCMD_BUFFER0            (0x0<<2)
  74 #define OCMD_BUFFER1            (0x1<<2)
  75 #define OCMD_FIELD_SELECT       (0x1<<2)
  76 #define OCMD_FIELD0             (0x0<<1)
  77 #define OCMD_FIELD1             (0x1<<1)
  78 #define OCMD_ENABLE             (0x1<<0)
  79
  80 /* OCONFIG register */
  81 #define OCONF_PIPE_MASK         (0x1<<18)
  82 #define OCONF_PIPE_A            (0x0<<18)
  83 #define OCONF_PIPE_B            (0x1<<18)
  84 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  85 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  86 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  87 #define OCONF_CSC_BYPASS        (0x1<<4)
  88 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  89 #define OCONF_TEST_MODE         (0x1<<2)
  90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  91 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  92
  93 /* DCLRKM (dst-key) register */
  94 #define DST_KEY_ENABLE          (0x1<<31)
  95 #define CLK_RGB24_MASK          0x0
  96 #define CLK_RGB16_MASK          0x070307
  97 #define CLK_RGB15_MASK          0x070707
  98 #define CLK_RGB8I_MASK          0xffffff
  99
 100 #define RGB16_TO_COLORKEY(c) \
 101         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 102 #define RGB15_TO_COLORKEY(c) \
 103         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 104
 105 /* overlay flip addr flag */
 106 #define OFC_UPDATE              0x1
 107
 108 /* polyphase filter coefficients */
 109 #define N_HORIZ_Y_TAPS          5
 110 #define N_VERT_Y_TAPS           3
 111 #define N_HORIZ_UV_TAPS         3
 112 #define N_VERT_UV_TAPS          3
 113 #define N_PHASES                17
 114 #define MAX_TAPS                5
 115
 116 /* memory bufferd overlay registers */
 117 struct overlay_registers {
 118         u32 OBUF_0Y;
 119         u32 OBUF_1Y;
 120         u32 OBUF_0U;
 121         u32 OBUF_0V;
 122         u32 OBUF_1U;
 123         u32 OBUF_1V;
 124         u32 OSTRIDE;
 125         u32 YRGB_VPH;
 126         u32 UV_VPH;
 127         u32 HORZ_PH;
 128         u32 INIT_PHS;
 129         u32 DWINPOS;
 130         u32 DWINSZ;
 131         u32 SWIDTH;
 132         u32 SWIDTHSW;
 133         u32 SHEIGHT;
 134         u32 YRGBSCALE;
 135         u32 UVSCALE;
 136         u32 OCLRC0;
 137         u32 OCLRC1;
 138         u32 DCLRKV;
 139         u32 DCLRKM;
 140         u32 SCLRKVH;
 141         u32 SCLRKVL;
 142         u32 SCLRKEN;
 143         u32 OCONFIG;
 144         u32 OCMD;
 145         u32 RESERVED1; /* 0x6C */
 146         u32 OSTART_0Y;
 147         u32 OSTART_1Y;
 148         u32 OSTART_0U;
 149         u32 OSTART_0V;
 150         u32 OSTART_1U;
 151         u32 OSTART_1V;
 152         u32 OTILEOFF_0Y;
 153         u32 OTILEOFF_1Y;
 154         u32 OTILEOFF_0U;
 155         u32 OTILEOFF_0V;
 156         u32 OTILEOFF_1U;
 157         u32 OTILEOFF_1V;
 158         u32 FASTHSCALE; /* 0xA0 */
 159         u32 UVSCALEV; /* 0xA4 */
 160         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 161         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 162         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 163         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 164         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 165         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 166         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 167         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 168         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 169 };
 170
 171 struct intel_overlay {
 172         struct drm_i915_private *i915;
 173         struct intel_crtc *crtc;
 174         struct i915_vma *vma;
 175         struct i915_vma *old_vma;
 176         bool active;
 177         bool pfit_active;
 178         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 179         u32 color_key:24;
 180         u32 color_key_enabled:1;
 181         u32 brightness, contrast, saturation;
 182         u32 old_xscale, old_yscale;
 183         /* register access */
 184         u32 flip_addr;
 185         struct drm_i915_gem_object *reg_bo;
 186         /* flip handling */
 187         struct i915_gem_active last_flip;
 188 };
 189
 190 static struct overlay_registers __iomem *
 191 intel_overlay_map_regs(struct intel_overlay *overlay)
 192 {
 193         struct drm_i915_private *dev_priv = overlay->i915;
 194         struct overlay_registers __iomem *regs;
 195
 196         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
 197                 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
 198         else
 199                 regs = io_mapping_map_wc(&dev_priv->ggtt.mappable,
 200                                          overlay->flip_addr,
 201                                          PAGE_SIZE);
 202
 203         return regs;
 204 }
 205
 206 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 207                                      struct overlay_registers __iomem *regs)
 208 {
 209         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
 210                 io_mapping_unmap(regs);
 211 }
 212
 213 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 214                                          struct drm_i915_gem_request *req,
 215                                          i915_gem_retire_fn retire)
 216 {
 217         GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
 218                                         &overlay->i915->drm.struct_mutex));
 219         i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
 220                                       &overlay->i915->drm.struct_mutex);
 221         i915_gem_active_set(&overlay->last_flip, req);
 222         i915_add_request(req);
 223 }
 224
 225 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 226                                          struct drm_i915_gem_request *req,
 227                                          i915_gem_retire_fn retire)
 228 {
 229         intel_overlay_submit_request(overlay, req, retire);
 230         return i915_gem_active_retire(&overlay->last_flip,
 231                                       &overlay->i915->drm.struct_mutex);
 232 }
 233
 234 static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
 235 {
 236         struct drm_i915_private *dev_priv = overlay->i915;
 237         struct intel_engine_cs *engine = dev_priv->engine[RCS];
 238
 239         return i915_gem_request_alloc(engine, dev_priv->kernel_context);
 240 }
 241
 242 /* overlay needs to be disable in OCMD reg */
 243 static int intel_overlay_on(struct intel_overlay *overlay)
 244 {
 245         struct drm_i915_private *dev_priv = overlay->i915;
 246         struct drm_i915_gem_request *req;
 247         struct intel_ring *ring;
 248         int ret;
 249
 250         WARN_ON(overlay->active);
 251         WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 252
 253         req = alloc_request(overlay);
 254         if (IS_ERR(req))
 255                 return PTR_ERR(req);
 256
 257         ret = intel_ring_begin(req, 4);
 258         if (ret) {
 259                 i915_add_request_no_flush(req);
 260                 return ret;
 261         }
 262
 263         overlay->active = true;
 264
 265         ring = req->ring;
 266         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 267         intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
 268         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 269         intel_ring_emit(ring, MI_NOOP);
 270         intel_ring_advance(ring);
 271
 272         return intel_overlay_do_wait_request(overlay, req, NULL);
 273 }
 274
 275 /* overlay needs to be enabled in OCMD reg */
 276 static int intel_overlay_continue(struct intel_overlay *overlay,
 277                                   bool load_polyphase_filter)
 278 {
 279         struct drm_i915_private *dev_priv = overlay->i915;
 280         struct drm_i915_gem_request *req;
 281         struct intel_ring *ring;
 282         u32 flip_addr = overlay->flip_addr;
 283         u32 tmp;
 284         int ret;
 285
 286         WARN_ON(!overlay->active);
 287
 288         if (load_polyphase_filter)
 289                 flip_addr |= OFC_UPDATE;
 290
 291         /* check for underruns */
 292         tmp = I915_READ(DOVSTA);
 293         if (tmp & (1 << 17))
 294                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 295
 296         req = alloc_request(overlay);
 297         if (IS_ERR(req))
 298                 return PTR_ERR(req);
 299
 300         ret = intel_ring_begin(req, 2);
 301         if (ret) {
 302                 i915_add_request_no_flush(req);
 303                 return ret;
 304         }
 305
 306         ring = req->ring;
 307         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 308         intel_ring_emit(ring, flip_addr);
 309         intel_ring_advance(ring);
 310
 311         intel_overlay_submit_request(overlay, req, NULL);
 312
 313         return 0;
 314 }
 315
 316 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
 317                                                struct drm_i915_gem_request *req)
 318 {
 319         struct intel_overlay *overlay =
 320                 container_of(active, typeof(*overlay), last_flip);
 321         struct i915_vma *vma;
 322
 323         vma = fetch_and_zero(&overlay->old_vma);
 324         if (WARN_ON(!vma))
 325                 return;
 326
 327         i915_gem_track_fb(vma->obj, NULL,
 328                           INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 329
 330         i915_gem_object_unpin_from_display_plane(vma);
 331         i915_vma_put(vma);
 332 }
 333
 334 static void intel_overlay_off_tail(struct i915_gem_active *active,
 335                                    struct drm_i915_gem_request *req)
 336 {
 337         struct intel_overlay *overlay =
 338                 container_of(active, typeof(*overlay), last_flip);
 339         struct i915_vma *vma;
 340
 341         /* never have the overlay hw on without showing a frame */
 342         vma = fetch_and_zero(&overlay->vma);
 343         if (WARN_ON(!vma))
 344                 return;
 345
 346         i915_gem_object_unpin_from_display_plane(vma);
 347         i915_vma_put(vma);
 348
 349         overlay->crtc->overlay = NULL;
 350         overlay->crtc = NULL;
 351         overlay->active = false;
 352 }
 353
 354 /* overlay needs to be disabled in OCMD reg */
 355 static int intel_overlay_off(struct intel_overlay *overlay)
 356 {
 357         struct drm_i915_private *dev_priv = overlay->i915;
 358         struct drm_i915_gem_request *req;
 359         struct intel_ring *ring;
 360         u32 flip_addr = overlay->flip_addr;
 361         int ret;
 362
 363         WARN_ON(!overlay->active);
 364
 365         /* According to intel docs the overlay hw may hang (when switching
 366          * off) without loading the filter coeffs. It is however unclear whether
 367          * this applies to the disabling of the overlay or to the switching off
 368          * of the hw. Do it in both cases */
 369         flip_addr |= OFC_UPDATE;
 370
 371         req = alloc_request(overlay);
 372         if (IS_ERR(req))
 373                 return PTR_ERR(req);
 374
 375         ret = intel_ring_begin(req, 6);
 376         if (ret) {
 377                 i915_add_request_no_flush(req);
 378                 return ret;
 379         }
 380
 381         ring = req->ring;
 382         /* wait for overlay to go idle */
 383         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 384         intel_ring_emit(ring, flip_addr);
 385         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 386         /* turn overlay off */
 387         if (IS_I830(dev_priv)) {
 388                 /* Workaround: Don't disable the overlay fully, since otherwise
 389                  * it dies on the next OVERLAY_ON cmd. */
 390                 intel_ring_emit(ring, MI_NOOP);
 391                 intel_ring_emit(ring, MI_NOOP);
 392                 intel_ring_emit(ring, MI_NOOP);
 393         } else {
 394                 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 395                 intel_ring_emit(ring, flip_addr);
 396                 intel_ring_emit(ring,
 397                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 398         }
 399         intel_ring_advance(ring);
 400
 401         return intel_overlay_do_wait_request(overlay, req,
 402                                              intel_overlay_off_tail);
 403 }
 404
 405 /* recover from an interruption due to a signal
 406  * We have to be careful not to repeat work forever an make forward progess. */
 407 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 408 {
 409         return i915_gem_active_retire(&overlay->last_flip,
 410                                       &overlay->i915->drm.struct_mutex);
 411 }
 412
 413 /* Wait for pending overlay flip and release old frame.
 414  * Needs to be called before the overlay register are changed
 415  * via intel_overlay_(un)map_regs
 416  */
 417 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 418 {
 419         struct drm_i915_private *dev_priv = overlay->i915;
 420         int ret;
 421
 422         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 423
 424         /* Only wait if there is actually an old frame to release to
 425          * guarantee forward progress.
 426          */
 427         if (!overlay->old_vma)
 428                 return 0;
 429
 430         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 431                 /* synchronous slowpath */
 432                 struct drm_i915_gem_request *req;
 433                 struct intel_ring *ring;
 434
 435                 req = alloc_request(overlay);
 436                 if (IS_ERR(req))
 437                         return PTR_ERR(req);
 438
 439                 ret = intel_ring_begin(req, 2);
 440                 if (ret) {
 441                         i915_add_request_no_flush(req);
 442                         return ret;
 443                 }
 444
 445                 ring = req->ring;
 446                 intel_ring_emit(ring,
 447                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 448                 intel_ring_emit(ring, MI_NOOP);
 449                 intel_ring_advance(ring);
 450
 451                 ret = intel_overlay_do_wait_request(overlay, req,
 452                                                     intel_overlay_release_old_vid_tail);
 453                 if (ret)
 454                         return ret;
 455         } else
 456                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 457
 458         return 0;
 459 }
 460
 461 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 462 {
 463         struct intel_overlay *overlay = dev_priv->overlay;
 464
 465         if (!overlay)
 466                 return;
 467
 468         intel_overlay_release_old_vid(overlay);
 469
 470         overlay->old_xscale = 0;
 471         overlay->old_yscale = 0;
 472         overlay->crtc = NULL;
 473         overlay->active = false;
 474 }
 475
 476 struct put_image_params {
 477         int format;
 478         short dst_x;
 479         short dst_y;
 480         short dst_w;
 481         short dst_h;
 482         short src_w;
 483         short src_scan_h;
 484         short src_scan_w;
 485         short src_h;
 486         short stride_Y;
 487         short stride_UV;
 488         int offset_Y;
 489         int offset_U;
 490         int offset_V;
 491 };
 492
 493 static int packed_depth_bytes(u32 format)
 494 {
 495         switch (format & I915_OVERLAY_DEPTH_MASK) {
 496         case I915_OVERLAY_YUV422:
 497                 return 4;
 498         case I915_OVERLAY_YUV411:
 499                 /* return 6; not implemented */
 500         default:
 501                 return -EINVAL;
 502         }
 503 }
 504
 505 static int packed_width_bytes(u32 format, short width)
 506 {
 507         switch (format & I915_OVERLAY_DEPTH_MASK) {
 508         case I915_OVERLAY_YUV422:
 509                 return width << 1;
 510         default:
 511                 return -EINVAL;
 512         }
 513 }
 514
 515 static int uv_hsubsampling(u32 format)
 516 {
 517         switch (format & I915_OVERLAY_DEPTH_MASK) {
 518         case I915_OVERLAY_YUV422:
 519         case I915_OVERLAY_YUV420:
 520                 return 2;
 521         case I915_OVERLAY_YUV411:
 522         case I915_OVERLAY_YUV410:
 523                 return 4;
 524         default:
 525                 return -EINVAL;
 526         }
 527 }
 528
 529 static int uv_vsubsampling(u32 format)
 530 {
 531         switch (format & I915_OVERLAY_DEPTH_MASK) {
 532         case I915_OVERLAY_YUV420:
 533         case I915_OVERLAY_YUV410:
 534                 return 2;
 535         case I915_OVERLAY_YUV422:
 536         case I915_OVERLAY_YUV411:
 537                 return 1;
 538         default:
 539                 return -EINVAL;
 540         }
 541 }
 542
 543 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 544 {
 545         u32 mask, shift, ret;
 546         if (IS_GEN2(dev_priv)) {
 547                 mask = 0x1f;
 548                 shift = 5;
 549         } else {
 550                 mask = 0x3f;
 551                 shift = 6;
 552         }
 553         ret = ((offset + width + mask) >> shift) - (offset >> shift);
 554         if (!IS_GEN2(dev_priv))
 555                 ret <<= 1;
 556         ret -= 1;
 557         return ret << 2;
 558 }
 559
 560 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
 561         0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
 562         0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
 563         0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
 564         0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
 565         0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
 566         0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
 567         0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
 568         0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
 569         0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
 570         0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
 571         0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
 572         0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
 573         0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
 574         0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
 575         0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
 576         0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
 577         0xb000, 0x3000, 0x0800, 0x3000, 0xb000
 578 };
 579
 580 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
 581         0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
 582         0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
 583         0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
 584         0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
 585         0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
 586         0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
 587         0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
 588         0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
 589         0x3000, 0x0800, 0x3000
 590 };
 591
 592 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 593 {
 594         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 595         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 596                     sizeof(uv_static_hcoeffs));
 597 }
 598
 599 static bool update_scaling_factors(struct intel_overlay *overlay,
 600                                    struct overlay_registers __iomem *regs,
 601                                    struct put_image_params *params)
 602 {
 603         /* fixed point with a 12 bit shift */
 604         u32 xscale, yscale, xscale_UV, yscale_UV;
 605 #define FP_SHIFT 12
 606 #define FRACT_MASK 0xfff
 607         bool scale_changed = false;
 608         int uv_hscale = uv_hsubsampling(params->format);
 609         int uv_vscale = uv_vsubsampling(params->format);
 610
 611         if (params->dst_w > 1)
 612                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 613                         /(params->dst_w);
 614         else
 615                 xscale = 1 << FP_SHIFT;
 616
 617         if (params->dst_h > 1)
 618                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 619                         /(params->dst_h);
 620         else
 621                 yscale = 1 << FP_SHIFT;
 622
 623         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 624         xscale_UV = xscale/uv_hscale;
 625         yscale_UV = yscale/uv_vscale;
 626         /* make the Y scale to UV scale ratio an exact multiply */
 627         xscale = xscale_UV * uv_hscale;
 628         yscale = yscale_UV * uv_vscale;
 629         /*} else {
 630           xscale_UV = 0;
 631           yscale_UV = 0;
 632           }*/
 633
 634         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 635                 scale_changed = true;
 636         overlay->old_xscale = xscale;
 637         overlay->old_yscale = yscale;
 638
 639         iowrite32(((yscale & FRACT_MASK) << 20) |
 640                   ((xscale >> FP_SHIFT)  << 16) |
 641                   ((xscale & FRACT_MASK) << 3),
 642                  &regs->YRGBSCALE);
 643
 644         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 645                   ((xscale_UV >> FP_SHIFT)  << 16) |
 646                   ((xscale_UV & FRACT_MASK) << 3),
 647                  &regs->UVSCALE);
 648
 649         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 650                    ((yscale_UV >> FP_SHIFT) << 0)),
 651                  &regs->UVSCALEV);
 652
 653         if (scale_changed)
 654                 update_polyphase_filter(regs);
 655
 656         return scale_changed;
 657 }
 658
 659 static void update_colorkey(struct intel_overlay *overlay,
 660                             struct overlay_registers __iomem *regs)
 661 {
 662         const struct drm_framebuffer *fb =
 663                 overlay->crtc->base.primary->fb;
 664         u32 key = overlay->color_key;
 665         u32 flags;
 666
 667         flags = 0;
 668         if (overlay->color_key_enabled)
 669                 flags |= DST_KEY_ENABLE;
 670
 671         switch (fb->format->format) {
 672         case DRM_FORMAT_C8:
 673                 key = 0;
 674                 flags |= CLK_RGB8I_MASK;
 675                 break;
 676         case DRM_FORMAT_XRGB1555:
 677                 key = RGB15_TO_COLORKEY(key);
 678                 flags |= CLK_RGB15_MASK;
 679                 break;
 680         case DRM_FORMAT_RGB565:
 681                 key = RGB16_TO_COLORKEY(key);
 682                 flags |= CLK_RGB16_MASK;
 683                 break;
 684         default:
 685                 flags |= CLK_RGB24_MASK;
 686                 break;
 687         }
 688
 689         iowrite32(key, &regs->DCLRKV);
 690         iowrite32(flags, &regs->DCLRKM);
 691 }
 692
 693 static u32 overlay_cmd_reg(struct put_image_params *params)
 694 {
 695         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 696
 697         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 698                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 699                 case I915_OVERLAY_YUV422:
 700                         cmd |= OCMD_YUV_422_PLANAR;
 701                         break;
 702                 case I915_OVERLAY_YUV420:
 703                         cmd |= OCMD_YUV_420_PLANAR;
 704                         break;
 705                 case I915_OVERLAY_YUV411:
 706                 case I915_OVERLAY_YUV410:
 707                         cmd |= OCMD_YUV_410_PLANAR;
 708                         break;
 709                 }
 710         } else { /* YUV packed */
 711                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 712                 case I915_OVERLAY_YUV422:
 713                         cmd |= OCMD_YUV_422_PACKED;
 714                         break;
 715                 case I915_OVERLAY_YUV411:
 716                         cmd |= OCMD_YUV_411_PACKED;
 717                         break;
 718                 }
 719
 720                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 721                 case I915_OVERLAY_NO_SWAP:
 722                         break;
 723                 case I915_OVERLAY_UV_SWAP:
 724                         cmd |= OCMD_UV_SWAP;
 725                         break;
 726                 case I915_OVERLAY_Y_SWAP:
 727                         cmd |= OCMD_Y_SWAP;
 728                         break;
 729                 case I915_OVERLAY_Y_AND_UV_SWAP:
 730                         cmd |= OCMD_Y_AND_UV_SWAP;
 731                         break;
 732                 }
 733         }
 734
 735         return cmd;
 736 }
 737
 738 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 739                                       struct drm_i915_gem_object *new_bo,
 740                                       struct put_image_params *params)
 741 {
 742         int ret, tmp_width;
 743         struct overlay_registers __iomem *regs;
 744         bool scale_changed = false;
 745         struct drm_i915_private *dev_priv = overlay->i915;
 746         u32 swidth, swidthsw, sheight, ostride;
 747         enum pipe pipe = overlay->crtc->pipe;
 748         struct i915_vma *vma;
 749
 750         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 751         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 752
 753         ret = intel_overlay_release_old_vid(overlay);
 754         if (ret != 0)
 755                 return ret;
 756
 757         vma = i915_gem_object_pin_to_display_plane(new_bo, 0,
 758                                                    &i915_ggtt_view_normal);
 759         if (IS_ERR(vma))
 760                 return PTR_ERR(vma);
 761
 762         ret = i915_vma_put_fence(vma);
 763         if (ret)
 764                 goto out_unpin;
 765
 766         if (!overlay->active) {
 767                 u32 oconfig;
 768                 regs = intel_overlay_map_regs(overlay);
 769                 if (!regs) {
 770                         ret = -ENOMEM;
 771                         goto out_unpin;
 772                 }
 773                 oconfig = OCONF_CC_OUT_8BIT;
 774                 if (IS_GEN4(dev_priv))
 775                         oconfig |= OCONF_CSC_MODE_BT709;
 776                 oconfig |= pipe == 0 ?
 777                         OCONF_PIPE_A : OCONF_PIPE_B;
 778                 iowrite32(oconfig, &regs->OCONFIG);
 779                 intel_overlay_unmap_regs(overlay, regs);
 780
 781                 ret = intel_overlay_on(overlay);
 782                 if (ret != 0)
 783                         goto out_unpin;
 784         }
 785
 786         regs = intel_overlay_map_regs(overlay);
 787         if (!regs) {
 788                 ret = -ENOMEM;
 789                 goto out_unpin;
 790         }
 791
 792         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 793         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 794
 795         if (params->format & I915_OVERLAY_YUV_PACKED)
 796                 tmp_width = packed_width_bytes(params->format, params->src_w);
 797         else
 798                 tmp_width = params->src_w;
 799
 800         swidth = params->src_w;
 801         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 802         sheight = params->src_h;
 803         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 804         ostride = params->stride_Y;
 805
 806         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 807                 int uv_hscale = uv_hsubsampling(params->format);
 808                 int uv_vscale = uv_vsubsampling(params->format);
 809                 u32 tmp_U, tmp_V;
 810                 swidth |= (params->src_w/uv_hscale) << 16;
 811                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 812                                       params->src_w/uv_hscale);
 813                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 814                                       params->src_w/uv_hscale);
 815                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 816                 sheight |= (params->src_h/uv_vscale) << 16;
 817                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 818                           &regs->OBUF_0U);
 819                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 820                           &regs->OBUF_0V);
 821                 ostride |= params->stride_UV << 16;
 822         }
 823
 824         iowrite32(swidth, &regs->SWIDTH);
 825         iowrite32(swidthsw, &regs->SWIDTHSW);
 826         iowrite32(sheight, &regs->SHEIGHT);
 827         iowrite32(ostride, &regs->OSTRIDE);
 828
 829         scale_changed = update_scaling_factors(overlay, regs, params);
 830
 831         update_colorkey(overlay, regs);
 832
 833         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 834
 835         intel_overlay_unmap_regs(overlay, regs);
 836
 837         ret = intel_overlay_continue(overlay, scale_changed);
 838         if (ret)
 839                 goto out_unpin;
 840
 841         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 842                           vma->obj, INTEL_FRONTBUFFER_OVERLAY(pipe));
 843
 844         overlay->old_vma = overlay->vma;
 845         overlay->vma = vma;
 846
 847         intel_frontbuffer_flip(dev_priv, INTEL_FRONTBUFFER_OVERLAY(pipe));
 848
 849         return 0;
 850
 851 out_unpin:
 852         i915_gem_object_unpin_from_display_plane(vma);
 853         return ret;
 854 }
 855
 856 int intel_overlay_switch_off(struct intel_overlay *overlay)
 857 {
 858         struct drm_i915_private *dev_priv = overlay->i915;
 859         struct overlay_registers __iomem *regs;
 860         int ret;
 861
 862         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 863         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 864
 865         ret = intel_overlay_recover_from_interrupt(overlay);
 866         if (ret != 0)
 867                 return ret;
 868
 869         if (!overlay->active)
 870                 return 0;
 871
 872         ret = intel_overlay_release_old_vid(overlay);
 873         if (ret != 0)
 874                 return ret;
 875
 876         regs = intel_overlay_map_regs(overlay);
 877         iowrite32(0, &regs->OCMD);
 878         intel_overlay_unmap_regs(overlay, regs);
 879
 880         return intel_overlay_off(overlay);
 881 }
 882
 883 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 884                                           struct intel_crtc *crtc)
 885 {
 886         if (!crtc->active)
 887                 return -EINVAL;
 888
 889         /* can't use the overlay with double wide pipe */
 890         if (crtc->config->double_wide)
 891                 return -EINVAL;
 892
 893         return 0;
 894 }
 895
 896 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 897 {
 898         struct drm_i915_private *dev_priv = overlay->i915;
 899         u32 pfit_control = I915_READ(PFIT_CONTROL);
 900         u32 ratio;
 901
 902         /* XXX: This is not the same logic as in the xorg driver, but more in
 903          * line with the intel documentation for the i965
 904          */
 905         if (INTEL_GEN(dev_priv) >= 4) {
 906                 /* on i965 use the PGM reg to read out the autoscaler values */
 907                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 908         } else {
 909                 if (pfit_control & VERT_AUTO_SCALE)
 910                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 911                 else
 912                         ratio = I915_READ(PFIT_PGM_RATIOS);
 913                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 914         }
 915
 916         overlay->pfit_vscale_ratio = ratio;
 917 }
 918
 919 static int check_overlay_dst(struct intel_overlay *overlay,
 920                              struct drm_intel_overlay_put_image *rec)
 921 {
 922         struct drm_display_mode *mode = &overlay->crtc->base.mode;
 923
 924         if (rec->dst_x < mode->hdisplay &&
 925             rec->dst_x + rec->dst_width <= mode->hdisplay &&
 926             rec->dst_y < mode->vdisplay &&
 927             rec->dst_y + rec->dst_height <= mode->vdisplay)
 928                 return 0;
 929         else
 930                 return -EINVAL;
 931 }
 932
 933 static int check_overlay_scaling(struct put_image_params *rec)
 934 {
 935         u32 tmp;
 936
 937         /* downscaling limit is 8.0 */
 938         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 939         if (tmp > 7)
 940                 return -EINVAL;
 941         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 942         if (tmp > 7)
 943                 return -EINVAL;
 944
 945         return 0;
 946 }
 947
 948 static int check_overlay_src(struct drm_i915_private *dev_priv,
 949                              struct drm_intel_overlay_put_image *rec,
 950                              struct drm_i915_gem_object *new_bo)
 951 {
 952         int uv_hscale = uv_hsubsampling(rec->flags);
 953         int uv_vscale = uv_vsubsampling(rec->flags);
 954         u32 stride_mask;
 955         int depth;
 956         u32 tmp;
 957
 958         /* check src dimensions */
 959         if (IS_845G(dev_priv) || IS_I830(dev_priv)) {
 960                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 961                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 962                         return -EINVAL;
 963         } else {
 964                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 965                     rec->src_width  > IMAGE_MAX_WIDTH)
 966                         return -EINVAL;
 967         }
 968
 969         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 970         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 971             rec->src_width  < N_HORIZ_Y_TAPS*4)
 972                 return -EINVAL;
 973
 974         /* check alignment constraints */
 975         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 976         case I915_OVERLAY_RGB:
 977                 /* not implemented */
 978                 return -EINVAL;
 979
 980         case I915_OVERLAY_YUV_PACKED:
 981                 if (uv_vscale != 1)
 982                         return -EINVAL;
 983
 984                 depth = packed_depth_bytes(rec->flags);
 985                 if (depth < 0)
 986                         return depth;
 987
 988                 /* ignore UV planes */
 989                 rec->stride_UV = 0;
 990                 rec->offset_U = 0;
 991                 rec->offset_V = 0;
 992                 /* check pixel alignment */
 993                 if (rec->offset_Y % depth)
 994                         return -EINVAL;
 995                 break;
 996
 997         case I915_OVERLAY_YUV_PLANAR:
 998                 if (uv_vscale < 0 || uv_hscale < 0)
 999                         return -EINVAL;
1000                 /* no offset restrictions for planar formats */
1001                 break;
1002
1003         default:
1004                 return -EINVAL;
1005         }
1006
1007         if (rec->src_width % uv_hscale)
1008                 return -EINVAL;
1009
1010         /* stride checking */
1011         if (IS_I830(dev_priv) || IS_845G(dev_priv))
1012                 stride_mask = 255;
1013         else
1014                 stride_mask = 63;
1015
1016         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1017                 return -EINVAL;
1018         if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
1019                 return -EINVAL;
1020
1021         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1022                 4096 : 8192;
1023         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1024                 return -EINVAL;
1025
1026         /* check buffer dimensions */
1027         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1028         case I915_OVERLAY_RGB:
1029         case I915_OVERLAY_YUV_PACKED:
1030                 /* always 4 Y values per depth pixels */
1031                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1032                         return -EINVAL;
1033
1034                 tmp = rec->stride_Y*rec->src_height;
1035                 if (rec->offset_Y + tmp > new_bo->base.size)
1036                         return -EINVAL;
1037                 break;
1038
1039         case I915_OVERLAY_YUV_PLANAR:
1040                 if (rec->src_width > rec->stride_Y)
1041                         return -EINVAL;
1042                 if (rec->src_width/uv_hscale > rec->stride_UV)
1043                         return -EINVAL;
1044
1045                 tmp = rec->stride_Y * rec->src_height;
1046                 if (rec->offset_Y + tmp > new_bo->base.size)
1047                         return -EINVAL;
1048
1049                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1050                 if (rec->offset_U + tmp > new_bo->base.size ||
1051                     rec->offset_V + tmp > new_bo->base.size)
1052                         return -EINVAL;
1053                 break;
1054         }
1055
1056         return 0;
1057 }
1058
1059 /**
1060  * Return the pipe currently connected to the panel fitter,
1061  * or -1 if the panel fitter is not present or not in use
1062  */
1063 static int intel_panel_fitter_pipe(struct drm_i915_private *dev_priv)
1064 {
1065         u32  pfit_control;
1066
1067         /* i830 doesn't have a panel fitter */
1068         if (INTEL_GEN(dev_priv) <= 3 &&
1069             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
1070                 return -1;
1071
1072         pfit_control = I915_READ(PFIT_CONTROL);
1073
1074         /* See if the panel fitter is in use */
1075         if ((pfit_control & PFIT_ENABLE) == 0)
1076                 return -1;
1077
1078         /* 965 can place panel fitter on either pipe */
1079         if (IS_GEN4(dev_priv))
1080                 return (pfit_control >> 29) & 0x3;
1081
1082         /* older chips can only use pipe 1 */
1083         return 1;
1084 }
1085
1086 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1087                                   struct drm_file *file_priv)
1088 {
1089         struct drm_intel_overlay_put_image *put_image_rec = data;
1090         struct drm_i915_private *dev_priv = to_i915(dev);
1091         struct intel_overlay *overlay;
1092         struct drm_crtc *drmmode_crtc;
1093         struct intel_crtc *crtc;
1094         struct drm_i915_gem_object *new_bo;
1095         struct put_image_params *params;
1096         int ret;
1097
1098         overlay = dev_priv->overlay;
1099         if (!overlay) {
1100                 DRM_DEBUG("userspace bug: no overlay\n");
1101                 return -ENODEV;
1102         }
1103
1104         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1105                 drm_modeset_lock_all(dev);
1106                 mutex_lock(&dev->struct_mutex);
1107
1108                 ret = intel_overlay_switch_off(overlay);
1109
1110                 mutex_unlock(&dev->struct_mutex);
1111                 drm_modeset_unlock_all(dev);
1112
1113                 return ret;
1114         }
1115
1116         params = kmalloc(sizeof(*params), GFP_KERNEL);
1117         if (!params)
1118                 return -ENOMEM;
1119
1120         drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1121         if (!drmmode_crtc) {
1122                 ret = -ENOENT;
1123                 goto out_free;
1124         }
1125         crtc = to_intel_crtc(drmmode_crtc);
1126
1127         new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle);
1128         if (!new_bo) {
1129                 ret = -ENOENT;
1130                 goto out_free;
1131         }
1132
1133         drm_modeset_lock_all(dev);
1134         mutex_lock(&dev->struct_mutex);
1135
1136         if (i915_gem_object_is_tiled(new_bo)) {
1137                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1138                 ret = -EINVAL;
1139                 goto out_unlock;
1140         }
1141
1142         ret = intel_overlay_recover_from_interrupt(overlay);
1143         if (ret != 0)
1144                 goto out_unlock;
1145
1146         if (overlay->crtc != crtc) {
1147                 struct drm_display_mode *mode = &crtc->base.mode;
1148                 ret = intel_overlay_switch_off(overlay);
1149                 if (ret != 0)
1150                         goto out_unlock;
1151
1152                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1153                 if (ret != 0)
1154                         goto out_unlock;
1155
1156                 overlay->crtc = crtc;
1157                 crtc->overlay = overlay;
1158
1159                 /* line too wide, i.e. one-line-mode */
1160                 if (mode->hdisplay > 1024 &&
1161                     intel_panel_fitter_pipe(dev_priv) == crtc->pipe) {
1162                         overlay->pfit_active = true;
1163                         update_pfit_vscale_ratio(overlay);
1164                 } else
1165                         overlay->pfit_active = false;
1166         }
1167
1168         ret = check_overlay_dst(overlay, put_image_rec);
1169         if (ret != 0)
1170                 goto out_unlock;
1171
1172         if (overlay->pfit_active) {
1173                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1174                                  overlay->pfit_vscale_ratio);
1175                 /* shifting right rounds downwards, so add 1 */
1176                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1177                                  overlay->pfit_vscale_ratio) + 1;
1178         } else {
1179                 params->dst_y = put_image_rec->dst_y;
1180                 params->dst_h = put_image_rec->dst_height;
1181         }
1182         params->dst_x = put_image_rec->dst_x;
1183         params->dst_w = put_image_rec->dst_width;
1184
1185         params->src_w = put_image_rec->src_width;
1186         params->src_h = put_image_rec->src_height;
1187         params->src_scan_w = put_image_rec->src_scan_width;
1188         params->src_scan_h = put_image_rec->src_scan_height;
1189         if (params->src_scan_h > params->src_h ||
1190             params->src_scan_w > params->src_w) {
1191                 ret = -EINVAL;
1192                 goto out_unlock;
1193         }
1194
1195         ret = check_overlay_src(dev_priv, put_image_rec, new_bo);
1196         if (ret != 0)
1197                 goto out_unlock;
1198         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1199         params->stride_Y = put_image_rec->stride_Y;
1200         params->stride_UV = put_image_rec->stride_UV;
1201         params->offset_Y = put_image_rec->offset_Y;
1202         params->offset_U = put_image_rec->offset_U;
1203         params->offset_V = put_image_rec->offset_V;
1204
1205         /* Check scaling after src size to prevent a divide-by-zero. */
1206         ret = check_overlay_scaling(params);
1207         if (ret != 0)
1208                 goto out_unlock;
1209
1210         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1211         if (ret != 0)
1212                 goto out_unlock;
1213
1214         mutex_unlock(&dev->struct_mutex);
1215         drm_modeset_unlock_all(dev);
1216
1217         kfree(params);
1218
1219         return 0;
1220
1221 out_unlock:
1222         mutex_unlock(&dev->struct_mutex);
1223         drm_modeset_unlock_all(dev);
1224         i915_gem_object_put(new_bo);
1225 out_free:
1226         kfree(params);
1227
1228         return ret;
1229 }
1230
1231 static void update_reg_attrs(struct intel_overlay *overlay,
1232                              struct overlay_registers __iomem *regs)
1233 {
1234         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1235                   &regs->OCLRC0);
1236         iowrite32(overlay->saturation, &regs->OCLRC1);
1237 }
1238
1239 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1240 {
1241         int i;
1242
1243         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1244                 return false;
1245
1246         for (i = 0; i < 3; i++) {
1247                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1248                         return false;
1249         }
1250
1251         return true;
1252 }
1253
1254 static bool check_gamma5_errata(u32 gamma5)
1255 {
1256         int i;
1257
1258         for (i = 0; i < 3; i++) {
1259                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1260                         return false;
1261         }
1262
1263         return true;
1264 }
1265
1266 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1267 {
1268         if (!check_gamma_bounds(0, attrs->gamma0) ||
1269             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1270             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1271             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1272             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1273             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1274             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1275                 return -EINVAL;
1276
1277         if (!check_gamma5_errata(attrs->gamma5))
1278                 return -EINVAL;
1279
1280         return 0;
1281 }
1282
1283 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1284                               struct drm_file *file_priv)
1285 {
1286         struct drm_intel_overlay_attrs *attrs = data;
1287         struct drm_i915_private *dev_priv = to_i915(dev);
1288         struct intel_overlay *overlay;
1289         struct overlay_registers __iomem *regs;
1290         int ret;
1291
1292         overlay = dev_priv->overlay;
1293         if (!overlay) {
1294                 DRM_DEBUG("userspace bug: no overlay\n");
1295                 return -ENODEV;
1296         }
1297
1298         drm_modeset_lock_all(dev);
1299         mutex_lock(&dev->struct_mutex);
1300
1301         ret = -EINVAL;
1302         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1303                 attrs->color_key  = overlay->color_key;
1304                 attrs->brightness = overlay->brightness;
1305                 attrs->contrast   = overlay->contrast;
1306                 attrs->saturation = overlay->saturation;
1307
1308                 if (!IS_GEN2(dev_priv)) {
1309                         attrs->gamma0 = I915_READ(OGAMC0);
1310                         attrs->gamma1 = I915_READ(OGAMC1);
1311                         attrs->gamma2 = I915_READ(OGAMC2);
1312                         attrs->gamma3 = I915_READ(OGAMC3);
1313                         attrs->gamma4 = I915_READ(OGAMC4);
1314                         attrs->gamma5 = I915_READ(OGAMC5);
1315                 }
1316         } else {
1317                 if (attrs->brightness < -128 || attrs->brightness > 127)
1318                         goto out_unlock;
1319                 if (attrs->contrast > 255)
1320                         goto out_unlock;
1321                 if (attrs->saturation > 1023)
1322                         goto out_unlock;
1323
1324                 overlay->color_key  = attrs->color_key;
1325                 overlay->brightness = attrs->brightness;
1326                 overlay->contrast   = attrs->contrast;
1327                 overlay->saturation = attrs->saturation;
1328
1329                 regs = intel_overlay_map_regs(overlay);
1330                 if (!regs) {
1331                         ret = -ENOMEM;
1332                         goto out_unlock;
1333                 }
1334
1335                 update_reg_attrs(overlay, regs);
1336
1337                 intel_overlay_unmap_regs(overlay, regs);
1338
1339                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1340                         if (IS_GEN2(dev_priv))
1341                                 goto out_unlock;
1342
1343                         if (overlay->active) {
1344                                 ret = -EBUSY;
1345                                 goto out_unlock;
1346                         }
1347
1348                         ret = check_gamma(attrs);
1349                         if (ret)
1350                                 goto out_unlock;
1351
1352                         I915_WRITE(OGAMC0, attrs->gamma0);
1353                         I915_WRITE(OGAMC1, attrs->gamma1);
1354                         I915_WRITE(OGAMC2, attrs->gamma2);
1355                         I915_WRITE(OGAMC3, attrs->gamma3);
1356                         I915_WRITE(OGAMC4, attrs->gamma4);
1357                         I915_WRITE(OGAMC5, attrs->gamma5);
1358                 }
1359         }
1360         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1361
1362         ret = 0;
1363 out_unlock:
1364         mutex_unlock(&dev->struct_mutex);
1365         drm_modeset_unlock_all(dev);
1366
1367         return ret;
1368 }
1369
1370 void intel_setup_overlay(struct drm_i915_private *dev_priv)
1371 {
1372         struct intel_overlay *overlay;
1373         struct drm_i915_gem_object *reg_bo;
1374         struct overlay_registers __iomem *regs;
1375         struct i915_vma *vma = NULL;
1376         int ret;
1377
1378         if (!HAS_OVERLAY(dev_priv))
1379                 return;
1380
1381         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1382         if (!overlay)
1383                 return;
1384
1385         mutex_lock(&dev_priv->drm.struct_mutex);
1386         if (WARN_ON(dev_priv->overlay))
1387                 goto out_free;
1388
1389         overlay->i915 = dev_priv;
1390
1391         reg_bo = NULL;
1392         if (!OVERLAY_NEEDS_PHYSICAL(dev_priv))
1393                 reg_bo = i915_gem_object_create_stolen(&dev_priv->drm,
1394                                                        PAGE_SIZE);
1395         if (reg_bo == NULL)
1396                 reg_bo = i915_gem_object_create(&dev_priv->drm, PAGE_SIZE);
1397         if (IS_ERR(reg_bo))
1398                 goto out_free;
1399         overlay->reg_bo = reg_bo;
1400
1401         if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) {
1402                 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1403                 if (ret) {
1404                         DRM_ERROR("failed to attach phys overlay regs\n");
1405                         goto out_free_bo;
1406                 }
1407                 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1408         } else {
1409                 vma = i915_gem_object_ggtt_pin(reg_bo, NULL,
1410                                                0, PAGE_SIZE, PIN_MAPPABLE);
1411                 if (IS_ERR(vma)) {
1412                         DRM_ERROR("failed to pin overlay register bo\n");
1413                         ret = PTR_ERR(vma);
1414                         goto out_free_bo;
1415                 }
1416                 overlay->flip_addr = i915_ggtt_offset(vma);
1417
1418                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1419                 if (ret) {
1420                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1421                         goto out_unpin_bo;
1422                 }
1423         }
1424
1425         /* init all values */
1426         overlay->color_key = 0x0101fe;
1427         overlay->color_key_enabled = true;
1428         overlay->brightness = -19;
1429         overlay->contrast = 75;
1430         overlay->saturation = 146;
1431
1432         init_request_active(&overlay->last_flip, NULL);
1433
1434         regs = intel_overlay_map_regs(overlay);
1435         if (!regs)
1436                 goto out_unpin_bo;
1437
1438         memset_io(regs, 0, sizeof(struct overlay_registers));
1439         update_polyphase_filter(regs);
1440         update_reg_attrs(overlay, regs);
1441
1442         intel_overlay_unmap_regs(overlay, regs);
1443
1444         dev_priv->overlay = overlay;
1445         mutex_unlock(&dev_priv->drm.struct_mutex);
1446         DRM_INFO("initialized overlay support\n");
1447         return;
1448
1449 out_unpin_bo:
1450         if (vma)
1451                 i915_vma_unpin(vma);
1452 out_free_bo:
1453         i915_gem_object_put(reg_bo);
1454 out_free:
1455         mutex_unlock(&dev_priv->drm.struct_mutex);
1456         kfree(overlay);
1457         return;
1458 }
1459
1460 void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
1461 {
1462         if (!dev_priv->overlay)
1463                 return;
1464
1465         /* The bo's should be free'd by the generic code already.
1466          * Furthermore modesetting teardown happens beforehand so the
1467          * hardware should be off already */
1468         WARN_ON(dev_priv->overlay->active);
1469
1470         i915_gem_object_put(dev_priv->overlay->reg_bo);
1471         kfree(dev_priv->overlay);
1472 }
1473
1474 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1475
1476 struct intel_overlay_error_state {
1477         struct overlay_registers regs;
1478         unsigned long base;
1479         u32 dovsta;
1480         u32 isr;
1481 };
1482
1483 static struct overlay_registers __iomem *
1484 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1485 {
1486         struct drm_i915_private *dev_priv = overlay->i915;
1487         struct overlay_registers __iomem *regs;
1488
1489         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
1490                 /* Cast to make sparse happy, but it's wc memory anyway, so
1491                  * equivalent to the wc io mapping on X86. */
1492                 regs = (struct overlay_registers __iomem *)
1493                         overlay->reg_bo->phys_handle->vaddr;
1494         else
1495                 regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable,
1496                                                 overlay->flip_addr);
1497
1498         return regs;
1499 }
1500
1501 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1502                                         struct overlay_registers __iomem *regs)
1503 {
1504         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
1505                 io_mapping_unmap_atomic(regs);
1506 }
1507
1508 struct intel_overlay_error_state *
1509 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1510 {
1511         struct intel_overlay *overlay = dev_priv->overlay;
1512         struct intel_overlay_error_state *error;
1513         struct overlay_registers __iomem *regs;
1514
1515         if (!overlay || !overlay->active)
1516                 return NULL;
1517
1518         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1519         if (error == NULL)
1520                 return NULL;
1521
1522         error->dovsta = I915_READ(DOVSTA);
1523         error->isr = I915_READ(ISR);
1524         error->base = overlay->flip_addr;
1525
1526         regs = intel_overlay_map_regs_atomic(overlay);
1527         if (!regs)
1528                 goto err;
1529
1530         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1531         intel_overlay_unmap_regs_atomic(overlay, regs);
1532
1533         return error;
1534
1535 err:
1536         kfree(error);
1537         return NULL;
1538 }
1539
1540 void
1541 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1542                                 struct intel_overlay_error_state *error)
1543 {
1544         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1545                           error->dovsta, error->isr);
1546         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1547                           error->base);
1548
1549 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1550         P(OBUF_0Y);
1551         P(OBUF_1Y);
1552         P(OBUF_0U);
1553         P(OBUF_0V);
1554         P(OBUF_1U);
1555         P(OBUF_1V);
1556         P(OSTRIDE);
1557         P(YRGB_VPH);
1558         P(UV_VPH);
1559         P(HORZ_PH);
1560         P(INIT_PHS);
1561         P(DWINPOS);
1562         P(DWINSZ);
1563         P(SWIDTH);
1564         P(SWIDTHSW);
1565         P(SHEIGHT);
1566         P(YRGBSCALE);
1567         P(UVSCALE);
1568         P(OCLRC0);
1569         P(OCLRC1);
1570         P(DCLRKV);
1571         P(DCLRKM);
1572         P(SCLRKVH);
1573         P(SCLRKVL);
1574         P(SCLRKEN);
1575         P(OCONFIG);
1576         P(OCMD);
1577         P(OSTART_0Y);
1578         P(OSTART_1Y);
1579         P(OSTART_0U);
1580         P(OSTART_0V);
1581         P(OSTART_1U);
1582         P(OSTART_1V);
1583         P(OTILEOFF_0Y);
1584         P(OTILEOFF_1Y);
1585         P(OTILEOFF_0U);
1586         P(OTILEOFF_0V);
1587         P(OTILEOFF_1U);
1588         P(OTILEOFF_1V);
1589         P(FASTHSCALE);
1590         P(UVSCALEV);
1591 #undef P
1592 }
1593
1594 #endif