4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
34 /* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38 #define IMAGE_MAX_WIDTH 2048
39 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40 /* on 830 and 845 these large limits result in the card hanging */
41 #define IMAGE_MAX_WIDTH_LEGACY 1024
42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44 /* overlay register definitions */
46 #define OCMD_TILED_SURFACE (0x1<<19)
47 #define OCMD_MIRROR_MASK (0x3<<17)
48 #define OCMD_MIRROR_MODE (0x3<<17)
49 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50 #define OCMD_MIRROR_VERTICAL (0x2<<17)
51 #define OCMD_MIRROR_BOTH (0x3<<17)
52 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60 #define OCMD_YUV_422_PACKED (0x8<<10)
61 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62 #define OCMD_YUV_420_PLANAR (0xc<<10)
63 #define OCMD_YUV_422_PLANAR (0xd<<10)
64 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
67 #define OCMD_BUF_TYPE_MASK (0x1<<5)
68 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
69 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
70 #define OCMD_TEST_MODE (0x1<<4)
71 #define OCMD_BUFFER_SELECT (0x3<<2)
72 #define OCMD_BUFFER0 (0x0<<2)
73 #define OCMD_BUFFER1 (0x1<<2)
74 #define OCMD_FIELD_SELECT (0x1<<2)
75 #define OCMD_FIELD0 (0x0<<1)
76 #define OCMD_FIELD1 (0x1<<1)
77 #define OCMD_ENABLE (0x1<<0)
79 /* OCONFIG register */
80 #define OCONF_PIPE_MASK (0x1<<18)
81 #define OCONF_PIPE_A (0x0<<18)
82 #define OCONF_PIPE_B (0x1<<18)
83 #define OCONF_GAMMA2_ENABLE (0x1<<16)
84 #define OCONF_CSC_MODE_BT601 (0x0<<5)
85 #define OCONF_CSC_MODE_BT709 (0x1<<5)
86 #define OCONF_CSC_BYPASS (0x1<<4)
87 #define OCONF_CC_OUT_8BIT (0x1<<3)
88 #define OCONF_TEST_MODE (0x1<<2)
89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
90 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92 /* DCLRKM (dst-key) register */
93 #define DST_KEY_ENABLE (0x1<<31)
94 #define CLK_RGB24_MASK 0x0
95 #define CLK_RGB16_MASK 0x070307
96 #define CLK_RGB15_MASK 0x070707
97 #define CLK_RGB8I_MASK 0xffffff
99 #define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101 #define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104 /* overlay flip addr flag */
105 #define OFC_UPDATE 0x1
107 /* polyphase filter coefficients */
108 #define N_HORIZ_Y_TAPS 5
109 #define N_VERT_Y_TAPS 3
110 #define N_HORIZ_UV_TAPS 3
111 #define N_VERT_UV_TAPS 3
115 /* memory bufferd overlay registers */
116 struct overlay_registers {
144 u32 RESERVED1; /* 0x6C */
157 u32 FASTHSCALE; /* 0xA0 */
158 u32 UVSCALEV; /* 0xA4 */
159 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
161 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
162 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
163 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
164 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
165 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
166 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
167 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
170 struct intel_overlay {
171 struct drm_device *dev;
172 struct intel_crtc *crtc;
173 struct drm_i915_gem_object *vid_bo;
174 struct drm_i915_gem_object *old_vid_bo;
177 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
179 u32 brightness, contrast, saturation;
180 u32 old_xscale, old_yscale;
181 /* register access */
183 struct drm_i915_gem_object *reg_bo;
185 uint32_t last_flip_req;
186 void (*flip_tail)(struct intel_overlay *);
189 static struct overlay_registers __iomem *
190 intel_overlay_map_regs(struct intel_overlay *overlay)
192 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
193 struct overlay_registers __iomem *regs;
195 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
196 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
198 regs = io_mapping_map_wc(dev_priv->gtt.mappable,
199 i915_gem_obj_ggtt_offset(overlay->reg_bo));
204 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
205 struct overlay_registers __iomem *regs)
207 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
208 io_mapping_unmap(regs);
211 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
212 void (*tail)(struct intel_overlay *))
214 struct drm_device *dev = overlay->dev;
215 struct drm_i915_private *dev_priv = dev->dev_private;
216 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
219 BUG_ON(overlay->last_flip_req);
220 ret = i915_add_request(ring, &overlay->last_flip_req);
224 overlay->flip_tail = tail;
225 ret = i915_wait_seqno(ring, overlay->last_flip_req);
228 i915_gem_retire_requests(dev);
230 overlay->last_flip_req = 0;
234 /* overlay needs to be disable in OCMD reg */
235 static int intel_overlay_on(struct intel_overlay *overlay)
237 struct drm_device *dev = overlay->dev;
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
242 BUG_ON(overlay->active);
245 WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
247 ret = intel_ring_begin(ring, 4);
251 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
252 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
253 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
254 intel_ring_emit(ring, MI_NOOP);
255 intel_ring_advance(ring);
257 return intel_overlay_do_wait_request(overlay, NULL);
260 /* overlay needs to be enabled in OCMD reg */
261 static int intel_overlay_continue(struct intel_overlay *overlay,
262 bool load_polyphase_filter)
264 struct drm_device *dev = overlay->dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
267 u32 flip_addr = overlay->flip_addr;
271 BUG_ON(!overlay->active);
273 if (load_polyphase_filter)
274 flip_addr |= OFC_UPDATE;
276 /* check for underruns */
277 tmp = I915_READ(DOVSTA);
279 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
281 ret = intel_ring_begin(ring, 2);
285 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
286 intel_ring_emit(ring, flip_addr);
287 intel_ring_advance(ring);
289 return i915_add_request(ring, &overlay->last_flip_req);
292 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
294 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
296 i915_gem_object_ggtt_unpin(obj);
297 drm_gem_object_unreference(&obj->base);
299 overlay->old_vid_bo = NULL;
302 static void intel_overlay_off_tail(struct intel_overlay *overlay)
304 struct drm_i915_gem_object *obj = overlay->vid_bo;
306 /* never have the overlay hw on without showing a frame */
307 BUG_ON(!overlay->vid_bo);
309 i915_gem_object_ggtt_unpin(obj);
310 drm_gem_object_unreference(&obj->base);
311 overlay->vid_bo = NULL;
313 overlay->crtc->overlay = NULL;
314 overlay->crtc = NULL;
318 /* overlay needs to be disabled in OCMD reg */
319 static int intel_overlay_off(struct intel_overlay *overlay)
321 struct drm_device *dev = overlay->dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
324 u32 flip_addr = overlay->flip_addr;
327 BUG_ON(!overlay->active);
329 /* According to intel docs the overlay hw may hang (when switching
330 * off) without loading the filter coeffs. It is however unclear whether
331 * this applies to the disabling of the overlay or to the switching off
332 * of the hw. Do it in both cases */
333 flip_addr |= OFC_UPDATE;
335 ret = intel_ring_begin(ring, 6);
339 /* wait for overlay to go idle */
340 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
341 intel_ring_emit(ring, flip_addr);
342 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
343 /* turn overlay off */
345 /* Workaround: Don't disable the overlay fully, since otherwise
346 * it dies on the next OVERLAY_ON cmd. */
347 intel_ring_emit(ring, MI_NOOP);
348 intel_ring_emit(ring, MI_NOOP);
349 intel_ring_emit(ring, MI_NOOP);
351 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
352 intel_ring_emit(ring, flip_addr);
353 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
355 intel_ring_advance(ring);
357 return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
360 /* recover from an interruption due to a signal
361 * We have to be careful not to repeat work forever an make forward progess. */
362 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
364 struct drm_device *dev = overlay->dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
369 if (overlay->last_flip_req == 0)
372 ret = i915_wait_seqno(ring, overlay->last_flip_req);
375 i915_gem_retire_requests(dev);
377 if (overlay->flip_tail)
378 overlay->flip_tail(overlay);
380 overlay->last_flip_req = 0;
384 /* Wait for pending overlay flip and release old frame.
385 * Needs to be called before the overlay register are changed
386 * via intel_overlay_(un)map_regs
388 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
390 struct drm_device *dev = overlay->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
395 /* Only wait if there is actually an old frame to release to
396 * guarantee forward progress.
398 if (!overlay->old_vid_bo)
401 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
402 /* synchronous slowpath */
403 ret = intel_ring_begin(ring, 2);
407 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
408 intel_ring_emit(ring, MI_NOOP);
409 intel_ring_advance(ring);
411 ret = intel_overlay_do_wait_request(overlay,
412 intel_overlay_release_old_vid_tail);
417 intel_overlay_release_old_vid_tail(overlay);
420 i915_gem_track_fb(overlay->old_vid_bo, NULL,
421 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
425 struct put_image_params {
442 static int packed_depth_bytes(u32 format)
444 switch (format & I915_OVERLAY_DEPTH_MASK) {
445 case I915_OVERLAY_YUV422:
447 case I915_OVERLAY_YUV411:
448 /* return 6; not implemented */
454 static int packed_width_bytes(u32 format, short width)
456 switch (format & I915_OVERLAY_DEPTH_MASK) {
457 case I915_OVERLAY_YUV422:
464 static int uv_hsubsampling(u32 format)
466 switch (format & I915_OVERLAY_DEPTH_MASK) {
467 case I915_OVERLAY_YUV422:
468 case I915_OVERLAY_YUV420:
470 case I915_OVERLAY_YUV411:
471 case I915_OVERLAY_YUV410:
478 static int uv_vsubsampling(u32 format)
480 switch (format & I915_OVERLAY_DEPTH_MASK) {
481 case I915_OVERLAY_YUV420:
482 case I915_OVERLAY_YUV410:
484 case I915_OVERLAY_YUV422:
485 case I915_OVERLAY_YUV411:
492 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
494 u32 mask, shift, ret;
502 ret = ((offset + width + mask) >> shift) - (offset >> shift);
509 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
510 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
511 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
512 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
513 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
514 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
515 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
516 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
517 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
518 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
519 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
520 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
521 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
522 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
523 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
524 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
525 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
526 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
529 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
530 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
531 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
532 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
533 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
534 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
535 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
536 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
537 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
538 0x3000, 0x0800, 0x3000
541 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
543 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
544 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
545 sizeof(uv_static_hcoeffs));
548 static bool update_scaling_factors(struct intel_overlay *overlay,
549 struct overlay_registers __iomem *regs,
550 struct put_image_params *params)
552 /* fixed point with a 12 bit shift */
553 u32 xscale, yscale, xscale_UV, yscale_UV;
555 #define FRACT_MASK 0xfff
556 bool scale_changed = false;
557 int uv_hscale = uv_hsubsampling(params->format);
558 int uv_vscale = uv_vsubsampling(params->format);
560 if (params->dst_w > 1)
561 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
564 xscale = 1 << FP_SHIFT;
566 if (params->dst_h > 1)
567 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
570 yscale = 1 << FP_SHIFT;
572 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
573 xscale_UV = xscale/uv_hscale;
574 yscale_UV = yscale/uv_vscale;
575 /* make the Y scale to UV scale ratio an exact multiply */
576 xscale = xscale_UV * uv_hscale;
577 yscale = yscale_UV * uv_vscale;
583 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
584 scale_changed = true;
585 overlay->old_xscale = xscale;
586 overlay->old_yscale = yscale;
588 iowrite32(((yscale & FRACT_MASK) << 20) |
589 ((xscale >> FP_SHIFT) << 16) |
590 ((xscale & FRACT_MASK) << 3),
593 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
594 ((xscale_UV >> FP_SHIFT) << 16) |
595 ((xscale_UV & FRACT_MASK) << 3),
598 iowrite32((((yscale >> FP_SHIFT) << 16) |
599 ((yscale_UV >> FP_SHIFT) << 0)),
603 update_polyphase_filter(regs);
605 return scale_changed;
608 static void update_colorkey(struct intel_overlay *overlay,
609 struct overlay_registers __iomem *regs)
611 u32 key = overlay->color_key;
613 switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
615 iowrite32(0, ®s->DCLRKV);
616 iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, ®s->DCLRKM);
620 if (overlay->crtc->base.primary->fb->depth == 15) {
621 iowrite32(RGB15_TO_COLORKEY(key), ®s->DCLRKV);
622 iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
625 iowrite32(RGB16_TO_COLORKEY(key), ®s->DCLRKV);
626 iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
633 iowrite32(key, ®s->DCLRKV);
634 iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, ®s->DCLRKM);
639 static u32 overlay_cmd_reg(struct put_image_params *params)
641 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
643 if (params->format & I915_OVERLAY_YUV_PLANAR) {
644 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
645 case I915_OVERLAY_YUV422:
646 cmd |= OCMD_YUV_422_PLANAR;
648 case I915_OVERLAY_YUV420:
649 cmd |= OCMD_YUV_420_PLANAR;
651 case I915_OVERLAY_YUV411:
652 case I915_OVERLAY_YUV410:
653 cmd |= OCMD_YUV_410_PLANAR;
656 } else { /* YUV packed */
657 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
658 case I915_OVERLAY_YUV422:
659 cmd |= OCMD_YUV_422_PACKED;
661 case I915_OVERLAY_YUV411:
662 cmd |= OCMD_YUV_411_PACKED;
666 switch (params->format & I915_OVERLAY_SWAP_MASK) {
667 case I915_OVERLAY_NO_SWAP:
669 case I915_OVERLAY_UV_SWAP:
672 case I915_OVERLAY_Y_SWAP:
675 case I915_OVERLAY_Y_AND_UV_SWAP:
676 cmd |= OCMD_Y_AND_UV_SWAP;
684 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
685 struct drm_i915_gem_object *new_bo,
686 struct put_image_params *params)
689 struct overlay_registers __iomem *regs;
690 bool scale_changed = false;
691 struct drm_device *dev = overlay->dev;
692 u32 swidth, swidthsw, sheight, ostride;
693 enum pipe pipe = overlay->crtc->pipe;
695 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
696 BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
699 ret = intel_overlay_release_old_vid(overlay);
703 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
707 ret = i915_gem_object_put_fence(new_bo);
711 if (!overlay->active) {
713 regs = intel_overlay_map_regs(overlay);
718 oconfig = OCONF_CC_OUT_8BIT;
719 if (IS_GEN4(overlay->dev))
720 oconfig |= OCONF_CSC_MODE_BT709;
721 oconfig |= pipe == 0 ?
722 OCONF_PIPE_A : OCONF_PIPE_B;
723 iowrite32(oconfig, ®s->OCONFIG);
724 intel_overlay_unmap_regs(overlay, regs);
726 ret = intel_overlay_on(overlay);
731 regs = intel_overlay_map_regs(overlay);
737 iowrite32((params->dst_y << 16) | params->dst_x, ®s->DWINPOS);
738 iowrite32((params->dst_h << 16) | params->dst_w, ®s->DWINSZ);
740 if (params->format & I915_OVERLAY_YUV_PACKED)
741 tmp_width = packed_width_bytes(params->format, params->src_w);
743 tmp_width = params->src_w;
745 swidth = params->src_w;
746 swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
747 sheight = params->src_h;
748 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, ®s->OBUF_0Y);
749 ostride = params->stride_Y;
751 if (params->format & I915_OVERLAY_YUV_PLANAR) {
752 int uv_hscale = uv_hsubsampling(params->format);
753 int uv_vscale = uv_vsubsampling(params->format);
755 swidth |= (params->src_w/uv_hscale) << 16;
756 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
757 params->src_w/uv_hscale);
758 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
759 params->src_w/uv_hscale);
760 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
761 sheight |= (params->src_h/uv_vscale) << 16;
762 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, ®s->OBUF_0U);
763 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, ®s->OBUF_0V);
764 ostride |= params->stride_UV << 16;
767 iowrite32(swidth, ®s->SWIDTH);
768 iowrite32(swidthsw, ®s->SWIDTHSW);
769 iowrite32(sheight, ®s->SHEIGHT);
770 iowrite32(ostride, ®s->OSTRIDE);
772 scale_changed = update_scaling_factors(overlay, regs, params);
774 update_colorkey(overlay, regs);
776 iowrite32(overlay_cmd_reg(params), ®s->OCMD);
778 intel_overlay_unmap_regs(overlay, regs);
780 ret = intel_overlay_continue(overlay, scale_changed);
784 i915_gem_track_fb(overlay->vid_bo, new_bo,
785 INTEL_FRONTBUFFER_OVERLAY(pipe));
787 overlay->old_vid_bo = overlay->vid_bo;
788 overlay->vid_bo = new_bo;
790 intel_frontbuffer_flip(dev,
791 INTEL_FRONTBUFFER_OVERLAY(pipe));
796 i915_gem_object_ggtt_unpin(new_bo);
800 int intel_overlay_switch_off(struct intel_overlay *overlay)
802 struct overlay_registers __iomem *regs;
803 struct drm_device *dev = overlay->dev;
806 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
807 BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
809 ret = intel_overlay_recover_from_interrupt(overlay);
813 if (!overlay->active)
816 ret = intel_overlay_release_old_vid(overlay);
820 regs = intel_overlay_map_regs(overlay);
821 iowrite32(0, ®s->OCMD);
822 intel_overlay_unmap_regs(overlay, regs);
824 ret = intel_overlay_off(overlay);
828 intel_overlay_off_tail(overlay);
832 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
833 struct intel_crtc *crtc)
838 /* can't use the overlay with double wide pipe */
839 if (crtc->config.double_wide)
845 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
847 struct drm_device *dev = overlay->dev;
848 struct drm_i915_private *dev_priv = dev->dev_private;
849 u32 pfit_control = I915_READ(PFIT_CONTROL);
852 /* XXX: This is not the same logic as in the xorg driver, but more in
853 * line with the intel documentation for the i965
855 if (INTEL_INFO(dev)->gen >= 4) {
856 /* on i965 use the PGM reg to read out the autoscaler values */
857 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
859 if (pfit_control & VERT_AUTO_SCALE)
860 ratio = I915_READ(PFIT_AUTO_RATIOS);
862 ratio = I915_READ(PFIT_PGM_RATIOS);
863 ratio >>= PFIT_VERT_SCALE_SHIFT;
866 overlay->pfit_vscale_ratio = ratio;
869 static int check_overlay_dst(struct intel_overlay *overlay,
870 struct drm_intel_overlay_put_image *rec)
872 struct drm_display_mode *mode = &overlay->crtc->base.mode;
874 if (rec->dst_x < mode->hdisplay &&
875 rec->dst_x + rec->dst_width <= mode->hdisplay &&
876 rec->dst_y < mode->vdisplay &&
877 rec->dst_y + rec->dst_height <= mode->vdisplay)
883 static int check_overlay_scaling(struct put_image_params *rec)
887 /* downscaling limit is 8.0 */
888 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
891 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
898 static int check_overlay_src(struct drm_device *dev,
899 struct drm_intel_overlay_put_image *rec,
900 struct drm_i915_gem_object *new_bo)
902 int uv_hscale = uv_hsubsampling(rec->flags);
903 int uv_vscale = uv_vsubsampling(rec->flags);
908 /* check src dimensions */
909 if (IS_845G(dev) || IS_I830(dev)) {
910 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
911 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
914 if (rec->src_height > IMAGE_MAX_HEIGHT ||
915 rec->src_width > IMAGE_MAX_WIDTH)
919 /* better safe than sorry, use 4 as the maximal subsampling ratio */
920 if (rec->src_height < N_VERT_Y_TAPS*4 ||
921 rec->src_width < N_HORIZ_Y_TAPS*4)
924 /* check alignment constraints */
925 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
926 case I915_OVERLAY_RGB:
927 /* not implemented */
930 case I915_OVERLAY_YUV_PACKED:
934 depth = packed_depth_bytes(rec->flags);
938 /* ignore UV planes */
942 /* check pixel alignment */
943 if (rec->offset_Y % depth)
947 case I915_OVERLAY_YUV_PLANAR:
948 if (uv_vscale < 0 || uv_hscale < 0)
950 /* no offset restrictions for planar formats */
957 if (rec->src_width % uv_hscale)
960 /* stride checking */
961 if (IS_I830(dev) || IS_845G(dev))
966 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
968 if (IS_GEN4(dev) && rec->stride_Y < 512)
971 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
973 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
976 /* check buffer dimensions */
977 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
978 case I915_OVERLAY_RGB:
979 case I915_OVERLAY_YUV_PACKED:
980 /* always 4 Y values per depth pixels */
981 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
984 tmp = rec->stride_Y*rec->src_height;
985 if (rec->offset_Y + tmp > new_bo->base.size)
989 case I915_OVERLAY_YUV_PLANAR:
990 if (rec->src_width > rec->stride_Y)
992 if (rec->src_width/uv_hscale > rec->stride_UV)
995 tmp = rec->stride_Y * rec->src_height;
996 if (rec->offset_Y + tmp > new_bo->base.size)
999 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1000 if (rec->offset_U + tmp > new_bo->base.size ||
1001 rec->offset_V + tmp > new_bo->base.size)
1010 * Return the pipe currently connected to the panel fitter,
1011 * or -1 if the panel fitter is not present or not in use
1013 static int intel_panel_fitter_pipe(struct drm_device *dev)
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1018 /* i830 doesn't have a panel fitter */
1019 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
1022 pfit_control = I915_READ(PFIT_CONTROL);
1024 /* See if the panel fitter is in use */
1025 if ((pfit_control & PFIT_ENABLE) == 0)
1028 /* 965 can place panel fitter on either pipe */
1030 return (pfit_control >> 29) & 0x3;
1032 /* older chips can only use pipe 1 */
1036 int intel_overlay_put_image(struct drm_device *dev, void *data,
1037 struct drm_file *file_priv)
1039 struct drm_intel_overlay_put_image *put_image_rec = data;
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1041 struct intel_overlay *overlay;
1042 struct drm_crtc *drmmode_crtc;
1043 struct intel_crtc *crtc;
1044 struct drm_i915_gem_object *new_bo;
1045 struct put_image_params *params;
1048 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1049 overlay = dev_priv->overlay;
1051 DRM_DEBUG("userspace bug: no overlay\n");
1055 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1056 drm_modeset_lock_all(dev);
1057 mutex_lock(&dev->struct_mutex);
1059 ret = intel_overlay_switch_off(overlay);
1061 mutex_unlock(&dev->struct_mutex);
1062 drm_modeset_unlock_all(dev);
1067 params = kmalloc(sizeof(*params), GFP_KERNEL);
1071 drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1072 if (!drmmode_crtc) {
1076 crtc = to_intel_crtc(drmmode_crtc);
1078 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1079 put_image_rec->bo_handle));
1080 if (&new_bo->base == NULL) {
1085 drm_modeset_lock_all(dev);
1086 mutex_lock(&dev->struct_mutex);
1088 if (new_bo->tiling_mode) {
1089 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1094 ret = intel_overlay_recover_from_interrupt(overlay);
1098 if (overlay->crtc != crtc) {
1099 struct drm_display_mode *mode = &crtc->base.mode;
1100 ret = intel_overlay_switch_off(overlay);
1104 ret = check_overlay_possible_on_crtc(overlay, crtc);
1108 overlay->crtc = crtc;
1109 crtc->overlay = overlay;
1111 /* line too wide, i.e. one-line-mode */
1112 if (mode->hdisplay > 1024 &&
1113 intel_panel_fitter_pipe(dev) == crtc->pipe) {
1114 overlay->pfit_active = 1;
1115 update_pfit_vscale_ratio(overlay);
1117 overlay->pfit_active = 0;
1120 ret = check_overlay_dst(overlay, put_image_rec);
1124 if (overlay->pfit_active) {
1125 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1126 overlay->pfit_vscale_ratio);
1127 /* shifting right rounds downwards, so add 1 */
1128 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1129 overlay->pfit_vscale_ratio) + 1;
1131 params->dst_y = put_image_rec->dst_y;
1132 params->dst_h = put_image_rec->dst_height;
1134 params->dst_x = put_image_rec->dst_x;
1135 params->dst_w = put_image_rec->dst_width;
1137 params->src_w = put_image_rec->src_width;
1138 params->src_h = put_image_rec->src_height;
1139 params->src_scan_w = put_image_rec->src_scan_width;
1140 params->src_scan_h = put_image_rec->src_scan_height;
1141 if (params->src_scan_h > params->src_h ||
1142 params->src_scan_w > params->src_w) {
1147 ret = check_overlay_src(dev, put_image_rec, new_bo);
1150 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1151 params->stride_Y = put_image_rec->stride_Y;
1152 params->stride_UV = put_image_rec->stride_UV;
1153 params->offset_Y = put_image_rec->offset_Y;
1154 params->offset_U = put_image_rec->offset_U;
1155 params->offset_V = put_image_rec->offset_V;
1157 /* Check scaling after src size to prevent a divide-by-zero. */
1158 ret = check_overlay_scaling(params);
1162 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1166 mutex_unlock(&dev->struct_mutex);
1167 drm_modeset_unlock_all(dev);
1174 mutex_unlock(&dev->struct_mutex);
1175 drm_modeset_unlock_all(dev);
1176 drm_gem_object_unreference_unlocked(&new_bo->base);
1183 static void update_reg_attrs(struct intel_overlay *overlay,
1184 struct overlay_registers __iomem *regs)
1186 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1188 iowrite32(overlay->saturation, ®s->OCLRC1);
1191 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1195 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1198 for (i = 0; i < 3; i++) {
1199 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1206 static bool check_gamma5_errata(u32 gamma5)
1210 for (i = 0; i < 3; i++) {
1211 if (((gamma5 >> i*8) & 0xff) == 0x80)
1218 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1220 if (!check_gamma_bounds(0, attrs->gamma0) ||
1221 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1222 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1223 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1224 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1225 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1226 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1229 if (!check_gamma5_errata(attrs->gamma5))
1235 int intel_overlay_attrs(struct drm_device *dev, void *data,
1236 struct drm_file *file_priv)
1238 struct drm_intel_overlay_attrs *attrs = data;
1239 struct drm_i915_private *dev_priv = dev->dev_private;
1240 struct intel_overlay *overlay;
1241 struct overlay_registers __iomem *regs;
1244 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1245 overlay = dev_priv->overlay;
1247 DRM_DEBUG("userspace bug: no overlay\n");
1251 drm_modeset_lock_all(dev);
1252 mutex_lock(&dev->struct_mutex);
1255 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1256 attrs->color_key = overlay->color_key;
1257 attrs->brightness = overlay->brightness;
1258 attrs->contrast = overlay->contrast;
1259 attrs->saturation = overlay->saturation;
1261 if (!IS_GEN2(dev)) {
1262 attrs->gamma0 = I915_READ(OGAMC0);
1263 attrs->gamma1 = I915_READ(OGAMC1);
1264 attrs->gamma2 = I915_READ(OGAMC2);
1265 attrs->gamma3 = I915_READ(OGAMC3);
1266 attrs->gamma4 = I915_READ(OGAMC4);
1267 attrs->gamma5 = I915_READ(OGAMC5);
1270 if (attrs->brightness < -128 || attrs->brightness > 127)
1272 if (attrs->contrast > 255)
1274 if (attrs->saturation > 1023)
1277 overlay->color_key = attrs->color_key;
1278 overlay->brightness = attrs->brightness;
1279 overlay->contrast = attrs->contrast;
1280 overlay->saturation = attrs->saturation;
1282 regs = intel_overlay_map_regs(overlay);
1288 update_reg_attrs(overlay, regs);
1290 intel_overlay_unmap_regs(overlay, regs);
1292 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1296 if (overlay->active) {
1301 ret = check_gamma(attrs);
1305 I915_WRITE(OGAMC0, attrs->gamma0);
1306 I915_WRITE(OGAMC1, attrs->gamma1);
1307 I915_WRITE(OGAMC2, attrs->gamma2);
1308 I915_WRITE(OGAMC3, attrs->gamma3);
1309 I915_WRITE(OGAMC4, attrs->gamma4);
1310 I915_WRITE(OGAMC5, attrs->gamma5);
1316 mutex_unlock(&dev->struct_mutex);
1317 drm_modeset_unlock_all(dev);
1322 void intel_setup_overlay(struct drm_device *dev)
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct intel_overlay *overlay;
1326 struct drm_i915_gem_object *reg_bo;
1327 struct overlay_registers __iomem *regs;
1330 if (!HAS_OVERLAY(dev))
1333 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1337 mutex_lock(&dev->struct_mutex);
1338 if (WARN_ON(dev_priv->overlay))
1344 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1345 reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE);
1347 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1350 overlay->reg_bo = reg_bo;
1352 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1353 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1355 DRM_ERROR("failed to attach phys overlay regs\n");
1358 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1360 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
1362 DRM_ERROR("failed to pin overlay register bo\n");
1365 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo);
1367 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1369 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1374 /* init all values */
1375 overlay->color_key = 0x0101fe;
1376 overlay->brightness = -19;
1377 overlay->contrast = 75;
1378 overlay->saturation = 146;
1380 regs = intel_overlay_map_regs(overlay);
1384 memset_io(regs, 0, sizeof(struct overlay_registers));
1385 update_polyphase_filter(regs);
1386 update_reg_attrs(overlay, regs);
1388 intel_overlay_unmap_regs(overlay, regs);
1390 dev_priv->overlay = overlay;
1391 mutex_unlock(&dev->struct_mutex);
1392 DRM_INFO("initialized overlay support\n");
1396 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1397 i915_gem_object_ggtt_unpin(reg_bo);
1399 drm_gem_object_unreference(®_bo->base);
1401 mutex_unlock(&dev->struct_mutex);
1406 void intel_cleanup_overlay(struct drm_device *dev)
1408 struct drm_i915_private *dev_priv = dev->dev_private;
1410 if (!dev_priv->overlay)
1413 /* The bo's should be free'd by the generic code already.
1414 * Furthermore modesetting teardown happens beforehand so the
1415 * hardware should be off already */
1416 BUG_ON(dev_priv->overlay->active);
1418 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1419 kfree(dev_priv->overlay);
1422 struct intel_overlay_error_state {
1423 struct overlay_registers regs;
1429 static struct overlay_registers __iomem *
1430 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1432 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
1433 struct overlay_registers __iomem *regs;
1435 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1436 /* Cast to make sparse happy, but it's wc memory anyway, so
1437 * equivalent to the wc io mapping on X86. */
1438 regs = (struct overlay_registers __iomem *)
1439 overlay->reg_bo->phys_handle->vaddr;
1441 regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1442 i915_gem_obj_ggtt_offset(overlay->reg_bo));
1447 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1448 struct overlay_registers __iomem *regs)
1450 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1451 io_mapping_unmap_atomic(regs);
1455 struct intel_overlay_error_state *
1456 intel_overlay_capture_error_state(struct drm_device *dev)
1458 struct drm_i915_private *dev_priv = dev->dev_private;
1459 struct intel_overlay *overlay = dev_priv->overlay;
1460 struct intel_overlay_error_state *error;
1461 struct overlay_registers __iomem *regs;
1463 if (!overlay || !overlay->active)
1466 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1470 error->dovsta = I915_READ(DOVSTA);
1471 error->isr = I915_READ(ISR);
1472 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1473 error->base = (__force long)overlay->reg_bo->phys_handle->vaddr;
1475 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo);
1477 regs = intel_overlay_map_regs_atomic(overlay);
1481 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1482 intel_overlay_unmap_regs_atomic(overlay, regs);
1492 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1493 struct intel_overlay_error_state *error)
1495 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1496 error->dovsta, error->isr);
1497 i915_error_printf(m, " Register file at 0x%08lx:\n",
1500 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)