drivers/gpu/drm/i915/intel_panel.c

   1 /*
   2  * Copyright © 2006-2010 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  *      Chris Wilson <chris@chris-wilson.co.uk>
  29  */
  30
  31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32
  33 #include <linux/moduleparam.h>
  34 #include "intel_drv.h"
  35
  36 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  37
  38 void
  39 intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  40                        struct drm_display_mode *adjusted_mode)
  41 {
  42         drm_mode_copy(adjusted_mode, fixed_mode);
  43
  44         drm_mode_set_crtcinfo(adjusted_mode, 0);
  45 }
  46
  47 /* adjusted_mode has been preset to be the panel's fixed mode */
  48 void
  49 intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
  50                         struct intel_crtc_config *pipe_config,
  51                         int fitting_mode)
  52 {
  53         struct drm_display_mode *adjusted_mode;
  54         int x, y, width, height;
  55
  56         adjusted_mode = &pipe_config->adjusted_mode;
  57
  58         x = y = width = height = 0;
  59
  60         /* Native modes don't need fitting */
  61         if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
  62             adjusted_mode->vdisplay == pipe_config->pipe_src_h)
  63                 goto done;
  64
  65         switch (fitting_mode) {
  66         case DRM_MODE_SCALE_CENTER:
  67                 width = pipe_config->pipe_src_w;
  68                 height = pipe_config->pipe_src_h;
  69                 x = (adjusted_mode->hdisplay - width + 1)/2;
  70                 y = (adjusted_mode->vdisplay - height + 1)/2;
  71                 break;
  72
  73         case DRM_MODE_SCALE_ASPECT:
  74                 /* Scale but preserve the aspect ratio */
  75                 {
  76                         u32 scaled_width = adjusted_mode->hdisplay
  77                                 * pipe_config->pipe_src_h;
  78                         u32 scaled_height = pipe_config->pipe_src_w
  79                                 * adjusted_mode->vdisplay;
  80                         if (scaled_width > scaled_height) { /* pillar */
  81                                 width = scaled_height / pipe_config->pipe_src_h;
  82                                 if (width & 1)
  83                                         width++;
  84                                 x = (adjusted_mode->hdisplay - width + 1) / 2;
  85                                 y = 0;
  86                                 height = adjusted_mode->vdisplay;
  87                         } else if (scaled_width < scaled_height) { /* letter */
  88                                 height = scaled_width / pipe_config->pipe_src_w;
  89                                 if (height & 1)
  90                                     height++;
  91                                 y = (adjusted_mode->vdisplay - height + 1) / 2;
  92                                 x = 0;
  93                                 width = adjusted_mode->hdisplay;
  94                         } else {
  95                                 x = y = 0;
  96                                 width = adjusted_mode->hdisplay;
  97                                 height = adjusted_mode->vdisplay;
  98                         }
  99                 }
 100                 break;
 101
 102         case DRM_MODE_SCALE_FULLSCREEN:
 103                 x = y = 0;
 104                 width = adjusted_mode->hdisplay;
 105                 height = adjusted_mode->vdisplay;
 106                 break;
 107
 108         default:
 109                 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
 110                 return;
 111         }
 112
 113 done:
 114         pipe_config->pch_pfit.pos = (x << 16) | y;
 115         pipe_config->pch_pfit.size = (width << 16) | height;
 116         pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
 117 }
 118
 119 static void
 120 centre_horizontally(struct drm_display_mode *mode,
 121                     int width)
 122 {
 123         u32 border, sync_pos, blank_width, sync_width;
 124
 125         /* keep the hsync and hblank widths constant */
 126         sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
 127         blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
 128         sync_pos = (blank_width - sync_width + 1) / 2;
 129
 130         border = (mode->hdisplay - width + 1) / 2;
 131         border += border & 1; /* make the border even */
 132
 133         mode->crtc_hdisplay = width;
 134         mode->crtc_hblank_start = width + border;
 135         mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
 136
 137         mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
 138         mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
 139 }
 140
 141 static void
 142 centre_vertically(struct drm_display_mode *mode,
 143                   int height)
 144 {
 145         u32 border, sync_pos, blank_width, sync_width;
 146
 147         /* keep the vsync and vblank widths constant */
 148         sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
 149         blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
 150         sync_pos = (blank_width - sync_width + 1) / 2;
 151
 152         border = (mode->vdisplay - height + 1) / 2;
 153
 154         mode->crtc_vdisplay = height;
 155         mode->crtc_vblank_start = height + border;
 156         mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
 157
 158         mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
 159         mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
 160 }
 161
 162 static inline u32 panel_fitter_scaling(u32 source, u32 target)
 163 {
 164         /*
 165          * Floating point operation is not supported. So the FACTOR
 166          * is defined, which can avoid the floating point computation
 167          * when calculating the panel ratio.
 168          */
 169 #define ACCURACY 12
 170 #define FACTOR (1 << ACCURACY)
 171         u32 ratio = source * FACTOR / target;
 172         return (FACTOR * ratio + FACTOR/2) / FACTOR;
 173 }
 174
 175 static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
 176                               u32 *pfit_control)
 177 {
 178         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 179         u32 scaled_width = adjusted_mode->hdisplay *
 180                 pipe_config->pipe_src_h;
 181         u32 scaled_height = pipe_config->pipe_src_w *
 182                 adjusted_mode->vdisplay;
 183
 184         /* 965+ is easy, it does everything in hw */
 185         if (scaled_width > scaled_height)
 186                 *pfit_control |= PFIT_ENABLE |
 187                         PFIT_SCALING_PILLAR;
 188         else if (scaled_width < scaled_height)
 189                 *pfit_control |= PFIT_ENABLE |
 190                         PFIT_SCALING_LETTER;
 191         else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
 192                 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
 193 }
 194
 195 static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
 196                               u32 *pfit_control, u32 *pfit_pgm_ratios,
 197                               u32 *border)
 198 {
 199         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 200         u32 scaled_width = adjusted_mode->hdisplay *
 201                 pipe_config->pipe_src_h;
 202         u32 scaled_height = pipe_config->pipe_src_w *
 203                 adjusted_mode->vdisplay;
 204         u32 bits;
 205
 206         /*
 207          * For earlier chips we have to calculate the scaling
 208          * ratio by hand and program it into the
 209          * PFIT_PGM_RATIO register
 210          */
 211         if (scaled_width > scaled_height) { /* pillar */
 212                 centre_horizontally(adjusted_mode,
 213                                     scaled_height /
 214                                     pipe_config->pipe_src_h);
 215
 216                 *border = LVDS_BORDER_ENABLE;
 217                 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
 218                         bits = panel_fitter_scaling(pipe_config->pipe_src_h,
 219                                                     adjusted_mode->vdisplay);
 220
 221                         *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
 222                                              bits << PFIT_VERT_SCALE_SHIFT);
 223                         *pfit_control |= (PFIT_ENABLE |
 224                                           VERT_INTERP_BILINEAR |
 225                                           HORIZ_INTERP_BILINEAR);
 226                 }
 227         } else if (scaled_width < scaled_height) { /* letter */
 228                 centre_vertically(adjusted_mode,
 229                                   scaled_width /
 230                                   pipe_config->pipe_src_w);
 231
 232                 *border = LVDS_BORDER_ENABLE;
 233                 if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
 234                         bits = panel_fitter_scaling(pipe_config->pipe_src_w,
 235                                                     adjusted_mode->hdisplay);
 236
 237                         *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
 238                                              bits << PFIT_VERT_SCALE_SHIFT);
 239                         *pfit_control |= (PFIT_ENABLE |
 240                                           VERT_INTERP_BILINEAR |
 241                                           HORIZ_INTERP_BILINEAR);
 242                 }
 243         } else {
 244                 /* Aspects match, Let hw scale both directions */
 245                 *pfit_control |= (PFIT_ENABLE |
 246                                   VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
 247                                   VERT_INTERP_BILINEAR |
 248                                   HORIZ_INTERP_BILINEAR);
 249         }
 250 }
 251
 252 void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 253                               struct intel_crtc_config *pipe_config,
 254                               int fitting_mode)
 255 {
 256         struct drm_device *dev = intel_crtc->base.dev;
 257         u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
 258         struct drm_display_mode *adjusted_mode;
 259
 260         adjusted_mode = &pipe_config->adjusted_mode;
 261
 262         /* Native modes don't need fitting */
 263         if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
 264             adjusted_mode->vdisplay == pipe_config->pipe_src_h)
 265                 goto out;
 266
 267         switch (fitting_mode) {
 268         case DRM_MODE_SCALE_CENTER:
 269                 /*
 270                  * For centered modes, we have to calculate border widths &
 271                  * heights and modify the values programmed into the CRTC.
 272                  */
 273                 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
 274                 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
 275                 border = LVDS_BORDER_ENABLE;
 276                 break;
 277         case DRM_MODE_SCALE_ASPECT:
 278                 /* Scale but preserve the aspect ratio */
 279                 if (INTEL_INFO(dev)->gen >= 4)
 280                         i965_scale_aspect(pipe_config, &pfit_control);
 281                 else
 282                         i9xx_scale_aspect(pipe_config, &pfit_control,
 283                                           &pfit_pgm_ratios, &border);
 284                 break;
 285         case DRM_MODE_SCALE_FULLSCREEN:
 286                 /*
 287                  * Full scaling, even if it changes the aspect ratio.
 288                  * Fortunately this is all done for us in hw.
 289                  */
 290                 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
 291                     pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
 292                         pfit_control |= PFIT_ENABLE;
 293                         if (INTEL_INFO(dev)->gen >= 4)
 294                                 pfit_control |= PFIT_SCALING_AUTO;
 295                         else
 296                                 pfit_control |= (VERT_AUTO_SCALE |
 297                                                  VERT_INTERP_BILINEAR |
 298                                                  HORIZ_AUTO_SCALE |
 299                                                  HORIZ_INTERP_BILINEAR);
 300                 }
 301                 break;
 302         default:
 303                 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
 304                 return;
 305         }
 306
 307         /* 965+ wants fuzzy fitting */
 308         /* FIXME: handle multiple panels by failing gracefully */
 309         if (INTEL_INFO(dev)->gen >= 4)
 310                 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
 311                                  PFIT_FILTER_FUZZY);
 312
 313 out:
 314         if ((pfit_control & PFIT_ENABLE) == 0) {
 315                 pfit_control = 0;
 316                 pfit_pgm_ratios = 0;
 317         }
 318
 319         /* Make sure pre-965 set dither correctly for 18bpp panels. */
 320         if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
 321                 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
 322
 323         pipe_config->gmch_pfit.control = pfit_control;
 324         pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
 325         pipe_config->gmch_pfit.lvds_border_bits = border;
 326 }
 327
 328 static int is_backlight_combination_mode(struct drm_device *dev)
 329 {
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331
 332         if (IS_GEN4(dev))
 333                 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
 334
 335         if (IS_GEN2(dev))
 336                 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
 337
 338         return 0;
 339 }
 340
 341 /* XXX: query mode clock or hardware clock and program max PWM appropriately
 342  * when it's 0.
 343  */
 344 static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
 345 {
 346         struct drm_i915_private *dev_priv = dev->dev_private;
 347         u32 val;
 348
 349         WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
 350
 351         /* Restore the CTL value if it lost, e.g. GPU reset */
 352
 353         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 354                 val = I915_READ(BLC_PWM_PCH_CTL2);
 355                 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
 356                         dev_priv->regfile.saveBLC_PWM_CTL2 = val;
 357                 } else if (val == 0) {
 358                         val = dev_priv->regfile.saveBLC_PWM_CTL2;
 359                         I915_WRITE(BLC_PWM_PCH_CTL2, val);
 360                 }
 361         } else if (IS_VALLEYVIEW(dev)) {
 362                 val = I915_READ(VLV_BLC_PWM_CTL(pipe));
 363                 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
 364                         dev_priv->regfile.saveBLC_PWM_CTL = val;
 365                         dev_priv->regfile.saveBLC_PWM_CTL2 =
 366                                 I915_READ(VLV_BLC_PWM_CTL2(pipe));
 367                 } else if (val == 0) {
 368                         val = dev_priv->regfile.saveBLC_PWM_CTL;
 369                         I915_WRITE(VLV_BLC_PWM_CTL(pipe), val);
 370                         I915_WRITE(VLV_BLC_PWM_CTL2(pipe),
 371                                    dev_priv->regfile.saveBLC_PWM_CTL2);
 372                 }
 373
 374                 if (!val)
 375                         val = 0x0f42ffff;
 376         } else {
 377                 val = I915_READ(BLC_PWM_CTL);
 378                 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
 379                         dev_priv->regfile.saveBLC_PWM_CTL = val;
 380                         if (INTEL_INFO(dev)->gen >= 4)
 381                                 dev_priv->regfile.saveBLC_PWM_CTL2 =
 382                                         I915_READ(BLC_PWM_CTL2);
 383                 } else if (val == 0) {
 384                         val = dev_priv->regfile.saveBLC_PWM_CTL;
 385                         I915_WRITE(BLC_PWM_CTL, val);
 386                         if (INTEL_INFO(dev)->gen >= 4)
 387                                 I915_WRITE(BLC_PWM_CTL2,
 388                                            dev_priv->regfile.saveBLC_PWM_CTL2);
 389                 }
 390         }
 391
 392         return val;
 393 }
 394
 395 static u32 intel_panel_get_max_backlight(struct drm_device *dev,
 396                                          enum pipe pipe)
 397 {
 398         u32 max;
 399
 400         max = i915_read_blc_pwm_ctl(dev, pipe);
 401
 402         if (HAS_PCH_SPLIT(dev)) {
 403                 max >>= 16;
 404         } else {
 405                 if (INTEL_INFO(dev)->gen < 4)
 406                         max >>= 17;
 407                 else
 408                         max >>= 16;
 409
 410                 if (is_backlight_combination_mode(dev))
 411                         max *= 0xff;
 412         }
 413
 414         DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
 415
 416         return max;
 417 }
 418
 419 static int i915_panel_invert_brightness;
 420 MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
 421         "(-1 force normal, 0 machine defaults, 1 force inversion), please "
 422         "report PCI device ID, subsystem vendor and subsystem device ID "
 423         "to dri-devel@lists.freedesktop.org, if your machine needs it. "
 424         "It will then be included in an upcoming module version.");
 425 module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
 426 static u32 intel_panel_compute_brightness(struct drm_device *dev,
 427                                           enum pipe pipe, u32 val)
 428 {
 429         struct drm_i915_private *dev_priv = dev->dev_private;
 430
 431         if (i915_panel_invert_brightness < 0)
 432                 return val;
 433
 434         if (i915_panel_invert_brightness > 0 ||
 435             dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
 436                 u32 max = intel_panel_get_max_backlight(dev, pipe);
 437                 if (max)
 438                         return max - val;
 439         }
 440
 441         return val;
 442 }
 443
 444 static u32 intel_panel_get_backlight(struct drm_device *dev,
 445                                      enum pipe pipe)
 446 {
 447         struct drm_i915_private *dev_priv = dev->dev_private;
 448         u32 val;
 449         unsigned long flags;
 450         int reg;
 451
 452         spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 453
 454         if (IS_BROADWELL(dev)) {
 455                 val = I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
 456         } else if (HAS_PCH_SPLIT(dev)) {
 457                 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 458         } else {
 459                 if (IS_VALLEYVIEW(dev))
 460                         reg = VLV_BLC_PWM_CTL(pipe);
 461                 else
 462                         reg = BLC_PWM_CTL;
 463
 464                 val = I915_READ(reg) & BACKLIGHT_DUTY_CYCLE_MASK;
 465                 if (INTEL_INFO(dev)->gen < 4)
 466                         val >>= 1;
 467
 468                 if (is_backlight_combination_mode(dev)) {
 469                         u8 lbpc;
 470
 471                         pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
 472                         val *= lbpc;
 473                 }
 474         }
 475
 476         val = intel_panel_compute_brightness(dev, pipe, val);
 477
 478         spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
 479
 480         DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
 481         return val;
 482 }
 483
 484 static void intel_bdw_panel_set_backlight(struct drm_device *dev, u32 level)
 485 {
 486         struct drm_i915_private *dev_priv = dev->dev_private;
 487         u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 488         I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
 489 }
 490
 491 static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
 492 {
 493         struct drm_i915_private *dev_priv = dev->dev_private;
 494         u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 495         I915_WRITE(BLC_PWM_CPU_CTL, val | level);
 496 }
 497
 498 static void intel_panel_actually_set_backlight(struct drm_device *dev,
 499                                                enum pipe pipe, u32 level)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         u32 tmp;
 503         int reg;
 504
 505         DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
 506         level = intel_panel_compute_brightness(dev, pipe, level);
 507
 508         if (IS_BROADWELL(dev))
 509                 return intel_bdw_panel_set_backlight(dev, level);
 510         else if (HAS_PCH_SPLIT(dev))
 511                 return intel_pch_panel_set_backlight(dev, level);
 512
 513         if (is_backlight_combination_mode(dev)) {
 514                 u32 max = intel_panel_get_max_backlight(dev, pipe);
 515                 u8 lbpc;
 516
 517                 /* we're screwed, but keep behaviour backwards compatible */
 518                 if (!max)
 519                         max = 1;
 520
 521                 lbpc = level * 0xfe / max + 1;
 522                 level /= lbpc;
 523                 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
 524         }
 525
 526         if (IS_VALLEYVIEW(dev))
 527                 reg = VLV_BLC_PWM_CTL(pipe);
 528         else
 529                 reg = BLC_PWM_CTL;
 530
 531         tmp = I915_READ(reg);
 532         if (INTEL_INFO(dev)->gen < 4)
 533                 level <<= 1;
 534         tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
 535         I915_WRITE(reg, tmp | level);
 536 }
 537
 538 /* set backlight brightness to level in range [0..max] */
 539 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 540                                u32 max)
 541 {
 542         struct drm_device *dev = connector->base.dev;
 543         struct drm_i915_private *dev_priv = dev->dev_private;
 544         enum pipe pipe = intel_get_pipe_from_connector(connector);
 545         u32 freq;
 546         unsigned long flags;
 547
 548         if (pipe == INVALID_PIPE)
 549                 return;
 550
 551         spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 552
 553         freq = intel_panel_get_max_backlight(dev, pipe);
 554         if (!freq) {
 555                 /* we are screwed, bail out */
 556                 goto out;
 557         }
 558
 559         /* scale to hardware, but be careful to not overflow */
 560         if (freq < max)
 561                 level = level * freq / max;
 562         else
 563                 level = freq / max * level;
 564
 565         dev_priv->backlight.level = level;
 566         if (dev_priv->backlight.device)
 567                 dev_priv->backlight.device->props.brightness = level;
 568
 569         if (dev_priv->backlight.enabled)
 570                 intel_panel_actually_set_backlight(dev, pipe, level);
 571 out:
 572         spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
 573 }
 574
 575 void intel_panel_disable_backlight(struct intel_connector *connector)
 576 {
 577         struct drm_device *dev = connector->base.dev;
 578         struct drm_i915_private *dev_priv = dev->dev_private;
 579         enum pipe pipe = intel_get_pipe_from_connector(connector);
 580         unsigned long flags;
 581
 582         if (pipe == INVALID_PIPE)
 583                 return;
 584
 585         /*
 586          * Do not disable backlight on the vgaswitcheroo path. When switching
 587          * away from i915, the other client may depend on i915 to handle the
 588          * backlight. This will leave the backlight on unnecessarily when
 589          * another client is not activated.
 590          */
 591         if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
 592                 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
 593                 return;
 594         }
 595
 596         spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 597
 598         dev_priv->backlight.enabled = false;
 599         intel_panel_actually_set_backlight(dev, pipe, 0);
 600
 601         if (INTEL_INFO(dev)->gen >= 4) {
 602                 uint32_t reg, tmp;
 603
 604                 if (HAS_PCH_SPLIT(dev))
 605                         reg = BLC_PWM_CPU_CTL2;
 606                 else if (IS_VALLEYVIEW(dev))
 607                         reg = VLV_BLC_PWM_CTL2(pipe);
 608                 else
 609                         reg = BLC_PWM_CTL2;
 610
 611                 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
 612
 613                 if (HAS_PCH_SPLIT(dev)) {
 614                         tmp = I915_READ(BLC_PWM_PCH_CTL1);
 615                         tmp &= ~BLM_PCH_PWM_ENABLE;
 616                         I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
 617                 }
 618         }
 619
 620         spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
 621 }
 622
 623 void intel_panel_enable_backlight(struct intel_connector *connector)
 624 {
 625         struct drm_device *dev = connector->base.dev;
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         enum pipe pipe = intel_get_pipe_from_connector(connector);
 628         enum transcoder cpu_transcoder =
 629                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
 630         unsigned long flags;
 631
 632         if (pipe == INVALID_PIPE)
 633                 return;
 634
 635         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 636
 637         spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 638
 639         if (dev_priv->backlight.level == 0) {
 640                 dev_priv->backlight.level = intel_panel_get_max_backlight(dev,
 641                                                                           pipe);
 642                 if (dev_priv->backlight.device)
 643                         dev_priv->backlight.device->props.brightness =
 644                                 dev_priv->backlight.level;
 645         }
 646
 647         if (INTEL_INFO(dev)->gen >= 4) {
 648                 uint32_t reg, tmp;
 649
 650                 if (HAS_PCH_SPLIT(dev))
 651                         reg = BLC_PWM_CPU_CTL2;
 652                 else if (IS_VALLEYVIEW(dev))
 653                         reg = VLV_BLC_PWM_CTL2(pipe);
 654                 else
 655                         reg = BLC_PWM_CTL2;
 656
 657                 tmp = I915_READ(reg);
 658
 659                 /* Note that this can also get called through dpms changes. And
 660                  * we don't track the backlight dpms state, hence check whether
 661                  * we have to do anything first. */
 662                 if (tmp & BLM_PWM_ENABLE)
 663                         goto set_level;
 664
 665                 if (INTEL_INFO(dev)->num_pipes == 3)
 666                         tmp &= ~BLM_PIPE_SELECT_IVB;
 667                 else
 668                         tmp &= ~BLM_PIPE_SELECT;
 669
 670                 if (cpu_transcoder == TRANSCODER_EDP)
 671                         tmp |= BLM_TRANSCODER_EDP;
 672                 else
 673                         tmp |= BLM_PIPE(cpu_transcoder);
 674                 tmp &= ~BLM_PWM_ENABLE;
 675
 676                 I915_WRITE(reg, tmp);
 677                 POSTING_READ(reg);
 678                 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
 679
 680                 if (IS_BROADWELL(dev)) {
 681                         /*
 682                          * Broadwell requires PCH override to drive the PCH
 683                          * backlight pin. The above will configure the CPU
 684                          * backlight pin, which we don't plan to use.
 685                          */
 686                         tmp = I915_READ(BLC_PWM_PCH_CTL1);
 687                         tmp |= BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE;
 688                         I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
 689                 } else if (HAS_PCH_SPLIT(dev) &&
 690                     !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
 691                         tmp = I915_READ(BLC_PWM_PCH_CTL1);
 692                         tmp |= BLM_PCH_PWM_ENABLE;
 693                         tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
 694                         I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
 695                 }
 696         }
 697
 698 set_level:
 699         /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
 700          * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
 701          * registers are set.
 702          */
 703         dev_priv->backlight.enabled = true;
 704         intel_panel_actually_set_backlight(dev, pipe,
 705                                            dev_priv->backlight.level);
 706
 707         spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
 708 }
 709
 710 /* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */
 711 static void intel_panel_init_backlight_regs(struct drm_device *dev)
 712 {
 713         struct drm_i915_private *dev_priv = dev->dev_private;
 714
 715         if (IS_VALLEYVIEW(dev)) {
 716                 enum pipe pipe;
 717
 718                 for_each_pipe(pipe) {
 719                         u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe));
 720
 721                         /* Skip if the modulation freq is already set */
 722                         if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK)
 723                                 continue;
 724
 725                         cur_val &= BACKLIGHT_DUTY_CYCLE_MASK;
 726                         I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) |
 727                                    cur_val);
 728                 }
 729         }
 730 }
 731
 732 static void intel_panel_init_backlight(struct drm_device *dev)
 733 {
 734         struct drm_i915_private *dev_priv = dev->dev_private;
 735
 736         intel_panel_init_backlight_regs(dev);
 737
 738         dev_priv->backlight.level = intel_panel_get_backlight(dev, 0);
 739         dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
 740 }
 741
 742 enum drm_connector_status
 743 intel_panel_detect(struct drm_device *dev)
 744 {
 745         struct drm_i915_private *dev_priv = dev->dev_private;
 746
 747         /* Assume that the BIOS does not lie through the OpRegion... */
 748         if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
 749                 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
 750                         connector_status_connected :
 751                         connector_status_disconnected;
 752         }
 753
 754         switch (i915_panel_ignore_lid) {
 755         case -2:
 756                 return connector_status_connected;
 757         case -1:
 758                 return connector_status_disconnected;
 759         default:
 760                 return connector_status_unknown;
 761         }
 762 }
 763
 764 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
 765 static int intel_panel_update_status(struct backlight_device *bd)
 766 {
 767         struct intel_connector *connector = bl_get_data(bd);
 768         struct drm_device *dev = connector->base.dev;
 769
 770         mutex_lock(&dev->mode_config.mutex);
 771         DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n",
 772                       bd->props.brightness, bd->props.max_brightness);
 773         intel_panel_set_backlight(connector, bd->props.brightness,
 774                                   bd->props.max_brightness);
 775         mutex_unlock(&dev->mode_config.mutex);
 776         return 0;
 777 }
 778
 779 static int intel_panel_get_brightness(struct backlight_device *bd)
 780 {
 781         struct intel_connector *connector = bl_get_data(bd);
 782         struct drm_device *dev = connector->base.dev;
 783         enum pipe pipe;
 784
 785         mutex_lock(&dev->mode_config.mutex);
 786         pipe = intel_get_pipe_from_connector(connector);
 787         mutex_unlock(&dev->mode_config.mutex);
 788         if (pipe == INVALID_PIPE)
 789                 return 0;
 790
 791         return intel_panel_get_backlight(connector->base.dev, pipe);
 792 }
 793
 794 static const struct backlight_ops intel_panel_bl_ops = {
 795         .update_status = intel_panel_update_status,
 796         .get_brightness = intel_panel_get_brightness,
 797 };
 798
 799 int intel_panel_setup_backlight(struct drm_connector *connector)
 800 {
 801         struct drm_device *dev = connector->dev;
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         struct backlight_properties props;
 804         unsigned long flags;
 805
 806         intel_panel_init_backlight(dev);
 807
 808         if (WARN_ON(dev_priv->backlight.device))
 809                 return -ENODEV;
 810
 811         memset(&props, 0, sizeof(props));
 812         props.type = BACKLIGHT_RAW;
 813         props.brightness = dev_priv->backlight.level;
 814
 815         spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 816         props.max_brightness = intel_panel_get_max_backlight(dev, 0);
 817         spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
 818
 819         if (props.max_brightness == 0) {
 820                 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
 821                 return -ENODEV;
 822         }
 823         dev_priv->backlight.device =
 824                 backlight_device_register("intel_backlight",
 825                                           connector->kdev,
 826                                           to_intel_connector(connector),
 827                                           &intel_panel_bl_ops, &props);
 828
 829         if (IS_ERR(dev_priv->backlight.device)) {
 830                 DRM_ERROR("Failed to register backlight: %ld\n",
 831                           PTR_ERR(dev_priv->backlight.device));
 832                 dev_priv->backlight.device = NULL;
 833                 return -ENODEV;
 834         }
 835         return 0;
 836 }
 837
 838 void intel_panel_destroy_backlight(struct drm_device *dev)
 839 {
 840         struct drm_i915_private *dev_priv = dev->dev_private;
 841         if (dev_priv->backlight.device) {
 842                 backlight_device_unregister(dev_priv->backlight.device);
 843                 dev_priv->backlight.device = NULL;
 844         }
 845 }
 846 #else
 847 int intel_panel_setup_backlight(struct drm_connector *connector)
 848 {
 849         intel_panel_init_backlight(connector->dev);
 850         return 0;
 851 }
 852
 853 void intel_panel_destroy_backlight(struct drm_device *dev)
 854 {
 855         return;
 856 }
 857 #endif
 858
 859 int intel_panel_init(struct intel_panel *panel,
 860                      struct drm_display_mode *fixed_mode)
 861 {
 862         panel->fixed_mode = fixed_mode;
 863
 864         return 0;
 865 }
 866
 867 void intel_panel_fini(struct intel_panel *panel)
 868 {
 869         struct intel_connector *intel_connector =
 870                 container_of(panel, struct intel_connector, panel);
 871
 872         if (panel->fixed_mode)
 873                 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
 874 }