drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static bool intel_crtc_active(struct drm_crtc *crtc)
  48 {
  49         /* Be paranoid as we can arrive here with only partial
  50          * state retrieved from the hardware during setup.
  51          */
  52         return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  53 }
  54
  55 static void i8xx_disable_fbc(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         u32 fbc_ctl;
  59
  60         /* Disable compression */
  61         fbc_ctl = I915_READ(FBC_CONTROL);
  62         if ((fbc_ctl & FBC_CTL_EN) == 0)
  63                 return;
  64
  65         fbc_ctl &= ~FBC_CTL_EN;
  66         I915_WRITE(FBC_CONTROL, fbc_ctl);
  67
  68         /* Wait for compressing bit to clear */
  69         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  70                 DRM_DEBUG_KMS("FBC idle timed out\n");
  71                 return;
  72         }
  73
  74         DRM_DEBUG_KMS("disabled FBC\n");
  75 }
  76
  77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  78 {
  79         struct drm_device *dev = crtc->dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct drm_framebuffer *fb = crtc->fb;
  82         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  83         struct drm_i915_gem_object *obj = intel_fb->obj;
  84         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  85         int cfb_pitch;
  86         int plane, i;
  87         u32 fbc_ctl, fbc_ctl2;
  88
  89         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  90         if (fb->pitches[0] < cfb_pitch)
  91                 cfb_pitch = fb->pitches[0];
  92
  93         /* FBC_CTL wants 64B units */
  94         cfb_pitch = (cfb_pitch / 64) - 1;
  95         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  96
  97         /* Clear old tags */
  98         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  99                 I915_WRITE(FBC_TAG + (i * 4), 0);
 100
 101         /* Set it up... */
 102         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 103         fbc_ctl2 |= plane;
 104         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 105         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 106
 107         /* enable it... */
 108         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 109         if (IS_I945GM(dev))
 110                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 111         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 112         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 113         fbc_ctl |= obj->fence_reg;
 114         I915_WRITE(FBC_CONTROL, fbc_ctl);
 115
 116         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 117                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 118 }
 119
 120 static bool i8xx_fbc_enabled(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123
 124         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 125 }
 126
 127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 128 {
 129         struct drm_device *dev = crtc->dev;
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         struct drm_framebuffer *fb = crtc->fb;
 132         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 133         struct drm_i915_gem_object *obj = intel_fb->obj;
 134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 135         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 136         unsigned long stall_watermark = 200;
 137         u32 dpfc_ctl;
 138
 139         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 140         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 141         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 142
 143         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 144                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 145                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 146         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 147
 148         /* enable it... */
 149         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 150
 151         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 152 }
 153
 154 static void g4x_disable_fbc(struct drm_device *dev)
 155 {
 156         struct drm_i915_private *dev_priv = dev->dev_private;
 157         u32 dpfc_ctl;
 158
 159         /* Disable compression */
 160         dpfc_ctl = I915_READ(DPFC_CONTROL);
 161         if (dpfc_ctl & DPFC_CTL_EN) {
 162                 dpfc_ctl &= ~DPFC_CTL_EN;
 163                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 164
 165                 DRM_DEBUG_KMS("disabled FBC\n");
 166         }
 167 }
 168
 169 static bool g4x_fbc_enabled(struct drm_device *dev)
 170 {
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172
 173         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 174 }
 175
 176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 177 {
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         u32 blt_ecoskpd;
 180
 181         /* Make sure blitter notifies FBC of writes */
 182         gen6_gt_force_wake_get(dev_priv);
 183         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 184         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 185                 GEN6_BLITTER_LOCK_SHIFT;
 186         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 187         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 188         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 189         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 190                          GEN6_BLITTER_LOCK_SHIFT);
 191         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 192         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 193         gen6_gt_force_wake_put(dev_priv);
 194 }
 195
 196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 197 {
 198         struct drm_device *dev = crtc->dev;
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         struct drm_framebuffer *fb = crtc->fb;
 201         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 202         struct drm_i915_gem_object *obj = intel_fb->obj;
 203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 204         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 205         unsigned long stall_watermark = 200;
 206         u32 dpfc_ctl;
 207
 208         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 209         dpfc_ctl &= DPFC_RESERVED;
 210         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 211         /* Set persistent mode for front-buffer rendering, ala X. */
 212         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 213         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 214         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 215
 216         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 217                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 218                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 219         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 220         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 221         /* enable it... */
 222         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 223
 224         if (IS_GEN6(dev)) {
 225                 I915_WRITE(SNB_DPFC_CTL_SA,
 226                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 227                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 228                 sandybridge_blit_fbc_update(dev);
 229         }
 230
 231         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 232 }
 233
 234 static void ironlake_disable_fbc(struct drm_device *dev)
 235 {
 236         struct drm_i915_private *dev_priv = dev->dev_private;
 237         u32 dpfc_ctl;
 238
 239         /* Disable compression */
 240         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 241         if (dpfc_ctl & DPFC_CTL_EN) {
 242                 dpfc_ctl &= ~DPFC_CTL_EN;
 243                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 244
 245                 if (IS_IVYBRIDGE(dev))
 246                         /* WaFbcDisableDpfcClockGating:ivb */
 247                         I915_WRITE(ILK_DSPCLK_GATE_D,
 248                                    I915_READ(ILK_DSPCLK_GATE_D) &
 249                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 250
 251                 if (IS_HASWELL(dev))
 252                         /* WaFbcDisableDpfcClockGating:hsw */
 253                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 254                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
 255                                    ~HSW_DPFC_GATING_DISABLE);
 256
 257                 DRM_DEBUG_KMS("disabled FBC\n");
 258         }
 259 }
 260
 261 static bool ironlake_fbc_enabled(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264
 265         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 266 }
 267
 268 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 269 {
 270         struct drm_device *dev = crtc->dev;
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         struct drm_framebuffer *fb = crtc->fb;
 273         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 274         struct drm_i915_gem_object *obj = intel_fb->obj;
 275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 276
 277         I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 278
 279         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 280                    IVB_DPFC_CTL_FENCE_EN |
 281                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 282
 283         if (IS_IVYBRIDGE(dev)) {
 284                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 285                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 286                 /* WaFbcDisableDpfcClockGating:ivb */
 287                 I915_WRITE(ILK_DSPCLK_GATE_D,
 288                            I915_READ(ILK_DSPCLK_GATE_D) |
 289                            ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 290         } else {
 291                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 292                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 293                            HSW_BYPASS_FBC_QUEUE);
 294                 /* WaFbcDisableDpfcClockGating:hsw */
 295                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 296                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
 297                            HSW_DPFC_GATING_DISABLE);
 298         }
 299
 300         I915_WRITE(SNB_DPFC_CTL_SA,
 301                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 302         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 303
 304         sandybridge_blit_fbc_update(dev);
 305
 306         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 307 }
 308
 309 bool intel_fbc_enabled(struct drm_device *dev)
 310 {
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312
 313         if (!dev_priv->display.fbc_enabled)
 314                 return false;
 315
 316         return dev_priv->display.fbc_enabled(dev);
 317 }
 318
 319 static void intel_fbc_work_fn(struct work_struct *__work)
 320 {
 321         struct intel_fbc_work *work =
 322                 container_of(to_delayed_work(__work),
 323                              struct intel_fbc_work, work);
 324         struct drm_device *dev = work->crtc->dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326
 327         mutex_lock(&dev->struct_mutex);
 328         if (work == dev_priv->fbc_work) {
 329                 /* Double check that we haven't switched fb without cancelling
 330                  * the prior work.
 331                  */
 332                 if (work->crtc->fb == work->fb) {
 333                         dev_priv->display.enable_fbc(work->crtc,
 334                                                      work->interval);
 335
 336                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 337                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 338                         dev_priv->cfb_y = work->crtc->y;
 339                 }
 340
 341                 dev_priv->fbc_work = NULL;
 342         }
 343         mutex_unlock(&dev->struct_mutex);
 344
 345         kfree(work);
 346 }
 347
 348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 349 {
 350         if (dev_priv->fbc_work == NULL)
 351                 return;
 352
 353         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 354
 355         /* Synchronisation is provided by struct_mutex and checking of
 356          * dev_priv->fbc_work, so we can perform the cancellation
 357          * entirely asynchronously.
 358          */
 359         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 360                 /* tasklet was killed before being run, clean up */
 361                 kfree(dev_priv->fbc_work);
 362
 363         /* Mark the work as no longer wanted so that if it does
 364          * wake-up (because the work was already running and waiting
 365          * for our mutex), it will discover that is no longer
 366          * necessary to run.
 367          */
 368         dev_priv->fbc_work = NULL;
 369 }
 370
 371 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 372 {
 373         struct intel_fbc_work *work;
 374         struct drm_device *dev = crtc->dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         if (!dev_priv->display.enable_fbc)
 378                 return;
 379
 380         intel_cancel_fbc_work(dev_priv);
 381
 382         work = kzalloc(sizeof *work, GFP_KERNEL);
 383         if (work == NULL) {
 384                 dev_priv->display.enable_fbc(crtc, interval);
 385                 return;
 386         }
 387
 388         work->crtc = crtc;
 389         work->fb = crtc->fb;
 390         work->interval = interval;
 391         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 392
 393         dev_priv->fbc_work = work;
 394
 395         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 396
 397         /* Delay the actual enabling to let pageflipping cease and the
 398          * display to settle before starting the compression. Note that
 399          * this delay also serves a second purpose: it allows for a
 400          * vblank to pass after disabling the FBC before we attempt
 401          * to modify the control registers.
 402          *
 403          * A more complicated solution would involve tracking vblanks
 404          * following the termination of the page-flipping sequence
 405          * and indeed performing the enable as a co-routine and not
 406          * waiting synchronously upon the vblank.
 407          */
 408         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 409 }
 410
 411 void intel_disable_fbc(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         intel_cancel_fbc_work(dev_priv);
 416
 417         if (!dev_priv->display.disable_fbc)
 418                 return;
 419
 420         dev_priv->display.disable_fbc(dev);
 421         dev_priv->cfb_plane = -1;
 422 }
 423
 424 /**
 425  * intel_update_fbc - enable/disable FBC as needed
 426  * @dev: the drm_device
 427  *
 428  * Set up the framebuffer compression hardware at mode set time.  We
 429  * enable it if possible:
 430  *   - plane A only (on pre-965)
 431  *   - no pixel mulitply/line duplication
 432  *   - no alpha buffer discard
 433  *   - no dual wide
 434  *   - framebuffer <= 2048 in width, 1536 in height
 435  *
 436  * We can't assume that any compression will take place (worst case),
 437  * so the compressed buffer has to be the same size as the uncompressed
 438  * one.  It also must reside (along with the line length buffer) in
 439  * stolen memory.
 440  *
 441  * We need to enable/disable FBC on a global basis.
 442  */
 443 void intel_update_fbc(struct drm_device *dev)
 444 {
 445         struct drm_i915_private *dev_priv = dev->dev_private;
 446         struct drm_crtc *crtc = NULL, *tmp_crtc;
 447         struct intel_crtc *intel_crtc;
 448         struct drm_framebuffer *fb;
 449         struct intel_framebuffer *intel_fb;
 450         struct drm_i915_gem_object *obj;
 451         int enable_fbc;
 452
 453         if (!i915_powersave)
 454                 return;
 455
 456         if (!I915_HAS_FBC(dev))
 457                 return;
 458
 459         /*
 460          * If FBC is already on, we just have to verify that we can
 461          * keep it that way...
 462          * Need to disable if:
 463          *   - more than one pipe is active
 464          *   - changing FBC params (stride, fence, mode)
 465          *   - new fb is too large to fit in compressed buffer
 466          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 467          */
 468         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 469                 if (intel_crtc_active(tmp_crtc) &&
 470                     !to_intel_crtc(tmp_crtc)->primary_disabled) {
 471                         if (crtc) {
 472                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 473                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 474                                 goto out_disable;
 475                         }
 476                         crtc = tmp_crtc;
 477                 }
 478         }
 479
 480         if (!crtc || crtc->fb == NULL) {
 481                 DRM_DEBUG_KMS("no output, disabling\n");
 482                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 483                 goto out_disable;
 484         }
 485
 486         intel_crtc = to_intel_crtc(crtc);
 487         fb = crtc->fb;
 488         intel_fb = to_intel_framebuffer(fb);
 489         obj = intel_fb->obj;
 490
 491         enable_fbc = i915_enable_fbc;
 492         if (enable_fbc < 0) {
 493                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 494                 enable_fbc = 1;
 495                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
 496                         enable_fbc = 0;
 497         }
 498         if (!enable_fbc) {
 499                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 500                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 501                 goto out_disable;
 502         }
 503         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 504             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 505                 DRM_DEBUG_KMS("mode incompatible with compression, "
 506                               "disabling\n");
 507                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 508                 goto out_disable;
 509         }
 510         if ((crtc->mode.hdisplay > 2048) ||
 511             (crtc->mode.vdisplay > 1536)) {
 512                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 513                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 514                 goto out_disable;
 515         }
 516         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 517             intel_crtc->plane != 0) {
 518                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 519                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 520                 goto out_disable;
 521         }
 522
 523         /* The use of a CPU fence is mandatory in order to detect writes
 524          * by the CPU to the scanout and trigger updates to the FBC.
 525          */
 526         if (obj->tiling_mode != I915_TILING_X ||
 527             obj->fence_reg == I915_FENCE_REG_NONE) {
 528                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 529                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 530                 goto out_disable;
 531         }
 532
 533         /* If the kernel debugger is active, always disable compression */
 534         if (in_dbg_master())
 535                 goto out_disable;
 536
 537         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 538                 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 539                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 540                 goto out_disable;
 541         }
 542
 543         /* If the scanout has not changed, don't modify the FBC settings.
 544          * Note that we make the fundamental assumption that the fb->obj
 545          * cannot be unpinned (and have its GTT offset and fence revoked)
 546          * without first being decoupled from the scanout and FBC disabled.
 547          */
 548         if (dev_priv->cfb_plane == intel_crtc->plane &&
 549             dev_priv->cfb_fb == fb->base.id &&
 550             dev_priv->cfb_y == crtc->y)
 551                 return;
 552
 553         if (intel_fbc_enabled(dev)) {
 554                 /* We update FBC along two paths, after changing fb/crtc
 555                  * configuration (modeswitching) and after page-flipping
 556                  * finishes. For the latter, we know that not only did
 557                  * we disable the FBC at the start of the page-flip
 558                  * sequence, but also more than one vblank has passed.
 559                  *
 560                  * For the former case of modeswitching, it is possible
 561                  * to switch between two FBC valid configurations
 562                  * instantaneously so we do need to disable the FBC
 563                  * before we can modify its control registers. We also
 564                  * have to wait for the next vblank for that to take
 565                  * effect. However, since we delay enabling FBC we can
 566                  * assume that a vblank has passed since disabling and
 567                  * that we can safely alter the registers in the deferred
 568                  * callback.
 569                  *
 570                  * In the scenario that we go from a valid to invalid
 571                  * and then back to valid FBC configuration we have
 572                  * no strict enforcement that a vblank occurred since
 573                  * disabling the FBC. However, along all current pipe
 574                  * disabling paths we do need to wait for a vblank at
 575                  * some point. And we wait before enabling FBC anyway.
 576                  */
 577                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 578                 intel_disable_fbc(dev);
 579         }
 580
 581         intel_enable_fbc(crtc, 500);
 582         return;
 583
 584 out_disable:
 585         /* Multiple disables should be harmless */
 586         if (intel_fbc_enabled(dev)) {
 587                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 588                 intel_disable_fbc(dev);
 589         }
 590         i915_gem_stolen_cleanup_compression(dev);
 591 }
 592
 593 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 594 {
 595         drm_i915_private_t *dev_priv = dev->dev_private;
 596         u32 tmp;
 597
 598         tmp = I915_READ(CLKCFG);
 599
 600         switch (tmp & CLKCFG_FSB_MASK) {
 601         case CLKCFG_FSB_533:
 602                 dev_priv->fsb_freq = 533; /* 133*4 */
 603                 break;
 604         case CLKCFG_FSB_800:
 605                 dev_priv->fsb_freq = 800; /* 200*4 */
 606                 break;
 607         case CLKCFG_FSB_667:
 608                 dev_priv->fsb_freq =  667; /* 167*4 */
 609                 break;
 610         case CLKCFG_FSB_400:
 611                 dev_priv->fsb_freq = 400; /* 100*4 */
 612                 break;
 613         }
 614
 615         switch (tmp & CLKCFG_MEM_MASK) {
 616         case CLKCFG_MEM_533:
 617                 dev_priv->mem_freq = 533;
 618                 break;
 619         case CLKCFG_MEM_667:
 620                 dev_priv->mem_freq = 667;
 621                 break;
 622         case CLKCFG_MEM_800:
 623                 dev_priv->mem_freq = 800;
 624                 break;
 625         }
 626
 627         /* detect pineview DDR3 setting */
 628         tmp = I915_READ(CSHRDDR3CTL);
 629         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 630 }
 631
 632 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 633 {
 634         drm_i915_private_t *dev_priv = dev->dev_private;
 635         u16 ddrpll, csipll;
 636
 637         ddrpll = I915_READ16(DDRMPLL1);
 638         csipll = I915_READ16(CSIPLL0);
 639
 640         switch (ddrpll & 0xff) {
 641         case 0xc:
 642                 dev_priv->mem_freq = 800;
 643                 break;
 644         case 0x10:
 645                 dev_priv->mem_freq = 1066;
 646                 break;
 647         case 0x14:
 648                 dev_priv->mem_freq = 1333;
 649                 break;
 650         case 0x18:
 651                 dev_priv->mem_freq = 1600;
 652                 break;
 653         default:
 654                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 655                                  ddrpll & 0xff);
 656                 dev_priv->mem_freq = 0;
 657                 break;
 658         }
 659
 660         dev_priv->ips.r_t = dev_priv->mem_freq;
 661
 662         switch (csipll & 0x3ff) {
 663         case 0x00c:
 664                 dev_priv->fsb_freq = 3200;
 665                 break;
 666         case 0x00e:
 667                 dev_priv->fsb_freq = 3733;
 668                 break;
 669         case 0x010:
 670                 dev_priv->fsb_freq = 4266;
 671                 break;
 672         case 0x012:
 673                 dev_priv->fsb_freq = 4800;
 674                 break;
 675         case 0x014:
 676                 dev_priv->fsb_freq = 5333;
 677                 break;
 678         case 0x016:
 679                 dev_priv->fsb_freq = 5866;
 680                 break;
 681         case 0x018:
 682                 dev_priv->fsb_freq = 6400;
 683                 break;
 684         default:
 685                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 686                                  csipll & 0x3ff);
 687                 dev_priv->fsb_freq = 0;
 688                 break;
 689         }
 690
 691         if (dev_priv->fsb_freq == 3200) {
 692                 dev_priv->ips.c_m = 0;
 693         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 694                 dev_priv->ips.c_m = 1;
 695         } else {
 696                 dev_priv->ips.c_m = 2;
 697         }
 698 }
 699
 700 static const struct cxsr_latency cxsr_latency_table[] = {
 701         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 702         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 703         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 704         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 705         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 706
 707         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 708         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 709         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 710         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 711         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 712
 713         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 714         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 715         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 716         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 717         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 718
 719         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 720         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 721         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 722         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 723         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 724
 725         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 726         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 727         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 728         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 729         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 730
 731         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 732         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 733         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 734         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 735         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 736 };
 737
 738 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 739                                                          int is_ddr3,
 740                                                          int fsb,
 741                                                          int mem)
 742 {
 743         const struct cxsr_latency *latency;
 744         int i;
 745
 746         if (fsb == 0 || mem == 0)
 747                 return NULL;
 748
 749         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 750                 latency = &cxsr_latency_table[i];
 751                 if (is_desktop == latency->is_desktop &&
 752                     is_ddr3 == latency->is_ddr3 &&
 753                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 754                         return latency;
 755         }
 756
 757         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 758
 759         return NULL;
 760 }
 761
 762 static void pineview_disable_cxsr(struct drm_device *dev)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765
 766         /* deactivate cxsr */
 767         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 768 }
 769
 770 /*
 771  * Latency for FIFO fetches is dependent on several factors:
 772  *   - memory configuration (speed, channels)
 773  *   - chipset
 774  *   - current MCH state
 775  * It can be fairly high in some situations, so here we assume a fairly
 776  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 777  * set this value too high, the FIFO will fetch frequently to stay full)
 778  * and power consumption (set it too low to save power and we might see
 779  * FIFO underruns and display "flicker").
 780  *
 781  * A value of 5us seems to be a good balance; safe for very low end
 782  * platforms but not overly aggressive on lower latency configs.
 783  */
 784 static const int latency_ns = 5000;
 785
 786 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 787 {
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         uint32_t dsparb = I915_READ(DSPARB);
 790         int size;
 791
 792         size = dsparb & 0x7f;
 793         if (plane)
 794                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 795
 796         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 797                       plane ? "B" : "A", size);
 798
 799         return size;
 800 }
 801
 802 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 803 {
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         uint32_t dsparb = I915_READ(DSPARB);
 806         int size;
 807
 808         size = dsparb & 0x1ff;
 809         if (plane)
 810                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 811         size >>= 1; /* Convert to cachelines */
 812
 813         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 814                       plane ? "B" : "A", size);
 815
 816         return size;
 817 }
 818
 819 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 820 {
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822         uint32_t dsparb = I915_READ(DSPARB);
 823         int size;
 824
 825         size = dsparb & 0x7f;
 826         size >>= 2; /* Convert to cachelines */
 827
 828         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 829                       plane ? "B" : "A",
 830                       size);
 831
 832         return size;
 833 }
 834
 835 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 836 {
 837         struct drm_i915_private *dev_priv = dev->dev_private;
 838         uint32_t dsparb = I915_READ(DSPARB);
 839         int size;
 840
 841         size = dsparb & 0x7f;
 842         size >>= 1; /* Convert to cachelines */
 843
 844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 845                       plane ? "B" : "A", size);
 846
 847         return size;
 848 }
 849
 850 /* Pineview has different values for various configs */
 851 static const struct intel_watermark_params pineview_display_wm = {
 852         PINEVIEW_DISPLAY_FIFO,
 853         PINEVIEW_MAX_WM,
 854         PINEVIEW_DFT_WM,
 855         PINEVIEW_GUARD_WM,
 856         PINEVIEW_FIFO_LINE_SIZE
 857 };
 858 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 859         PINEVIEW_DISPLAY_FIFO,
 860         PINEVIEW_MAX_WM,
 861         PINEVIEW_DFT_HPLLOFF_WM,
 862         PINEVIEW_GUARD_WM,
 863         PINEVIEW_FIFO_LINE_SIZE
 864 };
 865 static const struct intel_watermark_params pineview_cursor_wm = {
 866         PINEVIEW_CURSOR_FIFO,
 867         PINEVIEW_CURSOR_MAX_WM,
 868         PINEVIEW_CURSOR_DFT_WM,
 869         PINEVIEW_CURSOR_GUARD_WM,
 870         PINEVIEW_FIFO_LINE_SIZE,
 871 };
 872 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 873         PINEVIEW_CURSOR_FIFO,
 874         PINEVIEW_CURSOR_MAX_WM,
 875         PINEVIEW_CURSOR_DFT_WM,
 876         PINEVIEW_CURSOR_GUARD_WM,
 877         PINEVIEW_FIFO_LINE_SIZE
 878 };
 879 static const struct intel_watermark_params g4x_wm_info = {
 880         G4X_FIFO_SIZE,
 881         G4X_MAX_WM,
 882         G4X_MAX_WM,
 883         2,
 884         G4X_FIFO_LINE_SIZE,
 885 };
 886 static const struct intel_watermark_params g4x_cursor_wm_info = {
 887         I965_CURSOR_FIFO,
 888         I965_CURSOR_MAX_WM,
 889         I965_CURSOR_DFT_WM,
 890         2,
 891         G4X_FIFO_LINE_SIZE,
 892 };
 893 static const struct intel_watermark_params valleyview_wm_info = {
 894         VALLEYVIEW_FIFO_SIZE,
 895         VALLEYVIEW_MAX_WM,
 896         VALLEYVIEW_MAX_WM,
 897         2,
 898         G4X_FIFO_LINE_SIZE,
 899 };
 900 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 901         I965_CURSOR_FIFO,
 902         VALLEYVIEW_CURSOR_MAX_WM,
 903         I965_CURSOR_DFT_WM,
 904         2,
 905         G4X_FIFO_LINE_SIZE,
 906 };
 907 static const struct intel_watermark_params i965_cursor_wm_info = {
 908         I965_CURSOR_FIFO,
 909         I965_CURSOR_MAX_WM,
 910         I965_CURSOR_DFT_WM,
 911         2,
 912         I915_FIFO_LINE_SIZE,
 913 };
 914 static const struct intel_watermark_params i945_wm_info = {
 915         I945_FIFO_SIZE,
 916         I915_MAX_WM,
 917         1,
 918         2,
 919         I915_FIFO_LINE_SIZE
 920 };
 921 static const struct intel_watermark_params i915_wm_info = {
 922         I915_FIFO_SIZE,
 923         I915_MAX_WM,
 924         1,
 925         2,
 926         I915_FIFO_LINE_SIZE
 927 };
 928 static const struct intel_watermark_params i855_wm_info = {
 929         I855GM_FIFO_SIZE,
 930         I915_MAX_WM,
 931         1,
 932         2,
 933         I830_FIFO_LINE_SIZE
 934 };
 935 static const struct intel_watermark_params i830_wm_info = {
 936         I830_FIFO_SIZE,
 937         I915_MAX_WM,
 938         1,
 939         2,
 940         I830_FIFO_LINE_SIZE
 941 };
 942
 943 static const struct intel_watermark_params ironlake_display_wm_info = {
 944         ILK_DISPLAY_FIFO,
 945         ILK_DISPLAY_MAXWM,
 946         ILK_DISPLAY_DFTWM,
 947         2,
 948         ILK_FIFO_LINE_SIZE
 949 };
 950 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 951         ILK_CURSOR_FIFO,
 952         ILK_CURSOR_MAXWM,
 953         ILK_CURSOR_DFTWM,
 954         2,
 955         ILK_FIFO_LINE_SIZE
 956 };
 957 static const struct intel_watermark_params ironlake_display_srwm_info = {
 958         ILK_DISPLAY_SR_FIFO,
 959         ILK_DISPLAY_MAX_SRWM,
 960         ILK_DISPLAY_DFT_SRWM,
 961         2,
 962         ILK_FIFO_LINE_SIZE
 963 };
 964 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 965         ILK_CURSOR_SR_FIFO,
 966         ILK_CURSOR_MAX_SRWM,
 967         ILK_CURSOR_DFT_SRWM,
 968         2,
 969         ILK_FIFO_LINE_SIZE
 970 };
 971
 972 static const struct intel_watermark_params sandybridge_display_wm_info = {
 973         SNB_DISPLAY_FIFO,
 974         SNB_DISPLAY_MAXWM,
 975         SNB_DISPLAY_DFTWM,
 976         2,
 977         SNB_FIFO_LINE_SIZE
 978 };
 979 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 980         SNB_CURSOR_FIFO,
 981         SNB_CURSOR_MAXWM,
 982         SNB_CURSOR_DFTWM,
 983         2,
 984         SNB_FIFO_LINE_SIZE
 985 };
 986 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 987         SNB_DISPLAY_SR_FIFO,
 988         SNB_DISPLAY_MAX_SRWM,
 989         SNB_DISPLAY_DFT_SRWM,
 990         2,
 991         SNB_FIFO_LINE_SIZE
 992 };
 993 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 994         SNB_CURSOR_SR_FIFO,
 995         SNB_CURSOR_MAX_SRWM,
 996         SNB_CURSOR_DFT_SRWM,
 997         2,
 998         SNB_FIFO_LINE_SIZE
 999 };
1000
1001
1002 /**
1003  * intel_calculate_wm - calculate watermark level
1004  * @clock_in_khz: pixel clock
1005  * @wm: chip FIFO params
1006  * @pixel_size: display pixel size
1007  * @latency_ns: memory latency for the platform
1008  *
1009  * Calculate the watermark level (the level at which the display plane will
1010  * start fetching from memory again).  Each chip has a different display
1011  * FIFO size and allocation, so the caller needs to figure that out and pass
1012  * in the correct intel_watermark_params structure.
1013  *
1014  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1015  * on the pixel size.  When it reaches the watermark level, it'll start
1016  * fetching FIFO line sized based chunks from memory until the FIFO fills
1017  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1018  * will occur, and a display engine hang could result.
1019  */
1020 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1021                                         const struct intel_watermark_params *wm,
1022                                         int fifo_size,
1023                                         int pixel_size,
1024                                         unsigned long latency_ns)
1025 {
1026         long entries_required, wm_size;
1027
1028         /*
1029          * Note: we need to make sure we don't overflow for various clock &
1030          * latency values.
1031          * clocks go from a few thousand to several hundred thousand.
1032          * latency is usually a few thousand
1033          */
1034         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1035                 1000;
1036         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1037
1038         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1039
1040         wm_size = fifo_size - (entries_required + wm->guard_size);
1041
1042         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1043
1044         /* Don't promote wm_size to unsigned... */
1045         if (wm_size > (long)wm->max_wm)
1046                 wm_size = wm->max_wm;
1047         if (wm_size <= 0)
1048                 wm_size = wm->default_wm;
1049         return wm_size;
1050 }
1051
1052 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1053 {
1054         struct drm_crtc *crtc, *enabled = NULL;
1055
1056         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1057                 if (intel_crtc_active(crtc)) {
1058                         if (enabled)
1059                                 return NULL;
1060                         enabled = crtc;
1061                 }
1062         }
1063
1064         return enabled;
1065 }
1066
1067 static void pineview_update_wm(struct drm_device *dev)
1068 {
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         struct drm_crtc *crtc;
1071         const struct cxsr_latency *latency;
1072         u32 reg;
1073         unsigned long wm;
1074
1075         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1076                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1077         if (!latency) {
1078                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1079                 pineview_disable_cxsr(dev);
1080                 return;
1081         }
1082
1083         crtc = single_enabled_crtc(dev);
1084         if (crtc) {
1085                 int clock = crtc->mode.clock;
1086                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1087
1088                 /* Display SR */
1089                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1090                                         pineview_display_wm.fifo_size,
1091                                         pixel_size, latency->display_sr);
1092                 reg = I915_READ(DSPFW1);
1093                 reg &= ~DSPFW_SR_MASK;
1094                 reg |= wm << DSPFW_SR_SHIFT;
1095                 I915_WRITE(DSPFW1, reg);
1096                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1097
1098                 /* cursor SR */
1099                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1100                                         pineview_display_wm.fifo_size,
1101                                         pixel_size, latency->cursor_sr);
1102                 reg = I915_READ(DSPFW3);
1103                 reg &= ~DSPFW_CURSOR_SR_MASK;
1104                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1105                 I915_WRITE(DSPFW3, reg);
1106
1107                 /* Display HPLL off SR */
1108                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1109                                         pineview_display_hplloff_wm.fifo_size,
1110                                         pixel_size, latency->display_hpll_disable);
1111                 reg = I915_READ(DSPFW3);
1112                 reg &= ~DSPFW_HPLL_SR_MASK;
1113                 reg |= wm & DSPFW_HPLL_SR_MASK;
1114                 I915_WRITE(DSPFW3, reg);
1115
1116                 /* cursor HPLL off SR */
1117                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1118                                         pineview_display_hplloff_wm.fifo_size,
1119                                         pixel_size, latency->cursor_hpll_disable);
1120                 reg = I915_READ(DSPFW3);
1121                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1122                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1123                 I915_WRITE(DSPFW3, reg);
1124                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1125
1126                 /* activate cxsr */
1127                 I915_WRITE(DSPFW3,
1128                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1129                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1130         } else {
1131                 pineview_disable_cxsr(dev);
1132                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1133         }
1134 }
1135
1136 static bool g4x_compute_wm0(struct drm_device *dev,
1137                             int plane,
1138                             const struct intel_watermark_params *display,
1139                             int display_latency_ns,
1140                             const struct intel_watermark_params *cursor,
1141                             int cursor_latency_ns,
1142                             int *plane_wm,
1143                             int *cursor_wm)
1144 {
1145         struct drm_crtc *crtc;
1146         int htotal, hdisplay, clock, pixel_size;
1147         int line_time_us, line_count;
1148         int entries, tlb_miss;
1149
1150         crtc = intel_get_crtc_for_plane(dev, plane);
1151         if (!intel_crtc_active(crtc)) {
1152                 *cursor_wm = cursor->guard_size;
1153                 *plane_wm = display->guard_size;
1154                 return false;
1155         }
1156
1157         htotal = crtc->mode.htotal;
1158         hdisplay = crtc->mode.hdisplay;
1159         clock = crtc->mode.clock;
1160         pixel_size = crtc->fb->bits_per_pixel / 8;
1161
1162         /* Use the small buffer method to calculate plane watermark */
1163         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1164         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1165         if (tlb_miss > 0)
1166                 entries += tlb_miss;
1167         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1168         *plane_wm = entries + display->guard_size;
1169         if (*plane_wm > (int)display->max_wm)
1170                 *plane_wm = display->max_wm;
1171
1172         /* Use the large buffer method to calculate cursor watermark */
1173         line_time_us = ((htotal * 1000) / clock);
1174         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1175         entries = line_count * 64 * pixel_size;
1176         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1177         if (tlb_miss > 0)
1178                 entries += tlb_miss;
1179         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1180         *cursor_wm = entries + cursor->guard_size;
1181         if (*cursor_wm > (int)cursor->max_wm)
1182                 *cursor_wm = (int)cursor->max_wm;
1183
1184         return true;
1185 }
1186
1187 /*
1188  * Check the wm result.
1189  *
1190  * If any calculated watermark values is larger than the maximum value that
1191  * can be programmed into the associated watermark register, that watermark
1192  * must be disabled.
1193  */
1194 static bool g4x_check_srwm(struct drm_device *dev,
1195                            int display_wm, int cursor_wm,
1196                            const struct intel_watermark_params *display,
1197                            const struct intel_watermark_params *cursor)
1198 {
1199         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1200                       display_wm, cursor_wm);
1201
1202         if (display_wm > display->max_wm) {
1203                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1204                               display_wm, display->max_wm);
1205                 return false;
1206         }
1207
1208         if (cursor_wm > cursor->max_wm) {
1209                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1210                               cursor_wm, cursor->max_wm);
1211                 return false;
1212         }
1213
1214         if (!(display_wm || cursor_wm)) {
1215                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1216                 return false;
1217         }
1218
1219         return true;
1220 }
1221
1222 static bool g4x_compute_srwm(struct drm_device *dev,
1223                              int plane,
1224                              int latency_ns,
1225                              const struct intel_watermark_params *display,
1226                              const struct intel_watermark_params *cursor,
1227                              int *display_wm, int *cursor_wm)
1228 {
1229         struct drm_crtc *crtc;
1230         int hdisplay, htotal, pixel_size, clock;
1231         unsigned long line_time_us;
1232         int line_count, line_size;
1233         int small, large;
1234         int entries;
1235
1236         if (!latency_ns) {
1237                 *display_wm = *cursor_wm = 0;
1238                 return false;
1239         }
1240
1241         crtc = intel_get_crtc_for_plane(dev, plane);
1242         hdisplay = crtc->mode.hdisplay;
1243         htotal = crtc->mode.htotal;
1244         clock = crtc->mode.clock;
1245         pixel_size = crtc->fb->bits_per_pixel / 8;
1246
1247         line_time_us = (htotal * 1000) / clock;
1248         line_count = (latency_ns / line_time_us + 1000) / 1000;
1249         line_size = hdisplay * pixel_size;
1250
1251         /* Use the minimum of the small and large buffer method for primary */
1252         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1253         large = line_count * line_size;
1254
1255         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1256         *display_wm = entries + display->guard_size;
1257
1258         /* calculate the self-refresh watermark for display cursor */
1259         entries = line_count * pixel_size * 64;
1260         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1261         *cursor_wm = entries + cursor->guard_size;
1262
1263         return g4x_check_srwm(dev,
1264                               *display_wm, *cursor_wm,
1265                               display, cursor);
1266 }
1267
1268 static bool vlv_compute_drain_latency(struct drm_device *dev,
1269                                      int plane,
1270                                      int *plane_prec_mult,
1271                                      int *plane_dl,
1272                                      int *cursor_prec_mult,
1273                                      int *cursor_dl)
1274 {
1275         struct drm_crtc *crtc;
1276         int clock, pixel_size;
1277         int entries;
1278
1279         crtc = intel_get_crtc_for_plane(dev, plane);
1280         if (!intel_crtc_active(crtc))
1281                 return false;
1282
1283         clock = crtc->mode.clock;       /* VESA DOT Clock */
1284         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1285
1286         entries = (clock / 1000) * pixel_size;
1287         *plane_prec_mult = (entries > 256) ?
1288                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1289         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1290                                                      pixel_size);
1291
1292         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1293         *cursor_prec_mult = (entries > 256) ?
1294                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1295         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1296
1297         return true;
1298 }
1299
1300 /*
1301  * Update drain latency registers of memory arbiter
1302  *
1303  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1304  * to be programmed. Each plane has a drain latency multiplier and a drain
1305  * latency value.
1306  */
1307
1308 static void vlv_update_drain_latency(struct drm_device *dev)
1309 {
1310         struct drm_i915_private *dev_priv = dev->dev_private;
1311         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1312         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1313         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1314                                                         either 16 or 32 */
1315
1316         /* For plane A, Cursor A */
1317         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1318                                       &cursor_prec_mult, &cursora_dl)) {
1319                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1320                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1321                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1322                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1323
1324                 I915_WRITE(VLV_DDL1, cursora_prec |
1325                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1326                                 planea_prec | planea_dl);
1327         }
1328
1329         /* For plane B, Cursor B */
1330         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1331                                       &cursor_prec_mult, &cursorb_dl)) {
1332                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1333                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1334                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1335                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1336
1337                 I915_WRITE(VLV_DDL2, cursorb_prec |
1338                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1339                                 planeb_prec | planeb_dl);
1340         }
1341 }
1342
1343 #define single_plane_enabled(mask) is_power_of_2(mask)
1344
1345 static void valleyview_update_wm(struct drm_device *dev)
1346 {
1347         static const int sr_latency_ns = 12000;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350         int plane_sr, cursor_sr;
1351         int ignore_plane_sr, ignore_cursor_sr;
1352         unsigned int enabled = 0;
1353
1354         vlv_update_drain_latency(dev);
1355
1356         if (g4x_compute_wm0(dev, PIPE_A,
1357                             &valleyview_wm_info, latency_ns,
1358                             &valleyview_cursor_wm_info, latency_ns,
1359                             &planea_wm, &cursora_wm))
1360                 enabled |= 1 << PIPE_A;
1361
1362         if (g4x_compute_wm0(dev, PIPE_B,
1363                             &valleyview_wm_info, latency_ns,
1364                             &valleyview_cursor_wm_info, latency_ns,
1365                             &planeb_wm, &cursorb_wm))
1366                 enabled |= 1 << PIPE_B;
1367
1368         if (single_plane_enabled(enabled) &&
1369             g4x_compute_srwm(dev, ffs(enabled) - 1,
1370                              sr_latency_ns,
1371                              &valleyview_wm_info,
1372                              &valleyview_cursor_wm_info,
1373                              &plane_sr, &ignore_cursor_sr) &&
1374             g4x_compute_srwm(dev, ffs(enabled) - 1,
1375                              2*sr_latency_ns,
1376                              &valleyview_wm_info,
1377                              &valleyview_cursor_wm_info,
1378                              &ignore_plane_sr, &cursor_sr)) {
1379                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1380         } else {
1381                 I915_WRITE(FW_BLC_SELF_VLV,
1382                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1383                 plane_sr = cursor_sr = 0;
1384         }
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387                       planea_wm, cursora_wm,
1388                       planeb_wm, cursorb_wm,
1389                       plane_sr, cursor_sr);
1390
1391         I915_WRITE(DSPFW1,
1392                    (plane_sr << DSPFW_SR_SHIFT) |
1393                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1395                    planea_wm);
1396         I915_WRITE(DSPFW2,
1397                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1398                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1399         I915_WRITE(DSPFW3,
1400                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1401                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1402 }
1403
1404 static void g4x_update_wm(struct drm_device *dev)
1405 {
1406         static const int sr_latency_ns = 12000;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1409         int plane_sr, cursor_sr;
1410         unsigned int enabled = 0;
1411
1412         if (g4x_compute_wm0(dev, PIPE_A,
1413                             &g4x_wm_info, latency_ns,
1414                             &g4x_cursor_wm_info, latency_ns,
1415                             &planea_wm, &cursora_wm))
1416                 enabled |= 1 << PIPE_A;
1417
1418         if (g4x_compute_wm0(dev, PIPE_B,
1419                             &g4x_wm_info, latency_ns,
1420                             &g4x_cursor_wm_info, latency_ns,
1421                             &planeb_wm, &cursorb_wm))
1422                 enabled |= 1 << PIPE_B;
1423
1424         if (single_plane_enabled(enabled) &&
1425             g4x_compute_srwm(dev, ffs(enabled) - 1,
1426                              sr_latency_ns,
1427                              &g4x_wm_info,
1428                              &g4x_cursor_wm_info,
1429                              &plane_sr, &cursor_sr)) {
1430                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1431         } else {
1432                 I915_WRITE(FW_BLC_SELF,
1433                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1434                 plane_sr = cursor_sr = 0;
1435         }
1436
1437         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1438                       planea_wm, cursora_wm,
1439                       planeb_wm, cursorb_wm,
1440                       plane_sr, cursor_sr);
1441
1442         I915_WRITE(DSPFW1,
1443                    (plane_sr << DSPFW_SR_SHIFT) |
1444                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1445                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1446                    planea_wm);
1447         I915_WRITE(DSPFW2,
1448                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1449                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1450         /* HPLL off in SR has some issues on G4x... disable it */
1451         I915_WRITE(DSPFW3,
1452                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1453                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1454 }
1455
1456 static void i965_update_wm(struct drm_device *dev)
1457 {
1458         struct drm_i915_private *dev_priv = dev->dev_private;
1459         struct drm_crtc *crtc;
1460         int srwm = 1;
1461         int cursor_sr = 16;
1462
1463         /* Calc sr entries for one plane configs */
1464         crtc = single_enabled_crtc(dev);
1465         if (crtc) {
1466                 /* self-refresh has much higher latency */
1467                 static const int sr_latency_ns = 12000;
1468                 int clock = crtc->mode.clock;
1469                 int htotal = crtc->mode.htotal;
1470                 int hdisplay = crtc->mode.hdisplay;
1471                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1472                 unsigned long line_time_us;
1473                 int entries;
1474
1475                 line_time_us = ((htotal * 1000) / clock);
1476
1477                 /* Use ns/us then divide to preserve precision */
1478                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479                         pixel_size * hdisplay;
1480                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1481                 srwm = I965_FIFO_SIZE - entries;
1482                 if (srwm < 0)
1483                         srwm = 1;
1484                 srwm &= 0x1ff;
1485                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1486                               entries, srwm);
1487
1488                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1489                         pixel_size * 64;
1490                 entries = DIV_ROUND_UP(entries,
1491                                           i965_cursor_wm_info.cacheline_size);
1492                 cursor_sr = i965_cursor_wm_info.fifo_size -
1493                         (entries + i965_cursor_wm_info.guard_size);
1494
1495                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1496                         cursor_sr = i965_cursor_wm_info.max_wm;
1497
1498                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499                               "cursor %d\n", srwm, cursor_sr);
1500
1501                 if (IS_CRESTLINE(dev))
1502                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1503         } else {
1504                 /* Turn off self refresh if both pipes are enabled */
1505                 if (IS_CRESTLINE(dev))
1506                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1507                                    & ~FW_BLC_SELF_EN);
1508         }
1509
1510         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1511                       srwm);
1512
1513         /* 965 has limitations... */
1514         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1515                    (8 << 16) | (8 << 8) | (8 << 0));
1516         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1517         /* update cursor SR watermark */
1518         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1519 }
1520
1521 static void i9xx_update_wm(struct drm_device *dev)
1522 {
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         const struct intel_watermark_params *wm_info;
1525         uint32_t fwater_lo;
1526         uint32_t fwater_hi;
1527         int cwm, srwm = 1;
1528         int fifo_size;
1529         int planea_wm, planeb_wm;
1530         struct drm_crtc *crtc, *enabled = NULL;
1531
1532         if (IS_I945GM(dev))
1533                 wm_info = &i945_wm_info;
1534         else if (!IS_GEN2(dev))
1535                 wm_info = &i915_wm_info;
1536         else
1537                 wm_info = &i855_wm_info;
1538
1539         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540         crtc = intel_get_crtc_for_plane(dev, 0);
1541         if (intel_crtc_active(crtc)) {
1542                 int cpp = crtc->fb->bits_per_pixel / 8;
1543                 if (IS_GEN2(dev))
1544                         cpp = 4;
1545
1546                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1547                                                wm_info, fifo_size, cpp,
1548                                                latency_ns);
1549                 enabled = crtc;
1550         } else
1551                 planea_wm = fifo_size - wm_info->guard_size;
1552
1553         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554         crtc = intel_get_crtc_for_plane(dev, 1);
1555         if (intel_crtc_active(crtc)) {
1556                 int cpp = crtc->fb->bits_per_pixel / 8;
1557                 if (IS_GEN2(dev))
1558                         cpp = 4;
1559
1560                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1561                                                wm_info, fifo_size, cpp,
1562                                                latency_ns);
1563                 if (enabled == NULL)
1564                         enabled = crtc;
1565                 else
1566                         enabled = NULL;
1567         } else
1568                 planeb_wm = fifo_size - wm_info->guard_size;
1569
1570         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1571
1572         /*
1573          * Overlay gets an aggressive default since video jitter is bad.
1574          */
1575         cwm = 2;
1576
1577         /* Play safe and disable self-refresh before adjusting watermarks. */
1578         if (IS_I945G(dev) || IS_I945GM(dev))
1579                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1580         else if (IS_I915GM(dev))
1581                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1582
1583         /* Calc sr entries for one plane configs */
1584         if (HAS_FW_BLC(dev) && enabled) {
1585                 /* self-refresh has much higher latency */
1586                 static const int sr_latency_ns = 6000;
1587                 int clock = enabled->mode.clock;
1588                 int htotal = enabled->mode.htotal;
1589                 int hdisplay = enabled->mode.hdisplay;
1590                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1591                 unsigned long line_time_us;
1592                 int entries;
1593
1594                 line_time_us = (htotal * 1000) / clock;
1595
1596                 /* Use ns/us then divide to preserve precision */
1597                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1598                         pixel_size * hdisplay;
1599                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1600                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1601                 srwm = wm_info->fifo_size - entries;
1602                 if (srwm < 0)
1603                         srwm = 1;
1604
1605                 if (IS_I945G(dev) || IS_I945GM(dev))
1606                         I915_WRITE(FW_BLC_SELF,
1607                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1608                 else if (IS_I915GM(dev))
1609                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1610         }
1611
1612         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613                       planea_wm, planeb_wm, cwm, srwm);
1614
1615         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1616         fwater_hi = (cwm & 0x1f);
1617
1618         /* Set request length to 8 cachelines per fetch */
1619         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1620         fwater_hi = fwater_hi | (1 << 8);
1621
1622         I915_WRITE(FW_BLC, fwater_lo);
1623         I915_WRITE(FW_BLC2, fwater_hi);
1624
1625         if (HAS_FW_BLC(dev)) {
1626                 if (enabled) {
1627                         if (IS_I945G(dev) || IS_I945GM(dev))
1628                                 I915_WRITE(FW_BLC_SELF,
1629                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1630                         else if (IS_I915GM(dev))
1631                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1632                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1633                 } else
1634                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1635         }
1636 }
1637
1638 static void i830_update_wm(struct drm_device *dev)
1639 {
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         struct drm_crtc *crtc;
1642         uint32_t fwater_lo;
1643         int planea_wm;
1644
1645         crtc = single_enabled_crtc(dev);
1646         if (crtc == NULL)
1647                 return;
1648
1649         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1650                                        dev_priv->display.get_fifo_size(dev, 0),
1651                                        4, latency_ns);
1652         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1653         fwater_lo |= (3<<8) | planea_wm;
1654
1655         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1656
1657         I915_WRITE(FW_BLC, fwater_lo);
1658 }
1659
1660 #define ILK_LP0_PLANE_LATENCY           700
1661 #define ILK_LP0_CURSOR_LATENCY          1300
1662
1663 /*
1664  * Check the wm result.
1665  *
1666  * If any calculated watermark values is larger than the maximum value that
1667  * can be programmed into the associated watermark register, that watermark
1668  * must be disabled.
1669  */
1670 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1671                                 int fbc_wm, int display_wm, int cursor_wm,
1672                                 const struct intel_watermark_params *display,
1673                                 const struct intel_watermark_params *cursor)
1674 {
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1678                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1679
1680         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1681                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1682                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1683
1684                 /* fbc has it's own way to disable FBC WM */
1685                 I915_WRITE(DISP_ARB_CTL,
1686                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1687                 return false;
1688         } else if (INTEL_INFO(dev)->gen >= 6) {
1689                 /* enable FBC WM (except on ILK, where it must remain off) */
1690                 I915_WRITE(DISP_ARB_CTL,
1691                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1692         }
1693
1694         if (display_wm > display->max_wm) {
1695                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1696                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1697                 return false;
1698         }
1699
1700         if (cursor_wm > cursor->max_wm) {
1701                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1702                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1703                 return false;
1704         }
1705
1706         if (!(fbc_wm || display_wm || cursor_wm)) {
1707                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1708                 return false;
1709         }
1710
1711         return true;
1712 }
1713
1714 /*
1715  * Compute watermark values of WM[1-3],
1716  */
1717 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1718                                   int latency_ns,
1719                                   const struct intel_watermark_params *display,
1720                                   const struct intel_watermark_params *cursor,
1721                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1722 {
1723         struct drm_crtc *crtc;
1724         unsigned long line_time_us;
1725         int hdisplay, htotal, pixel_size, clock;
1726         int line_count, line_size;
1727         int small, large;
1728         int entries;
1729
1730         if (!latency_ns) {
1731                 *fbc_wm = *display_wm = *cursor_wm = 0;
1732                 return false;
1733         }
1734
1735         crtc = intel_get_crtc_for_plane(dev, plane);
1736         hdisplay = crtc->mode.hdisplay;
1737         htotal = crtc->mode.htotal;
1738         clock = crtc->mode.clock;
1739         pixel_size = crtc->fb->bits_per_pixel / 8;
1740
1741         line_time_us = (htotal * 1000) / clock;
1742         line_count = (latency_ns / line_time_us + 1000) / 1000;
1743         line_size = hdisplay * pixel_size;
1744
1745         /* Use the minimum of the small and large buffer method for primary */
1746         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1747         large = line_count * line_size;
1748
1749         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1750         *display_wm = entries + display->guard_size;
1751
1752         /*
1753          * Spec says:
1754          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1755          */
1756         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1757
1758         /* calculate the self-refresh watermark for display cursor */
1759         entries = line_count * pixel_size * 64;
1760         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1761         *cursor_wm = entries + cursor->guard_size;
1762
1763         return ironlake_check_srwm(dev, level,
1764                                    *fbc_wm, *display_wm, *cursor_wm,
1765                                    display, cursor);
1766 }
1767
1768 static void ironlake_update_wm(struct drm_device *dev)
1769 {
1770         struct drm_i915_private *dev_priv = dev->dev_private;
1771         int fbc_wm, plane_wm, cursor_wm;
1772         unsigned int enabled;
1773
1774         enabled = 0;
1775         if (g4x_compute_wm0(dev, PIPE_A,
1776                             &ironlake_display_wm_info,
1777                             ILK_LP0_PLANE_LATENCY,
1778                             &ironlake_cursor_wm_info,
1779                             ILK_LP0_CURSOR_LATENCY,
1780                             &plane_wm, &cursor_wm)) {
1781                 I915_WRITE(WM0_PIPEA_ILK,
1782                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1783                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1784                               " plane %d, " "cursor: %d\n",
1785                               plane_wm, cursor_wm);
1786                 enabled |= 1 << PIPE_A;
1787         }
1788
1789         if (g4x_compute_wm0(dev, PIPE_B,
1790                             &ironlake_display_wm_info,
1791                             ILK_LP0_PLANE_LATENCY,
1792                             &ironlake_cursor_wm_info,
1793                             ILK_LP0_CURSOR_LATENCY,
1794                             &plane_wm, &cursor_wm)) {
1795                 I915_WRITE(WM0_PIPEB_ILK,
1796                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1797                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1798                               " plane %d, cursor: %d\n",
1799                               plane_wm, cursor_wm);
1800                 enabled |= 1 << PIPE_B;
1801         }
1802
1803         /*
1804          * Calculate and update the self-refresh watermark only when one
1805          * display plane is used.
1806          */
1807         I915_WRITE(WM3_LP_ILK, 0);
1808         I915_WRITE(WM2_LP_ILK, 0);
1809         I915_WRITE(WM1_LP_ILK, 0);
1810
1811         if (!single_plane_enabled(enabled))
1812                 return;
1813         enabled = ffs(enabled) - 1;
1814
1815         /* WM1 */
1816         if (!ironlake_compute_srwm(dev, 1, enabled,
1817                                    ILK_READ_WM1_LATENCY() * 500,
1818                                    &ironlake_display_srwm_info,
1819                                    &ironlake_cursor_srwm_info,
1820                                    &fbc_wm, &plane_wm, &cursor_wm))
1821                 return;
1822
1823         I915_WRITE(WM1_LP_ILK,
1824                    WM1_LP_SR_EN |
1825                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1826                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1827                    (plane_wm << WM1_LP_SR_SHIFT) |
1828                    cursor_wm);
1829
1830         /* WM2 */
1831         if (!ironlake_compute_srwm(dev, 2, enabled,
1832                                    ILK_READ_WM2_LATENCY() * 500,
1833                                    &ironlake_display_srwm_info,
1834                                    &ironlake_cursor_srwm_info,
1835                                    &fbc_wm, &plane_wm, &cursor_wm))
1836                 return;
1837
1838         I915_WRITE(WM2_LP_ILK,
1839                    WM2_LP_EN |
1840                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1841                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1842                    (plane_wm << WM1_LP_SR_SHIFT) |
1843                    cursor_wm);
1844
1845         /*
1846          * WM3 is unsupported on ILK, probably because we don't have latency
1847          * data for that power state
1848          */
1849 }
1850
1851 static void sandybridge_update_wm(struct drm_device *dev)
1852 {
1853         struct drm_i915_private *dev_priv = dev->dev_private;
1854         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1855         u32 val;
1856         int fbc_wm, plane_wm, cursor_wm;
1857         unsigned int enabled;
1858
1859         enabled = 0;
1860         if (g4x_compute_wm0(dev, PIPE_A,
1861                             &sandybridge_display_wm_info, latency,
1862                             &sandybridge_cursor_wm_info, latency,
1863                             &plane_wm, &cursor_wm)) {
1864                 val = I915_READ(WM0_PIPEA_ILK);
1865                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1866                 I915_WRITE(WM0_PIPEA_ILK, val |
1867                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1868                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1869                               " plane %d, " "cursor: %d\n",
1870                               plane_wm, cursor_wm);
1871                 enabled |= 1 << PIPE_A;
1872         }
1873
1874         if (g4x_compute_wm0(dev, PIPE_B,
1875                             &sandybridge_display_wm_info, latency,
1876                             &sandybridge_cursor_wm_info, latency,
1877                             &plane_wm, &cursor_wm)) {
1878                 val = I915_READ(WM0_PIPEB_ILK);
1879                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1880                 I915_WRITE(WM0_PIPEB_ILK, val |
1881                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1882                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1883                               " plane %d, cursor: %d\n",
1884                               plane_wm, cursor_wm);
1885                 enabled |= 1 << PIPE_B;
1886         }
1887
1888         /*
1889          * Calculate and update the self-refresh watermark only when one
1890          * display plane is used.
1891          *
1892          * SNB support 3 levels of watermark.
1893          *
1894          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1895          * and disabled in the descending order
1896          *
1897          */
1898         I915_WRITE(WM3_LP_ILK, 0);
1899         I915_WRITE(WM2_LP_ILK, 0);
1900         I915_WRITE(WM1_LP_ILK, 0);
1901
1902         if (!single_plane_enabled(enabled) ||
1903             dev_priv->sprite_scaling_enabled)
1904                 return;
1905         enabled = ffs(enabled) - 1;
1906
1907         /* WM1 */
1908         if (!ironlake_compute_srwm(dev, 1, enabled,
1909                                    SNB_READ_WM1_LATENCY() * 500,
1910                                    &sandybridge_display_srwm_info,
1911                                    &sandybridge_cursor_srwm_info,
1912                                    &fbc_wm, &plane_wm, &cursor_wm))
1913                 return;
1914
1915         I915_WRITE(WM1_LP_ILK,
1916                    WM1_LP_SR_EN |
1917                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1918                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1919                    (plane_wm << WM1_LP_SR_SHIFT) |
1920                    cursor_wm);
1921
1922         /* WM2 */
1923         if (!ironlake_compute_srwm(dev, 2, enabled,
1924                                    SNB_READ_WM2_LATENCY() * 500,
1925                                    &sandybridge_display_srwm_info,
1926                                    &sandybridge_cursor_srwm_info,
1927                                    &fbc_wm, &plane_wm, &cursor_wm))
1928                 return;
1929
1930         I915_WRITE(WM2_LP_ILK,
1931                    WM2_LP_EN |
1932                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1933                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1934                    (plane_wm << WM1_LP_SR_SHIFT) |
1935                    cursor_wm);
1936
1937         /* WM3 */
1938         if (!ironlake_compute_srwm(dev, 3, enabled,
1939                                    SNB_READ_WM3_LATENCY() * 500,
1940                                    &sandybridge_display_srwm_info,
1941                                    &sandybridge_cursor_srwm_info,
1942                                    &fbc_wm, &plane_wm, &cursor_wm))
1943                 return;
1944
1945         I915_WRITE(WM3_LP_ILK,
1946                    WM3_LP_EN |
1947                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1948                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1949                    (plane_wm << WM1_LP_SR_SHIFT) |
1950                    cursor_wm);
1951 }
1952
1953 static void ivybridge_update_wm(struct drm_device *dev)
1954 {
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1957         u32 val;
1958         int fbc_wm, plane_wm, cursor_wm;
1959         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1960         unsigned int enabled;
1961
1962         enabled = 0;
1963         if (g4x_compute_wm0(dev, PIPE_A,
1964                             &sandybridge_display_wm_info, latency,
1965                             &sandybridge_cursor_wm_info, latency,
1966                             &plane_wm, &cursor_wm)) {
1967                 val = I915_READ(WM0_PIPEA_ILK);
1968                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1969                 I915_WRITE(WM0_PIPEA_ILK, val |
1970                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1971                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1972                               " plane %d, " "cursor: %d\n",
1973                               plane_wm, cursor_wm);
1974                 enabled |= 1 << PIPE_A;
1975         }
1976
1977         if (g4x_compute_wm0(dev, PIPE_B,
1978                             &sandybridge_display_wm_info, latency,
1979                             &sandybridge_cursor_wm_info, latency,
1980                             &plane_wm, &cursor_wm)) {
1981                 val = I915_READ(WM0_PIPEB_ILK);
1982                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1983                 I915_WRITE(WM0_PIPEB_ILK, val |
1984                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1985                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1986                               " plane %d, cursor: %d\n",
1987                               plane_wm, cursor_wm);
1988                 enabled |= 1 << PIPE_B;
1989         }
1990
1991         if (g4x_compute_wm0(dev, PIPE_C,
1992                             &sandybridge_display_wm_info, latency,
1993                             &sandybridge_cursor_wm_info, latency,
1994                             &plane_wm, &cursor_wm)) {
1995                 val = I915_READ(WM0_PIPEC_IVB);
1996                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1997                 I915_WRITE(WM0_PIPEC_IVB, val |
1998                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1999                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2000                               " plane %d, cursor: %d\n",
2001                               plane_wm, cursor_wm);
2002                 enabled |= 1 << PIPE_C;
2003         }
2004
2005         /*
2006          * Calculate and update the self-refresh watermark only when one
2007          * display plane is used.
2008          *
2009          * SNB support 3 levels of watermark.
2010          *
2011          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2012          * and disabled in the descending order
2013          *
2014          */
2015         I915_WRITE(WM3_LP_ILK, 0);
2016         I915_WRITE(WM2_LP_ILK, 0);
2017         I915_WRITE(WM1_LP_ILK, 0);
2018
2019         if (!single_plane_enabled(enabled) ||
2020             dev_priv->sprite_scaling_enabled)
2021                 return;
2022         enabled = ffs(enabled) - 1;
2023
2024         /* WM1 */
2025         if (!ironlake_compute_srwm(dev, 1, enabled,
2026                                    SNB_READ_WM1_LATENCY() * 500,
2027                                    &sandybridge_display_srwm_info,
2028                                    &sandybridge_cursor_srwm_info,
2029                                    &fbc_wm, &plane_wm, &cursor_wm))
2030                 return;
2031
2032         I915_WRITE(WM1_LP_ILK,
2033                    WM1_LP_SR_EN |
2034                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2035                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2036                    (plane_wm << WM1_LP_SR_SHIFT) |
2037                    cursor_wm);
2038
2039         /* WM2 */
2040         if (!ironlake_compute_srwm(dev, 2, enabled,
2041                                    SNB_READ_WM2_LATENCY() * 500,
2042                                    &sandybridge_display_srwm_info,
2043                                    &sandybridge_cursor_srwm_info,
2044                                    &fbc_wm, &plane_wm, &cursor_wm))
2045                 return;
2046
2047         I915_WRITE(WM2_LP_ILK,
2048                    WM2_LP_EN |
2049                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2050                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2051                    (plane_wm << WM1_LP_SR_SHIFT) |
2052                    cursor_wm);
2053
2054         /* WM3, note we have to correct the cursor latency */
2055         if (!ironlake_compute_srwm(dev, 3, enabled,
2056                                    SNB_READ_WM3_LATENCY() * 500,
2057                                    &sandybridge_display_srwm_info,
2058                                    &sandybridge_cursor_srwm_info,
2059                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2060             !ironlake_compute_srwm(dev, 3, enabled,
2061                                    2 * SNB_READ_WM3_LATENCY() * 500,
2062                                    &sandybridge_display_srwm_info,
2063                                    &sandybridge_cursor_srwm_info,
2064                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2065                 return;
2066
2067         I915_WRITE(WM3_LP_ILK,
2068                    WM3_LP_EN |
2069                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2070                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2071                    (plane_wm << WM1_LP_SR_SHIFT) |
2072                    cursor_wm);
2073 }
2074
2075 static void
2076 haswell_update_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2077 {
2078         struct drm_i915_private *dev_priv = dev->dev_private;
2079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080         enum pipe pipe = intel_crtc->pipe;
2081         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2082         u32 temp;
2083
2084         if (!intel_crtc_active(crtc)) {
2085                 I915_WRITE(PIPE_WM_LINETIME(pipe), 0);
2086                 return;
2087         }
2088
2089         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2090         temp &= ~PIPE_WM_LINETIME_MASK;
2091
2092         /* The WM are computed with base on how long it takes to fill a single
2093          * row at the given clock rate, multiplied by 8.
2094          * */
2095         temp |= PIPE_WM_LINETIME_TIME(
2096                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2097
2098         /* IPS watermarks are only used by pipe A, and are ignored by
2099          * pipes B and C.  They are calculated similarly to the common
2100          * linetime values, except that we are using CD clock frequency
2101          * in MHz instead of pixel rate for the division.
2102          *
2103          * This is a placeholder for the IPS watermark calculation code.
2104          */
2105
2106         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2107 }
2108
2109 static void haswell_update_wm(struct drm_device *dev)
2110 {
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         struct drm_crtc *crtc;
2113         enum pipe pipe;
2114
2115         /* Disable the LP WMs before changine the linetime registers. This is
2116          * just a temporary code that will be replaced soon. */
2117         I915_WRITE(WM3_LP_ILK, 0);
2118         I915_WRITE(WM2_LP_ILK, 0);
2119         I915_WRITE(WM1_LP_ILK, 0);
2120
2121         for_each_pipe(pipe) {
2122                 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2123                 haswell_update_linetime_wm(dev, crtc);
2124         }
2125
2126         sandybridge_update_wm(dev);
2127 }
2128
2129 static bool
2130 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2131                               uint32_t sprite_width, int pixel_size,
2132                               const struct intel_watermark_params *display,
2133                               int display_latency_ns, int *sprite_wm)
2134 {
2135         struct drm_crtc *crtc;
2136         int clock;
2137         int entries, tlb_miss;
2138
2139         crtc = intel_get_crtc_for_plane(dev, plane);
2140         if (!intel_crtc_active(crtc)) {
2141                 *sprite_wm = display->guard_size;
2142                 return false;
2143         }
2144
2145         clock = crtc->mode.clock;
2146
2147         /* Use the small buffer method to calculate the sprite watermark */
2148         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2149         tlb_miss = display->fifo_size*display->cacheline_size -
2150                 sprite_width * 8;
2151         if (tlb_miss > 0)
2152                 entries += tlb_miss;
2153         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2154         *sprite_wm = entries + display->guard_size;
2155         if (*sprite_wm > (int)display->max_wm)
2156                 *sprite_wm = display->max_wm;
2157
2158         return true;
2159 }
2160
2161 static bool
2162 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2163                                 uint32_t sprite_width, int pixel_size,
2164                                 const struct intel_watermark_params *display,
2165                                 int latency_ns, int *sprite_wm)
2166 {
2167         struct drm_crtc *crtc;
2168         unsigned long line_time_us;
2169         int clock;
2170         int line_count, line_size;
2171         int small, large;
2172         int entries;
2173
2174         if (!latency_ns) {
2175                 *sprite_wm = 0;
2176                 return false;
2177         }
2178
2179         crtc = intel_get_crtc_for_plane(dev, plane);
2180         clock = crtc->mode.clock;
2181         if (!clock) {
2182                 *sprite_wm = 0;
2183                 return false;
2184         }
2185
2186         line_time_us = (sprite_width * 1000) / clock;
2187         if (!line_time_us) {
2188                 *sprite_wm = 0;
2189                 return false;
2190         }
2191
2192         line_count = (latency_ns / line_time_us + 1000) / 1000;
2193         line_size = sprite_width * pixel_size;
2194
2195         /* Use the minimum of the small and large buffer method for primary */
2196         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2197         large = line_count * line_size;
2198
2199         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2200         *sprite_wm = entries + display->guard_size;
2201
2202         return *sprite_wm > 0x3ff ? false : true;
2203 }
2204
2205 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2206                                          uint32_t sprite_width, int pixel_size)
2207 {
2208         struct drm_i915_private *dev_priv = dev->dev_private;
2209         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2210         u32 val;
2211         int sprite_wm, reg;
2212         int ret;
2213
2214         switch (pipe) {
2215         case 0:
2216                 reg = WM0_PIPEA_ILK;
2217                 break;
2218         case 1:
2219                 reg = WM0_PIPEB_ILK;
2220                 break;
2221         case 2:
2222                 reg = WM0_PIPEC_IVB;
2223                 break;
2224         default:
2225                 return; /* bad pipe */
2226         }
2227
2228         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2229                                             &sandybridge_display_wm_info,
2230                                             latency, &sprite_wm);
2231         if (!ret) {
2232                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2233                               pipe_name(pipe));
2234                 return;
2235         }
2236
2237         val = I915_READ(reg);
2238         val &= ~WM0_PIPE_SPRITE_MASK;
2239         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2240         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2241
2242
2243         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2244                                               pixel_size,
2245                                               &sandybridge_display_srwm_info,
2246                                               SNB_READ_WM1_LATENCY() * 500,
2247                                               &sprite_wm);
2248         if (!ret) {
2249                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2250                               pipe_name(pipe));
2251                 return;
2252         }
2253         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2254
2255         /* Only IVB has two more LP watermarks for sprite */
2256         if (!IS_IVYBRIDGE(dev))
2257                 return;
2258
2259         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2260                                               pixel_size,
2261                                               &sandybridge_display_srwm_info,
2262                                               SNB_READ_WM2_LATENCY() * 500,
2263                                               &sprite_wm);
2264         if (!ret) {
2265                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2266                               pipe_name(pipe));
2267                 return;
2268         }
2269         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2270
2271         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2272                                               pixel_size,
2273                                               &sandybridge_display_srwm_info,
2274                                               SNB_READ_WM3_LATENCY() * 500,
2275                                               &sprite_wm);
2276         if (!ret) {
2277                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2278                               pipe_name(pipe));
2279                 return;
2280         }
2281         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2282 }
2283
2284 /**
2285  * intel_update_watermarks - update FIFO watermark values based on current modes
2286  *
2287  * Calculate watermark values for the various WM regs based on current mode
2288  * and plane configuration.
2289  *
2290  * There are several cases to deal with here:
2291  *   - normal (i.e. non-self-refresh)
2292  *   - self-refresh (SR) mode
2293  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2294  *   - lines are small relative to FIFO size (buffer can hold more than 2
2295  *     lines), so need to account for TLB latency
2296  *
2297  *   The normal calculation is:
2298  *     watermark = dotclock * bytes per pixel * latency
2299  *   where latency is platform & configuration dependent (we assume pessimal
2300  *   values here).
2301  *
2302  *   The SR calculation is:
2303  *     watermark = (trunc(latency/line time)+1) * surface width *
2304  *       bytes per pixel
2305  *   where
2306  *     line time = htotal / dotclock
2307  *     surface width = hdisplay for normal plane and 64 for cursor
2308  *   and latency is assumed to be high, as above.
2309  *
2310  * The final value programmed to the register should always be rounded up,
2311  * and include an extra 2 entries to account for clock crossings.
2312  *
2313  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2314  * to set the non-SR watermarks to 8.
2315  */
2316 void intel_update_watermarks(struct drm_device *dev)
2317 {
2318         struct drm_i915_private *dev_priv = dev->dev_private;
2319
2320         if (dev_priv->display.update_wm)
2321                 dev_priv->display.update_wm(dev);
2322 }
2323
2324 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2325                                     uint32_t sprite_width, int pixel_size)
2326 {
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328
2329         if (dev_priv->display.update_sprite_wm)
2330                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2331                                                    pixel_size);
2332 }
2333
2334 static struct drm_i915_gem_object *
2335 intel_alloc_context_page(struct drm_device *dev)
2336 {
2337         struct drm_i915_gem_object *ctx;
2338         int ret;
2339
2340         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341
2342         ctx = i915_gem_alloc_object(dev, 4096);
2343         if (!ctx) {
2344                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2345                 return NULL;
2346         }
2347
2348         ret = i915_gem_object_pin(ctx, 4096, true, false);
2349         if (ret) {
2350                 DRM_ERROR("failed to pin power context: %d\n", ret);
2351                 goto err_unref;
2352         }
2353
2354         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2355         if (ret) {
2356                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2357                 goto err_unpin;
2358         }
2359
2360         return ctx;
2361
2362 err_unpin:
2363         i915_gem_object_unpin(ctx);
2364 err_unref:
2365         drm_gem_object_unreference(&ctx->base);
2366         return NULL;
2367 }
2368
2369 /**
2370  * Lock protecting IPS related data structures
2371  */
2372 DEFINE_SPINLOCK(mchdev_lock);
2373
2374 /* Global for IPS driver to get at the current i915 device. Protected by
2375  * mchdev_lock. */
2376 static struct drm_i915_private *i915_mch_dev;
2377
2378 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2379 {
2380         struct drm_i915_private *dev_priv = dev->dev_private;
2381         u16 rgvswctl;
2382
2383         assert_spin_locked(&mchdev_lock);
2384
2385         rgvswctl = I915_READ16(MEMSWCTL);
2386         if (rgvswctl & MEMCTL_CMD_STS) {
2387                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2388                 return false; /* still busy with another command */
2389         }
2390
2391         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2392                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2393         I915_WRITE16(MEMSWCTL, rgvswctl);
2394         POSTING_READ16(MEMSWCTL);
2395
2396         rgvswctl |= MEMCTL_CMD_STS;
2397         I915_WRITE16(MEMSWCTL, rgvswctl);
2398
2399         return true;
2400 }
2401
2402 static void ironlake_enable_drps(struct drm_device *dev)
2403 {
2404         struct drm_i915_private *dev_priv = dev->dev_private;
2405         u32 rgvmodectl = I915_READ(MEMMODECTL);
2406         u8 fmax, fmin, fstart, vstart;
2407
2408         spin_lock_irq(&mchdev_lock);
2409
2410         /* Enable temp reporting */
2411         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2412         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2413
2414         /* 100ms RC evaluation intervals */
2415         I915_WRITE(RCUPEI, 100000);
2416         I915_WRITE(RCDNEI, 100000);
2417
2418         /* Set max/min thresholds to 90ms and 80ms respectively */
2419         I915_WRITE(RCBMAXAVG, 90000);
2420         I915_WRITE(RCBMINAVG, 80000);
2421
2422         I915_WRITE(MEMIHYST, 1);
2423
2424         /* Set up min, max, and cur for interrupt handling */
2425         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2426         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2427         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2428                 MEMMODE_FSTART_SHIFT;
2429
2430         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2431                 PXVFREQ_PX_SHIFT;
2432
2433         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2434         dev_priv->ips.fstart = fstart;
2435
2436         dev_priv->ips.max_delay = fstart;
2437         dev_priv->ips.min_delay = fmin;
2438         dev_priv->ips.cur_delay = fstart;
2439
2440         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2441                          fmax, fmin, fstart);
2442
2443         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2444
2445         /*
2446          * Interrupts will be enabled in ironlake_irq_postinstall
2447          */
2448
2449         I915_WRITE(VIDSTART, vstart);
2450         POSTING_READ(VIDSTART);
2451
2452         rgvmodectl |= MEMMODE_SWMODE_EN;
2453         I915_WRITE(MEMMODECTL, rgvmodectl);
2454
2455         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2456                 DRM_ERROR("stuck trying to change perf mode\n");
2457         mdelay(1);
2458
2459         ironlake_set_drps(dev, fstart);
2460
2461         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2462                 I915_READ(0x112e0);
2463         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2464         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2465         getrawmonotonic(&dev_priv->ips.last_time2);
2466
2467         spin_unlock_irq(&mchdev_lock);
2468 }
2469
2470 static void ironlake_disable_drps(struct drm_device *dev)
2471 {
2472         struct drm_i915_private *dev_priv = dev->dev_private;
2473         u16 rgvswctl;
2474
2475         spin_lock_irq(&mchdev_lock);
2476
2477         rgvswctl = I915_READ16(MEMSWCTL);
2478
2479         /* Ack interrupts, disable EFC interrupt */
2480         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2481         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2482         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2483         I915_WRITE(DEIIR, DE_PCU_EVENT);
2484         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2485
2486         /* Go back to the starting frequency */
2487         ironlake_set_drps(dev, dev_priv->ips.fstart);
2488         mdelay(1);
2489         rgvswctl |= MEMCTL_CMD_STS;
2490         I915_WRITE(MEMSWCTL, rgvswctl);
2491         mdelay(1);
2492
2493         spin_unlock_irq(&mchdev_lock);
2494 }
2495
2496 /* There's a funny hw issue where the hw returns all 0 when reading from
2497  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2498  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2499  * all limits and the gpu stuck at whatever frequency it is at atm).
2500  */
2501 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2502 {
2503         u32 limits;
2504
2505         limits = 0;
2506
2507         if (*val >= dev_priv->rps.max_delay)
2508                 *val = dev_priv->rps.max_delay;
2509         limits |= dev_priv->rps.max_delay << 24;
2510
2511         /* Only set the down limit when we've reached the lowest level to avoid
2512          * getting more interrupts, otherwise leave this clear. This prevents a
2513          * race in the hw when coming out of rc6: There's a tiny window where
2514          * the hw runs at the minimal clock before selecting the desired
2515          * frequency, if the down threshold expires in that window we will not
2516          * receive a down interrupt. */
2517         if (*val <= dev_priv->rps.min_delay) {
2518                 *val = dev_priv->rps.min_delay;
2519                 limits |= dev_priv->rps.min_delay << 16;
2520         }
2521
2522         return limits;
2523 }
2524
2525 void gen6_set_rps(struct drm_device *dev, u8 val)
2526 {
2527         struct drm_i915_private *dev_priv = dev->dev_private;
2528         u32 limits = gen6_rps_limits(dev_priv, &val);
2529
2530         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2531         WARN_ON(val > dev_priv->rps.max_delay);
2532         WARN_ON(val < dev_priv->rps.min_delay);
2533
2534         if (val == dev_priv->rps.cur_delay)
2535                 return;
2536
2537         if (IS_HASWELL(dev))
2538                 I915_WRITE(GEN6_RPNSWREQ,
2539                            HSW_FREQUENCY(val));
2540         else
2541                 I915_WRITE(GEN6_RPNSWREQ,
2542                            GEN6_FREQUENCY(val) |
2543                            GEN6_OFFSET(0) |
2544                            GEN6_AGGRESSIVE_TURBO);
2545
2546         /* Make sure we continue to get interrupts
2547          * until we hit the minimum or maximum frequencies.
2548          */
2549         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2550
2551         POSTING_READ(GEN6_RPNSWREQ);
2552
2553         dev_priv->rps.cur_delay = val;
2554
2555         trace_intel_gpu_freq_change(val * 50);
2556 }
2557
2558 void valleyview_set_rps(struct drm_device *dev, u8 val)
2559 {
2560         struct drm_i915_private *dev_priv = dev->dev_private;
2561         unsigned long timeout = jiffies + msecs_to_jiffies(10);
2562         u32 limits = gen6_rps_limits(dev_priv, &val);
2563         u32 pval;
2564
2565         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2566         WARN_ON(val > dev_priv->rps.max_delay);
2567         WARN_ON(val < dev_priv->rps.min_delay);
2568
2569         DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2570                          vlv_gpu_freq(dev_priv->mem_freq,
2571                                       dev_priv->rps.cur_delay),
2572                          vlv_gpu_freq(dev_priv->mem_freq, val));
2573
2574         if (val == dev_priv->rps.cur_delay)
2575                 return;
2576
2577         valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2578
2579         do {
2580                 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2581                 if (time_after(jiffies, timeout)) {
2582                         DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2583                         break;
2584                 }
2585                 udelay(10);
2586         } while (pval & 1);
2587
2588         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2589         if ((pval >> 8) != val)
2590                 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2591                           val, pval >> 8);
2592
2593         /* Make sure we continue to get interrupts
2594          * until we hit the minimum or maximum frequencies.
2595          */
2596         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2597
2598         dev_priv->rps.cur_delay = pval >> 8;
2599
2600         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2601 }
2602
2603
2604 static void gen6_disable_rps(struct drm_device *dev)
2605 {
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607
2608         I915_WRITE(GEN6_RC_CONTROL, 0);
2609         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2610         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2611         I915_WRITE(GEN6_PMIER, 0);
2612         /* Complete PM interrupt masking here doesn't race with the rps work
2613          * item again unmasking PM interrupts because that is using a different
2614          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2615          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2616
2617         spin_lock_irq(&dev_priv->rps.lock);
2618         dev_priv->rps.pm_iir = 0;
2619         spin_unlock_irq(&dev_priv->rps.lock);
2620
2621         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2622 }
2623
2624 static void valleyview_disable_rps(struct drm_device *dev)
2625 {
2626         struct drm_i915_private *dev_priv = dev->dev_private;
2627
2628         I915_WRITE(GEN6_RC_CONTROL, 0);
2629         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2630         I915_WRITE(GEN6_PMIER, 0);
2631         /* Complete PM interrupt masking here doesn't race with the rps work
2632          * item again unmasking PM interrupts because that is using a different
2633          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2634          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2635
2636         spin_lock_irq(&dev_priv->rps.lock);
2637         dev_priv->rps.pm_iir = 0;
2638         spin_unlock_irq(&dev_priv->rps.lock);
2639
2640         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2641
2642         if (dev_priv->vlv_pctx) {
2643                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2644                 dev_priv->vlv_pctx = NULL;
2645         }
2646 }
2647
2648 int intel_enable_rc6(const struct drm_device *dev)
2649 {
2650         /* Respect the kernel parameter if it is set */
2651         if (i915_enable_rc6 >= 0)
2652                 return i915_enable_rc6;
2653
2654         /* Disable RC6 on Ironlake */
2655         if (INTEL_INFO(dev)->gen == 5)
2656                 return 0;
2657
2658         if (IS_HASWELL(dev)) {
2659                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2660                 return INTEL_RC6_ENABLE;
2661         }
2662
2663         /* snb/ivb have more than one rc6 state. */
2664         if (INTEL_INFO(dev)->gen == 6) {
2665                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2666                 return INTEL_RC6_ENABLE;
2667         }
2668
2669         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2670         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2671 }
2672
2673 static void gen6_enable_rps(struct drm_device *dev)
2674 {
2675         struct drm_i915_private *dev_priv = dev->dev_private;
2676         struct intel_ring_buffer *ring;
2677         u32 rp_state_cap;
2678         u32 gt_perf_status;
2679         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2680         u32 gtfifodbg;
2681         int rc6_mode;
2682         int i, ret;
2683
2684         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2685
2686         /* Here begins a magic sequence of register writes to enable
2687          * auto-downclocking.
2688          *
2689          * Perhaps there might be some value in exposing these to
2690          * userspace...
2691          */
2692         I915_WRITE(GEN6_RC_STATE, 0);
2693
2694         /* Clear the DBG now so we don't confuse earlier errors */
2695         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2696                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2697                 I915_WRITE(GTFIFODBG, gtfifodbg);
2698         }
2699
2700         gen6_gt_force_wake_get(dev_priv);
2701
2702         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2703         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2704
2705         /* In units of 50MHz */
2706         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
2707         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2708         dev_priv->rps.cur_delay = 0;
2709
2710         /* disable the counters and set deterministic thresholds */
2711         I915_WRITE(GEN6_RC_CONTROL, 0);
2712
2713         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2714         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2715         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2716         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2717         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2718
2719         for_each_ring(ring, dev_priv, i)
2720                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2721
2722         I915_WRITE(GEN6_RC_SLEEP, 0);
2723         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2724         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2725         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2726         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2727
2728         /* Check if we are enabling RC6 */
2729         rc6_mode = intel_enable_rc6(dev_priv->dev);
2730         if (rc6_mode & INTEL_RC6_ENABLE)
2731                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2732
2733         /* We don't use those on Haswell */
2734         if (!IS_HASWELL(dev)) {
2735                 if (rc6_mode & INTEL_RC6p_ENABLE)
2736                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2737
2738                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2739                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2740         }
2741
2742         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2743                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2744                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2745                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2746
2747         I915_WRITE(GEN6_RC_CONTROL,
2748                    rc6_mask |
2749                    GEN6_RC_CTL_EI_MODE(1) |
2750                    GEN6_RC_CTL_HW_ENABLE);
2751
2752         if (IS_HASWELL(dev)) {
2753                 I915_WRITE(GEN6_RPNSWREQ,
2754                            HSW_FREQUENCY(10));
2755                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2756                            HSW_FREQUENCY(12));
2757         } else {
2758                 I915_WRITE(GEN6_RPNSWREQ,
2759                            GEN6_FREQUENCY(10) |
2760                            GEN6_OFFSET(0) |
2761                            GEN6_AGGRESSIVE_TURBO);
2762                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2763                            GEN6_FREQUENCY(12));
2764         }
2765
2766         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2767         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2768                    dev_priv->rps.max_delay << 24 |
2769                    dev_priv->rps.min_delay << 16);
2770
2771         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2772         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2773         I915_WRITE(GEN6_RP_UP_EI, 66000);
2774         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2775
2776         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2777         I915_WRITE(GEN6_RP_CONTROL,
2778                    GEN6_RP_MEDIA_TURBO |
2779                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2780                    GEN6_RP_MEDIA_IS_GFX |
2781                    GEN6_RP_ENABLE |
2782                    GEN6_RP_UP_BUSY_AVG |
2783                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2784
2785         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2786         if (!ret) {
2787                 pcu_mbox = 0;
2788                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2789                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2790                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
2791                                          (dev_priv->rps.max_delay & 0xff) * 50,
2792                                          (pcu_mbox & 0xff) * 50);
2793                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
2794                 }
2795         } else {
2796                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2797         }
2798
2799         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2800
2801         /* requires MSI enabled */
2802         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2803         spin_lock_irq(&dev_priv->rps.lock);
2804         WARN_ON(dev_priv->rps.pm_iir != 0);
2805         I915_WRITE(GEN6_PMIMR, 0);
2806         spin_unlock_irq(&dev_priv->rps.lock);
2807         /* enable all PM interrupts */
2808         I915_WRITE(GEN6_PMINTRMSK, 0);
2809
2810         rc6vids = 0;
2811         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2812         if (IS_GEN6(dev) && ret) {
2813                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2814         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2815                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2816                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2817                 rc6vids &= 0xffff00;
2818                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2819                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2820                 if (ret)
2821                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2822         }
2823
2824         gen6_gt_force_wake_put(dev_priv);
2825 }
2826
2827 static void gen6_update_ring_freq(struct drm_device *dev)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         int min_freq = 15;
2831         unsigned int gpu_freq;
2832         unsigned int max_ia_freq, min_ring_freq;
2833         int scaling_factor = 180;
2834
2835         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2836
2837         max_ia_freq = cpufreq_quick_get_max(0);
2838         /*
2839          * Default to measured freq if none found, PCU will ensure we don't go
2840          * over
2841          */
2842         if (!max_ia_freq)
2843                 max_ia_freq = tsc_khz;
2844
2845         /* Convert from kHz to MHz */
2846         max_ia_freq /= 1000;
2847
2848         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2849         /* convert DDR frequency from units of 133.3MHz to bandwidth */
2850         min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2851
2852         /*
2853          * For each potential GPU frequency, load a ring frequency we'd like
2854          * to use for memory access.  We do this by specifying the IA frequency
2855          * the PCU should use as a reference to determine the ring frequency.
2856          */
2857         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2858              gpu_freq--) {
2859                 int diff = dev_priv->rps.max_delay - gpu_freq;
2860                 unsigned int ia_freq = 0, ring_freq = 0;
2861
2862                 if (IS_HASWELL(dev)) {
2863                         ring_freq = (gpu_freq * 5 + 3) / 4;
2864                         ring_freq = max(min_ring_freq, ring_freq);
2865                         /* leave ia_freq as the default, chosen by cpufreq */
2866                 } else {
2867                         /* On older processors, there is no separate ring
2868                          * clock domain, so in order to boost the bandwidth
2869                          * of the ring, we need to upclock the CPU (ia_freq).
2870                          *
2871                          * For GPU frequencies less than 750MHz,
2872                          * just use the lowest ring freq.
2873                          */
2874                         if (gpu_freq < min_freq)
2875                                 ia_freq = 800;
2876                         else
2877                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2878                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2879                 }
2880
2881                 sandybridge_pcode_write(dev_priv,
2882                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2883                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2884                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2885                                         gpu_freq);
2886         }
2887 }
2888
2889 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2890 {
2891         u32 val, rp0;
2892
2893         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2894
2895         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2896         /* Clamp to max */
2897         rp0 = min_t(u32, rp0, 0xea);
2898
2899         return rp0;
2900 }
2901
2902 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2903 {
2904         u32 val, rpe;
2905
2906         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2907         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2908         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2909         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2910
2911         return rpe;
2912 }
2913
2914 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2915 {
2916         u32 val;
2917
2918         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2919
2920         return val & 0xff;
2921 }
2922
2923 static void vlv_rps_timer_work(struct work_struct *work)
2924 {
2925         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
2926                                                     rps.vlv_work.work);
2927
2928         /*
2929          * Timer fired, we must be idle.  Drop to min voltage state.
2930          * Note: we use RPe here since it should match the
2931          * Vmin we were shooting for.  That should give us better
2932          * perf when we come back out of RC6 than if we used the
2933          * min freq available.
2934          */
2935         mutex_lock(&dev_priv->rps.hw_lock);
2936         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
2937         mutex_unlock(&dev_priv->rps.hw_lock);
2938 }
2939
2940 static void valleyview_setup_pctx(struct drm_device *dev)
2941 {
2942         struct drm_i915_private *dev_priv = dev->dev_private;
2943         struct drm_i915_gem_object *pctx;
2944         unsigned long pctx_paddr;
2945         u32 pcbr;
2946         int pctx_size = 24*1024;
2947
2948         pcbr = I915_READ(VLV_PCBR);
2949         if (pcbr) {
2950                 /* BIOS set it up already, grab the pre-alloc'd space */
2951                 int pcbr_offset;
2952
2953                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
2954                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
2955                                                                       pcbr_offset,
2956                                                                       -1,
2957                                                                       pctx_size);
2958                 goto out;
2959         }
2960
2961         /*
2962          * From the Gunit register HAS:
2963          * The Gfx driver is expected to program this register and ensure
2964          * proper allocation within Gfx stolen memory.  For example, this
2965          * register should be programmed such than the PCBR range does not
2966          * overlap with other ranges, such as the frame buffer, protected
2967          * memory, or any other relevant ranges.
2968          */
2969         pctx = i915_gem_object_create_stolen(dev, pctx_size);
2970         if (!pctx) {
2971                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
2972                 return;
2973         }
2974
2975         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
2976         I915_WRITE(VLV_PCBR, pctx_paddr);
2977
2978 out:
2979         dev_priv->vlv_pctx = pctx;
2980 }
2981
2982 static void valleyview_enable_rps(struct drm_device *dev)
2983 {
2984         struct drm_i915_private *dev_priv = dev->dev_private;
2985         struct intel_ring_buffer *ring;
2986         u32 gtfifodbg, val, rpe;
2987         int i;
2988
2989         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2990
2991         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2992                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2993                 I915_WRITE(GTFIFODBG, gtfifodbg);
2994         }
2995
2996         valleyview_setup_pctx(dev);
2997
2998         gen6_gt_force_wake_get(dev_priv);
2999
3000         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3001         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3002         I915_WRITE(GEN6_RP_UP_EI, 66000);
3003         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3004
3005         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3006
3007         I915_WRITE(GEN6_RP_CONTROL,
3008                    GEN6_RP_MEDIA_TURBO |
3009                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3010                    GEN6_RP_MEDIA_IS_GFX |
3011                    GEN6_RP_ENABLE |
3012                    GEN6_RP_UP_BUSY_AVG |
3013                    GEN6_RP_DOWN_IDLE_CONT);
3014
3015         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3016         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3017         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3018
3019         for_each_ring(ring, dev_priv, i)
3020                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3021
3022         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3023
3024         /* allows RC6 residency counter to work */
3025         I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3026         I915_WRITE(GEN6_RC_CONTROL,
3027                    GEN7_RC_CTL_TO_MODE);
3028
3029         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
3030         switch ((val >> 6) & 3) {
3031         case 0:
3032         case 1:
3033                 dev_priv->mem_freq = 800;
3034                 break;
3035         case 2:
3036                 dev_priv->mem_freq = 1066;
3037                 break;
3038         case 3:
3039                 dev_priv->mem_freq = 1333;
3040                 break;
3041         }
3042         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3043
3044         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3045         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3046
3047         DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3048                          vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3049         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3050
3051         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3052         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3053         DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3054                                                      dev_priv->rps.max_delay));
3055
3056         rpe = valleyview_rps_rpe_freq(dev_priv);
3057         DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3058                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
3059         dev_priv->rps.rpe_delay = rpe;
3060
3061         val = valleyview_rps_min_freq(dev_priv);
3062         DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3063                                                             val));
3064         dev_priv->rps.min_delay = val;
3065
3066         DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3067                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
3068
3069         INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3070
3071         valleyview_set_rps(dev_priv->dev, rpe);
3072
3073         /* requires MSI enabled */
3074         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3075         spin_lock_irq(&dev_priv->rps.lock);
3076         WARN_ON(dev_priv->rps.pm_iir != 0);
3077         I915_WRITE(GEN6_PMIMR, 0);
3078         spin_unlock_irq(&dev_priv->rps.lock);
3079         /* enable all PM interrupts */
3080         I915_WRITE(GEN6_PMINTRMSK, 0);
3081
3082         gen6_gt_force_wake_put(dev_priv);
3083 }
3084
3085 void ironlake_teardown_rc6(struct drm_device *dev)
3086 {
3087         struct drm_i915_private *dev_priv = dev->dev_private;
3088
3089         if (dev_priv->ips.renderctx) {
3090                 i915_gem_object_unpin(dev_priv->ips.renderctx);
3091                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3092                 dev_priv->ips.renderctx = NULL;
3093         }
3094
3095         if (dev_priv->ips.pwrctx) {
3096                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3097                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3098                 dev_priv->ips.pwrctx = NULL;
3099         }
3100 }
3101
3102 static void ironlake_disable_rc6(struct drm_device *dev)
3103 {
3104         struct drm_i915_private *dev_priv = dev->dev_private;
3105
3106         if (I915_READ(PWRCTXA)) {
3107                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3108                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3109                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3110                          50);
3111
3112                 I915_WRITE(PWRCTXA, 0);
3113                 POSTING_READ(PWRCTXA);
3114
3115                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3116                 POSTING_READ(RSTDBYCTL);
3117         }
3118 }
3119
3120 static int ironlake_setup_rc6(struct drm_device *dev)
3121 {
3122         struct drm_i915_private *dev_priv = dev->dev_private;
3123
3124         if (dev_priv->ips.renderctx == NULL)
3125                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3126         if (!dev_priv->ips.renderctx)
3127                 return -ENOMEM;
3128
3129         if (dev_priv->ips.pwrctx == NULL)
3130                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3131         if (!dev_priv->ips.pwrctx) {
3132                 ironlake_teardown_rc6(dev);
3133                 return -ENOMEM;
3134         }
3135
3136         return 0;
3137 }
3138
3139 static void ironlake_enable_rc6(struct drm_device *dev)
3140 {
3141         struct drm_i915_private *dev_priv = dev->dev_private;
3142         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3143         bool was_interruptible;
3144         int ret;
3145
3146         /* rc6 disabled by default due to repeated reports of hanging during
3147          * boot and resume.
3148          */
3149         if (!intel_enable_rc6(dev))
3150                 return;
3151
3152         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3153
3154         ret = ironlake_setup_rc6(dev);
3155         if (ret)
3156                 return;
3157
3158         was_interruptible = dev_priv->mm.interruptible;
3159         dev_priv->mm.interruptible = false;
3160
3161         /*
3162          * GPU can automatically power down the render unit if given a page
3163          * to save state.
3164          */
3165         ret = intel_ring_begin(ring, 6);
3166         if (ret) {
3167                 ironlake_teardown_rc6(dev);
3168                 dev_priv->mm.interruptible = was_interruptible;
3169                 return;
3170         }
3171
3172         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3173         intel_ring_emit(ring, MI_SET_CONTEXT);
3174         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3175                         MI_MM_SPACE_GTT |
3176                         MI_SAVE_EXT_STATE_EN |
3177                         MI_RESTORE_EXT_STATE_EN |
3178                         MI_RESTORE_INHIBIT);
3179         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3180         intel_ring_emit(ring, MI_NOOP);
3181         intel_ring_emit(ring, MI_FLUSH);
3182         intel_ring_advance(ring);
3183
3184         /*
3185          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3186          * does an implicit flush, combined with MI_FLUSH above, it should be
3187          * safe to assume that renderctx is valid
3188          */
3189         ret = intel_ring_idle(ring);
3190         dev_priv->mm.interruptible = was_interruptible;
3191         if (ret) {
3192                 DRM_ERROR("failed to enable ironlake power savings\n");
3193                 ironlake_teardown_rc6(dev);
3194                 return;
3195         }
3196
3197         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3198         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3199 }
3200
3201 static unsigned long intel_pxfreq(u32 vidfreq)
3202 {
3203         unsigned long freq;
3204         int div = (vidfreq & 0x3f0000) >> 16;
3205         int post = (vidfreq & 0x3000) >> 12;
3206         int pre = (vidfreq & 0x7);
3207
3208         if (!pre)
3209                 return 0;
3210
3211         freq = ((div * 133333) / ((1<<post) * pre));
3212
3213         return freq;
3214 }
3215
3216 static const struct cparams {
3217         u16 i;
3218         u16 t;
3219         u16 m;
3220         u16 c;
3221 } cparams[] = {
3222         { 1, 1333, 301, 28664 },
3223         { 1, 1066, 294, 24460 },
3224         { 1, 800, 294, 25192 },
3225         { 0, 1333, 276, 27605 },
3226         { 0, 1066, 276, 27605 },
3227         { 0, 800, 231, 23784 },
3228 };
3229
3230 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3231 {
3232         u64 total_count, diff, ret;
3233         u32 count1, count2, count3, m = 0, c = 0;
3234         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3235         int i;
3236
3237         assert_spin_locked(&mchdev_lock);
3238
3239         diff1 = now - dev_priv->ips.last_time1;
3240
3241         /* Prevent division-by-zero if we are asking too fast.
3242          * Also, we don't get interesting results if we are polling
3243          * faster than once in 10ms, so just return the saved value
3244          * in such cases.
3245          */
3246         if (diff1 <= 10)
3247                 return dev_priv->ips.chipset_power;
3248
3249         count1 = I915_READ(DMIEC);
3250         count2 = I915_READ(DDREC);
3251         count3 = I915_READ(CSIEC);
3252
3253         total_count = count1 + count2 + count3;
3254
3255         /* FIXME: handle per-counter overflow */
3256         if (total_count < dev_priv->ips.last_count1) {
3257                 diff = ~0UL - dev_priv->ips.last_count1;
3258                 diff += total_count;
3259         } else {
3260                 diff = total_count - dev_priv->ips.last_count1;
3261         }
3262
3263         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3264                 if (cparams[i].i == dev_priv->ips.c_m &&
3265                     cparams[i].t == dev_priv->ips.r_t) {
3266                         m = cparams[i].m;
3267                         c = cparams[i].c;
3268                         break;
3269                 }
3270         }
3271
3272         diff = div_u64(diff, diff1);
3273         ret = ((m * diff) + c);
3274         ret = div_u64(ret, 10);
3275
3276         dev_priv->ips.last_count1 = total_count;
3277         dev_priv->ips.last_time1 = now;
3278
3279         dev_priv->ips.chipset_power = ret;
3280
3281         return ret;
3282 }
3283
3284 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3285 {
3286         unsigned long val;
3287
3288         if (dev_priv->info->gen != 5)
3289                 return 0;
3290
3291         spin_lock_irq(&mchdev_lock);
3292
3293         val = __i915_chipset_val(dev_priv);
3294
3295         spin_unlock_irq(&mchdev_lock);
3296
3297         return val;
3298 }
3299
3300 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3301 {
3302         unsigned long m, x, b;
3303         u32 tsfs;
3304
3305         tsfs = I915_READ(TSFS);
3306
3307         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3308         x = I915_READ8(TR1);
3309
3310         b = tsfs & TSFS_INTR_MASK;
3311
3312         return ((m * x) / 127) - b;
3313 }
3314
3315 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3316 {
3317         static const struct v_table {
3318                 u16 vd; /* in .1 mil */
3319                 u16 vm; /* in .1 mil */
3320         } v_table[] = {
3321                 { 0, 0, },
3322                 { 375, 0, },
3323                 { 500, 0, },
3324                 { 625, 0, },
3325                 { 750, 0, },
3326                 { 875, 0, },
3327                 { 1000, 0, },
3328                 { 1125, 0, },
3329                 { 4125, 3000, },
3330                 { 4125, 3000, },
3331                 { 4125, 3000, },
3332                 { 4125, 3000, },
3333                 { 4125, 3000, },
3334                 { 4125, 3000, },
3335                 { 4125, 3000, },
3336                 { 4125, 3000, },
3337                 { 4125, 3000, },
3338                 { 4125, 3000, },
3339                 { 4125, 3000, },
3340                 { 4125, 3000, },
3341                 { 4125, 3000, },
3342                 { 4125, 3000, },
3343                 { 4125, 3000, },
3344                 { 4125, 3000, },
3345                 { 4125, 3000, },
3346                 { 4125, 3000, },
3347                 { 4125, 3000, },
3348                 { 4125, 3000, },
3349                 { 4125, 3000, },
3350                 { 4125, 3000, },
3351                 { 4125, 3000, },
3352                 { 4125, 3000, },
3353                 { 4250, 3125, },
3354                 { 4375, 3250, },
3355                 { 4500, 3375, },
3356                 { 4625, 3500, },
3357                 { 4750, 3625, },
3358                 { 4875, 3750, },
3359                 { 5000, 3875, },
3360                 { 5125, 4000, },
3361                 { 5250, 4125, },
3362                 { 5375, 4250, },
3363                 { 5500, 4375, },
3364                 { 5625, 4500, },
3365                 { 5750, 4625, },
3366                 { 5875, 4750, },
3367                 { 6000, 4875, },
3368                 { 6125, 5000, },
3369                 { 6250, 5125, },
3370                 { 6375, 5250, },
3371                 { 6500, 5375, },
3372                 { 6625, 5500, },
3373                 { 6750, 5625, },
3374                 { 6875, 5750, },
3375                 { 7000, 5875, },
3376                 { 7125, 6000, },
3377                 { 7250, 6125, },
3378                 { 7375, 6250, },
3379                 { 7500, 6375, },
3380                 { 7625, 6500, },
3381                 { 7750, 6625, },
3382                 { 7875, 6750, },
3383                 { 8000, 6875, },
3384                 { 8125, 7000, },
3385                 { 8250, 7125, },
3386                 { 8375, 7250, },
3387                 { 8500, 7375, },
3388                 { 8625, 7500, },
3389                 { 8750, 7625, },
3390                 { 8875, 7750, },
3391                 { 9000, 7875, },
3392                 { 9125, 8000, },
3393                 { 9250, 8125, },
3394                 { 9375, 8250, },
3395                 { 9500, 8375, },
3396                 { 9625, 8500, },
3397                 { 9750, 8625, },
3398                 { 9875, 8750, },
3399                 { 10000, 8875, },
3400                 { 10125, 9000, },
3401                 { 10250, 9125, },
3402                 { 10375, 9250, },
3403                 { 10500, 9375, },
3404                 { 10625, 9500, },
3405                 { 10750, 9625, },
3406                 { 10875, 9750, },
3407                 { 11000, 9875, },
3408                 { 11125, 10000, },
3409                 { 11250, 10125, },
3410                 { 11375, 10250, },
3411                 { 11500, 10375, },
3412                 { 11625, 10500, },
3413                 { 11750, 10625, },
3414                 { 11875, 10750, },
3415                 { 12000, 10875, },
3416                 { 12125, 11000, },
3417                 { 12250, 11125, },
3418                 { 12375, 11250, },
3419                 { 12500, 11375, },
3420                 { 12625, 11500, },
3421                 { 12750, 11625, },
3422                 { 12875, 11750, },
3423                 { 13000, 11875, },
3424                 { 13125, 12000, },
3425                 { 13250, 12125, },
3426                 { 13375, 12250, },
3427                 { 13500, 12375, },
3428                 { 13625, 12500, },
3429                 { 13750, 12625, },
3430                 { 13875, 12750, },
3431                 { 14000, 12875, },
3432                 { 14125, 13000, },
3433                 { 14250, 13125, },
3434                 { 14375, 13250, },
3435                 { 14500, 13375, },
3436                 { 14625, 13500, },
3437                 { 14750, 13625, },
3438                 { 14875, 13750, },
3439                 { 15000, 13875, },
3440                 { 15125, 14000, },
3441                 { 15250, 14125, },
3442                 { 15375, 14250, },
3443                 { 15500, 14375, },
3444                 { 15625, 14500, },
3445                 { 15750, 14625, },
3446                 { 15875, 14750, },
3447                 { 16000, 14875, },
3448                 { 16125, 15000, },
3449         };
3450         if (dev_priv->info->is_mobile)
3451                 return v_table[pxvid].vm;
3452         else
3453                 return v_table[pxvid].vd;
3454 }
3455
3456 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3457 {
3458         struct timespec now, diff1;
3459         u64 diff;
3460         unsigned long diffms;
3461         u32 count;
3462
3463         assert_spin_locked(&mchdev_lock);
3464
3465         getrawmonotonic(&now);
3466         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3467
3468         /* Don't divide by 0 */
3469         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3470         if (!diffms)
3471                 return;
3472
3473         count = I915_READ(GFXEC);
3474
3475         if (count < dev_priv->ips.last_count2) {
3476                 diff = ~0UL - dev_priv->ips.last_count2;
3477                 diff += count;
3478         } else {
3479                 diff = count - dev_priv->ips.last_count2;
3480         }
3481
3482         dev_priv->ips.last_count2 = count;
3483         dev_priv->ips.last_time2 = now;
3484
3485         /* More magic constants... */
3486         diff = diff * 1181;
3487         diff = div_u64(diff, diffms * 10);
3488         dev_priv->ips.gfx_power = diff;
3489 }
3490
3491 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3492 {
3493         if (dev_priv->info->gen != 5)
3494                 return;
3495
3496         spin_lock_irq(&mchdev_lock);
3497
3498         __i915_update_gfx_val(dev_priv);
3499
3500         spin_unlock_irq(&mchdev_lock);
3501 }
3502
3503 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3504 {
3505         unsigned long t, corr, state1, corr2, state2;
3506         u32 pxvid, ext_v;
3507
3508         assert_spin_locked(&mchdev_lock);
3509
3510         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3511         pxvid = (pxvid >> 24) & 0x7f;
3512         ext_v = pvid_to_extvid(dev_priv, pxvid);
3513
3514         state1 = ext_v;
3515
3516         t = i915_mch_val(dev_priv);
3517
3518         /* Revel in the empirically derived constants */
3519
3520         /* Correction factor in 1/100000 units */
3521         if (t > 80)
3522                 corr = ((t * 2349) + 135940);
3523         else if (t >= 50)
3524                 corr = ((t * 964) + 29317);
3525         else /* < 50 */
3526                 corr = ((t * 301) + 1004);
3527
3528         corr = corr * ((150142 * state1) / 10000 - 78642);
3529         corr /= 100000;
3530         corr2 = (corr * dev_priv->ips.corr);
3531
3532         state2 = (corr2 * state1) / 10000;
3533         state2 /= 100; /* convert to mW */
3534
3535         __i915_update_gfx_val(dev_priv);
3536
3537         return dev_priv->ips.gfx_power + state2;
3538 }
3539
3540 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3541 {
3542         unsigned long val;
3543
3544         if (dev_priv->info->gen != 5)
3545                 return 0;
3546
3547         spin_lock_irq(&mchdev_lock);
3548
3549         val = __i915_gfx_val(dev_priv);
3550
3551         spin_unlock_irq(&mchdev_lock);
3552
3553         return val;
3554 }
3555
3556 /**
3557  * i915_read_mch_val - return value for IPS use
3558  *
3559  * Calculate and return a value for the IPS driver to use when deciding whether
3560  * we have thermal and power headroom to increase CPU or GPU power budget.
3561  */
3562 unsigned long i915_read_mch_val(void)
3563 {
3564         struct drm_i915_private *dev_priv;
3565         unsigned long chipset_val, graphics_val, ret = 0;
3566
3567         spin_lock_irq(&mchdev_lock);
3568         if (!i915_mch_dev)
3569                 goto out_unlock;
3570         dev_priv = i915_mch_dev;
3571
3572         chipset_val = __i915_chipset_val(dev_priv);
3573         graphics_val = __i915_gfx_val(dev_priv);
3574
3575         ret = chipset_val + graphics_val;
3576
3577 out_unlock:
3578         spin_unlock_irq(&mchdev_lock);
3579
3580         return ret;
3581 }
3582 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3583
3584 /**
3585  * i915_gpu_raise - raise GPU frequency limit
3586  *
3587  * Raise the limit; IPS indicates we have thermal headroom.
3588  */
3589 bool i915_gpu_raise(void)
3590 {
3591         struct drm_i915_private *dev_priv;
3592         bool ret = true;
3593
3594         spin_lock_irq(&mchdev_lock);
3595         if (!i915_mch_dev) {
3596                 ret = false;
3597                 goto out_unlock;
3598         }
3599         dev_priv = i915_mch_dev;
3600
3601         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3602                 dev_priv->ips.max_delay--;
3603
3604 out_unlock:
3605         spin_unlock_irq(&mchdev_lock);
3606
3607         return ret;
3608 }
3609 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3610
3611 /**
3612  * i915_gpu_lower - lower GPU frequency limit
3613  *
3614  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3615  * frequency maximum.
3616  */
3617 bool i915_gpu_lower(void)
3618 {
3619         struct drm_i915_private *dev_priv;
3620         bool ret = true;
3621
3622         spin_lock_irq(&mchdev_lock);
3623         if (!i915_mch_dev) {
3624                 ret = false;
3625                 goto out_unlock;
3626         }
3627         dev_priv = i915_mch_dev;
3628
3629         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3630                 dev_priv->ips.max_delay++;
3631
3632 out_unlock:
3633         spin_unlock_irq(&mchdev_lock);
3634
3635         return ret;
3636 }
3637 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3638
3639 /**
3640  * i915_gpu_busy - indicate GPU business to IPS
3641  *
3642  * Tell the IPS driver whether or not the GPU is busy.
3643  */
3644 bool i915_gpu_busy(void)
3645 {
3646         struct drm_i915_private *dev_priv;
3647         struct intel_ring_buffer *ring;
3648         bool ret = false;
3649         int i;
3650
3651         spin_lock_irq(&mchdev_lock);
3652         if (!i915_mch_dev)
3653                 goto out_unlock;
3654         dev_priv = i915_mch_dev;
3655
3656         for_each_ring(ring, dev_priv, i)
3657                 ret |= !list_empty(&ring->request_list);
3658
3659 out_unlock:
3660         spin_unlock_irq(&mchdev_lock);
3661
3662         return ret;
3663 }
3664 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3665
3666 /**
3667  * i915_gpu_turbo_disable - disable graphics turbo
3668  *
3669  * Disable graphics turbo by resetting the max frequency and setting the
3670  * current frequency to the default.
3671  */
3672 bool i915_gpu_turbo_disable(void)
3673 {
3674         struct drm_i915_private *dev_priv;
3675         bool ret = true;
3676
3677         spin_lock_irq(&mchdev_lock);
3678         if (!i915_mch_dev) {
3679                 ret = false;
3680                 goto out_unlock;
3681         }
3682         dev_priv = i915_mch_dev;
3683
3684         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3685
3686         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3687                 ret = false;
3688
3689 out_unlock:
3690         spin_unlock_irq(&mchdev_lock);
3691
3692         return ret;
3693 }
3694 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3695
3696 /**
3697  * Tells the intel_ips driver that the i915 driver is now loaded, if
3698  * IPS got loaded first.
3699  *
3700  * This awkward dance is so that neither module has to depend on the
3701  * other in order for IPS to do the appropriate communication of
3702  * GPU turbo limits to i915.
3703  */
3704 static void
3705 ips_ping_for_i915_load(void)
3706 {
3707         void (*link)(void);
3708
3709         link = symbol_get(ips_link_to_i915_driver);
3710         if (link) {
3711                 link();
3712                 symbol_put(ips_link_to_i915_driver);
3713         }
3714 }
3715
3716 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3717 {
3718         /* We only register the i915 ips part with intel-ips once everything is
3719          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3720         spin_lock_irq(&mchdev_lock);
3721         i915_mch_dev = dev_priv;
3722         spin_unlock_irq(&mchdev_lock);
3723
3724         ips_ping_for_i915_load();
3725 }
3726
3727 void intel_gpu_ips_teardown(void)
3728 {
3729         spin_lock_irq(&mchdev_lock);
3730         i915_mch_dev = NULL;
3731         spin_unlock_irq(&mchdev_lock);
3732 }
3733 static void intel_init_emon(struct drm_device *dev)
3734 {
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         u32 lcfuse;
3737         u8 pxw[16];
3738         int i;
3739
3740         /* Disable to program */
3741         I915_WRITE(ECR, 0);
3742         POSTING_READ(ECR);
3743
3744         /* Program energy weights for various events */
3745         I915_WRITE(SDEW, 0x15040d00);
3746         I915_WRITE(CSIEW0, 0x007f0000);
3747         I915_WRITE(CSIEW1, 0x1e220004);
3748         I915_WRITE(CSIEW2, 0x04000004);
3749
3750         for (i = 0; i < 5; i++)
3751                 I915_WRITE(PEW + (i * 4), 0);
3752         for (i = 0; i < 3; i++)
3753                 I915_WRITE(DEW + (i * 4), 0);
3754
3755         /* Program P-state weights to account for frequency power adjustment */
3756         for (i = 0; i < 16; i++) {
3757                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3758                 unsigned long freq = intel_pxfreq(pxvidfreq);
3759                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3760                         PXVFREQ_PX_SHIFT;
3761                 unsigned long val;
3762
3763                 val = vid * vid;
3764                 val *= (freq / 1000);
3765                 val *= 255;
3766                 val /= (127*127*900);
3767                 if (val > 0xff)
3768                         DRM_ERROR("bad pxval: %ld\n", val);
3769                 pxw[i] = val;
3770         }
3771         /* Render standby states get 0 weight */
3772         pxw[14] = 0;
3773         pxw[15] = 0;
3774
3775         for (i = 0; i < 4; i++) {
3776                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3777                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3778                 I915_WRITE(PXW + (i * 4), val);
3779         }
3780
3781         /* Adjust magic regs to magic values (more experimental results) */
3782         I915_WRITE(OGW0, 0);
3783         I915_WRITE(OGW1, 0);
3784         I915_WRITE(EG0, 0x00007f00);
3785         I915_WRITE(EG1, 0x0000000e);
3786         I915_WRITE(EG2, 0x000e0000);
3787         I915_WRITE(EG3, 0x68000300);
3788         I915_WRITE(EG4, 0x42000000);
3789         I915_WRITE(EG5, 0x00140031);
3790         I915_WRITE(EG6, 0);
3791         I915_WRITE(EG7, 0);
3792
3793         for (i = 0; i < 8; i++)
3794                 I915_WRITE(PXWL + (i * 4), 0);
3795
3796         /* Enable PMON + select events */
3797         I915_WRITE(ECR, 0x80000019);
3798
3799         lcfuse = I915_READ(LCFUSE02);
3800
3801         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3802 }
3803
3804 void intel_disable_gt_powersave(struct drm_device *dev)
3805 {
3806         struct drm_i915_private *dev_priv = dev->dev_private;
3807
3808         /* Interrupts should be disabled already to avoid re-arming. */
3809         WARN_ON(dev->irq_enabled);
3810
3811         if (IS_IRONLAKE_M(dev)) {
3812                 ironlake_disable_drps(dev);
3813                 ironlake_disable_rc6(dev);
3814         } else if (INTEL_INFO(dev)->gen >= 6) {
3815                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3816                 cancel_work_sync(&dev_priv->rps.work);
3817                 if (IS_VALLEYVIEW(dev))
3818                         cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
3819                 mutex_lock(&dev_priv->rps.hw_lock);
3820                 if (IS_VALLEYVIEW(dev))
3821                         valleyview_disable_rps(dev);
3822                 else
3823                         gen6_disable_rps(dev);
3824                 mutex_unlock(&dev_priv->rps.hw_lock);
3825         }
3826 }
3827
3828 static void intel_gen6_powersave_work(struct work_struct *work)
3829 {
3830         struct drm_i915_private *dev_priv =
3831                 container_of(work, struct drm_i915_private,
3832                              rps.delayed_resume_work.work);
3833         struct drm_device *dev = dev_priv->dev;
3834
3835         mutex_lock(&dev_priv->rps.hw_lock);
3836
3837         if (IS_VALLEYVIEW(dev)) {
3838                 valleyview_enable_rps(dev);
3839         } else {
3840                 gen6_enable_rps(dev);
3841                 gen6_update_ring_freq(dev);
3842         }
3843         mutex_unlock(&dev_priv->rps.hw_lock);
3844 }
3845
3846 void intel_enable_gt_powersave(struct drm_device *dev)
3847 {
3848         struct drm_i915_private *dev_priv = dev->dev_private;
3849
3850         if (IS_IRONLAKE_M(dev)) {
3851                 ironlake_enable_drps(dev);
3852                 ironlake_enable_rc6(dev);
3853                 intel_init_emon(dev);
3854         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3855                 /*
3856                  * PCU communication is slow and this doesn't need to be
3857                  * done at any specific time, so do this out of our fast path
3858                  * to make resume and init faster.
3859                  */
3860                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3861                                       round_jiffies_up_relative(HZ));
3862         }
3863 }
3864
3865 static void ibx_init_clock_gating(struct drm_device *dev)
3866 {
3867         struct drm_i915_private *dev_priv = dev->dev_private;
3868
3869         /*
3870          * On Ibex Peak and Cougar Point, we need to disable clock
3871          * gating for the panel power sequencer or it will fail to
3872          * start up when no ports are active.
3873          */
3874         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3875 }
3876
3877 static void ironlake_init_clock_gating(struct drm_device *dev)
3878 {
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3881
3882         /* Required for FBC */
3883         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3884                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3885                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3886
3887         I915_WRITE(PCH_3DCGDIS0,
3888                    MARIUNIT_CLOCK_GATE_DISABLE |
3889                    SVSMUNIT_CLOCK_GATE_DISABLE);
3890         I915_WRITE(PCH_3DCGDIS1,
3891                    VFMUNIT_CLOCK_GATE_DISABLE);
3892
3893         /*
3894          * According to the spec the following bits should be set in
3895          * order to enable memory self-refresh
3896          * The bit 22/21 of 0x42004
3897          * The bit 5 of 0x42020
3898          * The bit 15 of 0x45000
3899          */
3900         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3901                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3902                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3903         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3904         I915_WRITE(DISP_ARB_CTL,
3905                    (I915_READ(DISP_ARB_CTL) |
3906                     DISP_FBC_WM_DIS));
3907         I915_WRITE(WM3_LP_ILK, 0);
3908         I915_WRITE(WM2_LP_ILK, 0);
3909         I915_WRITE(WM1_LP_ILK, 0);
3910
3911         /*
3912          * Based on the document from hardware guys the following bits
3913          * should be set unconditionally in order to enable FBC.
3914          * The bit 22 of 0x42000
3915          * The bit 22 of 0x42004
3916          * The bit 7,8,9 of 0x42020.
3917          */
3918         if (IS_IRONLAKE_M(dev)) {
3919                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3920                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3921                            ILK_FBCQ_DIS);
3922                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3923                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3924                            ILK_DPARB_GATE);
3925         }
3926
3927         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3928
3929         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3930                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3931                    ILK_ELPIN_409_SELECT);
3932         I915_WRITE(_3D_CHICKEN2,
3933                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3934                    _3D_CHICKEN2_WM_READ_PIPELINED);
3935
3936         /* WaDisableRenderCachePipelinedFlush:ilk */
3937         I915_WRITE(CACHE_MODE_0,
3938                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3939
3940         ibx_init_clock_gating(dev);
3941 }
3942
3943 static void cpt_init_clock_gating(struct drm_device *dev)
3944 {
3945         struct drm_i915_private *dev_priv = dev->dev_private;
3946         int pipe;
3947         uint32_t val;
3948
3949         /*
3950          * On Ibex Peak and Cougar Point, we need to disable clock
3951          * gating for the panel power sequencer or it will fail to
3952          * start up when no ports are active.
3953          */
3954         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3955         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3956                    DPLS_EDP_PPS_FIX_DIS);
3957         /* The below fixes the weird display corruption, a few pixels shifted
3958          * downward, on (only) LVDS of some HP laptops with IVY.
3959          */
3960         for_each_pipe(pipe) {
3961                 val = I915_READ(TRANS_CHICKEN2(pipe));
3962                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3963                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3964                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3965                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3966                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3967                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3968                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3969                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3970         }
3971         /* WADP0ClockGatingDisable */
3972         for_each_pipe(pipe) {
3973                 I915_WRITE(TRANS_CHICKEN1(pipe),
3974                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3975         }
3976 }
3977
3978 static void gen6_check_mch_setup(struct drm_device *dev)
3979 {
3980         struct drm_i915_private *dev_priv = dev->dev_private;
3981         uint32_t tmp;
3982
3983         tmp = I915_READ(MCH_SSKPD);
3984         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3985                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3986                 DRM_INFO("This can cause pipe underruns and display issues.\n");
3987                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3988         }
3989 }
3990
3991 static void gen6_init_clock_gating(struct drm_device *dev)
3992 {
3993         struct drm_i915_private *dev_priv = dev->dev_private;
3994         int pipe;
3995         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3996
3997         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3998
3999         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4000                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4001                    ILK_ELPIN_409_SELECT);
4002
4003         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4004         I915_WRITE(_3D_CHICKEN,
4005                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4006
4007         /* WaSetupGtModeTdRowDispatch:snb */
4008         if (IS_SNB_GT1(dev))
4009                 I915_WRITE(GEN6_GT_MODE,
4010                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4011
4012         I915_WRITE(WM3_LP_ILK, 0);
4013         I915_WRITE(WM2_LP_ILK, 0);
4014         I915_WRITE(WM1_LP_ILK, 0);
4015
4016         I915_WRITE(CACHE_MODE_0,
4017                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4018
4019         I915_WRITE(GEN6_UCGCTL1,
4020                    I915_READ(GEN6_UCGCTL1) |
4021                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4022                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4023
4024         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4025          * gating disable must be set.  Failure to set it results in
4026          * flickering pixels due to Z write ordering failures after
4027          * some amount of runtime in the Mesa "fire" demo, and Unigine
4028          * Sanctuary and Tropics, and apparently anything else with
4029          * alpha test or pixel discard.
4030          *
4031          * According to the spec, bit 11 (RCCUNIT) must also be set,
4032          * but we didn't debug actual testcases to find it out.
4033          *
4034          * Also apply WaDisableVDSUnitClockGating:snb and
4035          * WaDisableRCPBUnitClockGating:snb.
4036          */
4037         I915_WRITE(GEN6_UCGCTL2,
4038                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4039                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4040                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4041
4042         /* Bspec says we need to always set all mask bits. */
4043         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4044                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4045
4046         /*
4047          * According to the spec the following bits should be
4048          * set in order to enable memory self-refresh and fbc:
4049          * The bit21 and bit22 of 0x42000
4050          * The bit21 and bit22 of 0x42004
4051          * The bit5 and bit7 of 0x42020
4052          * The bit14 of 0x70180
4053          * The bit14 of 0x71180
4054          */
4055         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4056                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4057                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4058         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4059                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4060                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4061         I915_WRITE(ILK_DSPCLK_GATE_D,
4062                    I915_READ(ILK_DSPCLK_GATE_D) |
4063                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4064                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4065
4066         /* WaMbcDriverBootEnable:snb */
4067         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4068                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4069
4070         for_each_pipe(pipe) {
4071                 I915_WRITE(DSPCNTR(pipe),
4072                            I915_READ(DSPCNTR(pipe)) |
4073                            DISPPLANE_TRICKLE_FEED_DISABLE);
4074                 intel_flush_display_plane(dev_priv, pipe);
4075         }
4076
4077         /* The default value should be 0x200 according to docs, but the two
4078          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4079         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4080         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4081
4082         cpt_init_clock_gating(dev);
4083
4084         gen6_check_mch_setup(dev);
4085 }
4086
4087 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4088 {
4089         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4090
4091         reg &= ~GEN7_FF_SCHED_MASK;
4092         reg |= GEN7_FF_TS_SCHED_HW;
4093         reg |= GEN7_FF_VS_SCHED_HW;
4094         reg |= GEN7_FF_DS_SCHED_HW;
4095
4096         if (IS_HASWELL(dev_priv->dev))
4097                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4098
4099         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4100 }
4101
4102 static void lpt_init_clock_gating(struct drm_device *dev)
4103 {
4104         struct drm_i915_private *dev_priv = dev->dev_private;
4105
4106         /*
4107          * TODO: this bit should only be enabled when really needed, then
4108          * disabled when not needed anymore in order to save power.
4109          */
4110         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4111                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4112                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4113                            PCH_LP_PARTITION_LEVEL_DISABLE);
4114
4115         /* WADPOClockGatingDisable:hsw */
4116         I915_WRITE(_TRANSA_CHICKEN1,
4117                    I915_READ(_TRANSA_CHICKEN1) |
4118                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4119 }
4120
4121 static void lpt_suspend_hw(struct drm_device *dev)
4122 {
4123         struct drm_i915_private *dev_priv = dev->dev_private;
4124
4125         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4126                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4127
4128                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4129                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4130         }
4131 }
4132
4133 static void haswell_init_clock_gating(struct drm_device *dev)
4134 {
4135         struct drm_i915_private *dev_priv = dev->dev_private;
4136         int pipe;
4137
4138         I915_WRITE(WM3_LP_ILK, 0);
4139         I915_WRITE(WM2_LP_ILK, 0);
4140         I915_WRITE(WM1_LP_ILK, 0);
4141
4142         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4143          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4144          */
4145         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4146
4147         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4148         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4149                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4150
4151         /* WaApplyL3ControlAndL3ChickenMode:hsw */
4152         I915_WRITE(GEN7_L3CNTLREG1,
4153                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4154         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4155                         GEN7_WA_L3_CHICKEN_MODE);
4156
4157         /* This is required by WaCatErrorRejectionIssue:hsw */
4158         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4159                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4160                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4161
4162         for_each_pipe(pipe) {
4163                 I915_WRITE(DSPCNTR(pipe),
4164                            I915_READ(DSPCNTR(pipe)) |
4165                            DISPPLANE_TRICKLE_FEED_DISABLE);
4166                 intel_flush_display_plane(dev_priv, pipe);
4167         }
4168
4169         /* WaVSRefCountFullforceMissDisable:hsw */
4170         gen7_setup_fixed_func_scheduler(dev_priv);
4171
4172         /* WaDisable4x2SubspanOptimization:hsw */
4173         I915_WRITE(CACHE_MODE_1,
4174                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4175
4176         /* WaMbcDriverBootEnable:hsw */
4177         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4178                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4179
4180         /* WaSwitchSolVfFArbitrationPriority:hsw */
4181         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4182
4183         /* XXX: This is a workaround for early silicon revisions and should be
4184          * removed later.
4185          */
4186         I915_WRITE(WM_DBG,
4187                         I915_READ(WM_DBG) |
4188                         WM_DBG_DISALLOW_MULTIPLE_LP |
4189                         WM_DBG_DISALLOW_SPRITE |
4190                         WM_DBG_DISALLOW_MAXFIFO);
4191
4192         lpt_init_clock_gating(dev);
4193 }
4194
4195 static void ivybridge_init_clock_gating(struct drm_device *dev)
4196 {
4197         struct drm_i915_private *dev_priv = dev->dev_private;
4198         int pipe;
4199         uint32_t snpcr;
4200
4201         I915_WRITE(WM3_LP_ILK, 0);
4202         I915_WRITE(WM2_LP_ILK, 0);
4203         I915_WRITE(WM1_LP_ILK, 0);
4204
4205         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4206
4207         /* WaDisableEarlyCull:ivb */
4208         I915_WRITE(_3D_CHICKEN3,
4209                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4210
4211         /* WaDisableBackToBackFlipFix:ivb */
4212         I915_WRITE(IVB_CHICKEN3,
4213                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4214                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4215
4216         /* WaDisablePSDDualDispatchEnable:ivb */
4217         if (IS_IVB_GT1(dev))
4218                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4219                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4220         else
4221                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4222                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4223
4224         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4225         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4226                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4227
4228         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4229         I915_WRITE(GEN7_L3CNTLREG1,
4230                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4231         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4232                    GEN7_WA_L3_CHICKEN_MODE);
4233         if (IS_IVB_GT1(dev))
4234                 I915_WRITE(GEN7_ROW_CHICKEN2,
4235                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4236         else
4237                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4238                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4239
4240
4241         /* WaForceL3Serialization:ivb */
4242         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4243                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4244
4245         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4246          * gating disable must be set.  Failure to set it results in
4247          * flickering pixels due to Z write ordering failures after
4248          * some amount of runtime in the Mesa "fire" demo, and Unigine
4249          * Sanctuary and Tropics, and apparently anything else with
4250          * alpha test or pixel discard.
4251          *
4252          * According to the spec, bit 11 (RCCUNIT) must also be set,
4253          * but we didn't debug actual testcases to find it out.
4254          *
4255          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4256          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4257          */
4258         I915_WRITE(GEN6_UCGCTL2,
4259                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4260                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4261
4262         /* This is required by WaCatErrorRejectionIssue:ivb */
4263         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4264                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4265                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4266
4267         for_each_pipe(pipe) {
4268                 I915_WRITE(DSPCNTR(pipe),
4269                            I915_READ(DSPCNTR(pipe)) |
4270                            DISPPLANE_TRICKLE_FEED_DISABLE);
4271                 intel_flush_display_plane(dev_priv, pipe);
4272         }
4273
4274         /* WaMbcDriverBootEnable:ivb */
4275         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4276                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4277
4278         /* WaVSRefCountFullforceMissDisable:ivb */
4279         gen7_setup_fixed_func_scheduler(dev_priv);
4280
4281         /* WaDisable4x2SubspanOptimization:ivb */
4282         I915_WRITE(CACHE_MODE_1,
4283                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4284
4285         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4286         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4287         snpcr |= GEN6_MBC_SNPCR_MED;
4288         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4289
4290         if (!HAS_PCH_NOP(dev))
4291                 cpt_init_clock_gating(dev);
4292
4293         gen6_check_mch_setup(dev);
4294 }
4295
4296 static void valleyview_init_clock_gating(struct drm_device *dev)
4297 {
4298         struct drm_i915_private *dev_priv = dev->dev_private;
4299         int pipe;
4300
4301         I915_WRITE(WM3_LP_ILK, 0);
4302         I915_WRITE(WM2_LP_ILK, 0);
4303         I915_WRITE(WM1_LP_ILK, 0);
4304
4305         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4306
4307         /* WaDisableEarlyCull:vlv */
4308         I915_WRITE(_3D_CHICKEN3,
4309                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4310
4311         /* WaDisableBackToBackFlipFix:vlv */
4312         I915_WRITE(IVB_CHICKEN3,
4313                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4314                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4315
4316         /* WaDisablePSDDualDispatchEnable:vlv */
4317         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4318                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4319                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4320
4321         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4322         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4323                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4324
4325         /* WaApplyL3ControlAndL3ChickenMode:vlv */
4326         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4327         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4328
4329         /* WaForceL3Serialization:vlv */
4330         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4331                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4332
4333         /* WaDisableDopClockGating:vlv */
4334         I915_WRITE(GEN7_ROW_CHICKEN2,
4335                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4336
4337         /* WaForceL3Serialization:vlv */
4338         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4339                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4340
4341         /* This is required by WaCatErrorRejectionIssue:vlv */
4342         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4343                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4344                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4345
4346         /* WaMbcDriverBootEnable:vlv */
4347         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4348                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4349
4350
4351         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4352          * gating disable must be set.  Failure to set it results in
4353          * flickering pixels due to Z write ordering failures after
4354          * some amount of runtime in the Mesa "fire" demo, and Unigine
4355          * Sanctuary and Tropics, and apparently anything else with
4356          * alpha test or pixel discard.
4357          *
4358          * According to the spec, bit 11 (RCCUNIT) must also be set,
4359          * but we didn't debug actual testcases to find it out.
4360          *
4361          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4362          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4363          *
4364          * Also apply WaDisableVDSUnitClockGating:vlv and
4365          * WaDisableRCPBUnitClockGating:vlv.
4366          */
4367         I915_WRITE(GEN6_UCGCTL2,
4368                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4369                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4370                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4371                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4372                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4373
4374         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4375
4376         for_each_pipe(pipe) {
4377                 I915_WRITE(DSPCNTR(pipe),
4378                            I915_READ(DSPCNTR(pipe)) |
4379                            DISPPLANE_TRICKLE_FEED_DISABLE);
4380                 intel_flush_display_plane(dev_priv, pipe);
4381         }
4382
4383         I915_WRITE(CACHE_MODE_1,
4384                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4385
4386         /*
4387          * WaDisableVLVClockGating_VBIIssue:vlv
4388          * Disable clock gating on th GCFG unit to prevent a delay
4389          * in the reporting of vblank events.
4390          */
4391         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4392
4393         /* Conservative clock gating settings for now */
4394         I915_WRITE(0x9400, 0xffffffff);
4395         I915_WRITE(0x9404, 0xffffffff);
4396         I915_WRITE(0x9408, 0xffffffff);
4397         I915_WRITE(0x940c, 0xffffffff);
4398         I915_WRITE(0x9410, 0xffffffff);
4399         I915_WRITE(0x9414, 0xffffffff);
4400         I915_WRITE(0x9418, 0xffffffff);
4401 }
4402
4403 static void g4x_init_clock_gating(struct drm_device *dev)
4404 {
4405         struct drm_i915_private *dev_priv = dev->dev_private;
4406         uint32_t dspclk_gate;
4407
4408         I915_WRITE(RENCLK_GATE_D1, 0);
4409         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4410                    GS_UNIT_CLOCK_GATE_DISABLE |
4411                    CL_UNIT_CLOCK_GATE_DISABLE);
4412         I915_WRITE(RAMCLK_GATE_D, 0);
4413         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4414                 OVRUNIT_CLOCK_GATE_DISABLE |
4415                 OVCUNIT_CLOCK_GATE_DISABLE;
4416         if (IS_GM45(dev))
4417                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4418         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4419
4420         /* WaDisableRenderCachePipelinedFlush */
4421         I915_WRITE(CACHE_MODE_0,
4422                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4423 }
4424
4425 static void crestline_init_clock_gating(struct drm_device *dev)
4426 {
4427         struct drm_i915_private *dev_priv = dev->dev_private;
4428
4429         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4430         I915_WRITE(RENCLK_GATE_D2, 0);
4431         I915_WRITE(DSPCLK_GATE_D, 0);
4432         I915_WRITE(RAMCLK_GATE_D, 0);
4433         I915_WRITE16(DEUC, 0);
4434 }
4435
4436 static void broadwater_init_clock_gating(struct drm_device *dev)
4437 {
4438         struct drm_i915_private *dev_priv = dev->dev_private;
4439
4440         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4441                    I965_RCC_CLOCK_GATE_DISABLE |
4442                    I965_RCPB_CLOCK_GATE_DISABLE |
4443                    I965_ISC_CLOCK_GATE_DISABLE |
4444                    I965_FBC_CLOCK_GATE_DISABLE);
4445         I915_WRITE(RENCLK_GATE_D2, 0);
4446 }
4447
4448 static void gen3_init_clock_gating(struct drm_device *dev)
4449 {
4450         struct drm_i915_private *dev_priv = dev->dev_private;
4451         u32 dstate = I915_READ(D_STATE);
4452
4453         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4454                 DSTATE_DOT_CLOCK_GATING;
4455         I915_WRITE(D_STATE, dstate);
4456
4457         if (IS_PINEVIEW(dev))
4458                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4459
4460         /* IIR "flip pending" means done if this bit is set */
4461         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4462 }
4463
4464 static void i85x_init_clock_gating(struct drm_device *dev)
4465 {
4466         struct drm_i915_private *dev_priv = dev->dev_private;
4467
4468         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4469 }
4470
4471 static void i830_init_clock_gating(struct drm_device *dev)
4472 {
4473         struct drm_i915_private *dev_priv = dev->dev_private;
4474
4475         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4476 }
4477
4478 void intel_init_clock_gating(struct drm_device *dev)
4479 {
4480         struct drm_i915_private *dev_priv = dev->dev_private;
4481
4482         dev_priv->display.init_clock_gating(dev);
4483 }
4484
4485 void intel_suspend_hw(struct drm_device *dev)
4486 {
4487         if (HAS_PCH_LPT(dev))
4488                 lpt_suspend_hw(dev);
4489 }
4490
4491 /**
4492  * We should only use the power well if we explicitly asked the hardware to
4493  * enable it, so check if it's enabled and also check if we've requested it to
4494  * be enabled.
4495  */
4496 bool intel_display_power_enabled(struct drm_device *dev,
4497                                  enum intel_display_power_domain domain)
4498 {
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500
4501         if (!HAS_POWER_WELL(dev))
4502                 return true;
4503
4504         switch (domain) {
4505         case POWER_DOMAIN_PIPE_A:
4506         case POWER_DOMAIN_TRANSCODER_EDP:
4507                 return true;
4508         case POWER_DOMAIN_PIPE_B:
4509         case POWER_DOMAIN_PIPE_C:
4510         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4511         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4512         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4513         case POWER_DOMAIN_TRANSCODER_A:
4514         case POWER_DOMAIN_TRANSCODER_B:
4515         case POWER_DOMAIN_TRANSCODER_C:
4516                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4517                        (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4518         default:
4519                 BUG();
4520         }
4521 }
4522
4523 void intel_set_power_well(struct drm_device *dev, bool enable)
4524 {
4525         struct drm_i915_private *dev_priv = dev->dev_private;
4526         bool is_enabled, enable_requested;
4527         uint32_t tmp;
4528
4529         if (!HAS_POWER_WELL(dev))
4530                 return;
4531
4532         if (!i915_disable_power_well && !enable)
4533                 return;
4534
4535         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4536         is_enabled = tmp & HSW_PWR_WELL_STATE;
4537         enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4538
4539         if (enable) {
4540                 if (!enable_requested)
4541                         I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4542
4543                 if (!is_enabled) {
4544                         DRM_DEBUG_KMS("Enabling power well\n");
4545                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4546                                       HSW_PWR_WELL_STATE), 20))
4547                                 DRM_ERROR("Timeout enabling power well\n");
4548                 }
4549         } else {
4550                 if (enable_requested) {
4551                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4552                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
4553                 }
4554         }
4555 }
4556
4557 /*
4558  * Starting with Haswell, we have a "Power Down Well" that can be turned off
4559  * when not needed anymore. We have 4 registers that can request the power well
4560  * to be enabled, and it will only be disabled if none of the registers is
4561  * requesting it to be enabled.
4562  */
4563 void intel_init_power_well(struct drm_device *dev)
4564 {
4565         struct drm_i915_private *dev_priv = dev->dev_private;
4566
4567         if (!HAS_POWER_WELL(dev))
4568                 return;
4569
4570         /* For now, we need the power well to be always enabled. */
4571         intel_set_power_well(dev, true);
4572
4573         /* We're taking over the BIOS, so clear any requests made by it since
4574          * the driver is in charge now. */
4575         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4576                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4577 }
4578
4579 /* Set up chip specific power management-related functions */
4580 void intel_init_pm(struct drm_device *dev)
4581 {
4582         struct drm_i915_private *dev_priv = dev->dev_private;
4583
4584         if (I915_HAS_FBC(dev)) {
4585                 if (HAS_PCH_SPLIT(dev)) {
4586                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4587                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4588                                 dev_priv->display.enable_fbc =
4589                                         gen7_enable_fbc;
4590                         else
4591                                 dev_priv->display.enable_fbc =
4592                                         ironlake_enable_fbc;
4593                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4594                 } else if (IS_GM45(dev)) {
4595                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4596                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4597                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4598                 } else if (IS_CRESTLINE(dev)) {
4599                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4600                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4601                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4602                 }
4603                 /* 855GM needs testing */
4604         }
4605
4606         /* For cxsr */
4607         if (IS_PINEVIEW(dev))
4608                 i915_pineview_get_mem_freq(dev);
4609         else if (IS_GEN5(dev))
4610                 i915_ironlake_get_mem_freq(dev);
4611
4612         /* For FIFO watermark updates */
4613         if (HAS_PCH_SPLIT(dev)) {
4614                 if (IS_GEN5(dev)) {
4615                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4616                                 dev_priv->display.update_wm = ironlake_update_wm;
4617                         else {
4618                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4619                                               "Disable CxSR\n");
4620                                 dev_priv->display.update_wm = NULL;
4621                         }
4622                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4623                 } else if (IS_GEN6(dev)) {
4624                         if (SNB_READ_WM0_LATENCY()) {
4625                                 dev_priv->display.update_wm = sandybridge_update_wm;
4626                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4627                         } else {
4628                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4629                                               "Disable CxSR\n");
4630                                 dev_priv->display.update_wm = NULL;
4631                         }
4632                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4633                 } else if (IS_IVYBRIDGE(dev)) {
4634                         if (SNB_READ_WM0_LATENCY()) {
4635                                 dev_priv->display.update_wm = ivybridge_update_wm;
4636                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4637                         } else {
4638                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4639                                               "Disable CxSR\n");
4640                                 dev_priv->display.update_wm = NULL;
4641                         }
4642                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4643                 } else if (IS_HASWELL(dev)) {
4644                         if (SNB_READ_WM0_LATENCY()) {
4645                                 dev_priv->display.update_wm = haswell_update_wm;
4646                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4647                         } else {
4648                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4649                                               "Disable CxSR\n");
4650                                 dev_priv->display.update_wm = NULL;
4651                         }
4652                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4653                 } else
4654                         dev_priv->display.update_wm = NULL;
4655         } else if (IS_VALLEYVIEW(dev)) {
4656                 dev_priv->display.update_wm = valleyview_update_wm;
4657                 dev_priv->display.init_clock_gating =
4658                         valleyview_init_clock_gating;
4659         } else if (IS_PINEVIEW(dev)) {
4660                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4661                                             dev_priv->is_ddr3,
4662                                             dev_priv->fsb_freq,
4663                                             dev_priv->mem_freq)) {
4664                         DRM_INFO("failed to find known CxSR latency "
4665                                  "(found ddr%s fsb freq %d, mem freq %d), "
4666                                  "disabling CxSR\n",
4667                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4668                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4669                         /* Disable CxSR and never update its watermark again */
4670                         pineview_disable_cxsr(dev);
4671                         dev_priv->display.update_wm = NULL;
4672                 } else
4673                         dev_priv->display.update_wm = pineview_update_wm;
4674                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4675         } else if (IS_G4X(dev)) {
4676                 dev_priv->display.update_wm = g4x_update_wm;
4677                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4678         } else if (IS_GEN4(dev)) {
4679                 dev_priv->display.update_wm = i965_update_wm;
4680                 if (IS_CRESTLINE(dev))
4681                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4682                 else if (IS_BROADWATER(dev))
4683                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4684         } else if (IS_GEN3(dev)) {
4685                 dev_priv->display.update_wm = i9xx_update_wm;
4686                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4687                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4688         } else if (IS_I865G(dev)) {
4689                 dev_priv->display.update_wm = i830_update_wm;
4690                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4691                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4692         } else if (IS_I85X(dev)) {
4693                 dev_priv->display.update_wm = i9xx_update_wm;
4694                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4695                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4696         } else {
4697                 dev_priv->display.update_wm = i830_update_wm;
4698                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4699                 if (IS_845G(dev))
4700                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4701                 else
4702                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4703         }
4704 }
4705
4706 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4707 {
4708         u32 gt_thread_status_mask;
4709
4710         if (IS_HASWELL(dev_priv->dev))
4711                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4712         else
4713                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4714
4715         /* w/a for a sporadic read returning 0 by waiting for the GT
4716          * thread to wake up.
4717          */
4718         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4719                 DRM_ERROR("GT thread status wait timed out\n");
4720 }
4721
4722 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4723 {
4724         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4725         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4726 }
4727
4728 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4729 {
4730         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
4731                             FORCEWAKE_ACK_TIMEOUT_MS))
4732                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4733
4734         I915_WRITE_NOTRACE(FORCEWAKE, 1);
4735         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4736
4737         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
4738                             FORCEWAKE_ACK_TIMEOUT_MS))
4739                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4740
4741         /* WaRsForcewakeWaitTC0:snb */
4742         __gen6_gt_wait_for_thread_c0(dev_priv);
4743 }
4744
4745 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4746 {
4747         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4748         /* something from same cacheline, but !FORCEWAKE_MT */
4749         POSTING_READ(ECOBUS);
4750 }
4751
4752 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4753 {
4754         u32 forcewake_ack;
4755
4756         if (IS_HASWELL(dev_priv->dev))
4757                 forcewake_ack = FORCEWAKE_ACK_HSW;
4758         else
4759                 forcewake_ack = FORCEWAKE_MT_ACK;
4760
4761         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
4762                             FORCEWAKE_ACK_TIMEOUT_MS))
4763                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4764
4765         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4766         /* something from same cacheline, but !FORCEWAKE_MT */
4767         POSTING_READ(ECOBUS);
4768
4769         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
4770                             FORCEWAKE_ACK_TIMEOUT_MS))
4771                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4772
4773         /* WaRsForcewakeWaitTC0:ivb,hsw */
4774         __gen6_gt_wait_for_thread_c0(dev_priv);
4775 }
4776
4777 /*
4778  * Generally this is called implicitly by the register read function. However,
4779  * if some sequence requires the GT to not power down then this function should
4780  * be called at the beginning of the sequence followed by a call to
4781  * gen6_gt_force_wake_put() at the end of the sequence.
4782  */
4783 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4784 {
4785         unsigned long irqflags;
4786
4787         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4788         if (dev_priv->forcewake_count++ == 0)
4789                 dev_priv->gt.force_wake_get(dev_priv);
4790         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4791 }
4792
4793 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4794 {
4795         u32 gtfifodbg;
4796         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4797         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4798              "MMIO read or write has been dropped %x\n", gtfifodbg))
4799                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4800 }
4801
4802 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4803 {
4804         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4805         /* something from same cacheline, but !FORCEWAKE */
4806         POSTING_READ(ECOBUS);
4807         gen6_gt_check_fifodbg(dev_priv);
4808 }
4809
4810 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4811 {
4812         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4813         /* something from same cacheline, but !FORCEWAKE_MT */
4814         POSTING_READ(ECOBUS);
4815         gen6_gt_check_fifodbg(dev_priv);
4816 }
4817
4818 /*
4819  * see gen6_gt_force_wake_get()
4820  */
4821 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4822 {
4823         unsigned long irqflags;
4824
4825         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4826         if (--dev_priv->forcewake_count == 0)
4827                 dev_priv->gt.force_wake_put(dev_priv);
4828         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4829 }
4830
4831 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4832 {
4833         int ret = 0;
4834
4835         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4836                 int loop = 500;
4837                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4838                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4839                         udelay(10);
4840                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4841                 }
4842                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4843                         ++ret;
4844                 dev_priv->gt_fifo_count = fifo;
4845         }
4846         dev_priv->gt_fifo_count--;
4847
4848         return ret;
4849 }
4850
4851 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4852 {
4853         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4854         /* something from same cacheline, but !FORCEWAKE_VLV */
4855         POSTING_READ(FORCEWAKE_ACK_VLV);
4856 }
4857
4858 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4859 {
4860         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
4861                             FORCEWAKE_ACK_TIMEOUT_MS))
4862                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4863
4864         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4865         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4866                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4867
4868         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
4869                             FORCEWAKE_ACK_TIMEOUT_MS))
4870                 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4871
4872         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4873                              FORCEWAKE_KERNEL),
4874                             FORCEWAKE_ACK_TIMEOUT_MS))
4875                 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
4876
4877         /* WaRsForcewakeWaitTC0:vlv */
4878         __gen6_gt_wait_for_thread_c0(dev_priv);
4879 }
4880
4881 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4882 {
4883         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4884         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4885                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4886         /* The below doubles as a POSTING_READ */
4887         gen6_gt_check_fifodbg(dev_priv);
4888 }
4889
4890 void intel_gt_reset(struct drm_device *dev)
4891 {
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893
4894         if (IS_VALLEYVIEW(dev)) {
4895                 vlv_force_wake_reset(dev_priv);
4896         } else if (INTEL_INFO(dev)->gen >= 6) {
4897                 __gen6_gt_force_wake_reset(dev_priv);
4898                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4899                         __gen6_gt_force_wake_mt_reset(dev_priv);
4900         }
4901 }
4902
4903 void intel_gt_init(struct drm_device *dev)
4904 {
4905         struct drm_i915_private *dev_priv = dev->dev_private;
4906
4907         spin_lock_init(&dev_priv->gt_lock);
4908
4909         intel_gt_reset(dev);
4910
4911         if (IS_VALLEYVIEW(dev)) {
4912                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4913                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4914         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4915                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4916                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4917         } else if (IS_GEN6(dev)) {
4918                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4919                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4920         }
4921         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4922                           intel_gen6_powersave_work);
4923 }
4924
4925 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4926 {
4927         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4928
4929         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4930                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4931                 return -EAGAIN;
4932         }
4933
4934         I915_WRITE(GEN6_PCODE_DATA, *val);
4935         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4936
4937         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4938                      500)) {
4939                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4940                 return -ETIMEDOUT;
4941         }
4942
4943         *val = I915_READ(GEN6_PCODE_DATA);
4944         I915_WRITE(GEN6_PCODE_DATA, 0);
4945
4946         return 0;
4947 }
4948
4949 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4950 {
4951         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4952
4953         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4954                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4955                 return -EAGAIN;
4956         }
4957
4958         I915_WRITE(GEN6_PCODE_DATA, val);
4959         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4960
4961         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4962                      500)) {
4963                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4964                 return -ETIMEDOUT;
4965         }
4966
4967         I915_WRITE(GEN6_PCODE_DATA, 0);
4968
4969         return 0;
4970 }
4971
4972 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
4973                         u8 addr, u32 *val)
4974 {
4975         u32 cmd, devfn, be, bar;
4976
4977         bar = 0;
4978         be = 0xf;
4979         devfn = PCI_DEVFN(2, 0);
4980
4981         cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4982                 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4983                 (bar << IOSF_BAR_SHIFT);
4984
4985         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4986
4987         if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4988                 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4989                                  opcode == PUNIT_OPCODE_REG_READ ?
4990                                  "read" : "write");
4991                 return -EAGAIN;
4992         }
4993
4994         I915_WRITE(VLV_IOSF_ADDR, addr);
4995         if (opcode == PUNIT_OPCODE_REG_WRITE)
4996                 I915_WRITE(VLV_IOSF_DATA, *val);
4997         I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4998
4999         if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
5000                      5)) {
5001                 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
5002                           opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
5003                           addr);
5004                 return -ETIMEDOUT;
5005         }
5006
5007         if (opcode == PUNIT_OPCODE_REG_READ)
5008                 *val = I915_READ(VLV_IOSF_DATA);
5009         I915_WRITE(VLV_IOSF_DATA, 0);
5010
5011         return 0;
5012 }
5013
5014 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
5015 {
5016         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
5017                             addr, val);
5018 }
5019
5020 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
5021 {
5022         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
5023                             addr, &val);
5024 }
5025
5026 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
5027 {
5028         return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
5029                             addr, val);
5030 }
5031
5032 int vlv_gpu_freq(int ddr_freq, int val)
5033 {
5034         int mult, base;
5035
5036         switch (ddr_freq) {
5037         case 800:
5038                 mult = 20;
5039                 base = 120;
5040                 break;
5041         case 1066:
5042                 mult = 22;
5043                 base = 133;
5044                 break;
5045         case 1333:
5046                 mult = 21;
5047                 base = 125;
5048                 break;
5049         default:
5050                 return -1;
5051         }
5052
5053         return ((val - 0xbd) * mult) + base;
5054 }
5055
5056 int vlv_freq_opcode(int ddr_freq, int val)
5057 {
5058         int mult, base;
5059
5060         switch (ddr_freq) {
5061         case 800:
5062                 mult = 20;
5063                 base = 120;
5064                 break;
5065         case 1066:
5066                 mult = 22;
5067                 base = 133;
5068                 break;
5069         case 1333:
5070                 mult = 21;
5071                 base = 125;
5072                 break;
5073         default:
5074                 return -1;
5075         }
5076
5077         val /= mult;
5078         val -= base / mult;
5079         val += 0xbd;
5080
5081         if (val > 0xea)
5082                 val = 0xea;
5083
5084         return val;
5085 }
5086