drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void gen9_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaEnableLbsSlaRetryTimerDecrement:skl */
  60         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
  61                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
  62
  63         /* WaDisableKillLogic:bxt,skl */
  64         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  65                    ECOCHK_DIS_TLB);
  66 }
  67
  68 static void skl_init_clock_gating(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         gen9_init_clock_gating(dev);
  73
  74         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
  75                 /* WaDisableHDCInvalidation:skl */
  76                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  77                            BDW_DISABLE_HDC_INVALIDATION);
  78
  79                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
  80                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
  81                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
  82         }
  83
  84         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
  85          * involving this register should also be added to WA batch as required.
  86          */
  87         if (INTEL_REVID(dev) <= SKL_REVID_E0)
  88                 /* WaDisableLSQCROPERFforOCL:skl */
  89                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
  90                            GEN8_LQSC_RO_PERF_DIS);
  91
  92         /* WaEnableGapsTsvCreditFix:skl */
  93         if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
  94                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
  95                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
  96         }
  97 }
  98
  99 static void bxt_init_clock_gating(struct drm_device *dev)
 100 {
 101         struct drm_i915_private *dev_priv = dev->dev_private;
 102
 103         gen9_init_clock_gating(dev);
 104
 105         /* WaDisableSDEUnitClockGating:bxt */
 106         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 107                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 108
 109         /*
 110          * FIXME:
 111          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 112          */
 113         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 114                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 115
 116         /* WaStoreMultiplePTEenable:bxt */
 117         /* This is a requirement according to Hardware specification */
 118         if (INTEL_REVID(dev) == BXT_REVID_A0)
 119                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 120
 121         /* WaSetClckGatingDisableMedia:bxt */
 122         if (INTEL_REVID(dev) == BXT_REVID_A0) {
 123                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
 124                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
 125         }
 126 }
 127
 128 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 129 {
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         u32 tmp;
 132
 133         tmp = I915_READ(CLKCFG);
 134
 135         switch (tmp & CLKCFG_FSB_MASK) {
 136         case CLKCFG_FSB_533:
 137                 dev_priv->fsb_freq = 533; /* 133*4 */
 138                 break;
 139         case CLKCFG_FSB_800:
 140                 dev_priv->fsb_freq = 800; /* 200*4 */
 141                 break;
 142         case CLKCFG_FSB_667:
 143                 dev_priv->fsb_freq =  667; /* 167*4 */
 144                 break;
 145         case CLKCFG_FSB_400:
 146                 dev_priv->fsb_freq = 400; /* 100*4 */
 147                 break;
 148         }
 149
 150         switch (tmp & CLKCFG_MEM_MASK) {
 151         case CLKCFG_MEM_533:
 152                 dev_priv->mem_freq = 533;
 153                 break;
 154         case CLKCFG_MEM_667:
 155                 dev_priv->mem_freq = 667;
 156                 break;
 157         case CLKCFG_MEM_800:
 158                 dev_priv->mem_freq = 800;
 159                 break;
 160         }
 161
 162         /* detect pineview DDR3 setting */
 163         tmp = I915_READ(CSHRDDR3CTL);
 164         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 165 }
 166
 167 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 168 {
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         u16 ddrpll, csipll;
 171
 172         ddrpll = I915_READ16(DDRMPLL1);
 173         csipll = I915_READ16(CSIPLL0);
 174
 175         switch (ddrpll & 0xff) {
 176         case 0xc:
 177                 dev_priv->mem_freq = 800;
 178                 break;
 179         case 0x10:
 180                 dev_priv->mem_freq = 1066;
 181                 break;
 182         case 0x14:
 183                 dev_priv->mem_freq = 1333;
 184                 break;
 185         case 0x18:
 186                 dev_priv->mem_freq = 1600;
 187                 break;
 188         default:
 189                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 190                                  ddrpll & 0xff);
 191                 dev_priv->mem_freq = 0;
 192                 break;
 193         }
 194
 195         dev_priv->ips.r_t = dev_priv->mem_freq;
 196
 197         switch (csipll & 0x3ff) {
 198         case 0x00c:
 199                 dev_priv->fsb_freq = 3200;
 200                 break;
 201         case 0x00e:
 202                 dev_priv->fsb_freq = 3733;
 203                 break;
 204         case 0x010:
 205                 dev_priv->fsb_freq = 4266;
 206                 break;
 207         case 0x012:
 208                 dev_priv->fsb_freq = 4800;
 209                 break;
 210         case 0x014:
 211                 dev_priv->fsb_freq = 5333;
 212                 break;
 213         case 0x016:
 214                 dev_priv->fsb_freq = 5866;
 215                 break;
 216         case 0x018:
 217                 dev_priv->fsb_freq = 6400;
 218                 break;
 219         default:
 220                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 221                                  csipll & 0x3ff);
 222                 dev_priv->fsb_freq = 0;
 223                 break;
 224         }
 225
 226         if (dev_priv->fsb_freq == 3200) {
 227                 dev_priv->ips.c_m = 0;
 228         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 229                 dev_priv->ips.c_m = 1;
 230         } else {
 231                 dev_priv->ips.c_m = 2;
 232         }
 233 }
 234
 235 static const struct cxsr_latency cxsr_latency_table[] = {
 236         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 237         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 238         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 239         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 240         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 241
 242         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 243         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 244         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 245         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 246         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 247
 248         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 249         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 250         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 251         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 252         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 253
 254         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 255         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 256         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 257         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 258         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 259
 260         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 261         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 262         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 263         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 264         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 265
 266         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 267         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 268         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 269         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 270         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 271 };
 272
 273 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 274                                                          int is_ddr3,
 275                                                          int fsb,
 276                                                          int mem)
 277 {
 278         const struct cxsr_latency *latency;
 279         int i;
 280
 281         if (fsb == 0 || mem == 0)
 282                 return NULL;
 283
 284         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 285                 latency = &cxsr_latency_table[i];
 286                 if (is_desktop == latency->is_desktop &&
 287                     is_ddr3 == latency->is_ddr3 &&
 288                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 289                         return latency;
 290         }
 291
 292         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 293
 294         return NULL;
 295 }
 296
 297 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 298 {
 299         u32 val;
 300
 301         mutex_lock(&dev_priv->rps.hw_lock);
 302
 303         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 304         if (enable)
 305                 val &= ~FORCE_DDR_HIGH_FREQ;
 306         else
 307                 val |= FORCE_DDR_HIGH_FREQ;
 308         val &= ~FORCE_DDR_LOW_FREQ;
 309         val |= FORCE_DDR_FREQ_REQ_ACK;
 310         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 311
 312         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 313                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 314                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 315
 316         mutex_unlock(&dev_priv->rps.hw_lock);
 317 }
 318
 319 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 320 {
 321         u32 val;
 322
 323         mutex_lock(&dev_priv->rps.hw_lock);
 324
 325         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 326         if (enable)
 327                 val |= DSP_MAXFIFO_PM5_ENABLE;
 328         else
 329                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 330         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 331
 332         mutex_unlock(&dev_priv->rps.hw_lock);
 333 }
 334
 335 #define FW_WM(value, plane) \
 336         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 337
 338 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 339 {
 340         struct drm_device *dev = dev_priv->dev;
 341         u32 val;
 342
 343         if (IS_VALLEYVIEW(dev)) {
 344                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 345                 POSTING_READ(FW_BLC_SELF_VLV);
 346                 dev_priv->wm.vlv.cxsr = enable;
 347         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 348                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 349                 POSTING_READ(FW_BLC_SELF);
 350         } else if (IS_PINEVIEW(dev)) {
 351                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 352                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 353                 I915_WRITE(DSPFW3, val);
 354                 POSTING_READ(DSPFW3);
 355         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 356                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 357                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 358                 I915_WRITE(FW_BLC_SELF, val);
 359                 POSTING_READ(FW_BLC_SELF);
 360         } else if (IS_I915GM(dev)) {
 361                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 362                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 363                 I915_WRITE(INSTPM, val);
 364                 POSTING_READ(INSTPM);
 365         } else {
 366                 return;
 367         }
 368
 369         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 370                       enable ? "enabled" : "disabled");
 371 }
 372
 373
 374 /*
 375  * Latency for FIFO fetches is dependent on several factors:
 376  *   - memory configuration (speed, channels)
 377  *   - chipset
 378  *   - current MCH state
 379  * It can be fairly high in some situations, so here we assume a fairly
 380  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 381  * set this value too high, the FIFO will fetch frequently to stay full)
 382  * and power consumption (set it too low to save power and we might see
 383  * FIFO underruns and display "flicker").
 384  *
 385  * A value of 5us seems to be a good balance; safe for very low end
 386  * platforms but not overly aggressive on lower latency configs.
 387  */
 388 static const int pessimal_latency_ns = 5000;
 389
 390 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 391         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 392
 393 static int vlv_get_fifo_size(struct drm_device *dev,
 394                               enum pipe pipe, int plane)
 395 {
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397         int sprite0_start, sprite1_start, size;
 398
 399         switch (pipe) {
 400                 uint32_t dsparb, dsparb2, dsparb3;
 401         case PIPE_A:
 402                 dsparb = I915_READ(DSPARB);
 403                 dsparb2 = I915_READ(DSPARB2);
 404                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 405                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 406                 break;
 407         case PIPE_B:
 408                 dsparb = I915_READ(DSPARB);
 409                 dsparb2 = I915_READ(DSPARB2);
 410                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 411                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 412                 break;
 413         case PIPE_C:
 414                 dsparb2 = I915_READ(DSPARB2);
 415                 dsparb3 = I915_READ(DSPARB3);
 416                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 417                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 418                 break;
 419         default:
 420                 return 0;
 421         }
 422
 423         switch (plane) {
 424         case 0:
 425                 size = sprite0_start;
 426                 break;
 427         case 1:
 428                 size = sprite1_start - sprite0_start;
 429                 break;
 430         case 2:
 431                 size = 512 - 1 - sprite1_start;
 432                 break;
 433         default:
 434                 return 0;
 435         }
 436
 437         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 438                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 439                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 440                       size);
 441
 442         return size;
 443 }
 444
 445 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 446 {
 447         struct drm_i915_private *dev_priv = dev->dev_private;
 448         uint32_t dsparb = I915_READ(DSPARB);
 449         int size;
 450
 451         size = dsparb & 0x7f;
 452         if (plane)
 453                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 454
 455         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 456                       plane ? "B" : "A", size);
 457
 458         return size;
 459 }
 460
 461 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 462 {
 463         struct drm_i915_private *dev_priv = dev->dev_private;
 464         uint32_t dsparb = I915_READ(DSPARB);
 465         int size;
 466
 467         size = dsparb & 0x1ff;
 468         if (plane)
 469                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 470         size >>= 1; /* Convert to cachelines */
 471
 472         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 473                       plane ? "B" : "A", size);
 474
 475         return size;
 476 }
 477
 478 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481         uint32_t dsparb = I915_READ(DSPARB);
 482         int size;
 483
 484         size = dsparb & 0x7f;
 485         size >>= 2; /* Convert to cachelines */
 486
 487         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 488                       plane ? "B" : "A",
 489                       size);
 490
 491         return size;
 492 }
 493
 494 /* Pineview has different values for various configs */
 495 static const struct intel_watermark_params pineview_display_wm = {
 496         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 497         .max_wm = PINEVIEW_MAX_WM,
 498         .default_wm = PINEVIEW_DFT_WM,
 499         .guard_size = PINEVIEW_GUARD_WM,
 500         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 501 };
 502 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 503         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 504         .max_wm = PINEVIEW_MAX_WM,
 505         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 506         .guard_size = PINEVIEW_GUARD_WM,
 507         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 508 };
 509 static const struct intel_watermark_params pineview_cursor_wm = {
 510         .fifo_size = PINEVIEW_CURSOR_FIFO,
 511         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 512         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 513         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 514         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 515 };
 516 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 517         .fifo_size = PINEVIEW_CURSOR_FIFO,
 518         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 519         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 520         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 521         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 522 };
 523 static const struct intel_watermark_params g4x_wm_info = {
 524         .fifo_size = G4X_FIFO_SIZE,
 525         .max_wm = G4X_MAX_WM,
 526         .default_wm = G4X_MAX_WM,
 527         .guard_size = 2,
 528         .cacheline_size = G4X_FIFO_LINE_SIZE,
 529 };
 530 static const struct intel_watermark_params g4x_cursor_wm_info = {
 531         .fifo_size = I965_CURSOR_FIFO,
 532         .max_wm = I965_CURSOR_MAX_WM,
 533         .default_wm = I965_CURSOR_DFT_WM,
 534         .guard_size = 2,
 535         .cacheline_size = G4X_FIFO_LINE_SIZE,
 536 };
 537 static const struct intel_watermark_params valleyview_wm_info = {
 538         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 539         .max_wm = VALLEYVIEW_MAX_WM,
 540         .default_wm = VALLEYVIEW_MAX_WM,
 541         .guard_size = 2,
 542         .cacheline_size = G4X_FIFO_LINE_SIZE,
 543 };
 544 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 545         .fifo_size = I965_CURSOR_FIFO,
 546         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 547         .default_wm = I965_CURSOR_DFT_WM,
 548         .guard_size = 2,
 549         .cacheline_size = G4X_FIFO_LINE_SIZE,
 550 };
 551 static const struct intel_watermark_params i965_cursor_wm_info = {
 552         .fifo_size = I965_CURSOR_FIFO,
 553         .max_wm = I965_CURSOR_MAX_WM,
 554         .default_wm = I965_CURSOR_DFT_WM,
 555         .guard_size = 2,
 556         .cacheline_size = I915_FIFO_LINE_SIZE,
 557 };
 558 static const struct intel_watermark_params i945_wm_info = {
 559         .fifo_size = I945_FIFO_SIZE,
 560         .max_wm = I915_MAX_WM,
 561         .default_wm = 1,
 562         .guard_size = 2,
 563         .cacheline_size = I915_FIFO_LINE_SIZE,
 564 };
 565 static const struct intel_watermark_params i915_wm_info = {
 566         .fifo_size = I915_FIFO_SIZE,
 567         .max_wm = I915_MAX_WM,
 568         .default_wm = 1,
 569         .guard_size = 2,
 570         .cacheline_size = I915_FIFO_LINE_SIZE,
 571 };
 572 static const struct intel_watermark_params i830_a_wm_info = {
 573         .fifo_size = I855GM_FIFO_SIZE,
 574         .max_wm = I915_MAX_WM,
 575         .default_wm = 1,
 576         .guard_size = 2,
 577         .cacheline_size = I830_FIFO_LINE_SIZE,
 578 };
 579 static const struct intel_watermark_params i830_bc_wm_info = {
 580         .fifo_size = I855GM_FIFO_SIZE,
 581         .max_wm = I915_MAX_WM/2,
 582         .default_wm = 1,
 583         .guard_size = 2,
 584         .cacheline_size = I830_FIFO_LINE_SIZE,
 585 };
 586 static const struct intel_watermark_params i845_wm_info = {
 587         .fifo_size = I830_FIFO_SIZE,
 588         .max_wm = I915_MAX_WM,
 589         .default_wm = 1,
 590         .guard_size = 2,
 591         .cacheline_size = I830_FIFO_LINE_SIZE,
 592 };
 593
 594 /**
 595  * intel_calculate_wm - calculate watermark level
 596  * @clock_in_khz: pixel clock
 597  * @wm: chip FIFO params
 598  * @pixel_size: display pixel size
 599  * @latency_ns: memory latency for the platform
 600  *
 601  * Calculate the watermark level (the level at which the display plane will
 602  * start fetching from memory again).  Each chip has a different display
 603  * FIFO size and allocation, so the caller needs to figure that out and pass
 604  * in the correct intel_watermark_params structure.
 605  *
 606  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 607  * on the pixel size.  When it reaches the watermark level, it'll start
 608  * fetching FIFO line sized based chunks from memory until the FIFO fills
 609  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 610  * will occur, and a display engine hang could result.
 611  */
 612 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 613                                         const struct intel_watermark_params *wm,
 614                                         int fifo_size,
 615                                         int pixel_size,
 616                                         unsigned long latency_ns)
 617 {
 618         long entries_required, wm_size;
 619
 620         /*
 621          * Note: we need to make sure we don't overflow for various clock &
 622          * latency values.
 623          * clocks go from a few thousand to several hundred thousand.
 624          * latency is usually a few thousand
 625          */
 626         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 627                 1000;
 628         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 629
 630         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 631
 632         wm_size = fifo_size - (entries_required + wm->guard_size);
 633
 634         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 635
 636         /* Don't promote wm_size to unsigned... */
 637         if (wm_size > (long)wm->max_wm)
 638                 wm_size = wm->max_wm;
 639         if (wm_size <= 0)
 640                 wm_size = wm->default_wm;
 641
 642         /*
 643          * Bspec seems to indicate that the value shouldn't be lower than
 644          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 645          * Lets go for 8 which is the burst size since certain platforms
 646          * already use a hardcoded 8 (which is what the spec says should be
 647          * done).
 648          */
 649         if (wm_size <= 8)
 650                 wm_size = 8;
 651
 652         return wm_size;
 653 }
 654
 655 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 656 {
 657         struct drm_crtc *crtc, *enabled = NULL;
 658
 659         for_each_crtc(dev, crtc) {
 660                 if (intel_crtc_active(crtc)) {
 661                         if (enabled)
 662                                 return NULL;
 663                         enabled = crtc;
 664                 }
 665         }
 666
 667         return enabled;
 668 }
 669
 670 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 671 {
 672         struct drm_device *dev = unused_crtc->dev;
 673         struct drm_i915_private *dev_priv = dev->dev_private;
 674         struct drm_crtc *crtc;
 675         const struct cxsr_latency *latency;
 676         u32 reg;
 677         unsigned long wm;
 678
 679         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 680                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 681         if (!latency) {
 682                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 683                 intel_set_memory_cxsr(dev_priv, false);
 684                 return;
 685         }
 686
 687         crtc = single_enabled_crtc(dev);
 688         if (crtc) {
 689                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 690                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 691                 int clock = adjusted_mode->crtc_clock;
 692
 693                 /* Display SR */
 694                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 695                                         pineview_display_wm.fifo_size,
 696                                         pixel_size, latency->display_sr);
 697                 reg = I915_READ(DSPFW1);
 698                 reg &= ~DSPFW_SR_MASK;
 699                 reg |= FW_WM(wm, SR);
 700                 I915_WRITE(DSPFW1, reg);
 701                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 702
 703                 /* cursor SR */
 704                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 705                                         pineview_display_wm.fifo_size,
 706                                         pixel_size, latency->cursor_sr);
 707                 reg = I915_READ(DSPFW3);
 708                 reg &= ~DSPFW_CURSOR_SR_MASK;
 709                 reg |= FW_WM(wm, CURSOR_SR);
 710                 I915_WRITE(DSPFW3, reg);
 711
 712                 /* Display HPLL off SR */
 713                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 714                                         pineview_display_hplloff_wm.fifo_size,
 715                                         pixel_size, latency->display_hpll_disable);
 716                 reg = I915_READ(DSPFW3);
 717                 reg &= ~DSPFW_HPLL_SR_MASK;
 718                 reg |= FW_WM(wm, HPLL_SR);
 719                 I915_WRITE(DSPFW3, reg);
 720
 721                 /* cursor HPLL off SR */
 722                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 723                                         pineview_display_hplloff_wm.fifo_size,
 724                                         pixel_size, latency->cursor_hpll_disable);
 725                 reg = I915_READ(DSPFW3);
 726                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 727                 reg |= FW_WM(wm, HPLL_CURSOR);
 728                 I915_WRITE(DSPFW3, reg);
 729                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 730
 731                 intel_set_memory_cxsr(dev_priv, true);
 732         } else {
 733                 intel_set_memory_cxsr(dev_priv, false);
 734         }
 735 }
 736
 737 static bool g4x_compute_wm0(struct drm_device *dev,
 738                             int plane,
 739                             const struct intel_watermark_params *display,
 740                             int display_latency_ns,
 741                             const struct intel_watermark_params *cursor,
 742                             int cursor_latency_ns,
 743                             int *plane_wm,
 744                             int *cursor_wm)
 745 {
 746         struct drm_crtc *crtc;
 747         const struct drm_display_mode *adjusted_mode;
 748         int htotal, hdisplay, clock, pixel_size;
 749         int line_time_us, line_count;
 750         int entries, tlb_miss;
 751
 752         crtc = intel_get_crtc_for_plane(dev, plane);
 753         if (!intel_crtc_active(crtc)) {
 754                 *cursor_wm = cursor->guard_size;
 755                 *plane_wm = display->guard_size;
 756                 return false;
 757         }
 758
 759         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 760         clock = adjusted_mode->crtc_clock;
 761         htotal = adjusted_mode->crtc_htotal;
 762         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 763         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 764
 765         /* Use the small buffer method to calculate plane watermark */
 766         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 767         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 768         if (tlb_miss > 0)
 769                 entries += tlb_miss;
 770         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 771         *plane_wm = entries + display->guard_size;
 772         if (*plane_wm > (int)display->max_wm)
 773                 *plane_wm = display->max_wm;
 774
 775         /* Use the large buffer method to calculate cursor watermark */
 776         line_time_us = max(htotal * 1000 / clock, 1);
 777         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 778         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 779         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 780         if (tlb_miss > 0)
 781                 entries += tlb_miss;
 782         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 783         *cursor_wm = entries + cursor->guard_size;
 784         if (*cursor_wm > (int)cursor->max_wm)
 785                 *cursor_wm = (int)cursor->max_wm;
 786
 787         return true;
 788 }
 789
 790 /*
 791  * Check the wm result.
 792  *
 793  * If any calculated watermark values is larger than the maximum value that
 794  * can be programmed into the associated watermark register, that watermark
 795  * must be disabled.
 796  */
 797 static bool g4x_check_srwm(struct drm_device *dev,
 798                            int display_wm, int cursor_wm,
 799                            const struct intel_watermark_params *display,
 800                            const struct intel_watermark_params *cursor)
 801 {
 802         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 803                       display_wm, cursor_wm);
 804
 805         if (display_wm > display->max_wm) {
 806                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 807                               display_wm, display->max_wm);
 808                 return false;
 809         }
 810
 811         if (cursor_wm > cursor->max_wm) {
 812                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 813                               cursor_wm, cursor->max_wm);
 814                 return false;
 815         }
 816
 817         if (!(display_wm || cursor_wm)) {
 818                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 819                 return false;
 820         }
 821
 822         return true;
 823 }
 824
 825 static bool g4x_compute_srwm(struct drm_device *dev,
 826                              int plane,
 827                              int latency_ns,
 828                              const struct intel_watermark_params *display,
 829                              const struct intel_watermark_params *cursor,
 830                              int *display_wm, int *cursor_wm)
 831 {
 832         struct drm_crtc *crtc;
 833         const struct drm_display_mode *adjusted_mode;
 834         int hdisplay, htotal, pixel_size, clock;
 835         unsigned long line_time_us;
 836         int line_count, line_size;
 837         int small, large;
 838         int entries;
 839
 840         if (!latency_ns) {
 841                 *display_wm = *cursor_wm = 0;
 842                 return false;
 843         }
 844
 845         crtc = intel_get_crtc_for_plane(dev, plane);
 846         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 847         clock = adjusted_mode->crtc_clock;
 848         htotal = adjusted_mode->crtc_htotal;
 849         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 850         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 851
 852         line_time_us = max(htotal * 1000 / clock, 1);
 853         line_count = (latency_ns / line_time_us + 1000) / 1000;
 854         line_size = hdisplay * pixel_size;
 855
 856         /* Use the minimum of the small and large buffer method for primary */
 857         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 858         large = line_count * line_size;
 859
 860         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 861         *display_wm = entries + display->guard_size;
 862
 863         /* calculate the self-refresh watermark for display cursor */
 864         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 865         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 866         *cursor_wm = entries + cursor->guard_size;
 867
 868         return g4x_check_srwm(dev,
 869                               *display_wm, *cursor_wm,
 870                               display, cursor);
 871 }
 872
 873 #define FW_WM_VLV(value, plane) \
 874         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 875
 876 static void vlv_write_wm_values(struct intel_crtc *crtc,
 877                                 const struct vlv_wm_values *wm)
 878 {
 879         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 880         enum pipe pipe = crtc->pipe;
 881
 882         I915_WRITE(VLV_DDL(pipe),
 883                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 884                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 885                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 886                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 887
 888         I915_WRITE(DSPFW1,
 889                    FW_WM(wm->sr.plane, SR) |
 890                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 891                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 892                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 893         I915_WRITE(DSPFW2,
 894                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 895                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 896                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 897         I915_WRITE(DSPFW3,
 898                    FW_WM(wm->sr.cursor, CURSOR_SR));
 899
 900         if (IS_CHERRYVIEW(dev_priv)) {
 901                 I915_WRITE(DSPFW7_CHV,
 902                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 903                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 904                 I915_WRITE(DSPFW8_CHV,
 905                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 906                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 907                 I915_WRITE(DSPFW9_CHV,
 908                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 909                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 910                 I915_WRITE(DSPHOWM,
 911                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 912                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 913                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 914                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 915                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 916                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 917                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 918                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 919                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 920                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 921         } else {
 922                 I915_WRITE(DSPFW7,
 923                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 924                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 925                 I915_WRITE(DSPHOWM,
 926                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 927                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 928                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 929                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 930                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 931                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 932                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 933         }
 934
 935         /* zero (unused) WM1 watermarks */
 936         I915_WRITE(DSPFW4, 0);
 937         I915_WRITE(DSPFW5, 0);
 938         I915_WRITE(DSPFW6, 0);
 939         I915_WRITE(DSPHOWM1, 0);
 940
 941         POSTING_READ(DSPFW1);
 942 }
 943
 944 #undef FW_WM_VLV
 945
 946 enum vlv_wm_level {
 947         VLV_WM_LEVEL_PM2,
 948         VLV_WM_LEVEL_PM5,
 949         VLV_WM_LEVEL_DDR_DVFS,
 950 };
 951
 952 /* latency must be in 0.1us units. */
 953 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 954                                    unsigned int pipe_htotal,
 955                                    unsigned int horiz_pixels,
 956                                    unsigned int bytes_per_pixel,
 957                                    unsigned int latency)
 958 {
 959         unsigned int ret;
 960
 961         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 962         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 963         ret = DIV_ROUND_UP(ret, 64);
 964
 965         return ret;
 966 }
 967
 968 static void vlv_setup_wm_latency(struct drm_device *dev)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971
 972         /* all latencies in usec */
 973         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 974
 975         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 976
 977         if (IS_CHERRYVIEW(dev_priv)) {
 978                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 979                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 980
 981                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 982         }
 983 }
 984
 985 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 986                                      struct intel_crtc *crtc,
 987                                      const struct intel_plane_state *state,
 988                                      int level)
 989 {
 990         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 991         int clock, htotal, pixel_size, width, wm;
 992
 993         if (dev_priv->wm.pri_latency[level] == 0)
 994                 return USHRT_MAX;
 995
 996         if (!state->visible)
 997                 return 0;
 998
 999         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1000         clock = crtc->config->base.adjusted_mode.crtc_clock;
1001         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1002         width = crtc->config->pipe_src_w;
1003         if (WARN_ON(htotal == 0))
1004                 htotal = 1;
1005
1006         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007                 /*
1008                  * FIXME the formula gives values that are
1009                  * too big for the cursor FIFO, and hence we
1010                  * would never be able to use cursors. For
1011                  * now just hardcode the watermark.
1012                  */
1013                 wm = 63;
1014         } else {
1015                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1016                                     dev_priv->wm.pri_latency[level] * 10);
1017         }
1018
1019         return min_t(int, wm, USHRT_MAX);
1020 }
1021
1022 static void vlv_compute_fifo(struct intel_crtc *crtc)
1023 {
1024         struct drm_device *dev = crtc->base.dev;
1025         struct vlv_wm_state *wm_state = &crtc->wm_state;
1026         struct intel_plane *plane;
1027         unsigned int total_rate = 0;
1028         const int fifo_size = 512 - 1;
1029         int fifo_extra, fifo_left = fifo_size;
1030
1031         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1032                 struct intel_plane_state *state =
1033                         to_intel_plane_state(plane->base.state);
1034
1035                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036                         continue;
1037
1038                 if (state->visible) {
1039                         wm_state->num_active_planes++;
1040                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041                 }
1042         }
1043
1044         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045                 struct intel_plane_state *state =
1046                         to_intel_plane_state(plane->base.state);
1047                 unsigned int rate;
1048
1049                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1050                         plane->wm.fifo_size = 63;
1051                         continue;
1052                 }
1053
1054                 if (!state->visible) {
1055                         plane->wm.fifo_size = 0;
1056                         continue;
1057                 }
1058
1059                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1060                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1061                 fifo_left -= plane->wm.fifo_size;
1062         }
1063
1064         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1065
1066         /* spread the remainder evenly */
1067         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1068                 int plane_extra;
1069
1070                 if (fifo_left == 0)
1071                         break;
1072
1073                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1074                         continue;
1075
1076                 /* give it all to the first plane if none are active */
1077                 if (plane->wm.fifo_size == 0 &&
1078                     wm_state->num_active_planes)
1079                         continue;
1080
1081                 plane_extra = min(fifo_extra, fifo_left);
1082                 plane->wm.fifo_size += plane_extra;
1083                 fifo_left -= plane_extra;
1084         }
1085
1086         WARN_ON(fifo_left != 0);
1087 }
1088
1089 static void vlv_invert_wms(struct intel_crtc *crtc)
1090 {
1091         struct vlv_wm_state *wm_state = &crtc->wm_state;
1092         int level;
1093
1094         for (level = 0; level < wm_state->num_levels; level++) {
1095                 struct drm_device *dev = crtc->base.dev;
1096                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097                 struct intel_plane *plane;
1098
1099                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1100                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1101
1102                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103                         switch (plane->base.type) {
1104                                 int sprite;
1105                         case DRM_PLANE_TYPE_CURSOR:
1106                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1107                                         wm_state->wm[level].cursor;
1108                                 break;
1109                         case DRM_PLANE_TYPE_PRIMARY:
1110                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1111                                         wm_state->wm[level].primary;
1112                                 break;
1113                         case DRM_PLANE_TYPE_OVERLAY:
1114                                 sprite = plane->plane;
1115                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1116                                         wm_state->wm[level].sprite[sprite];
1117                                 break;
1118                         }
1119                 }
1120         }
1121 }
1122
1123 static void vlv_compute_wm(struct intel_crtc *crtc)
1124 {
1125         struct drm_device *dev = crtc->base.dev;
1126         struct vlv_wm_state *wm_state = &crtc->wm_state;
1127         struct intel_plane *plane;
1128         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1129         int level;
1130
1131         memset(wm_state, 0, sizeof(*wm_state));
1132
1133         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1134         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1135
1136         wm_state->num_active_planes = 0;
1137
1138         vlv_compute_fifo(crtc);
1139
1140         if (wm_state->num_active_planes != 1)
1141                 wm_state->cxsr = false;
1142
1143         if (wm_state->cxsr) {
1144                 for (level = 0; level < wm_state->num_levels; level++) {
1145                         wm_state->sr[level].plane = sr_fifo_size;
1146                         wm_state->sr[level].cursor = 63;
1147                 }
1148         }
1149
1150         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1151                 struct intel_plane_state *state =
1152                         to_intel_plane_state(plane->base.state);
1153
1154                 if (!state->visible)
1155                         continue;
1156
1157                 /* normal watermarks */
1158                 for (level = 0; level < wm_state->num_levels; level++) {
1159                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1160                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1161
1162                         /* hack */
1163                         if (WARN_ON(level == 0 && wm > max_wm))
1164                                 wm = max_wm;
1165
1166                         if (wm > plane->wm.fifo_size)
1167                                 break;
1168
1169                         switch (plane->base.type) {
1170                                 int sprite;
1171                         case DRM_PLANE_TYPE_CURSOR:
1172                                 wm_state->wm[level].cursor = wm;
1173                                 break;
1174                         case DRM_PLANE_TYPE_PRIMARY:
1175                                 wm_state->wm[level].primary = wm;
1176                                 break;
1177                         case DRM_PLANE_TYPE_OVERLAY:
1178                                 sprite = plane->plane;
1179                                 wm_state->wm[level].sprite[sprite] = wm;
1180                                 break;
1181                         }
1182                 }
1183
1184                 wm_state->num_levels = level;
1185
1186                 if (!wm_state->cxsr)
1187                         continue;
1188
1189                 /* maxfifo watermarks */
1190                 switch (plane->base.type) {
1191                         int sprite, level;
1192                 case DRM_PLANE_TYPE_CURSOR:
1193                         for (level = 0; level < wm_state->num_levels; level++)
1194                                 wm_state->sr[level].cursor =
1195                                         wm_state->sr[level].cursor;
1196                         break;
1197                 case DRM_PLANE_TYPE_PRIMARY:
1198                         for (level = 0; level < wm_state->num_levels; level++)
1199                                 wm_state->sr[level].plane =
1200                                         min(wm_state->sr[level].plane,
1201                                             wm_state->wm[level].primary);
1202                         break;
1203                 case DRM_PLANE_TYPE_OVERLAY:
1204                         sprite = plane->plane;
1205                         for (level = 0; level < wm_state->num_levels; level++)
1206                                 wm_state->sr[level].plane =
1207                                         min(wm_state->sr[level].plane,
1208                                             wm_state->wm[level].sprite[sprite]);
1209                         break;
1210                 }
1211         }
1212
1213         /* clear any (partially) filled invalid levels */
1214         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1215                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1216                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1217         }
1218
1219         vlv_invert_wms(crtc);
1220 }
1221
1222 #define VLV_FIFO(plane, value) \
1223         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1224
1225 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1226 {
1227         struct drm_device *dev = crtc->base.dev;
1228         struct drm_i915_private *dev_priv = to_i915(dev);
1229         struct intel_plane *plane;
1230         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1231
1232         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1233                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1234                         WARN_ON(plane->wm.fifo_size != 63);
1235                         continue;
1236                 }
1237
1238                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1239                         sprite0_start = plane->wm.fifo_size;
1240                 else if (plane->plane == 0)
1241                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1242                 else
1243                         fifo_size = sprite1_start + plane->wm.fifo_size;
1244         }
1245
1246         WARN_ON(fifo_size != 512 - 1);
1247
1248         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1249                       pipe_name(crtc->pipe), sprite0_start,
1250                       sprite1_start, fifo_size);
1251
1252         switch (crtc->pipe) {
1253                 uint32_t dsparb, dsparb2, dsparb3;
1254         case PIPE_A:
1255                 dsparb = I915_READ(DSPARB);
1256                 dsparb2 = I915_READ(DSPARB2);
1257
1258                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1259                             VLV_FIFO(SPRITEB, 0xff));
1260                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1261                            VLV_FIFO(SPRITEB, sprite1_start));
1262
1263                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1264                              VLV_FIFO(SPRITEB_HI, 0x1));
1265                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1266                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1267
1268                 I915_WRITE(DSPARB, dsparb);
1269                 I915_WRITE(DSPARB2, dsparb2);
1270                 break;
1271         case PIPE_B:
1272                 dsparb = I915_READ(DSPARB);
1273                 dsparb2 = I915_READ(DSPARB2);
1274
1275                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1276                             VLV_FIFO(SPRITED, 0xff));
1277                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1278                            VLV_FIFO(SPRITED, sprite1_start));
1279
1280                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1281                              VLV_FIFO(SPRITED_HI, 0xff));
1282                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1283                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1284
1285                 I915_WRITE(DSPARB, dsparb);
1286                 I915_WRITE(DSPARB2, dsparb2);
1287                 break;
1288         case PIPE_C:
1289                 dsparb3 = I915_READ(DSPARB3);
1290                 dsparb2 = I915_READ(DSPARB2);
1291
1292                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1293                              VLV_FIFO(SPRITEF, 0xff));
1294                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1295                             VLV_FIFO(SPRITEF, sprite1_start));
1296
1297                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1298                              VLV_FIFO(SPRITEF_HI, 0xff));
1299                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1300                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1301
1302                 I915_WRITE(DSPARB3, dsparb3);
1303                 I915_WRITE(DSPARB2, dsparb2);
1304                 break;
1305         default:
1306                 break;
1307         }
1308 }
1309
1310 #undef VLV_FIFO
1311
1312 static void vlv_merge_wm(struct drm_device *dev,
1313                          struct vlv_wm_values *wm)
1314 {
1315         struct intel_crtc *crtc;
1316         int num_active_crtcs = 0;
1317
1318         wm->level = to_i915(dev)->wm.max_level;
1319         wm->cxsr = true;
1320
1321         for_each_intel_crtc(dev, crtc) {
1322                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1323
1324                 if (!crtc->active)
1325                         continue;
1326
1327                 if (!wm_state->cxsr)
1328                         wm->cxsr = false;
1329
1330                 num_active_crtcs++;
1331                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1332         }
1333
1334         if (num_active_crtcs != 1)
1335                 wm->cxsr = false;
1336
1337         if (num_active_crtcs > 1)
1338                 wm->level = VLV_WM_LEVEL_PM2;
1339
1340         for_each_intel_crtc(dev, crtc) {
1341                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1342                 enum pipe pipe = crtc->pipe;
1343
1344                 if (!crtc->active)
1345                         continue;
1346
1347                 wm->pipe[pipe] = wm_state->wm[wm->level];
1348                 if (wm->cxsr)
1349                         wm->sr = wm_state->sr[wm->level];
1350
1351                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1352                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1353                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1354                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1355         }
1356 }
1357
1358 static void vlv_update_wm(struct drm_crtc *crtc)
1359 {
1360         struct drm_device *dev = crtc->dev;
1361         struct drm_i915_private *dev_priv = dev->dev_private;
1362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1363         enum pipe pipe = intel_crtc->pipe;
1364         struct vlv_wm_values wm = {};
1365
1366         vlv_compute_wm(intel_crtc);
1367         vlv_merge_wm(dev, &wm);
1368
1369         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1370                 /* FIXME should be part of crtc atomic commit */
1371                 vlv_pipe_set_fifo_size(intel_crtc);
1372                 return;
1373         }
1374
1375         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1376             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1377                 chv_set_memory_dvfs(dev_priv, false);
1378
1379         if (wm.level < VLV_WM_LEVEL_PM5 &&
1380             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1381                 chv_set_memory_pm5(dev_priv, false);
1382
1383         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1384                 intel_set_memory_cxsr(dev_priv, false);
1385
1386         /* FIXME should be part of crtc atomic commit */
1387         vlv_pipe_set_fifo_size(intel_crtc);
1388
1389         vlv_write_wm_values(intel_crtc, &wm);
1390
1391         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1393                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1394                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1395                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1396
1397         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1398                 intel_set_memory_cxsr(dev_priv, true);
1399
1400         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1401             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1402                 chv_set_memory_pm5(dev_priv, true);
1403
1404         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1405             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1406                 chv_set_memory_dvfs(dev_priv, true);
1407
1408         dev_priv->wm.vlv = wm;
1409 }
1410
1411 #define single_plane_enabled(mask) is_power_of_2(mask)
1412
1413 static void g4x_update_wm(struct drm_crtc *crtc)
1414 {
1415         struct drm_device *dev = crtc->dev;
1416         static const int sr_latency_ns = 12000;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1419         int plane_sr, cursor_sr;
1420         unsigned int enabled = 0;
1421         bool cxsr_enabled;
1422
1423         if (g4x_compute_wm0(dev, PIPE_A,
1424                             &g4x_wm_info, pessimal_latency_ns,
1425                             &g4x_cursor_wm_info, pessimal_latency_ns,
1426                             &planea_wm, &cursora_wm))
1427                 enabled |= 1 << PIPE_A;
1428
1429         if (g4x_compute_wm0(dev, PIPE_B,
1430                             &g4x_wm_info, pessimal_latency_ns,
1431                             &g4x_cursor_wm_info, pessimal_latency_ns,
1432                             &planeb_wm, &cursorb_wm))
1433                 enabled |= 1 << PIPE_B;
1434
1435         if (single_plane_enabled(enabled) &&
1436             g4x_compute_srwm(dev, ffs(enabled) - 1,
1437                              sr_latency_ns,
1438                              &g4x_wm_info,
1439                              &g4x_cursor_wm_info,
1440                              &plane_sr, &cursor_sr)) {
1441                 cxsr_enabled = true;
1442         } else {
1443                 cxsr_enabled = false;
1444                 intel_set_memory_cxsr(dev_priv, false);
1445                 plane_sr = cursor_sr = 0;
1446         }
1447
1448         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1449                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1450                       planea_wm, cursora_wm,
1451                       planeb_wm, cursorb_wm,
1452                       plane_sr, cursor_sr);
1453
1454         I915_WRITE(DSPFW1,
1455                    FW_WM(plane_sr, SR) |
1456                    FW_WM(cursorb_wm, CURSORB) |
1457                    FW_WM(planeb_wm, PLANEB) |
1458                    FW_WM(planea_wm, PLANEA));
1459         I915_WRITE(DSPFW2,
1460                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1461                    FW_WM(cursora_wm, CURSORA));
1462         /* HPLL off in SR has some issues on G4x... disable it */
1463         I915_WRITE(DSPFW3,
1464                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1465                    FW_WM(cursor_sr, CURSOR_SR));
1466
1467         if (cxsr_enabled)
1468                 intel_set_memory_cxsr(dev_priv, true);
1469 }
1470
1471 static void i965_update_wm(struct drm_crtc *unused_crtc)
1472 {
1473         struct drm_device *dev = unused_crtc->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         struct drm_crtc *crtc;
1476         int srwm = 1;
1477         int cursor_sr = 16;
1478         bool cxsr_enabled;
1479
1480         /* Calc sr entries for one plane configs */
1481         crtc = single_enabled_crtc(dev);
1482         if (crtc) {
1483                 /* self-refresh has much higher latency */
1484                 static const int sr_latency_ns = 12000;
1485                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1486                 int clock = adjusted_mode->crtc_clock;
1487                 int htotal = adjusted_mode->crtc_htotal;
1488                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1489                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1490                 unsigned long line_time_us;
1491                 int entries;
1492
1493                 line_time_us = max(htotal * 1000 / clock, 1);
1494
1495                 /* Use ns/us then divide to preserve precision */
1496                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497                         pixel_size * hdisplay;
1498                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499                 srwm = I965_FIFO_SIZE - entries;
1500                 if (srwm < 0)
1501                         srwm = 1;
1502                 srwm &= 0x1ff;
1503                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504                               entries, srwm);
1505
1506                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1507                         pixel_size * crtc->cursor->state->crtc_w;
1508                 entries = DIV_ROUND_UP(entries,
1509                                           i965_cursor_wm_info.cacheline_size);
1510                 cursor_sr = i965_cursor_wm_info.fifo_size -
1511                         (entries + i965_cursor_wm_info.guard_size);
1512
1513                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514                         cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517                               "cursor %d\n", srwm, cursor_sr);
1518
1519                 cxsr_enabled = true;
1520         } else {
1521                 cxsr_enabled = false;
1522                 /* Turn off self refresh if both pipes are enabled */
1523                 intel_set_memory_cxsr(dev_priv, false);
1524         }
1525
1526         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527                       srwm);
1528
1529         /* 965 has limitations... */
1530         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531                    FW_WM(8, CURSORB) |
1532                    FW_WM(8, PLANEB) |
1533                    FW_WM(8, PLANEA));
1534         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535                    FW_WM(8, PLANEC_OLD));
1536         /* update cursor SR watermark */
1537         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1538
1539         if (cxsr_enabled)
1540                 intel_set_memory_cxsr(dev_priv, true);
1541 }
1542
1543 #undef FW_WM
1544
1545 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1546 {
1547         struct drm_device *dev = unused_crtc->dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         const struct intel_watermark_params *wm_info;
1550         uint32_t fwater_lo;
1551         uint32_t fwater_hi;
1552         int cwm, srwm = 1;
1553         int fifo_size;
1554         int planea_wm, planeb_wm;
1555         struct drm_crtc *crtc, *enabled = NULL;
1556
1557         if (IS_I945GM(dev))
1558                 wm_info = &i945_wm_info;
1559         else if (!IS_GEN2(dev))
1560                 wm_info = &i915_wm_info;
1561         else
1562                 wm_info = &i830_a_wm_info;
1563
1564         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565         crtc = intel_get_crtc_for_plane(dev, 0);
1566         if (intel_crtc_active(crtc)) {
1567                 const struct drm_display_mode *adjusted_mode;
1568                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1569                 if (IS_GEN2(dev))
1570                         cpp = 4;
1571
1572                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1573                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1574                                                wm_info, fifo_size, cpp,
1575                                                pessimal_latency_ns);
1576                 enabled = crtc;
1577         } else {
1578                 planea_wm = fifo_size - wm_info->guard_size;
1579                 if (planea_wm > (long)wm_info->max_wm)
1580                         planea_wm = wm_info->max_wm;
1581         }
1582
1583         if (IS_GEN2(dev))
1584                 wm_info = &i830_bc_wm_info;
1585
1586         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587         crtc = intel_get_crtc_for_plane(dev, 1);
1588         if (intel_crtc_active(crtc)) {
1589                 const struct drm_display_mode *adjusted_mode;
1590                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1591                 if (IS_GEN2(dev))
1592                         cpp = 4;
1593
1594                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1595                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1596                                                wm_info, fifo_size, cpp,
1597                                                pessimal_latency_ns);
1598                 if (enabled == NULL)
1599                         enabled = crtc;
1600                 else
1601                         enabled = NULL;
1602         } else {
1603                 planeb_wm = fifo_size - wm_info->guard_size;
1604                 if (planeb_wm > (long)wm_info->max_wm)
1605                         planeb_wm = wm_info->max_wm;
1606         }
1607
1608         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
1610         if (IS_I915GM(dev) && enabled) {
1611                 struct drm_i915_gem_object *obj;
1612
1613                 obj = intel_fb_obj(enabled->primary->state->fb);
1614
1615                 /* self-refresh seems busted with untiled */
1616                 if (obj->tiling_mode == I915_TILING_NONE)
1617                         enabled = NULL;
1618         }
1619
1620         /*
1621          * Overlay gets an aggressive default since video jitter is bad.
1622          */
1623         cwm = 2;
1624
1625         /* Play safe and disable self-refresh before adjusting watermarks. */
1626         intel_set_memory_cxsr(dev_priv, false);
1627
1628         /* Calc sr entries for one plane configs */
1629         if (HAS_FW_BLC(dev) && enabled) {
1630                 /* self-refresh has much higher latency */
1631                 static const int sr_latency_ns = 6000;
1632                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1633                 int clock = adjusted_mode->crtc_clock;
1634                 int htotal = adjusted_mode->crtc_htotal;
1635                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1636                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1637                 unsigned long line_time_us;
1638                 int entries;
1639
1640                 line_time_us = max(htotal * 1000 / clock, 1);
1641
1642                 /* Use ns/us then divide to preserve precision */
1643                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644                         pixel_size * hdisplay;
1645                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647                 srwm = wm_info->fifo_size - entries;
1648                 if (srwm < 0)
1649                         srwm = 1;
1650
1651                 if (IS_I945G(dev) || IS_I945GM(dev))
1652                         I915_WRITE(FW_BLC_SELF,
1653                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654                 else if (IS_I915GM(dev))
1655                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656         }
1657
1658         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659                       planea_wm, planeb_wm, cwm, srwm);
1660
1661         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662         fwater_hi = (cwm & 0x1f);
1663
1664         /* Set request length to 8 cachelines per fetch */
1665         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666         fwater_hi = fwater_hi | (1 << 8);
1667
1668         I915_WRITE(FW_BLC, fwater_lo);
1669         I915_WRITE(FW_BLC2, fwater_hi);
1670
1671         if (enabled)
1672                 intel_set_memory_cxsr(dev_priv, true);
1673 }
1674
1675 static void i845_update_wm(struct drm_crtc *unused_crtc)
1676 {
1677         struct drm_device *dev = unused_crtc->dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         struct drm_crtc *crtc;
1680         const struct drm_display_mode *adjusted_mode;
1681         uint32_t fwater_lo;
1682         int planea_wm;
1683
1684         crtc = single_enabled_crtc(dev);
1685         if (crtc == NULL)
1686                 return;
1687
1688         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1689         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1690                                        &i845_wm_info,
1691                                        dev_priv->display.get_fifo_size(dev, 0),
1692                                        4, pessimal_latency_ns);
1693         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1694         fwater_lo |= (3<<8) | planea_wm;
1695
1696         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1697
1698         I915_WRITE(FW_BLC, fwater_lo);
1699 }
1700
1701 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1702 {
1703         uint32_t pixel_rate;
1704
1705         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1706
1707         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1708          * adjust the pixel_rate here. */
1709
1710         if (pipe_config->pch_pfit.enabled) {
1711                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1712                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1713
1714                 pipe_w = pipe_config->pipe_src_w;
1715                 pipe_h = pipe_config->pipe_src_h;
1716
1717                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1718                 pfit_h = pfit_size & 0xFFFF;
1719                 if (pipe_w < pfit_w)
1720                         pipe_w = pfit_w;
1721                 if (pipe_h < pfit_h)
1722                         pipe_h = pfit_h;
1723
1724                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1725                                      pfit_w * pfit_h);
1726         }
1727
1728         return pixel_rate;
1729 }
1730
1731 /* latency must be in 0.1us units. */
1732 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1733                                uint32_t latency)
1734 {
1735         uint64_t ret;
1736
1737         if (WARN(latency == 0, "Latency value missing\n"))
1738                 return UINT_MAX;
1739
1740         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1741         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1742
1743         return ret;
1744 }
1745
1746 /* latency must be in 0.1us units. */
1747 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1748                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1749                                uint32_t latency)
1750 {
1751         uint32_t ret;
1752
1753         if (WARN(latency == 0, "Latency value missing\n"))
1754                 return UINT_MAX;
1755
1756         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1757         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1758         ret = DIV_ROUND_UP(ret, 64) + 2;
1759         return ret;
1760 }
1761
1762 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1763                            uint8_t bytes_per_pixel)
1764 {
1765         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1766 }
1767
1768 struct ilk_wm_maximums {
1769         uint16_t pri;
1770         uint16_t spr;
1771         uint16_t cur;
1772         uint16_t fbc;
1773 };
1774
1775 /*
1776  * For both WM_PIPE and WM_LP.
1777  * mem_value must be in 0.1us units.
1778  */
1779 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1780                                    const struct intel_plane_state *pstate,
1781                                    uint32_t mem_value,
1782                                    bool is_lp)
1783 {
1784         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1785         uint32_t method1, method2;
1786
1787         if (!cstate->base.active || !pstate->visible)
1788                 return 0;
1789
1790         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1791
1792         if (!is_lp)
1793                 return method1;
1794
1795         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1796                                  cstate->base.adjusted_mode.crtc_htotal,
1797                                  drm_rect_width(&pstate->dst),
1798                                  bpp,
1799                                  mem_value);
1800
1801         return min(method1, method2);
1802 }
1803
1804 /*
1805  * For both WM_PIPE and WM_LP.
1806  * mem_value must be in 0.1us units.
1807  */
1808 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1809                                    const struct intel_plane_state *pstate,
1810                                    uint32_t mem_value)
1811 {
1812         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1813         uint32_t method1, method2;
1814
1815         if (!cstate->base.active || !pstate->visible)
1816                 return 0;
1817
1818         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1819         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1820                                  cstate->base.adjusted_mode.crtc_htotal,
1821                                  drm_rect_width(&pstate->dst),
1822                                  bpp,
1823                                  mem_value);
1824         return min(method1, method2);
1825 }
1826
1827 /*
1828  * For both WM_PIPE and WM_LP.
1829  * mem_value must be in 0.1us units.
1830  */
1831 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1832                                    const struct intel_plane_state *pstate,
1833                                    uint32_t mem_value)
1834 {
1835         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1836
1837         if (!cstate->base.active || !pstate->visible)
1838                 return 0;
1839
1840         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1841                               cstate->base.adjusted_mode.crtc_htotal,
1842                               drm_rect_width(&pstate->dst),
1843                               bpp,
1844                               mem_value);
1845 }
1846
1847 /* Only for WM_LP. */
1848 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1849                                    const struct intel_plane_state *pstate,
1850                                    uint32_t pri_val)
1851 {
1852         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1853
1854         if (!cstate->base.active || !pstate->visible)
1855                 return 0;
1856
1857         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1858 }
1859
1860 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1861 {
1862         if (INTEL_INFO(dev)->gen >= 8)
1863                 return 3072;
1864         else if (INTEL_INFO(dev)->gen >= 7)
1865                 return 768;
1866         else
1867                 return 512;
1868 }
1869
1870 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1871                                          int level, bool is_sprite)
1872 {
1873         if (INTEL_INFO(dev)->gen >= 8)
1874                 /* BDW primary/sprite plane watermarks */
1875                 return level == 0 ? 255 : 2047;
1876         else if (INTEL_INFO(dev)->gen >= 7)
1877                 /* IVB/HSW primary/sprite plane watermarks */
1878                 return level == 0 ? 127 : 1023;
1879         else if (!is_sprite)
1880                 /* ILK/SNB primary plane watermarks */
1881                 return level == 0 ? 127 : 511;
1882         else
1883                 /* ILK/SNB sprite plane watermarks */
1884                 return level == 0 ? 63 : 255;
1885 }
1886
1887 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1888                                           int level)
1889 {
1890         if (INTEL_INFO(dev)->gen >= 7)
1891                 return level == 0 ? 63 : 255;
1892         else
1893                 return level == 0 ? 31 : 63;
1894 }
1895
1896 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1897 {
1898         if (INTEL_INFO(dev)->gen >= 8)
1899                 return 31;
1900         else
1901                 return 15;
1902 }
1903
1904 /* Calculate the maximum primary/sprite plane watermark */
1905 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1906                                      int level,
1907                                      const struct intel_wm_config *config,
1908                                      enum intel_ddb_partitioning ddb_partitioning,
1909                                      bool is_sprite)
1910 {
1911         unsigned int fifo_size = ilk_display_fifo_size(dev);
1912
1913         /* if sprites aren't enabled, sprites get nothing */
1914         if (is_sprite && !config->sprites_enabled)
1915                 return 0;
1916
1917         /* HSW allows LP1+ watermarks even with multiple pipes */
1918         if (level == 0 || config->num_pipes_active > 1) {
1919                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1920
1921                 /*
1922                  * For some reason the non self refresh
1923                  * FIFO size is only half of the self
1924                  * refresh FIFO size on ILK/SNB.
1925                  */
1926                 if (INTEL_INFO(dev)->gen <= 6)
1927                         fifo_size /= 2;
1928         }
1929
1930         if (config->sprites_enabled) {
1931                 /* level 0 is always calculated with 1:1 split */
1932                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1933                         if (is_sprite)
1934                                 fifo_size *= 5;
1935                         fifo_size /= 6;
1936                 } else {
1937                         fifo_size /= 2;
1938                 }
1939         }
1940
1941         /* clamp to max that the registers can hold */
1942         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1943 }
1944
1945 /* Calculate the maximum cursor plane watermark */
1946 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1947                                       int level,
1948                                       const struct intel_wm_config *config)
1949 {
1950         /* HSW LP1+ watermarks w/ multiple pipes */
1951         if (level > 0 && config->num_pipes_active > 1)
1952                 return 64;
1953
1954         /* otherwise just report max that registers can hold */
1955         return ilk_cursor_wm_reg_max(dev, level);
1956 }
1957
1958 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1959                                     int level,
1960                                     const struct intel_wm_config *config,
1961                                     enum intel_ddb_partitioning ddb_partitioning,
1962                                     struct ilk_wm_maximums *max)
1963 {
1964         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1965         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1966         max->cur = ilk_cursor_wm_max(dev, level, config);
1967         max->fbc = ilk_fbc_wm_reg_max(dev);
1968 }
1969
1970 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1971                                         int level,
1972                                         struct ilk_wm_maximums *max)
1973 {
1974         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1975         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1976         max->cur = ilk_cursor_wm_reg_max(dev, level);
1977         max->fbc = ilk_fbc_wm_reg_max(dev);
1978 }
1979
1980 static bool ilk_validate_wm_level(int level,
1981                                   const struct ilk_wm_maximums *max,
1982                                   struct intel_wm_level *result)
1983 {
1984         bool ret;
1985
1986         /* already determined to be invalid? */
1987         if (!result->enable)
1988                 return false;
1989
1990         result->enable = result->pri_val <= max->pri &&
1991                          result->spr_val <= max->spr &&
1992                          result->cur_val <= max->cur;
1993
1994         ret = result->enable;
1995
1996         /*
1997          * HACK until we can pre-compute everything,
1998          * and thus fail gracefully if LP0 watermarks
1999          * are exceeded...
2000          */
2001         if (level == 0 && !result->enable) {
2002                 if (result->pri_val > max->pri)
2003                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2004                                       level, result->pri_val, max->pri);
2005                 if (result->spr_val > max->spr)
2006                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2007                                       level, result->spr_val, max->spr);
2008                 if (result->cur_val > max->cur)
2009                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2010                                       level, result->cur_val, max->cur);
2011
2012                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2013                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2014                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2015                 result->enable = true;
2016         }
2017
2018         return ret;
2019 }
2020
2021 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2022                                  const struct intel_crtc *intel_crtc,
2023                                  int level,
2024                                  struct intel_crtc_state *cstate,
2025                                  struct intel_plane_state *pristate,
2026                                  struct intel_plane_state *sprstate,
2027                                  struct intel_plane_state *curstate,
2028                                  struct intel_wm_level *result)
2029 {
2030         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2031         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2032         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2033
2034         /* WM1+ latency values stored in 0.5us units */
2035         if (level > 0) {
2036                 pri_latency *= 5;
2037                 spr_latency *= 5;
2038                 cur_latency *= 5;
2039         }
2040
2041         result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2042                                              pri_latency, level);
2043         result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044         result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2045         result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2046         result->enable = true;
2047 }
2048
2049 static uint32_t
2050 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2051 {
2052         struct drm_i915_private *dev_priv = dev->dev_private;
2053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2054         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2055         u32 linetime, ips_linetime;
2056
2057         if (!intel_crtc->active)
2058                 return 0;
2059
2060         /* The WM are computed with base on how long it takes to fill a single
2061          * row at the given clock rate, multiplied by 8.
2062          * */
2063         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2064                                      adjusted_mode->crtc_clock);
2065         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2066                                          dev_priv->cdclk_freq);
2067
2068         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2069                PIPE_WM_LINETIME_TIME(linetime);
2070 }
2071
2072 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2073 {
2074         struct drm_i915_private *dev_priv = dev->dev_private;
2075
2076         if (IS_GEN9(dev)) {
2077                 uint32_t val;
2078                 int ret, i;
2079                 int level, max_level = ilk_wm_max_level(dev);
2080
2081                 /* read the first set of memory latencies[0:3] */
2082                 val = 0; /* data0 to be programmed to 0 for first set */
2083                 mutex_lock(&dev_priv->rps.hw_lock);
2084                 ret = sandybridge_pcode_read(dev_priv,
2085                                              GEN9_PCODE_READ_MEM_LATENCY,
2086                                              &val);
2087                 mutex_unlock(&dev_priv->rps.hw_lock);
2088
2089                 if (ret) {
2090                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2091                         return;
2092                 }
2093
2094                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2095                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2096                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2097                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2098                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2099                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2100                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2101
2102                 /* read the second set of memory latencies[4:7] */
2103                 val = 1; /* data0 to be programmed to 1 for second set */
2104                 mutex_lock(&dev_priv->rps.hw_lock);
2105                 ret = sandybridge_pcode_read(dev_priv,
2106                                              GEN9_PCODE_READ_MEM_LATENCY,
2107                                              &val);
2108                 mutex_unlock(&dev_priv->rps.hw_lock);
2109                 if (ret) {
2110                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2111                         return;
2112                 }
2113
2114                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2115                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2116                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2117                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2118                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2119                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2120                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2121
2122                 /*
2123                  * WaWmMemoryReadLatency:skl
2124                  *
2125                  * punit doesn't take into account the read latency so we need
2126                  * to add 2us to the various latency levels we retrieve from
2127                  * the punit.
2128                  *   - W0 is a bit special in that it's the only level that
2129                  *   can't be disabled if we want to have display working, so
2130                  *   we always add 2us there.
2131                  *   - For levels >=1, punit returns 0us latency when they are
2132                  *   disabled, so we respect that and don't add 2us then
2133                  *
2134                  * Additionally, if a level n (n > 1) has a 0us latency, all
2135                  * levels m (m >= n) need to be disabled. We make sure to
2136                  * sanitize the values out of the punit to satisfy this
2137                  * requirement.
2138                  */
2139                 wm[0] += 2;
2140                 for (level = 1; level <= max_level; level++)
2141                         if (wm[level] != 0)
2142                                 wm[level] += 2;
2143                         else {
2144                                 for (i = level + 1; i <= max_level; i++)
2145                                         wm[i] = 0;
2146
2147                                 break;
2148                         }
2149         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2150                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2151
2152                 wm[0] = (sskpd >> 56) & 0xFF;
2153                 if (wm[0] == 0)
2154                         wm[0] = sskpd & 0xF;
2155                 wm[1] = (sskpd >> 4) & 0xFF;
2156                 wm[2] = (sskpd >> 12) & 0xFF;
2157                 wm[3] = (sskpd >> 20) & 0x1FF;
2158                 wm[4] = (sskpd >> 32) & 0x1FF;
2159         } else if (INTEL_INFO(dev)->gen >= 6) {
2160                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2161
2162                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2163                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2164                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2165                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2166         } else if (INTEL_INFO(dev)->gen >= 5) {
2167                 uint32_t mltr = I915_READ(MLTR_ILK);
2168
2169                 /* ILK primary LP0 latency is 700 ns */
2170                 wm[0] = 7;
2171                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2172                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2173         }
2174 }
2175
2176 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2177 {
2178         /* ILK sprite LP0 latency is 1300 ns */
2179         if (INTEL_INFO(dev)->gen == 5)
2180                 wm[0] = 13;
2181 }
2182
2183 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184 {
2185         /* ILK cursor LP0 latency is 1300 ns */
2186         if (INTEL_INFO(dev)->gen == 5)
2187                 wm[0] = 13;
2188
2189         /* WaDoubleCursorLP3Latency:ivb */
2190         if (IS_IVYBRIDGE(dev))
2191                 wm[3] *= 2;
2192 }
2193
2194 int ilk_wm_max_level(const struct drm_device *dev)
2195 {
2196         /* how many WM levels are we expecting */
2197         if (INTEL_INFO(dev)->gen >= 9)
2198                 return 7;
2199         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2200                 return 4;
2201         else if (INTEL_INFO(dev)->gen >= 6)
2202                 return 3;
2203         else
2204                 return 2;
2205 }
2206
2207 static void intel_print_wm_latency(struct drm_device *dev,
2208                                    const char *name,
2209                                    const uint16_t wm[8])
2210 {
2211         int level, max_level = ilk_wm_max_level(dev);
2212
2213         for (level = 0; level <= max_level; level++) {
2214                 unsigned int latency = wm[level];
2215
2216                 if (latency == 0) {
2217                         DRM_ERROR("%s WM%d latency not provided\n",
2218                                   name, level);
2219                         continue;
2220                 }
2221
2222                 /*
2223                  * - latencies are in us on gen9.
2224                  * - before then, WM1+ latency values are in 0.5us units
2225                  */
2226                 if (IS_GEN9(dev))
2227                         latency *= 10;
2228                 else if (level > 0)
2229                         latency *= 5;
2230
2231                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2232                               name, level, wm[level],
2233                               latency / 10, latency % 10);
2234         }
2235 }
2236
2237 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2238                                     uint16_t wm[5], uint16_t min)
2239 {
2240         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2241
2242         if (wm[0] >= min)
2243                 return false;
2244
2245         wm[0] = max(wm[0], min);
2246         for (level = 1; level <= max_level; level++)
2247                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2248
2249         return true;
2250 }
2251
2252 static void snb_wm_latency_quirk(struct drm_device *dev)
2253 {
2254         struct drm_i915_private *dev_priv = dev->dev_private;
2255         bool changed;
2256
2257         /*
2258          * The BIOS provided WM memory latency values are often
2259          * inadequate for high resolution displays. Adjust them.
2260          */
2261         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2262                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2263                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2264
2265         if (!changed)
2266                 return;
2267
2268         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2269         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2270         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2271         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2272 }
2273
2274 static void ilk_setup_wm_latency(struct drm_device *dev)
2275 {
2276         struct drm_i915_private *dev_priv = dev->dev_private;
2277
2278         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2279
2280         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2281                sizeof(dev_priv->wm.pri_latency));
2282         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2283                sizeof(dev_priv->wm.pri_latency));
2284
2285         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2286         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2287
2288         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2289         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2290         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2291
2292         if (IS_GEN6(dev))
2293                 snb_wm_latency_quirk(dev);
2294 }
2295
2296 static void skl_setup_wm_latency(struct drm_device *dev)
2297 {
2298         struct drm_i915_private *dev_priv = dev->dev_private;
2299
2300         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2301         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2302 }
2303
2304 /* Compute new watermarks for the pipe */
2305 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2306                                struct drm_atomic_state *state)
2307 {
2308         struct intel_pipe_wm *pipe_wm;
2309         struct drm_device *dev = intel_crtc->base.dev;
2310         const struct drm_i915_private *dev_priv = dev->dev_private;
2311         struct intel_crtc_state *cstate = NULL;
2312         struct intel_plane *intel_plane;
2313         struct drm_plane_state *ps;
2314         struct intel_plane_state *pristate = NULL;
2315         struct intel_plane_state *sprstate = NULL;
2316         struct intel_plane_state *curstate = NULL;
2317         int level, max_level = ilk_wm_max_level(dev);
2318         /* LP0 watermark maximums depend on this pipe alone */
2319         struct intel_wm_config config = {
2320                 .num_pipes_active = 1,
2321         };
2322         struct ilk_wm_maximums max;
2323
2324         cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2325         if (IS_ERR(cstate))
2326                 return PTR_ERR(cstate);
2327
2328         pipe_wm = &cstate->wm.optimal.ilk;
2329
2330         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2331                 ps = drm_atomic_get_plane_state(state,
2332                                                 &intel_plane->base);
2333                 if (IS_ERR(ps))
2334                         return PTR_ERR(ps);
2335
2336                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2337                         pristate = to_intel_plane_state(ps);
2338                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2339                         sprstate = to_intel_plane_state(ps);
2340                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2341                         curstate = to_intel_plane_state(ps);
2342         }
2343
2344         config.sprites_enabled = sprstate->visible;
2345         config.sprites_scaled = sprstate->visible &&
2346                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2347                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2348
2349         pipe_wm->pipe_enabled = cstate->base.active;
2350         pipe_wm->sprites_enabled = config.sprites_enabled;
2351         pipe_wm->sprites_scaled = config.sprites_scaled;
2352
2353         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2354         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2355                 max_level = 1;
2356
2357         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2358         if (config.sprites_scaled)
2359                 max_level = 0;
2360
2361         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2362                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
2363
2364         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2365                 pipe_wm->linetime = hsw_compute_linetime_wm(dev,
2366                                                             &intel_crtc->base);
2367
2368         /* LP0 watermarks always use 1/2 DDB partitioning */
2369         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2370
2371         /* At least LP0 must be valid */
2372         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2373                 return -EINVAL;
2374
2375         ilk_compute_wm_reg_maximums(dev, 1, &max);
2376
2377         for (level = 1; level <= max_level; level++) {
2378                 struct intel_wm_level wm = {};
2379
2380                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2381                                      pristate, sprstate, curstate, &wm);
2382
2383                 /*
2384                  * Disable any watermark level that exceeds the
2385                  * register maximums since such watermarks are
2386                  * always invalid.
2387                  */
2388                 if (!ilk_validate_wm_level(level, &max, &wm))
2389                         break;
2390
2391                 pipe_wm->wm[level] = wm;
2392         }
2393
2394         return 0;
2395 }
2396
2397 /*
2398  * Merge the watermarks from all active pipes for a specific level.
2399  */
2400 static void ilk_merge_wm_level(struct drm_device *dev,
2401                                int level,
2402                                struct intel_wm_level *ret_wm)
2403 {
2404         const struct intel_crtc *intel_crtc;
2405
2406         ret_wm->enable = true;
2407
2408         for_each_intel_crtc(dev, intel_crtc) {
2409                 const struct intel_crtc_state *cstate =
2410                         to_intel_crtc_state(intel_crtc->base.state);
2411                 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2412                 const struct intel_wm_level *wm = &active->wm[level];
2413
2414                 if (!active->pipe_enabled)
2415                         continue;
2416
2417                 /*
2418                  * The watermark values may have been used in the past,
2419                  * so we must maintain them in the registers for some
2420                  * time even if the level is now disabled.
2421                  */
2422                 if (!wm->enable)
2423                         ret_wm->enable = false;
2424
2425                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2426                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2427                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2428                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2429         }
2430 }
2431
2432 /*
2433  * Merge all low power watermarks for all active pipes.
2434  */
2435 static void ilk_wm_merge(struct drm_device *dev,
2436                          const struct intel_wm_config *config,
2437                          const struct ilk_wm_maximums *max,
2438                          struct intel_pipe_wm *merged)
2439 {
2440         struct drm_i915_private *dev_priv = dev->dev_private;
2441         int level, max_level = ilk_wm_max_level(dev);
2442         int last_enabled_level = max_level;
2443
2444         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2445         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2446             config->num_pipes_active > 1)
2447                 return;
2448
2449         /* ILK: FBC WM must be disabled always */
2450         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2451
2452         /* merge each WM1+ level */
2453         for (level = 1; level <= max_level; level++) {
2454                 struct intel_wm_level *wm = &merged->wm[level];
2455
2456                 ilk_merge_wm_level(dev, level, wm);
2457
2458                 if (level > last_enabled_level)
2459                         wm->enable = false;
2460                 else if (!ilk_validate_wm_level(level, max, wm))
2461                         /* make sure all following levels get disabled */
2462                         last_enabled_level = level - 1;
2463
2464                 /*
2465                  * The spec says it is preferred to disable
2466                  * FBC WMs instead of disabling a WM level.
2467                  */
2468                 if (wm->fbc_val > max->fbc) {
2469                         if (wm->enable)
2470                                 merged->fbc_wm_enabled = false;
2471                         wm->fbc_val = 0;
2472                 }
2473         }
2474
2475         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2476         /*
2477          * FIXME this is racy. FBC might get enabled later.
2478          * What we should check here is whether FBC can be
2479          * enabled sometime later.
2480          */
2481         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2482             intel_fbc_enabled(dev_priv)) {
2483                 for (level = 2; level <= max_level; level++) {
2484                         struct intel_wm_level *wm = &merged->wm[level];
2485
2486                         wm->enable = false;
2487                 }
2488         }
2489 }
2490
2491 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2492 {
2493         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2494         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2495 }
2496
2497 /* The value we need to program into the WM_LPx latency field */
2498 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2499 {
2500         struct drm_i915_private *dev_priv = dev->dev_private;
2501
2502         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2503                 return 2 * level;
2504         else
2505                 return dev_priv->wm.pri_latency[level];
2506 }
2507
2508 static void ilk_compute_wm_results(struct drm_device *dev,
2509                                    const struct intel_pipe_wm *merged,
2510                                    enum intel_ddb_partitioning partitioning,
2511                                    struct ilk_wm_values *results)
2512 {
2513         struct intel_crtc *intel_crtc;
2514         int level, wm_lp;
2515
2516         results->enable_fbc_wm = merged->fbc_wm_enabled;
2517         results->partitioning = partitioning;
2518
2519         /* LP1+ register values */
2520         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2521                 const struct intel_wm_level *r;
2522
2523                 level = ilk_wm_lp_to_level(wm_lp, merged);
2524
2525                 r = &merged->wm[level];
2526
2527                 /*
2528                  * Maintain the watermark values even if the level is
2529                  * disabled. Doing otherwise could cause underruns.
2530                  */
2531                 results->wm_lp[wm_lp - 1] =
2532                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2533                         (r->pri_val << WM1_LP_SR_SHIFT) |
2534                         r->cur_val;
2535
2536                 if (r->enable)
2537                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2538
2539                 if (INTEL_INFO(dev)->gen >= 8)
2540                         results->wm_lp[wm_lp - 1] |=
2541                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2542                 else
2543                         results->wm_lp[wm_lp - 1] |=
2544                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2545
2546                 /*
2547                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2548                  * level is disabled. Doing otherwise could cause underruns.
2549                  */
2550                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2551                         WARN_ON(wm_lp != 1);
2552                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2553                 } else
2554                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2555         }
2556
2557         /* LP0 register values */
2558         for_each_intel_crtc(dev, intel_crtc) {
2559                 const struct intel_crtc_state *cstate =
2560                         to_intel_crtc_state(intel_crtc->base.state);
2561                 enum pipe pipe = intel_crtc->pipe;
2562                 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2563
2564                 if (WARN_ON(!r->enable))
2565                         continue;
2566
2567                 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2568
2569                 results->wm_pipe[pipe] =
2570                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2571                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2572                         r->cur_val;
2573         }
2574 }
2575
2576 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2577  * case both are at the same level. Prefer r1 in case they're the same. */
2578 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2579                                                   struct intel_pipe_wm *r1,
2580                                                   struct intel_pipe_wm *r2)
2581 {
2582         int level, max_level = ilk_wm_max_level(dev);
2583         int level1 = 0, level2 = 0;
2584
2585         for (level = 1; level <= max_level; level++) {
2586                 if (r1->wm[level].enable)
2587                         level1 = level;
2588                 if (r2->wm[level].enable)
2589                         level2 = level;
2590         }
2591
2592         if (level1 == level2) {
2593                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2594                         return r2;
2595                 else
2596                         return r1;
2597         } else if (level1 > level2) {
2598                 return r1;
2599         } else {
2600                 return r2;
2601         }
2602 }
2603
2604 /* dirty bits used to track which watermarks need changes */
2605 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2606 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2607 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2608 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2609 #define WM_DIRTY_FBC (1 << 24)
2610 #define WM_DIRTY_DDB (1 << 25)
2611
2612 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2613                                          const struct ilk_wm_values *old,
2614                                          const struct ilk_wm_values *new)
2615 {
2616         unsigned int dirty = 0;
2617         enum pipe pipe;
2618         int wm_lp;
2619
2620         for_each_pipe(dev_priv, pipe) {
2621                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2622                         dirty |= WM_DIRTY_LINETIME(pipe);
2623                         /* Must disable LP1+ watermarks too */
2624                         dirty |= WM_DIRTY_LP_ALL;
2625                 }
2626
2627                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2628                         dirty |= WM_DIRTY_PIPE(pipe);
2629                         /* Must disable LP1+ watermarks too */
2630                         dirty |= WM_DIRTY_LP_ALL;
2631                 }
2632         }
2633
2634         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2635                 dirty |= WM_DIRTY_FBC;
2636                 /* Must disable LP1+ watermarks too */
2637                 dirty |= WM_DIRTY_LP_ALL;
2638         }
2639
2640         if (old->partitioning != new->partitioning) {
2641                 dirty |= WM_DIRTY_DDB;
2642                 /* Must disable LP1+ watermarks too */
2643                 dirty |= WM_DIRTY_LP_ALL;
2644         }
2645
2646         /* LP1+ watermarks already deemed dirty, no need to continue */
2647         if (dirty & WM_DIRTY_LP_ALL)
2648                 return dirty;
2649
2650         /* Find the lowest numbered LP1+ watermark in need of an update... */
2651         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2652                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2653                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2654                         break;
2655         }
2656
2657         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2658         for (; wm_lp <= 3; wm_lp++)
2659                 dirty |= WM_DIRTY_LP(wm_lp);
2660
2661         return dirty;
2662 }
2663
2664 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2665                                unsigned int dirty)
2666 {
2667         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2668         bool changed = false;
2669
2670         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2671                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2672                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2673                 changed = true;
2674         }
2675         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2676                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2677                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2678                 changed = true;
2679         }
2680         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2681                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2682                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2683                 changed = true;
2684         }
2685
2686         /*
2687          * Don't touch WM1S_LP_EN here.
2688          * Doing so could cause underruns.
2689          */
2690
2691         return changed;
2692 }
2693
2694 /*
2695  * The spec says we shouldn't write when we don't need, because every write
2696  * causes WMs to be re-evaluated, expending some power.
2697  */
2698 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2699                                 struct ilk_wm_values *results)
2700 {
2701         struct drm_device *dev = dev_priv->dev;
2702         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2703         unsigned int dirty;
2704         uint32_t val;
2705
2706         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2707         if (!dirty)
2708                 return;
2709
2710         _ilk_disable_lp_wm(dev_priv, dirty);
2711
2712         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2713                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2714         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2715                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2716         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2717                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2718
2719         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2720                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2721         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2722                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2723         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2724                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2725
2726         if (dirty & WM_DIRTY_DDB) {
2727                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2728                         val = I915_READ(WM_MISC);
2729                         if (results->partitioning == INTEL_DDB_PART_1_2)
2730                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2731                         else
2732                                 val |= WM_MISC_DATA_PARTITION_5_6;
2733                         I915_WRITE(WM_MISC, val);
2734                 } else {
2735                         val = I915_READ(DISP_ARB_CTL2);
2736                         if (results->partitioning == INTEL_DDB_PART_1_2)
2737                                 val &= ~DISP_DATA_PARTITION_5_6;
2738                         else
2739                                 val |= DISP_DATA_PARTITION_5_6;
2740                         I915_WRITE(DISP_ARB_CTL2, val);
2741                 }
2742         }
2743
2744         if (dirty & WM_DIRTY_FBC) {
2745                 val = I915_READ(DISP_ARB_CTL);
2746                 if (results->enable_fbc_wm)
2747                         val &= ~DISP_FBC_WM_DIS;
2748                 else
2749                         val |= DISP_FBC_WM_DIS;
2750                 I915_WRITE(DISP_ARB_CTL, val);
2751         }
2752
2753         if (dirty & WM_DIRTY_LP(1) &&
2754             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2755                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2756
2757         if (INTEL_INFO(dev)->gen >= 7) {
2758                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2759                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2760                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2761                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2762         }
2763
2764         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2765                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2766         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2767                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2768         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2769                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2770
2771         dev_priv->wm.hw = *results;
2772 }
2773
2774 static bool ilk_disable_lp_wm(struct drm_device *dev)
2775 {
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777
2778         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2779 }
2780
2781 /*
2782  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2783  * different active planes.
2784  */
2785
2786 #define SKL_DDB_SIZE            896     /* in blocks */
2787 #define BXT_DDB_SIZE            512
2788
2789 /*
2790  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2791  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2792  * other universal planes are in indices 1..n.  Note that this may leave unused
2793  * indices between the top "sprite" plane and the cursor.
2794  */
2795 static int
2796 skl_wm_plane_id(const struct intel_plane *plane)
2797 {
2798         switch (plane->base.type) {
2799         case DRM_PLANE_TYPE_PRIMARY:
2800                 return 0;
2801         case DRM_PLANE_TYPE_CURSOR:
2802                 return PLANE_CURSOR;
2803         case DRM_PLANE_TYPE_OVERLAY:
2804                 return plane->plane + 1;
2805         default:
2806                 MISSING_CASE(plane->base.type);
2807                 return plane->plane;
2808         }
2809 }
2810
2811 static void
2812 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2813                                    const struct intel_crtc_state *cstate,
2814                                    const struct intel_wm_config *config,
2815                                    struct skl_ddb_entry *alloc /* out */)
2816 {
2817         struct drm_crtc *for_crtc = cstate->base.crtc;
2818         struct drm_crtc *crtc;
2819         unsigned int pipe_size, ddb_size;
2820         int nth_active_pipe;
2821
2822         if (!cstate->base.active) {
2823                 alloc->start = 0;
2824                 alloc->end = 0;
2825                 return;
2826         }
2827
2828         if (IS_BROXTON(dev))
2829                 ddb_size = BXT_DDB_SIZE;
2830         else
2831                 ddb_size = SKL_DDB_SIZE;
2832
2833         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2834
2835         nth_active_pipe = 0;
2836         for_each_crtc(dev, crtc) {
2837                 if (!to_intel_crtc(crtc)->active)
2838                         continue;
2839
2840                 if (crtc == for_crtc)
2841                         break;
2842
2843                 nth_active_pipe++;
2844         }
2845
2846         pipe_size = ddb_size / config->num_pipes_active;
2847         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2848         alloc->end = alloc->start + pipe_size;
2849 }
2850
2851 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2852 {
2853         if (config->num_pipes_active == 1)
2854                 return 32;
2855
2856         return 8;
2857 }
2858
2859 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2860 {
2861         entry->start = reg & 0x3ff;
2862         entry->end = (reg >> 16) & 0x3ff;
2863         if (entry->end)
2864                 entry->end += 1;
2865 }
2866
2867 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2868                           struct skl_ddb_allocation *ddb /* out */)
2869 {
2870         enum pipe pipe;
2871         int plane;
2872         u32 val;
2873
2874         for_each_pipe(dev_priv, pipe) {
2875                 for_each_plane(dev_priv, pipe, plane) {
2876                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2877                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2878                                                    val);
2879                 }
2880
2881                 val = I915_READ(CUR_BUF_CFG(pipe));
2882                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2883                                            val);
2884         }
2885 }
2886
2887 static unsigned int
2888 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2889                              const struct drm_plane_state *pstate,
2890                              int y)
2891 {
2892         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2893         struct drm_framebuffer *fb = pstate->fb;
2894
2895         /* for planar format */
2896         if (fb->pixel_format == DRM_FORMAT_NV12) {
2897                 if (y)  /* y-plane data rate */
2898                         return intel_crtc->config->pipe_src_w *
2899                                 intel_crtc->config->pipe_src_h *
2900                                 drm_format_plane_cpp(fb->pixel_format, 0);
2901                 else    /* uv-plane data rate */
2902                         return (intel_crtc->config->pipe_src_w/2) *
2903                                 (intel_crtc->config->pipe_src_h/2) *
2904                                 drm_format_plane_cpp(fb->pixel_format, 1);
2905         }
2906
2907         /* for packed formats */
2908         return intel_crtc->config->pipe_src_w *
2909                 intel_crtc->config->pipe_src_h *
2910                 drm_format_plane_cpp(fb->pixel_format, 0);
2911 }
2912
2913 /*
2914  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2915  * a 8192x4096@32bpp framebuffer:
2916  *   3 * 4096 * 8192  * 4 < 2^32
2917  */
2918 static unsigned int
2919 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2920 {
2921         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2922         struct drm_device *dev = intel_crtc->base.dev;
2923         const struct intel_plane *intel_plane;
2924         unsigned int total_data_rate = 0;
2925
2926         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2927                 const struct drm_plane_state *pstate = intel_plane->base.state;
2928
2929                 if (pstate->fb == NULL)
2930                         continue;
2931
2932                 /* packed/uv */
2933                 total_data_rate += skl_plane_relative_data_rate(cstate,
2934                                                                 pstate,
2935                                                                 0);
2936
2937                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2938                         /* y-plane */
2939                         total_data_rate += skl_plane_relative_data_rate(cstate,
2940                                                                         pstate,
2941                                                                         1);
2942         }
2943
2944         return total_data_rate;
2945 }
2946
2947 static void
2948 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2949                       struct skl_ddb_allocation *ddb /* out */)
2950 {
2951         struct drm_crtc *crtc = cstate->base.crtc;
2952         struct drm_device *dev = crtc->dev;
2953         struct drm_i915_private *dev_priv = to_i915(dev);
2954         struct intel_wm_config *config = &dev_priv->wm.config;
2955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956         struct intel_plane *intel_plane;
2957         enum pipe pipe = intel_crtc->pipe;
2958         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2959         uint16_t alloc_size, start, cursor_blocks;
2960         uint16_t minimum[I915_MAX_PLANES];
2961         uint16_t y_minimum[I915_MAX_PLANES];
2962         unsigned int total_data_rate;
2963
2964         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2965         alloc_size = skl_ddb_entry_size(alloc);
2966         if (alloc_size == 0) {
2967                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2968                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2969                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2970                 return;
2971         }
2972
2973         cursor_blocks = skl_cursor_allocation(config);
2974         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2975         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2976
2977         alloc_size -= cursor_blocks;
2978         alloc->end -= cursor_blocks;
2979
2980         /* 1. Allocate the mininum required blocks for each active plane */
2981         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2982                 struct drm_plane *plane = &intel_plane->base;
2983                 struct drm_framebuffer *fb = plane->fb;
2984                 int id = skl_wm_plane_id(intel_plane);
2985
2986                 if (fb == NULL)
2987                         continue;
2988                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2989                         continue;
2990
2991                 minimum[id] = 8;
2992                 alloc_size -= minimum[id];
2993                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2994                 alloc_size -= y_minimum[id];
2995         }
2996
2997         /*
2998          * 2. Distribute the remaining space in proportion to the amount of
2999          * data each plane needs to fetch from memory.
3000          *
3001          * FIXME: we may not allocate every single block here.
3002          */
3003         total_data_rate = skl_get_total_relative_data_rate(cstate);
3004
3005         start = alloc->start;
3006         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3007                 struct drm_plane *plane = &intel_plane->base;
3008                 struct drm_plane_state *pstate = intel_plane->base.state;
3009                 unsigned int data_rate, y_data_rate;
3010                 uint16_t plane_blocks, y_plane_blocks = 0;
3011                 int id = skl_wm_plane_id(intel_plane);
3012
3013                 if (pstate->fb == NULL)
3014                         continue;
3015                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3016                         continue;
3017
3018                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3019
3020                 /*
3021                  * allocation for (packed formats) or (uv-plane part of planar format):
3022                  * promote the expression to 64 bits to avoid overflowing, the
3023                  * result is < available as data_rate / total_data_rate < 1
3024                  */
3025                 plane_blocks = minimum[id];
3026                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3027                                         total_data_rate);
3028
3029                 ddb->plane[pipe][id].start = start;
3030                 ddb->plane[pipe][id].end = start + plane_blocks;
3031
3032                 start += plane_blocks;
3033
3034                 /*
3035                  * allocation for y_plane part of planar format:
3036                  */
3037                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3038                         y_data_rate = skl_plane_relative_data_rate(cstate,
3039                                                                    pstate,
3040                                                                    1);
3041                         y_plane_blocks = y_minimum[id];
3042                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3043                                                 total_data_rate);
3044
3045                         ddb->y_plane[pipe][id].start = start;
3046                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3047
3048                         start += y_plane_blocks;
3049                 }
3050
3051         }
3052
3053 }
3054
3055 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3056 {
3057         /* TODO: Take into account the scalers once we support them */
3058         return config->base.adjusted_mode.crtc_clock;
3059 }
3060
3061 /*
3062  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3063  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3064  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3065  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3066 */
3067 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3068                                uint32_t latency)
3069 {
3070         uint32_t wm_intermediate_val, ret;
3071
3072         if (latency == 0)
3073                 return UINT_MAX;
3074
3075         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3076         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3077
3078         return ret;
3079 }
3080
3081 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3082                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3083                                uint64_t tiling, uint32_t latency)
3084 {
3085         uint32_t ret;
3086         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3087         uint32_t wm_intermediate_val;
3088
3089         if (latency == 0)
3090                 return UINT_MAX;
3091
3092         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3093
3094         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3095             tiling == I915_FORMAT_MOD_Yf_TILED) {
3096                 plane_bytes_per_line *= 4;
3097                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3098                 plane_blocks_per_line /= 4;
3099         } else {
3100                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3101         }
3102
3103         wm_intermediate_val = latency * pixel_rate;
3104         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3105                                 plane_blocks_per_line;
3106
3107         return ret;
3108 }
3109
3110 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3111                                        const struct intel_crtc *intel_crtc)
3112 {
3113         struct drm_device *dev = intel_crtc->base.dev;
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3116         enum pipe pipe = intel_crtc->pipe;
3117
3118         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3119                    sizeof(new_ddb->plane[pipe])))
3120                 return true;
3121
3122         if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3123                     sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3124                 return true;
3125
3126         return false;
3127 }
3128
3129 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3130                                  struct intel_crtc_state *cstate,
3131                                  struct intel_plane *intel_plane,
3132                                  uint16_t ddb_allocation,
3133                                  int level,
3134                                  uint16_t *out_blocks, /* out */
3135                                  uint8_t *out_lines /* out */)
3136 {
3137         struct drm_plane *plane = &intel_plane->base;
3138         struct drm_framebuffer *fb = plane->state->fb;
3139         uint32_t latency = dev_priv->wm.skl_latency[level];
3140         uint32_t method1, method2;
3141         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3142         uint32_t res_blocks, res_lines;
3143         uint32_t selected_result;
3144         uint8_t bytes_per_pixel;
3145
3146         if (latency == 0 || !cstate->base.active || !fb)
3147                 return false;
3148
3149         bytes_per_pixel = (fb->pixel_format == DRM_FORMAT_NV12) ?
3150                 drm_format_plane_cpp(DRM_FORMAT_NV12, 0) :
3151                 drm_format_plane_cpp(DRM_FORMAT_NV12, 1);
3152         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3153                                  bytes_per_pixel,
3154                                  latency);
3155         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3156                                  cstate->base.adjusted_mode.crtc_htotal,
3157                                  cstate->pipe_src_w,
3158                                  bytes_per_pixel,
3159                                  fb->modifier[0],
3160                                  latency);
3161
3162         plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
3163         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3164
3165         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3166             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3167                 uint32_t min_scanlines = 4;
3168                 uint32_t y_tile_minimum;
3169                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3170                         int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3171                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3172                                 drm_format_plane_cpp(fb->pixel_format, 0);
3173
3174                         switch (bpp) {
3175                         case 1:
3176                                 min_scanlines = 16;
3177                                 break;
3178                         case 2:
3179                                 min_scanlines = 8;
3180                                 break;
3181                         case 8:
3182                                 WARN(1, "Unsupported pixel depth for rotation");
3183                         }
3184                 }
3185                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3186                 selected_result = max(method2, y_tile_minimum);
3187         } else {
3188                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3189                         selected_result = min(method1, method2);
3190                 else
3191                         selected_result = method1;
3192         }
3193
3194         res_blocks = selected_result + 1;
3195         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3196
3197         if (level >= 1 && level <= 7) {
3198                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3199                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3200                         res_lines += 4;
3201                 else
3202                         res_blocks++;
3203         }
3204
3205         if (res_blocks >= ddb_allocation || res_lines > 31)
3206                 return false;
3207
3208         *out_blocks = res_blocks;
3209         *out_lines = res_lines;
3210
3211         return true;
3212 }
3213
3214 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3215                                  struct skl_ddb_allocation *ddb,
3216                                  struct intel_crtc_state *cstate,
3217                                  int level,
3218                                  struct skl_wm_level *result)
3219 {
3220         struct drm_device *dev = dev_priv->dev;
3221         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3222         struct intel_plane *intel_plane;
3223         uint16_t ddb_blocks;
3224         enum pipe pipe = intel_crtc->pipe;
3225
3226         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3227                 int i = skl_wm_plane_id(intel_plane);
3228
3229                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3230
3231                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3232                                                 cstate,
3233                                                 intel_plane,
3234                                                 ddb_blocks,
3235                                                 level,
3236                                                 &result->plane_res_b[i],
3237                                                 &result->plane_res_l[i]);
3238         }
3239 }
3240
3241 static uint32_t
3242 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3243 {
3244         if (!cstate->base.active)
3245                 return 0;
3246
3247         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3248                 return 0;
3249
3250         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3251                             skl_pipe_pixel_rate(cstate));
3252 }
3253
3254 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3255                                       struct skl_wm_level *trans_wm /* out */)
3256 {
3257         struct drm_crtc *crtc = cstate->base.crtc;
3258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3259         struct intel_plane *intel_plane;
3260
3261         if (!cstate->base.active)
3262                 return;
3263
3264         /* Until we know more, just disable transition WMs */
3265         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3266                 int i = skl_wm_plane_id(intel_plane);
3267
3268                 trans_wm->plane_en[i] = false;
3269         }
3270 }
3271
3272 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3273                                 struct skl_ddb_allocation *ddb,
3274                                 struct skl_pipe_wm *pipe_wm)
3275 {
3276         struct drm_device *dev = cstate->base.crtc->dev;
3277         const struct drm_i915_private *dev_priv = dev->dev_private;
3278         int level, max_level = ilk_wm_max_level(dev);
3279
3280         for (level = 0; level <= max_level; level++) {
3281                 skl_compute_wm_level(dev_priv, ddb, cstate,
3282                                      level, &pipe_wm->wm[level]);
3283         }
3284         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3285
3286         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3287 }
3288
3289 static void skl_compute_wm_results(struct drm_device *dev,
3290                                    struct skl_pipe_wm *p_wm,
3291                                    struct skl_wm_values *r,
3292                                    struct intel_crtc *intel_crtc)
3293 {
3294         int level, max_level = ilk_wm_max_level(dev);
3295         enum pipe pipe = intel_crtc->pipe;
3296         uint32_t temp;
3297         int i;
3298
3299         for (level = 0; level <= max_level; level++) {
3300                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3301                         temp = 0;
3302
3303                         temp |= p_wm->wm[level].plane_res_l[i] <<
3304                                         PLANE_WM_LINES_SHIFT;
3305                         temp |= p_wm->wm[level].plane_res_b[i];
3306                         if (p_wm->wm[level].plane_en[i])
3307                                 temp |= PLANE_WM_EN;
3308
3309                         r->plane[pipe][i][level] = temp;
3310                 }
3311
3312                 temp = 0;
3313
3314                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3315                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3316
3317                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3318                         temp |= PLANE_WM_EN;
3319
3320                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3321
3322         }
3323
3324         /* transition WMs */
3325         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3326                 temp = 0;
3327                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3328                 temp |= p_wm->trans_wm.plane_res_b[i];
3329                 if (p_wm->trans_wm.plane_en[i])
3330                         temp |= PLANE_WM_EN;
3331
3332                 r->plane_trans[pipe][i] = temp;
3333         }
3334
3335         temp = 0;
3336         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3337         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3338         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3339                 temp |= PLANE_WM_EN;
3340
3341         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3342
3343         r->wm_linetime[pipe] = p_wm->linetime;
3344 }
3345
3346 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3347                                 const struct skl_ddb_entry *entry)
3348 {
3349         if (entry->end)
3350                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3351         else
3352                 I915_WRITE(reg, 0);
3353 }
3354
3355 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3356                                 const struct skl_wm_values *new)
3357 {
3358         struct drm_device *dev = dev_priv->dev;
3359         struct intel_crtc *crtc;
3360
3361         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3362                 int i, level, max_level = ilk_wm_max_level(dev);
3363                 enum pipe pipe = crtc->pipe;
3364
3365                 if (!new->dirty[pipe])
3366                         continue;
3367
3368                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3369
3370                 for (level = 0; level <= max_level; level++) {
3371                         for (i = 0; i < intel_num_planes(crtc); i++)
3372                                 I915_WRITE(PLANE_WM(pipe, i, level),
3373                                            new->plane[pipe][i][level]);
3374                         I915_WRITE(CUR_WM(pipe, level),
3375                                    new->plane[pipe][PLANE_CURSOR][level]);
3376                 }
3377                 for (i = 0; i < intel_num_planes(crtc); i++)
3378                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3379                                    new->plane_trans[pipe][i]);
3380                 I915_WRITE(CUR_WM_TRANS(pipe),
3381                            new->plane_trans[pipe][PLANE_CURSOR]);
3382
3383                 for (i = 0; i < intel_num_planes(crtc); i++) {
3384                         skl_ddb_entry_write(dev_priv,
3385                                             PLANE_BUF_CFG(pipe, i),
3386                                             &new->ddb.plane[pipe][i]);
3387                         skl_ddb_entry_write(dev_priv,
3388                                             PLANE_NV12_BUF_CFG(pipe, i),
3389                                             &new->ddb.y_plane[pipe][i]);
3390                 }
3391
3392                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3393                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3394         }
3395 }
3396
3397 /*
3398  * When setting up a new DDB allocation arrangement, we need to correctly
3399  * sequence the times at which the new allocations for the pipes are taken into
3400  * account or we'll have pipes fetching from space previously allocated to
3401  * another pipe.
3402  *
3403  * Roughly the sequence looks like:
3404  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3405  *     overlapping with a previous light-up pipe (another way to put it is:
3406  *     pipes with their new allocation strickly included into their old ones).
3407  *  2. re-allocate the other pipes that get their allocation reduced
3408  *  3. allocate the pipes having their allocation increased
3409  *
3410  * Steps 1. and 2. are here to take care of the following case:
3411  * - Initially DDB looks like this:
3412  *     |   B    |   C    |
3413  * - enable pipe A.
3414  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3415  *   allocation
3416  *     |  A  |  B  |  C  |
3417  *
3418  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3419  */
3420
3421 static void
3422 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3423 {
3424         int plane;
3425
3426         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3427
3428         for_each_plane(dev_priv, pipe, plane) {
3429                 I915_WRITE(PLANE_SURF(pipe, plane),
3430                            I915_READ(PLANE_SURF(pipe, plane)));
3431         }
3432         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3433 }
3434
3435 static bool
3436 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3437                             const struct skl_ddb_allocation *new,
3438                             enum pipe pipe)
3439 {
3440         uint16_t old_size, new_size;
3441
3442         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3443         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3444
3445         return old_size != new_size &&
3446                new->pipe[pipe].start >= old->pipe[pipe].start &&
3447                new->pipe[pipe].end <= old->pipe[pipe].end;
3448 }
3449
3450 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3451                                 struct skl_wm_values *new_values)
3452 {
3453         struct drm_device *dev = dev_priv->dev;
3454         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3455         bool reallocated[I915_MAX_PIPES] = {};
3456         struct intel_crtc *crtc;
3457         enum pipe pipe;
3458
3459         new_ddb = &new_values->ddb;
3460         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3461
3462         /*
3463          * First pass: flush the pipes with the new allocation contained into
3464          * the old space.
3465          *
3466          * We'll wait for the vblank on those pipes to ensure we can safely
3467          * re-allocate the freed space without this pipe fetching from it.
3468          */
3469         for_each_intel_crtc(dev, crtc) {
3470                 if (!crtc->active)
3471                         continue;
3472
3473                 pipe = crtc->pipe;
3474
3475                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3476                         continue;
3477
3478                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3479                 intel_wait_for_vblank(dev, pipe);
3480
3481                 reallocated[pipe] = true;
3482         }
3483
3484
3485         /*
3486          * Second pass: flush the pipes that are having their allocation
3487          * reduced, but overlapping with a previous allocation.
3488          *
3489          * Here as well we need to wait for the vblank to make sure the freed
3490          * space is not used anymore.
3491          */
3492         for_each_intel_crtc(dev, crtc) {
3493                 if (!crtc->active)
3494                         continue;
3495
3496                 pipe = crtc->pipe;
3497
3498                 if (reallocated[pipe])
3499                         continue;
3500
3501                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3502                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3503                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3504                         intel_wait_for_vblank(dev, pipe);
3505                         reallocated[pipe] = true;
3506                 }
3507         }
3508
3509         /*
3510          * Third pass: flush the pipes that got more space allocated.
3511          *
3512          * We don't need to actively wait for the update here, next vblank
3513          * will just get more DDB space with the correct WM values.
3514          */
3515         for_each_intel_crtc(dev, crtc) {
3516                 if (!crtc->active)
3517                         continue;
3518
3519                 pipe = crtc->pipe;
3520
3521                 /*
3522                  * At this point, only the pipes more space than before are
3523                  * left to re-allocate.
3524                  */
3525                 if (reallocated[pipe])
3526                         continue;
3527
3528                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3529         }
3530 }
3531
3532 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3533                                struct skl_ddb_allocation *ddb, /* out */
3534                                struct skl_pipe_wm *pipe_wm /* out */)
3535 {
3536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3537         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3538
3539         skl_allocate_pipe_ddb(cstate, ddb);
3540         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3541
3542         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3543                 return false;
3544
3545         intel_crtc->wm.active.skl = *pipe_wm;
3546
3547         return true;
3548 }
3549
3550 static void skl_update_other_pipe_wm(struct drm_device *dev,
3551                                      struct drm_crtc *crtc,
3552                                      struct skl_wm_values *r)
3553 {
3554         struct intel_crtc *intel_crtc;
3555         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3556
3557         /*
3558          * If the WM update hasn't changed the allocation for this_crtc (the
3559          * crtc we are currently computing the new WM values for), other
3560          * enabled crtcs will keep the same allocation and we don't need to
3561          * recompute anything for them.
3562          */
3563         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3564                 return;
3565
3566         /*
3567          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3568          * other active pipes need new DDB allocation and WM values.
3569          */
3570         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3571                                 base.head) {
3572                 struct skl_pipe_wm pipe_wm = {};
3573                 bool wm_changed;
3574
3575                 if (this_crtc->pipe == intel_crtc->pipe)
3576                         continue;
3577
3578                 if (!intel_crtc->active)
3579                         continue;
3580
3581                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3582                                                 &r->ddb, &pipe_wm);
3583
3584                 /*
3585                  * If we end up re-computing the other pipe WM values, it's
3586                  * because it was really needed, so we expect the WM values to
3587                  * be different.
3588                  */
3589                 WARN_ON(!wm_changed);
3590
3591                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3592                 r->dirty[intel_crtc->pipe] = true;
3593         }
3594 }
3595
3596 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3597 {
3598         watermarks->wm_linetime[pipe] = 0;
3599         memset(watermarks->plane[pipe], 0,
3600                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3601         memset(watermarks->plane_trans[pipe],
3602                0, sizeof(uint32_t) * I915_MAX_PLANES);
3603         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3604
3605         /* Clear ddb entries for pipe */
3606         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3607         memset(&watermarks->ddb.plane[pipe], 0,
3608                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3609         memset(&watermarks->ddb.y_plane[pipe], 0,
3610                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3611         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3612                sizeof(struct skl_ddb_entry));
3613
3614 }
3615
3616 static void skl_update_wm(struct drm_crtc *crtc)
3617 {
3618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619         struct drm_device *dev = crtc->dev;
3620         struct drm_i915_private *dev_priv = dev->dev_private;
3621         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3622         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3623         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3624
3625
3626         /* Clear all dirty flags */
3627         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3628
3629         skl_clear_wm(results, intel_crtc->pipe);
3630
3631         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3632                 return;
3633
3634         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3635         results->dirty[intel_crtc->pipe] = true;
3636
3637         skl_update_other_pipe_wm(dev, crtc, results);
3638         skl_write_wm_values(dev_priv, results);
3639         skl_flush_wm_values(dev_priv, results);
3640
3641         /* store the new configuration */
3642         dev_priv->wm.skl_hw = *results;
3643 }
3644
3645 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3646 {
3647         struct drm_device *dev = dev_priv->dev;
3648         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3649         struct ilk_wm_maximums max;
3650         struct intel_wm_config *config = &dev_priv->wm.config;
3651         struct ilk_wm_values results = {};
3652         enum intel_ddb_partitioning partitioning;
3653
3654         ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3655         ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
3656
3657         /* 5/6 split only in single pipe config on IVB+ */
3658         if (INTEL_INFO(dev)->gen >= 7 &&
3659             config->num_pipes_active == 1 && config->sprites_enabled) {
3660                 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3661                 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
3662
3663                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3664         } else {
3665                 best_lp_wm = &lp_wm_1_2;
3666         }
3667
3668         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3669                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3670
3671         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3672
3673         ilk_write_wm_values(dev_priv, &results);
3674 }
3675
3676 static void ilk_update_wm(struct drm_crtc *crtc)
3677 {
3678         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3680         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3681
3682         WARN_ON(cstate->base.active != intel_crtc->active);
3683
3684         /*
3685          * IVB workaround: must disable low power watermarks for at least
3686          * one frame before enabling scaling.  LP watermarks can be re-enabled
3687          * when scaling is disabled.
3688          *
3689          * WaCxSRDisabledForSpriteScaling:ivb
3690          */
3691         if (cstate->disable_lp_wm) {
3692                 ilk_disable_lp_wm(crtc->dev);
3693                 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3694         }
3695
3696         intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3697
3698         ilk_program_watermarks(dev_priv);
3699 }
3700
3701 static void skl_pipe_wm_active_state(uint32_t val,
3702                                      struct skl_pipe_wm *active,
3703                                      bool is_transwm,
3704                                      bool is_cursor,
3705                                      int i,
3706                                      int level)
3707 {
3708         bool is_enabled = (val & PLANE_WM_EN) != 0;
3709
3710         if (!is_transwm) {
3711                 if (!is_cursor) {
3712                         active->wm[level].plane_en[i] = is_enabled;
3713                         active->wm[level].plane_res_b[i] =
3714                                         val & PLANE_WM_BLOCKS_MASK;
3715                         active->wm[level].plane_res_l[i] =
3716                                         (val >> PLANE_WM_LINES_SHIFT) &
3717                                                 PLANE_WM_LINES_MASK;
3718                 } else {
3719                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3720                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3721                                         val & PLANE_WM_BLOCKS_MASK;
3722                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3723                                         (val >> PLANE_WM_LINES_SHIFT) &
3724                                                 PLANE_WM_LINES_MASK;
3725                 }
3726         } else {
3727                 if (!is_cursor) {
3728                         active->trans_wm.plane_en[i] = is_enabled;
3729                         active->trans_wm.plane_res_b[i] =
3730                                         val & PLANE_WM_BLOCKS_MASK;
3731                         active->trans_wm.plane_res_l[i] =
3732                                         (val >> PLANE_WM_LINES_SHIFT) &
3733                                                 PLANE_WM_LINES_MASK;
3734                 } else {
3735                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3736                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3737                                         val & PLANE_WM_BLOCKS_MASK;
3738                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3739                                         (val >> PLANE_WM_LINES_SHIFT) &
3740                                                 PLANE_WM_LINES_MASK;
3741                 }
3742         }
3743 }
3744
3745 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3746 {
3747         struct drm_device *dev = crtc->dev;
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3752         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3753         enum pipe pipe = intel_crtc->pipe;
3754         int level, i, max_level;
3755         uint32_t temp;
3756
3757         max_level = ilk_wm_max_level(dev);
3758
3759         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3760
3761         for (level = 0; level <= max_level; level++) {
3762                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3763                         hw->plane[pipe][i][level] =
3764                                         I915_READ(PLANE_WM(pipe, i, level));
3765                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3766         }
3767
3768         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3769                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3770         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3771
3772         if (!intel_crtc->active)
3773                 return;
3774
3775         hw->dirty[pipe] = true;
3776
3777         active->linetime = hw->wm_linetime[pipe];
3778
3779         for (level = 0; level <= max_level; level++) {
3780                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3781                         temp = hw->plane[pipe][i][level];
3782                         skl_pipe_wm_active_state(temp, active, false,
3783                                                 false, i, level);
3784                 }
3785                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3786                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3787         }
3788
3789         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3790                 temp = hw->plane_trans[pipe][i];
3791                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3792         }
3793
3794         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3795         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3796
3797         intel_crtc->wm.active.skl = *active;
3798 }
3799
3800 void skl_wm_get_hw_state(struct drm_device *dev)
3801 {
3802         struct drm_i915_private *dev_priv = dev->dev_private;
3803         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3804         struct drm_crtc *crtc;
3805
3806         skl_ddb_get_hw_state(dev_priv, ddb);
3807         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3808                 skl_pipe_wm_get_hw_state(crtc);
3809 }
3810
3811 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3812 {
3813         struct drm_device *dev = crtc->dev;
3814         struct drm_i915_private *dev_priv = dev->dev_private;
3815         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3817         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3818         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3819         enum pipe pipe = intel_crtc->pipe;
3820         static const unsigned int wm0_pipe_reg[] = {
3821                 [PIPE_A] = WM0_PIPEA_ILK,
3822                 [PIPE_B] = WM0_PIPEB_ILK,
3823                 [PIPE_C] = WM0_PIPEC_IVB,
3824         };
3825
3826         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3827         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3828                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3829
3830         active->pipe_enabled = intel_crtc->active;
3831
3832         if (active->pipe_enabled) {
3833                 u32 tmp = hw->wm_pipe[pipe];
3834
3835                 /*
3836                  * For active pipes LP0 watermark is marked as
3837                  * enabled, and LP1+ watermaks as disabled since
3838                  * we can't really reverse compute them in case
3839                  * multiple pipes are active.
3840                  */
3841                 active->wm[0].enable = true;
3842                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3843                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3844                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3845                 active->linetime = hw->wm_linetime[pipe];
3846         } else {
3847                 int level, max_level = ilk_wm_max_level(dev);
3848
3849                 /*
3850                  * For inactive pipes, all watermark levels
3851                  * should be marked as enabled but zeroed,
3852                  * which is what we'd compute them to.
3853                  */
3854                 for (level = 0; level <= max_level; level++)
3855                         active->wm[level].enable = true;
3856         }
3857
3858         intel_crtc->wm.active.ilk = *active;
3859 }
3860
3861 #define _FW_WM(value, plane) \
3862         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3863 #define _FW_WM_VLV(value, plane) \
3864         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3865
3866 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3867                                struct vlv_wm_values *wm)
3868 {
3869         enum pipe pipe;
3870         uint32_t tmp;
3871
3872         for_each_pipe(dev_priv, pipe) {
3873                 tmp = I915_READ(VLV_DDL(pipe));
3874
3875                 wm->ddl[pipe].primary =
3876                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3877                 wm->ddl[pipe].cursor =
3878                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3879                 wm->ddl[pipe].sprite[0] =
3880                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3881                 wm->ddl[pipe].sprite[1] =
3882                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3883         }
3884
3885         tmp = I915_READ(DSPFW1);
3886         wm->sr.plane = _FW_WM(tmp, SR);
3887         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3888         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3889         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3890
3891         tmp = I915_READ(DSPFW2);
3892         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3893         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3894         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3895
3896         tmp = I915_READ(DSPFW3);
3897         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3898
3899         if (IS_CHERRYVIEW(dev_priv)) {
3900                 tmp = I915_READ(DSPFW7_CHV);
3901                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3902                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3903
3904                 tmp = I915_READ(DSPFW8_CHV);
3905                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3906                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3907
3908                 tmp = I915_READ(DSPFW9_CHV);
3909                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3910                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3911
3912                 tmp = I915_READ(DSPHOWM);
3913                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3914                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3915                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3916                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3917                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3918                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3919                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3920                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3921                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3922                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3923         } else {
3924                 tmp = I915_READ(DSPFW7);
3925                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3926                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3927
3928                 tmp = I915_READ(DSPHOWM);
3929                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3930                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3931                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3932                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3933                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3934                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3935                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3936         }
3937 }
3938
3939 #undef _FW_WM
3940 #undef _FW_WM_VLV
3941
3942 void vlv_wm_get_hw_state(struct drm_device *dev)
3943 {
3944         struct drm_i915_private *dev_priv = to_i915(dev);
3945         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3946         struct intel_plane *plane;
3947         enum pipe pipe;
3948         u32 val;
3949
3950         vlv_read_wm_values(dev_priv, wm);
3951
3952         for_each_intel_plane(dev, plane) {
3953                 switch (plane->base.type) {
3954                         int sprite;
3955                 case DRM_PLANE_TYPE_CURSOR:
3956                         plane->wm.fifo_size = 63;
3957                         break;
3958                 case DRM_PLANE_TYPE_PRIMARY:
3959                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3960                         break;
3961                 case DRM_PLANE_TYPE_OVERLAY:
3962                         sprite = plane->plane;
3963                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3964                         break;
3965                 }
3966         }
3967
3968         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3969         wm->level = VLV_WM_LEVEL_PM2;
3970
3971         if (IS_CHERRYVIEW(dev_priv)) {
3972                 mutex_lock(&dev_priv->rps.hw_lock);
3973
3974                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3975                 if (val & DSP_MAXFIFO_PM5_ENABLE)
3976                         wm->level = VLV_WM_LEVEL_PM5;
3977
3978                 /*
3979                  * If DDR DVFS is disabled in the BIOS, Punit
3980                  * will never ack the request. So if that happens
3981                  * assume we don't have to enable/disable DDR DVFS
3982                  * dynamically. To test that just set the REQ_ACK
3983                  * bit to poke the Punit, but don't change the
3984                  * HIGH/LOW bits so that we don't actually change
3985                  * the current state.
3986                  */
3987                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3988                 val |= FORCE_DDR_FREQ_REQ_ACK;
3989                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3990
3991                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3992                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3993                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3994                                       "assuming DDR DVFS is disabled\n");
3995                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3996                 } else {
3997                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3998                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3999                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4000                 }
4001
4002                 mutex_unlock(&dev_priv->rps.hw_lock);
4003         }
4004
4005         for_each_pipe(dev_priv, pipe)
4006                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4007                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4008                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4009
4010         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4011                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4012 }
4013
4014 void ilk_wm_get_hw_state(struct drm_device *dev)
4015 {
4016         struct drm_i915_private *dev_priv = dev->dev_private;
4017         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4018         struct drm_crtc *crtc;
4019
4020         for_each_crtc(dev, crtc)
4021                 ilk_pipe_wm_get_hw_state(crtc);
4022
4023         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4024         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4025         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4026
4027         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4028         if (INTEL_INFO(dev)->gen >= 7) {
4029                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4030                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4031         }
4032
4033         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4034                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4035                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4036         else if (IS_IVYBRIDGE(dev))
4037                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4038                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4039
4040         hw->enable_fbc_wm =
4041                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4042 }
4043
4044 /**
4045  * intel_update_watermarks - update FIFO watermark values based on current modes
4046  *
4047  * Calculate watermark values for the various WM regs based on current mode
4048  * and plane configuration.
4049  *
4050  * There are several cases to deal with here:
4051  *   - normal (i.e. non-self-refresh)
4052  *   - self-refresh (SR) mode
4053  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4054  *   - lines are small relative to FIFO size (buffer can hold more than 2
4055  *     lines), so need to account for TLB latency
4056  *
4057  *   The normal calculation is:
4058  *     watermark = dotclock * bytes per pixel * latency
4059  *   where latency is platform & configuration dependent (we assume pessimal
4060  *   values here).
4061  *
4062  *   The SR calculation is:
4063  *     watermark = (trunc(latency/line time)+1) * surface width *
4064  *       bytes per pixel
4065  *   where
4066  *     line time = htotal / dotclock
4067  *     surface width = hdisplay for normal plane and 64 for cursor
4068  *   and latency is assumed to be high, as above.
4069  *
4070  * The final value programmed to the register should always be rounded up,
4071  * and include an extra 2 entries to account for clock crossings.
4072  *
4073  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4074  * to set the non-SR watermarks to 8.
4075  */
4076 void intel_update_watermarks(struct drm_crtc *crtc)
4077 {
4078         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4079
4080         if (dev_priv->display.update_wm)
4081                 dev_priv->display.update_wm(crtc);
4082 }
4083
4084 /**
4085  * Lock protecting IPS related data structures
4086  */
4087 DEFINE_SPINLOCK(mchdev_lock);
4088
4089 /* Global for IPS driver to get at the current i915 device. Protected by
4090  * mchdev_lock. */
4091 static struct drm_i915_private *i915_mch_dev;
4092
4093 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4094 {
4095         struct drm_i915_private *dev_priv = dev->dev_private;
4096         u16 rgvswctl;
4097
4098         assert_spin_locked(&mchdev_lock);
4099
4100         rgvswctl = I915_READ16(MEMSWCTL);
4101         if (rgvswctl & MEMCTL_CMD_STS) {
4102                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4103                 return false; /* still busy with another command */
4104         }
4105
4106         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4107                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4108         I915_WRITE16(MEMSWCTL, rgvswctl);
4109         POSTING_READ16(MEMSWCTL);
4110
4111         rgvswctl |= MEMCTL_CMD_STS;
4112         I915_WRITE16(MEMSWCTL, rgvswctl);
4113
4114         return true;
4115 }
4116
4117 static void ironlake_enable_drps(struct drm_device *dev)
4118 {
4119         struct drm_i915_private *dev_priv = dev->dev_private;
4120         u32 rgvmodectl = I915_READ(MEMMODECTL);
4121         u8 fmax, fmin, fstart, vstart;
4122
4123         spin_lock_irq(&mchdev_lock);
4124
4125         /* Enable temp reporting */
4126         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4127         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4128
4129         /* 100ms RC evaluation intervals */
4130         I915_WRITE(RCUPEI, 100000);
4131         I915_WRITE(RCDNEI, 100000);
4132
4133         /* Set max/min thresholds to 90ms and 80ms respectively */
4134         I915_WRITE(RCBMAXAVG, 90000);
4135         I915_WRITE(RCBMINAVG, 80000);
4136
4137         I915_WRITE(MEMIHYST, 1);
4138
4139         /* Set up min, max, and cur for interrupt handling */
4140         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4141         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4142         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4143                 MEMMODE_FSTART_SHIFT;
4144
4145         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4146                 PXVFREQ_PX_SHIFT;
4147
4148         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4149         dev_priv->ips.fstart = fstart;
4150
4151         dev_priv->ips.max_delay = fstart;
4152         dev_priv->ips.min_delay = fmin;
4153         dev_priv->ips.cur_delay = fstart;
4154
4155         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4156                          fmax, fmin, fstart);
4157
4158         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4159
4160         /*
4161          * Interrupts will be enabled in ironlake_irq_postinstall
4162          */
4163
4164         I915_WRITE(VIDSTART, vstart);
4165         POSTING_READ(VIDSTART);
4166
4167         rgvmodectl |= MEMMODE_SWMODE_EN;
4168         I915_WRITE(MEMMODECTL, rgvmodectl);
4169
4170         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4171                 DRM_ERROR("stuck trying to change perf mode\n");
4172         mdelay(1);
4173
4174         ironlake_set_drps(dev, fstart);
4175
4176         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4177                 I915_READ(DDREC) + I915_READ(CSIEC);
4178         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4179         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4180         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4181
4182         spin_unlock_irq(&mchdev_lock);
4183 }
4184
4185 static void ironlake_disable_drps(struct drm_device *dev)
4186 {
4187         struct drm_i915_private *dev_priv = dev->dev_private;
4188         u16 rgvswctl;
4189
4190         spin_lock_irq(&mchdev_lock);
4191
4192         rgvswctl = I915_READ16(MEMSWCTL);
4193
4194         /* Ack interrupts, disable EFC interrupt */
4195         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4196         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4197         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4198         I915_WRITE(DEIIR, DE_PCU_EVENT);
4199         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4200
4201         /* Go back to the starting frequency */
4202         ironlake_set_drps(dev, dev_priv->ips.fstart);
4203         mdelay(1);
4204         rgvswctl |= MEMCTL_CMD_STS;
4205         I915_WRITE(MEMSWCTL, rgvswctl);
4206         mdelay(1);
4207
4208         spin_unlock_irq(&mchdev_lock);
4209 }
4210
4211 /* There's a funny hw issue where the hw returns all 0 when reading from
4212  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4213  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4214  * all limits and the gpu stuck at whatever frequency it is at atm).
4215  */
4216 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4217 {
4218         u32 limits;
4219
4220         /* Only set the down limit when we've reached the lowest level to avoid
4221          * getting more interrupts, otherwise leave this clear. This prevents a
4222          * race in the hw when coming out of rc6: There's a tiny window where
4223          * the hw runs at the minimal clock before selecting the desired
4224          * frequency, if the down threshold expires in that window we will not
4225          * receive a down interrupt. */
4226         if (IS_GEN9(dev_priv->dev)) {
4227                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4228                 if (val <= dev_priv->rps.min_freq_softlimit)
4229                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4230         } else {
4231                 limits = dev_priv->rps.max_freq_softlimit << 24;
4232                 if (val <= dev_priv->rps.min_freq_softlimit)
4233                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4234         }
4235
4236         return limits;
4237 }
4238
4239 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4240 {
4241         int new_power;
4242         u32 threshold_up = 0, threshold_down = 0; /* in % */
4243         u32 ei_up = 0, ei_down = 0;
4244
4245         new_power = dev_priv->rps.power;
4246         switch (dev_priv->rps.power) {
4247         case LOW_POWER:
4248                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4249                         new_power = BETWEEN;
4250                 break;
4251
4252         case BETWEEN:
4253                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4254                         new_power = LOW_POWER;
4255                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4256                         new_power = HIGH_POWER;
4257                 break;
4258
4259         case HIGH_POWER:
4260                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4261                         new_power = BETWEEN;
4262                 break;
4263         }
4264         /* Max/min bins are special */
4265         if (val <= dev_priv->rps.min_freq_softlimit)
4266                 new_power = LOW_POWER;
4267         if (val >= dev_priv->rps.max_freq_softlimit)
4268                 new_power = HIGH_POWER;
4269         if (new_power == dev_priv->rps.power)
4270                 return;
4271
4272         /* Note the units here are not exactly 1us, but 1280ns. */
4273         switch (new_power) {
4274         case LOW_POWER:
4275                 /* Upclock if more than 95% busy over 16ms */
4276                 ei_up = 16000;
4277                 threshold_up = 95;
4278
4279                 /* Downclock if less than 85% busy over 32ms */
4280                 ei_down = 32000;
4281                 threshold_down = 85;
4282                 break;
4283
4284         case BETWEEN:
4285                 /* Upclock if more than 90% busy over 13ms */
4286                 ei_up = 13000;
4287                 threshold_up = 90;
4288
4289                 /* Downclock if less than 75% busy over 32ms */
4290                 ei_down = 32000;
4291                 threshold_down = 75;
4292                 break;
4293
4294         case HIGH_POWER:
4295                 /* Upclock if more than 85% busy over 10ms */
4296                 ei_up = 10000;
4297                 threshold_up = 85;
4298
4299                 /* Downclock if less than 60% busy over 32ms */
4300                 ei_down = 32000;
4301                 threshold_down = 60;
4302                 break;
4303         }
4304
4305         I915_WRITE(GEN6_RP_UP_EI,
4306                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4307         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4308                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4309
4310         I915_WRITE(GEN6_RP_DOWN_EI,
4311                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4312         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4313                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4314
4315          I915_WRITE(GEN6_RP_CONTROL,
4316                     GEN6_RP_MEDIA_TURBO |
4317                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4318                     GEN6_RP_MEDIA_IS_GFX |
4319                     GEN6_RP_ENABLE |
4320                     GEN6_RP_UP_BUSY_AVG |
4321                     GEN6_RP_DOWN_IDLE_AVG);
4322
4323         dev_priv->rps.power = new_power;
4324         dev_priv->rps.up_threshold = threshold_up;
4325         dev_priv->rps.down_threshold = threshold_down;
4326         dev_priv->rps.last_adj = 0;
4327 }
4328
4329 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4330 {
4331         u32 mask = 0;
4332
4333         if (val > dev_priv->rps.min_freq_softlimit)
4334                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4335         if (val < dev_priv->rps.max_freq_softlimit)
4336                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4337
4338         mask &= dev_priv->pm_rps_events;
4339
4340         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4341 }
4342
4343 /* gen6_set_rps is called to update the frequency request, but should also be
4344  * called when the range (min_delay and max_delay) is modified so that we can
4345  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4346 static void gen6_set_rps(struct drm_device *dev, u8 val)
4347 {
4348         struct drm_i915_private *dev_priv = dev->dev_private;
4349
4350         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4351         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4352                 return;
4353
4354         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4355         WARN_ON(val > dev_priv->rps.max_freq);
4356         WARN_ON(val < dev_priv->rps.min_freq);
4357
4358         /* min/max delay may still have been modified so be sure to
4359          * write the limits value.
4360          */
4361         if (val != dev_priv->rps.cur_freq) {
4362                 gen6_set_rps_thresholds(dev_priv, val);
4363
4364                 if (IS_GEN9(dev))
4365                         I915_WRITE(GEN6_RPNSWREQ,
4366                                    GEN9_FREQUENCY(val));
4367                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4368                         I915_WRITE(GEN6_RPNSWREQ,
4369                                    HSW_FREQUENCY(val));
4370                 else
4371                         I915_WRITE(GEN6_RPNSWREQ,
4372                                    GEN6_FREQUENCY(val) |
4373                                    GEN6_OFFSET(0) |
4374                                    GEN6_AGGRESSIVE_TURBO);
4375         }
4376
4377         /* Make sure we continue to get interrupts
4378          * until we hit the minimum or maximum frequencies.
4379          */
4380         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4381         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4382
4383         POSTING_READ(GEN6_RPNSWREQ);
4384
4385         dev_priv->rps.cur_freq = val;
4386         trace_intel_gpu_freq_change(val * 50);
4387 }
4388
4389 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4390 {
4391         struct drm_i915_private *dev_priv = dev->dev_private;
4392
4393         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4394         WARN_ON(val > dev_priv->rps.max_freq);
4395         WARN_ON(val < dev_priv->rps.min_freq);
4396
4397         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4398                       "Odd GPU freq value\n"))
4399                 val &= ~1;
4400
4401         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4402
4403         if (val != dev_priv->rps.cur_freq) {
4404                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4405                 if (!IS_CHERRYVIEW(dev_priv))
4406                         gen6_set_rps_thresholds(dev_priv, val);
4407         }
4408
4409         dev_priv->rps.cur_freq = val;
4410         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4411 }
4412
4413 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4414  *
4415  * * If Gfx is Idle, then
4416  * 1. Forcewake Media well.
4417  * 2. Request idle freq.
4418  * 3. Release Forcewake of Media well.
4419 */
4420 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4421 {
4422         u32 val = dev_priv->rps.idle_freq;
4423
4424         if (dev_priv->rps.cur_freq <= val)
4425                 return;
4426
4427         /* Wake up the media well, as that takes a lot less
4428          * power than the Render well. */
4429         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4430         valleyview_set_rps(dev_priv->dev, val);
4431         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4432 }
4433
4434 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4435 {
4436         mutex_lock(&dev_priv->rps.hw_lock);
4437         if (dev_priv->rps.enabled) {
4438                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4439                         gen6_rps_reset_ei(dev_priv);
4440                 I915_WRITE(GEN6_PMINTRMSK,
4441                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4442         }
4443         mutex_unlock(&dev_priv->rps.hw_lock);
4444 }
4445
4446 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4447 {
4448         struct drm_device *dev = dev_priv->dev;
4449
4450         mutex_lock(&dev_priv->rps.hw_lock);
4451         if (dev_priv->rps.enabled) {
4452                 if (IS_VALLEYVIEW(dev))
4453                         vlv_set_rps_idle(dev_priv);
4454                 else
4455                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4456                 dev_priv->rps.last_adj = 0;
4457                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4458         }
4459         mutex_unlock(&dev_priv->rps.hw_lock);
4460
4461         spin_lock(&dev_priv->rps.client_lock);
4462         while (!list_empty(&dev_priv->rps.clients))
4463                 list_del_init(dev_priv->rps.clients.next);
4464         spin_unlock(&dev_priv->rps.client_lock);
4465 }
4466
4467 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4468                     struct intel_rps_client *rps,
4469                     unsigned long submitted)
4470 {
4471         /* This is intentionally racy! We peek at the state here, then
4472          * validate inside the RPS worker.
4473          */
4474         if (!(dev_priv->mm.busy &&
4475               dev_priv->rps.enabled &&
4476               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4477                 return;
4478
4479         /* Force a RPS boost (and don't count it against the client) if
4480          * the GPU is severely congested.
4481          */
4482         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4483                 rps = NULL;
4484
4485         spin_lock(&dev_priv->rps.client_lock);
4486         if (rps == NULL || list_empty(&rps->link)) {
4487                 spin_lock_irq(&dev_priv->irq_lock);
4488                 if (dev_priv->rps.interrupts_enabled) {
4489                         dev_priv->rps.client_boost = true;
4490                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4491                 }
4492                 spin_unlock_irq(&dev_priv->irq_lock);
4493
4494                 if (rps != NULL) {
4495                         list_add(&rps->link, &dev_priv->rps.clients);
4496                         rps->boosts++;
4497                 } else
4498                         dev_priv->rps.boosts++;
4499         }
4500         spin_unlock(&dev_priv->rps.client_lock);
4501 }
4502
4503 void intel_set_rps(struct drm_device *dev, u8 val)
4504 {
4505         if (IS_VALLEYVIEW(dev))
4506                 valleyview_set_rps(dev, val);
4507         else
4508                 gen6_set_rps(dev, val);
4509 }
4510
4511 static void gen9_disable_rps(struct drm_device *dev)
4512 {
4513         struct drm_i915_private *dev_priv = dev->dev_private;
4514
4515         I915_WRITE(GEN6_RC_CONTROL, 0);
4516         I915_WRITE(GEN9_PG_ENABLE, 0);
4517 }
4518
4519 static void gen6_disable_rps(struct drm_device *dev)
4520 {
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522
4523         I915_WRITE(GEN6_RC_CONTROL, 0);
4524         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4525 }
4526
4527 static void cherryview_disable_rps(struct drm_device *dev)
4528 {
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530
4531         I915_WRITE(GEN6_RC_CONTROL, 0);
4532 }
4533
4534 static void valleyview_disable_rps(struct drm_device *dev)
4535 {
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537
4538         /* we're doing forcewake before Disabling RC6,
4539          * This what the BIOS expects when going into suspend */
4540         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4541
4542         I915_WRITE(GEN6_RC_CONTROL, 0);
4543
4544         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4545 }
4546
4547 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4548 {
4549         if (IS_VALLEYVIEW(dev)) {
4550                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4551                         mode = GEN6_RC_CTL_RC6_ENABLE;
4552                 else
4553                         mode = 0;
4554         }
4555         if (HAS_RC6p(dev))
4556                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4557                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4558                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4559                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4560
4561         else
4562                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4563                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4564 }
4565
4566 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4567 {
4568         /* No RC6 before Ironlake and code is gone for ilk. */
4569         if (INTEL_INFO(dev)->gen < 6)
4570                 return 0;
4571
4572         /* Respect the kernel parameter if it is set */
4573         if (enable_rc6 >= 0) {
4574                 int mask;
4575
4576                 if (HAS_RC6p(dev))
4577                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4578                                INTEL_RC6pp_ENABLE;
4579                 else
4580                         mask = INTEL_RC6_ENABLE;
4581
4582                 if ((enable_rc6 & mask) != enable_rc6)
4583                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4584                                       enable_rc6 & mask, enable_rc6, mask);
4585
4586                 return enable_rc6 & mask;
4587         }
4588
4589         if (IS_IVYBRIDGE(dev))
4590                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4591
4592         return INTEL_RC6_ENABLE;
4593 }
4594
4595 int intel_enable_rc6(const struct drm_device *dev)
4596 {
4597         return i915.enable_rc6;
4598 }
4599
4600 static void gen6_init_rps_frequencies(struct drm_device *dev)
4601 {
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603         uint32_t rp_state_cap;
4604         u32 ddcc_status = 0;
4605         int ret;
4606
4607         /* All of these values are in units of 50MHz */
4608         dev_priv->rps.cur_freq          = 0;
4609         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4610         if (IS_BROXTON(dev)) {
4611                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4612                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4613                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4614                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4615         } else {
4616                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4617                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4618                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4619                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4620         }
4621
4622         /* hw_max = RP0 until we check for overclocking */
4623         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4624
4625         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4626         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4627                 ret = sandybridge_pcode_read(dev_priv,
4628                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4629                                         &ddcc_status);
4630                 if (0 == ret)
4631                         dev_priv->rps.efficient_freq =
4632                                 clamp_t(u8,
4633                                         ((ddcc_status >> 8) & 0xff),
4634                                         dev_priv->rps.min_freq,
4635                                         dev_priv->rps.max_freq);
4636         }
4637
4638         if (IS_SKYLAKE(dev)) {
4639                 /* Store the frequency values in 16.66 MHZ units, which is
4640                    the natural hardware unit for SKL */
4641                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4642                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4643                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4644                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4645                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4646         }
4647
4648         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4649
4650         /* Preserve min/max settings in case of re-init */
4651         if (dev_priv->rps.max_freq_softlimit == 0)
4652                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4653
4654         if (dev_priv->rps.min_freq_softlimit == 0) {
4655                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4656                         dev_priv->rps.min_freq_softlimit =
4657                                 max_t(int, dev_priv->rps.efficient_freq,
4658                                       intel_freq_opcode(dev_priv, 450));
4659                 else
4660                         dev_priv->rps.min_freq_softlimit =
4661                                 dev_priv->rps.min_freq;
4662         }
4663 }
4664
4665 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4666 static void gen9_enable_rps(struct drm_device *dev)
4667 {
4668         struct drm_i915_private *dev_priv = dev->dev_private;
4669
4670         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4671
4672         gen6_init_rps_frequencies(dev);
4673
4674         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4675         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4676                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4677                 return;
4678         }
4679
4680         /* Program defaults and thresholds for RPS*/
4681         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4682                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4683
4684         /* 1 second timeout*/
4685         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4686                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4687
4688         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4689
4690         /* Leaning on the below call to gen6_set_rps to program/setup the
4691          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4692          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4693         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4694         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4695
4696         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4697 }
4698
4699 static void gen9_enable_rc6(struct drm_device *dev)
4700 {
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         struct intel_engine_cs *ring;
4703         uint32_t rc6_mask = 0;
4704         int unused;
4705
4706         /* 1a: Software RC state - RC0 */
4707         I915_WRITE(GEN6_RC_STATE, 0);
4708
4709         /* 1b: Get forcewake during program sequence. Although the driver
4710          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4711         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4712
4713         /* 2a: Disable RC states. */
4714         I915_WRITE(GEN6_RC_CONTROL, 0);
4715
4716         /* 2b: Program RC6 thresholds.*/
4717
4718         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4719         if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4720                                  (INTEL_REVID(dev) <= SKL_REVID_E0)))
4721                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4722         else
4723                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4724         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4725         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4726         for_each_ring(ring, dev_priv, unused)
4727                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4728
4729         if (HAS_GUC_UCODE(dev))
4730                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4731
4732         I915_WRITE(GEN6_RC_SLEEP, 0);
4733
4734         /* 2c: Program Coarse Power Gating Policies. */
4735         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4736         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4737
4738         /* 3a: Enable RC6 */
4739         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4740                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4741         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4742                         "on" : "off");
4743         /* WaRsUseTimeoutMode */
4744         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4745             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
4746                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4747                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4748                            GEN7_RC_CTL_TO_MODE |
4749                            rc6_mask);
4750         } else {
4751                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4752                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4753                            GEN6_RC_CTL_EI_MODE(1) |
4754                            rc6_mask);
4755         }
4756
4757         /*
4758          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4759          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4760          */
4761         if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4762             ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4763                 I915_WRITE(GEN9_PG_ENABLE, 0);
4764         else
4765                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4766                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4767
4768         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4769
4770 }
4771
4772 static void gen8_enable_rps(struct drm_device *dev)
4773 {
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775         struct intel_engine_cs *ring;
4776         uint32_t rc6_mask = 0;
4777         int unused;
4778
4779         /* 1a: Software RC state - RC0 */
4780         I915_WRITE(GEN6_RC_STATE, 0);
4781
4782         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4783          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4784         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4785
4786         /* 2a: Disable RC states. */
4787         I915_WRITE(GEN6_RC_CONTROL, 0);
4788
4789         /* Initialize rps frequencies */
4790         gen6_init_rps_frequencies(dev);
4791
4792         /* 2b: Program RC6 thresholds.*/
4793         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4794         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4795         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4796         for_each_ring(ring, dev_priv, unused)
4797                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4798         I915_WRITE(GEN6_RC_SLEEP, 0);
4799         if (IS_BROADWELL(dev))
4800                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4801         else
4802                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4803
4804         /* 3: Enable RC6 */
4805         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4806                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4807         intel_print_rc6_info(dev, rc6_mask);
4808         if (IS_BROADWELL(dev))
4809                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4810                                 GEN7_RC_CTL_TO_MODE |
4811                                 rc6_mask);
4812         else
4813                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4814                                 GEN6_RC_CTL_EI_MODE(1) |
4815                                 rc6_mask);
4816
4817         /* 4 Program defaults and thresholds for RPS*/
4818         I915_WRITE(GEN6_RPNSWREQ,
4819                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4820         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4821                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4822         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4823         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4824
4825         /* Docs recommend 900MHz, and 300 MHz respectively */
4826         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4827                    dev_priv->rps.max_freq_softlimit << 24 |
4828                    dev_priv->rps.min_freq_softlimit << 16);
4829
4830         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4831         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4832         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4833         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4834
4835         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4836
4837         /* 5: Enable RPS */
4838         I915_WRITE(GEN6_RP_CONTROL,
4839                    GEN6_RP_MEDIA_TURBO |
4840                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4841                    GEN6_RP_MEDIA_IS_GFX |
4842                    GEN6_RP_ENABLE |
4843                    GEN6_RP_UP_BUSY_AVG |
4844                    GEN6_RP_DOWN_IDLE_AVG);
4845
4846         /* 6: Ring frequency + overclocking (our driver does this later */
4847
4848         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4849         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4850
4851         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4852 }
4853
4854 static void gen6_enable_rps(struct drm_device *dev)
4855 {
4856         struct drm_i915_private *dev_priv = dev->dev_private;
4857         struct intel_engine_cs *ring;
4858         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4859         u32 gtfifodbg;
4860         int rc6_mode;
4861         int i, ret;
4862
4863         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4864
4865         /* Here begins a magic sequence of register writes to enable
4866          * auto-downclocking.
4867          *
4868          * Perhaps there might be some value in exposing these to
4869          * userspace...
4870          */
4871         I915_WRITE(GEN6_RC_STATE, 0);
4872
4873         /* Clear the DBG now so we don't confuse earlier errors */
4874         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4875                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4876                 I915_WRITE(GTFIFODBG, gtfifodbg);
4877         }
4878
4879         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4880
4881         /* Initialize rps frequencies */
4882         gen6_init_rps_frequencies(dev);
4883
4884         /* disable the counters and set deterministic thresholds */
4885         I915_WRITE(GEN6_RC_CONTROL, 0);
4886
4887         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4888         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4889         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4890         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4891         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4892
4893         for_each_ring(ring, dev_priv, i)
4894                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4895
4896         I915_WRITE(GEN6_RC_SLEEP, 0);
4897         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4898         if (IS_IVYBRIDGE(dev))
4899                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4900         else
4901                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4902         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4903         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4904
4905         /* Check if we are enabling RC6 */
4906         rc6_mode = intel_enable_rc6(dev_priv->dev);
4907         if (rc6_mode & INTEL_RC6_ENABLE)
4908                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4909
4910         /* We don't use those on Haswell */
4911         if (!IS_HASWELL(dev)) {
4912                 if (rc6_mode & INTEL_RC6p_ENABLE)
4913                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4914
4915                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4916                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4917         }
4918
4919         intel_print_rc6_info(dev, rc6_mask);
4920
4921         I915_WRITE(GEN6_RC_CONTROL,
4922                    rc6_mask |
4923                    GEN6_RC_CTL_EI_MODE(1) |
4924                    GEN6_RC_CTL_HW_ENABLE);
4925
4926         /* Power down if completely idle for over 50ms */
4927         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4928         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4929
4930         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4931         if (ret)
4932                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4933
4934         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4935         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4936                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4937                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4938                                  (pcu_mbox & 0xff) * 50);
4939                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4940         }
4941
4942         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4943         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4944
4945         rc6vids = 0;
4946         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4947         if (IS_GEN6(dev) && ret) {
4948                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4949         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4950                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4951                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4952                 rc6vids &= 0xffff00;
4953                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4954                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4955                 if (ret)
4956                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4957         }
4958
4959         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4960 }
4961
4962 static void __gen6_update_ring_freq(struct drm_device *dev)
4963 {
4964         struct drm_i915_private *dev_priv = dev->dev_private;
4965         int min_freq = 15;
4966         unsigned int gpu_freq;
4967         unsigned int max_ia_freq, min_ring_freq;
4968         unsigned int max_gpu_freq, min_gpu_freq;
4969         int scaling_factor = 180;
4970         struct cpufreq_policy *policy;
4971
4972         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4973
4974         policy = cpufreq_cpu_get(0);
4975         if (policy) {
4976                 max_ia_freq = policy->cpuinfo.max_freq;
4977                 cpufreq_cpu_put(policy);
4978         } else {
4979                 /*
4980                  * Default to measured freq if none found, PCU will ensure we
4981                  * don't go over
4982                  */
4983                 max_ia_freq = tsc_khz;
4984         }
4985
4986         /* Convert from kHz to MHz */
4987         max_ia_freq /= 1000;
4988
4989         min_ring_freq = I915_READ(DCLK) & 0xf;
4990         /* convert DDR frequency from units of 266.6MHz to bandwidth */
4991         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4992
4993         if (IS_SKYLAKE(dev)) {
4994                 /* Convert GT frequency to 50 HZ units */
4995                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4996                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4997         } else {
4998                 min_gpu_freq = dev_priv->rps.min_freq;
4999                 max_gpu_freq = dev_priv->rps.max_freq;
5000         }
5001
5002         /*
5003          * For each potential GPU frequency, load a ring frequency we'd like
5004          * to use for memory access.  We do this by specifying the IA frequency
5005          * the PCU should use as a reference to determine the ring frequency.
5006          */
5007         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5008                 int diff = max_gpu_freq - gpu_freq;
5009                 unsigned int ia_freq = 0, ring_freq = 0;
5010
5011                 if (IS_SKYLAKE(dev)) {
5012                         /*
5013                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5014                          * No floor required for ring frequency on SKL.
5015                          */
5016                         ring_freq = gpu_freq;
5017                 } else if (INTEL_INFO(dev)->gen >= 8) {
5018                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5019                         ring_freq = max(min_ring_freq, gpu_freq);
5020                 } else if (IS_HASWELL(dev)) {
5021                         ring_freq = mult_frac(gpu_freq, 5, 4);
5022                         ring_freq = max(min_ring_freq, ring_freq);
5023                         /* leave ia_freq as the default, chosen by cpufreq */
5024                 } else {
5025                         /* On older processors, there is no separate ring
5026                          * clock domain, so in order to boost the bandwidth
5027                          * of the ring, we need to upclock the CPU (ia_freq).
5028                          *
5029                          * For GPU frequencies less than 750MHz,
5030                          * just use the lowest ring freq.
5031                          */
5032                         if (gpu_freq < min_freq)
5033                                 ia_freq = 800;
5034                         else
5035                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5036                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5037                 }
5038
5039                 sandybridge_pcode_write(dev_priv,
5040                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5041                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5042                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5043                                         gpu_freq);
5044         }
5045 }
5046
5047 void gen6_update_ring_freq(struct drm_device *dev)
5048 {
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050
5051         if (!HAS_CORE_RING_FREQ(dev))
5052                 return;
5053
5054         mutex_lock(&dev_priv->rps.hw_lock);
5055         __gen6_update_ring_freq(dev);
5056         mutex_unlock(&dev_priv->rps.hw_lock);
5057 }
5058
5059 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5060 {
5061         struct drm_device *dev = dev_priv->dev;
5062         u32 val, rp0;
5063
5064         if (dev->pdev->revision >= 0x20) {
5065                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5066
5067                 switch (INTEL_INFO(dev)->eu_total) {
5068                 case 8:
5069                                 /* (2 * 4) config */
5070                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5071                                 break;
5072                 case 12:
5073                                 /* (2 * 6) config */
5074                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5075                                 break;
5076                 case 16:
5077                                 /* (2 * 8) config */
5078                 default:
5079                                 /* Setting (2 * 8) Min RP0 for any other combination */
5080                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5081                                 break;
5082                 }
5083                 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5084         } else {
5085                 /* For pre-production hardware */
5086                 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5087                 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5088                        PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5089         }
5090         return rp0;
5091 }
5092
5093 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5094 {
5095         u32 val, rpe;
5096
5097         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5098         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5099
5100         return rpe;
5101 }
5102
5103 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5104 {
5105         struct drm_device *dev = dev_priv->dev;
5106         u32 val, rp1;
5107
5108         if (dev->pdev->revision >= 0x20) {
5109                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5110                 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5111         } else {
5112                 /* For pre-production hardware */
5113                 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5114                 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5115                        PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5116         }
5117         return rp1;
5118 }
5119
5120 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5121 {
5122         u32 val, rp1;
5123
5124         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5125
5126         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5127
5128         return rp1;
5129 }
5130
5131 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5132 {
5133         u32 val, rp0;
5134
5135         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5136
5137         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5138         /* Clamp to max */
5139         rp0 = min_t(u32, rp0, 0xea);
5140
5141         return rp0;
5142 }
5143
5144 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5145 {
5146         u32 val, rpe;
5147
5148         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5149         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5150         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5151         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5152
5153         return rpe;
5154 }
5155
5156 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5157 {
5158         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5159 }
5160
5161 /* Check that the pctx buffer wasn't move under us. */
5162 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5163 {
5164         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5165
5166         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5167                              dev_priv->vlv_pctx->stolen->start);
5168 }
5169
5170
5171 /* Check that the pcbr address is not empty. */
5172 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5173 {
5174         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5175
5176         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5177 }
5178
5179 static void cherryview_setup_pctx(struct drm_device *dev)
5180 {
5181         struct drm_i915_private *dev_priv = dev->dev_private;
5182         unsigned long pctx_paddr, paddr;
5183         struct i915_gtt *gtt = &dev_priv->gtt;
5184         u32 pcbr;
5185         int pctx_size = 32*1024;
5186
5187         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5188
5189         pcbr = I915_READ(VLV_PCBR);
5190         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5191                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5192                 paddr = (dev_priv->mm.stolen_base +
5193                          (gtt->stolen_size - pctx_size));
5194
5195                 pctx_paddr = (paddr & (~4095));
5196                 I915_WRITE(VLV_PCBR, pctx_paddr);
5197         }
5198
5199         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5200 }
5201
5202 static void valleyview_setup_pctx(struct drm_device *dev)
5203 {
5204         struct drm_i915_private *dev_priv = dev->dev_private;
5205         struct drm_i915_gem_object *pctx;
5206         unsigned long pctx_paddr;
5207         u32 pcbr;
5208         int pctx_size = 24*1024;
5209
5210         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5211
5212         pcbr = I915_READ(VLV_PCBR);
5213         if (pcbr) {
5214                 /* BIOS set it up already, grab the pre-alloc'd space */
5215                 int pcbr_offset;
5216
5217                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5218                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5219                                                                       pcbr_offset,
5220                                                                       I915_GTT_OFFSET_NONE,
5221                                                                       pctx_size);
5222                 goto out;
5223         }
5224
5225         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5226
5227         /*
5228          * From the Gunit register HAS:
5229          * The Gfx driver is expected to program this register and ensure
5230          * proper allocation within Gfx stolen memory.  For example, this
5231          * register should be programmed such than the PCBR range does not
5232          * overlap with other ranges, such as the frame buffer, protected
5233          * memory, or any other relevant ranges.
5234          */
5235         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5236         if (!pctx) {
5237                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5238                 return;
5239         }
5240
5241         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5242         I915_WRITE(VLV_PCBR, pctx_paddr);
5243
5244 out:
5245         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5246         dev_priv->vlv_pctx = pctx;
5247 }
5248
5249 static void valleyview_cleanup_pctx(struct drm_device *dev)
5250 {
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252
5253         if (WARN_ON(!dev_priv->vlv_pctx))
5254                 return;
5255
5256         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5257         dev_priv->vlv_pctx = NULL;
5258 }
5259
5260 static void valleyview_init_gt_powersave(struct drm_device *dev)
5261 {
5262         struct drm_i915_private *dev_priv = dev->dev_private;
5263         u32 val;
5264
5265         valleyview_setup_pctx(dev);
5266
5267         mutex_lock(&dev_priv->rps.hw_lock);
5268
5269         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5270         switch ((val >> 6) & 3) {
5271         case 0:
5272         case 1:
5273                 dev_priv->mem_freq = 800;
5274                 break;
5275         case 2:
5276                 dev_priv->mem_freq = 1066;
5277                 break;
5278         case 3:
5279                 dev_priv->mem_freq = 1333;
5280                 break;
5281         }
5282         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5283
5284         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5285         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5286         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5287                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5288                          dev_priv->rps.max_freq);
5289
5290         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5291         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5292                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5293                          dev_priv->rps.efficient_freq);
5294
5295         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5296         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5297                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5298                          dev_priv->rps.rp1_freq);
5299
5300         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5301         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5302                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5303                          dev_priv->rps.min_freq);
5304
5305         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5306
5307         /* Preserve min/max settings in case of re-init */
5308         if (dev_priv->rps.max_freq_softlimit == 0)
5309                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5310
5311         if (dev_priv->rps.min_freq_softlimit == 0)
5312                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5313
5314         mutex_unlock(&dev_priv->rps.hw_lock);
5315 }
5316
5317 static void cherryview_init_gt_powersave(struct drm_device *dev)
5318 {
5319         struct drm_i915_private *dev_priv = dev->dev_private;
5320         u32 val;
5321
5322         cherryview_setup_pctx(dev);
5323
5324         mutex_lock(&dev_priv->rps.hw_lock);
5325
5326         mutex_lock(&dev_priv->sb_lock);
5327         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5328         mutex_unlock(&dev_priv->sb_lock);
5329
5330         switch ((val >> 2) & 0x7) {
5331         case 3:
5332                 dev_priv->mem_freq = 2000;
5333                 break;
5334         default:
5335                 dev_priv->mem_freq = 1600;
5336                 break;
5337         }
5338         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5339
5340         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5341         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5342         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5343                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5344                          dev_priv->rps.max_freq);
5345
5346         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5347         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5348                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5349                          dev_priv->rps.efficient_freq);
5350
5351         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5352         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5353                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5354                          dev_priv->rps.rp1_freq);
5355
5356         /* PUnit validated range is only [RPe, RP0] */
5357         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5358         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5359                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5360                          dev_priv->rps.min_freq);
5361
5362         WARN_ONCE((dev_priv->rps.max_freq |
5363                    dev_priv->rps.efficient_freq |
5364                    dev_priv->rps.rp1_freq |
5365                    dev_priv->rps.min_freq) & 1,
5366                   "Odd GPU freq values\n");
5367
5368         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5369
5370         /* Preserve min/max settings in case of re-init */
5371         if (dev_priv->rps.max_freq_softlimit == 0)
5372                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5373
5374         if (dev_priv->rps.min_freq_softlimit == 0)
5375                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5376
5377         mutex_unlock(&dev_priv->rps.hw_lock);
5378 }
5379
5380 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5381 {
5382         valleyview_cleanup_pctx(dev);
5383 }
5384
5385 static void cherryview_enable_rps(struct drm_device *dev)
5386 {
5387         struct drm_i915_private *dev_priv = dev->dev_private;
5388         struct intel_engine_cs *ring;
5389         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5390         int i;
5391
5392         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5393
5394         gtfifodbg = I915_READ(GTFIFODBG);
5395         if (gtfifodbg) {
5396                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5397                                  gtfifodbg);
5398                 I915_WRITE(GTFIFODBG, gtfifodbg);
5399         }
5400
5401         cherryview_check_pctx(dev_priv);
5402
5403         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5404          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5405         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5406
5407         /*  Disable RC states. */
5408         I915_WRITE(GEN6_RC_CONTROL, 0);
5409
5410         /* 2a: Program RC6 thresholds.*/
5411         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5412         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5413         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5414
5415         for_each_ring(ring, dev_priv, i)
5416                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5417         I915_WRITE(GEN6_RC_SLEEP, 0);
5418
5419         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5420         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5421
5422         /* allows RC6 residency counter to work */
5423         I915_WRITE(VLV_COUNTER_CONTROL,
5424                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5425                                       VLV_MEDIA_RC6_COUNT_EN |
5426                                       VLV_RENDER_RC6_COUNT_EN));
5427
5428         /* For now we assume BIOS is allocating and populating the PCBR  */
5429         pcbr = I915_READ(VLV_PCBR);
5430
5431         /* 3: Enable RC6 */
5432         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5433                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5434                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5435
5436         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5437
5438         /* 4 Program defaults and thresholds for RPS*/
5439         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5440         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5441         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5442         I915_WRITE(GEN6_RP_UP_EI, 66000);
5443         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5444
5445         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5446
5447         /* 5: Enable RPS */
5448         I915_WRITE(GEN6_RP_CONTROL,
5449                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5450                    GEN6_RP_MEDIA_IS_GFX |
5451                    GEN6_RP_ENABLE |
5452                    GEN6_RP_UP_BUSY_AVG |
5453                    GEN6_RP_DOWN_IDLE_AVG);
5454
5455         /* Setting Fixed Bias */
5456         val = VLV_OVERRIDE_EN |
5457                   VLV_SOC_TDP_EN |
5458                   CHV_BIAS_CPU_50_SOC_50;
5459         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5460
5461         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5462
5463         /* RPS code assumes GPLL is used */
5464         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5465
5466         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5467         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5468
5469         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5470         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5471                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5472                          dev_priv->rps.cur_freq);
5473
5474         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5475                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5476                          dev_priv->rps.efficient_freq);
5477
5478         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5479
5480         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5481 }
5482
5483 static void valleyview_enable_rps(struct drm_device *dev)
5484 {
5485         struct drm_i915_private *dev_priv = dev->dev_private;
5486         struct intel_engine_cs *ring;
5487         u32 gtfifodbg, val, rc6_mode = 0;
5488         int i;
5489
5490         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5491
5492         valleyview_check_pctx(dev_priv);
5493
5494         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5495                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5496                                  gtfifodbg);
5497                 I915_WRITE(GTFIFODBG, gtfifodbg);
5498         }
5499
5500         /* If VLV, Forcewake all wells, else re-direct to regular path */
5501         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5502
5503         /*  Disable RC states. */
5504         I915_WRITE(GEN6_RC_CONTROL, 0);
5505
5506         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5507         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5508         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5509         I915_WRITE(GEN6_RP_UP_EI, 66000);
5510         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5511
5512         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5513
5514         I915_WRITE(GEN6_RP_CONTROL,
5515                    GEN6_RP_MEDIA_TURBO |
5516                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5517                    GEN6_RP_MEDIA_IS_GFX |
5518                    GEN6_RP_ENABLE |
5519                    GEN6_RP_UP_BUSY_AVG |
5520                    GEN6_RP_DOWN_IDLE_CONT);
5521
5522         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5523         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5524         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5525
5526         for_each_ring(ring, dev_priv, i)
5527                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5528
5529         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5530
5531         /* allows RC6 residency counter to work */
5532         I915_WRITE(VLV_COUNTER_CONTROL,
5533                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5534                                       VLV_RENDER_RC0_COUNT_EN |
5535                                       VLV_MEDIA_RC6_COUNT_EN |
5536                                       VLV_RENDER_RC6_COUNT_EN));
5537
5538         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5539                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5540
5541         intel_print_rc6_info(dev, rc6_mode);
5542
5543         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5544
5545         /* Setting Fixed Bias */
5546         val = VLV_OVERRIDE_EN |
5547                   VLV_SOC_TDP_EN |
5548                   VLV_BIAS_CPU_125_SOC_875;
5549         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5550
5551         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5552
5553         /* RPS code assumes GPLL is used */
5554         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5555
5556         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5557         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5558
5559         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5560         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5561                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5562                          dev_priv->rps.cur_freq);
5563
5564         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5565                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5566                          dev_priv->rps.efficient_freq);
5567
5568         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5569
5570         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5571 }
5572
5573 static unsigned long intel_pxfreq(u32 vidfreq)
5574 {
5575         unsigned long freq;
5576         int div = (vidfreq & 0x3f0000) >> 16;
5577         int post = (vidfreq & 0x3000) >> 12;
5578         int pre = (vidfreq & 0x7);
5579
5580         if (!pre)
5581                 return 0;
5582
5583         freq = ((div * 133333) / ((1<<post) * pre));
5584
5585         return freq;
5586 }
5587
5588 static const struct cparams {
5589         u16 i;
5590         u16 t;
5591         u16 m;
5592         u16 c;
5593 } cparams[] = {
5594         { 1, 1333, 301, 28664 },
5595         { 1, 1066, 294, 24460 },
5596         { 1, 800, 294, 25192 },
5597         { 0, 1333, 276, 27605 },
5598         { 0, 1066, 276, 27605 },
5599         { 0, 800, 231, 23784 },
5600 };
5601
5602 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5603 {
5604         u64 total_count, diff, ret;
5605         u32 count1, count2, count3, m = 0, c = 0;
5606         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5607         int i;
5608
5609         assert_spin_locked(&mchdev_lock);
5610
5611         diff1 = now - dev_priv->ips.last_time1;
5612
5613         /* Prevent division-by-zero if we are asking too fast.
5614          * Also, we don't get interesting results if we are polling
5615          * faster than once in 10ms, so just return the saved value
5616          * in such cases.
5617          */
5618         if (diff1 <= 10)
5619                 return dev_priv->ips.chipset_power;
5620
5621         count1 = I915_READ(DMIEC);
5622         count2 = I915_READ(DDREC);
5623         count3 = I915_READ(CSIEC);
5624
5625         total_count = count1 + count2 + count3;
5626
5627         /* FIXME: handle per-counter overflow */
5628         if (total_count < dev_priv->ips.last_count1) {
5629                 diff = ~0UL - dev_priv->ips.last_count1;
5630                 diff += total_count;
5631         } else {
5632                 diff = total_count - dev_priv->ips.last_count1;
5633         }
5634
5635         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5636                 if (cparams[i].i == dev_priv->ips.c_m &&
5637                     cparams[i].t == dev_priv->ips.r_t) {
5638                         m = cparams[i].m;
5639                         c = cparams[i].c;
5640                         break;
5641                 }
5642         }
5643
5644         diff = div_u64(diff, diff1);
5645         ret = ((m * diff) + c);
5646         ret = div_u64(ret, 10);
5647
5648         dev_priv->ips.last_count1 = total_count;
5649         dev_priv->ips.last_time1 = now;
5650
5651         dev_priv->ips.chipset_power = ret;
5652
5653         return ret;
5654 }
5655
5656 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5657 {
5658         struct drm_device *dev = dev_priv->dev;
5659         unsigned long val;
5660
5661         if (INTEL_INFO(dev)->gen != 5)
5662                 return 0;
5663
5664         spin_lock_irq(&mchdev_lock);
5665
5666         val = __i915_chipset_val(dev_priv);
5667
5668         spin_unlock_irq(&mchdev_lock);
5669
5670         return val;
5671 }
5672
5673 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5674 {
5675         unsigned long m, x, b;
5676         u32 tsfs;
5677
5678         tsfs = I915_READ(TSFS);
5679
5680         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5681         x = I915_READ8(TR1);
5682
5683         b = tsfs & TSFS_INTR_MASK;
5684
5685         return ((m * x) / 127) - b;
5686 }
5687
5688 static int _pxvid_to_vd(u8 pxvid)
5689 {
5690         if (pxvid == 0)
5691                 return 0;
5692
5693         if (pxvid >= 8 && pxvid < 31)
5694                 pxvid = 31;
5695
5696         return (pxvid + 2) * 125;
5697 }
5698
5699 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5700 {
5701         struct drm_device *dev = dev_priv->dev;
5702         const int vd = _pxvid_to_vd(pxvid);
5703         const int vm = vd - 1125;
5704
5705         if (INTEL_INFO(dev)->is_mobile)
5706                 return vm > 0 ? vm : 0;
5707
5708         return vd;
5709 }
5710
5711 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5712 {
5713         u64 now, diff, diffms;
5714         u32 count;
5715
5716         assert_spin_locked(&mchdev_lock);
5717
5718         now = ktime_get_raw_ns();
5719         diffms = now - dev_priv->ips.last_time2;
5720         do_div(diffms, NSEC_PER_MSEC);
5721
5722         /* Don't divide by 0 */
5723         if (!diffms)
5724                 return;
5725
5726         count = I915_READ(GFXEC);
5727
5728         if (count < dev_priv->ips.last_count2) {
5729                 diff = ~0UL - dev_priv->ips.last_count2;
5730                 diff += count;
5731         } else {
5732                 diff = count - dev_priv->ips.last_count2;
5733         }
5734
5735         dev_priv->ips.last_count2 = count;
5736         dev_priv->ips.last_time2 = now;
5737
5738         /* More magic constants... */
5739         diff = diff * 1181;
5740         diff = div_u64(diff, diffms * 10);
5741         dev_priv->ips.gfx_power = diff;
5742 }
5743
5744 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5745 {
5746         struct drm_device *dev = dev_priv->dev;
5747
5748         if (INTEL_INFO(dev)->gen != 5)
5749                 return;
5750
5751         spin_lock_irq(&mchdev_lock);
5752
5753         __i915_update_gfx_val(dev_priv);
5754
5755         spin_unlock_irq(&mchdev_lock);
5756 }
5757
5758 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5759 {
5760         unsigned long t, corr, state1, corr2, state2;
5761         u32 pxvid, ext_v;
5762
5763         assert_spin_locked(&mchdev_lock);
5764
5765         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5766         pxvid = (pxvid >> 24) & 0x7f;
5767         ext_v = pvid_to_extvid(dev_priv, pxvid);
5768
5769         state1 = ext_v;
5770
5771         t = i915_mch_val(dev_priv);
5772
5773         /* Revel in the empirically derived constants */
5774
5775         /* Correction factor in 1/100000 units */
5776         if (t > 80)
5777                 corr = ((t * 2349) + 135940);
5778         else if (t >= 50)
5779                 corr = ((t * 964) + 29317);
5780         else /* < 50 */
5781                 corr = ((t * 301) + 1004);
5782
5783         corr = corr * ((150142 * state1) / 10000 - 78642);
5784         corr /= 100000;
5785         corr2 = (corr * dev_priv->ips.corr);
5786
5787         state2 = (corr2 * state1) / 10000;
5788         state2 /= 100; /* convert to mW */
5789
5790         __i915_update_gfx_val(dev_priv);
5791
5792         return dev_priv->ips.gfx_power + state2;
5793 }
5794
5795 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5796 {
5797         struct drm_device *dev = dev_priv->dev;
5798         unsigned long val;
5799
5800         if (INTEL_INFO(dev)->gen != 5)
5801                 return 0;
5802
5803         spin_lock_irq(&mchdev_lock);
5804
5805         val = __i915_gfx_val(dev_priv);
5806
5807         spin_unlock_irq(&mchdev_lock);
5808
5809         return val;
5810 }
5811
5812 /**
5813  * i915_read_mch_val - return value for IPS use
5814  *
5815  * Calculate and return a value for the IPS driver to use when deciding whether
5816  * we have thermal and power headroom to increase CPU or GPU power budget.
5817  */
5818 unsigned long i915_read_mch_val(void)
5819 {
5820         struct drm_i915_private *dev_priv;
5821         unsigned long chipset_val, graphics_val, ret = 0;
5822
5823         spin_lock_irq(&mchdev_lock);
5824         if (!i915_mch_dev)
5825                 goto out_unlock;
5826         dev_priv = i915_mch_dev;
5827
5828         chipset_val = __i915_chipset_val(dev_priv);
5829         graphics_val = __i915_gfx_val(dev_priv);
5830
5831         ret = chipset_val + graphics_val;
5832
5833 out_unlock:
5834         spin_unlock_irq(&mchdev_lock);
5835
5836         return ret;
5837 }
5838 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5839
5840 /**
5841  * i915_gpu_raise - raise GPU frequency limit
5842  *
5843  * Raise the limit; IPS indicates we have thermal headroom.
5844  */
5845 bool i915_gpu_raise(void)
5846 {
5847         struct drm_i915_private *dev_priv;
5848         bool ret = true;
5849
5850         spin_lock_irq(&mchdev_lock);
5851         if (!i915_mch_dev) {
5852                 ret = false;
5853                 goto out_unlock;
5854         }
5855         dev_priv = i915_mch_dev;
5856
5857         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5858                 dev_priv->ips.max_delay--;
5859
5860 out_unlock:
5861         spin_unlock_irq(&mchdev_lock);
5862
5863         return ret;
5864 }
5865 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5866
5867 /**
5868  * i915_gpu_lower - lower GPU frequency limit
5869  *
5870  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5871  * frequency maximum.
5872  */
5873 bool i915_gpu_lower(void)
5874 {
5875         struct drm_i915_private *dev_priv;
5876         bool ret = true;
5877
5878         spin_lock_irq(&mchdev_lock);
5879         if (!i915_mch_dev) {
5880                 ret = false;
5881                 goto out_unlock;
5882         }
5883         dev_priv = i915_mch_dev;
5884
5885         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5886                 dev_priv->ips.max_delay++;
5887
5888 out_unlock:
5889         spin_unlock_irq(&mchdev_lock);
5890
5891         return ret;
5892 }
5893 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5894
5895 /**
5896  * i915_gpu_busy - indicate GPU business to IPS
5897  *
5898  * Tell the IPS driver whether or not the GPU is busy.
5899  */
5900 bool i915_gpu_busy(void)
5901 {
5902         struct drm_i915_private *dev_priv;
5903         struct intel_engine_cs *ring;
5904         bool ret = false;
5905         int i;
5906
5907         spin_lock_irq(&mchdev_lock);
5908         if (!i915_mch_dev)
5909                 goto out_unlock;
5910         dev_priv = i915_mch_dev;
5911
5912         for_each_ring(ring, dev_priv, i)
5913                 ret |= !list_empty(&ring->request_list);
5914
5915 out_unlock:
5916         spin_unlock_irq(&mchdev_lock);
5917
5918         return ret;
5919 }
5920 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5921
5922 /**
5923  * i915_gpu_turbo_disable - disable graphics turbo
5924  *
5925  * Disable graphics turbo by resetting the max frequency and setting the
5926  * current frequency to the default.
5927  */
5928 bool i915_gpu_turbo_disable(void)
5929 {
5930         struct drm_i915_private *dev_priv;
5931         bool ret = true;
5932
5933         spin_lock_irq(&mchdev_lock);
5934         if (!i915_mch_dev) {
5935                 ret = false;
5936                 goto out_unlock;
5937         }
5938         dev_priv = i915_mch_dev;
5939
5940         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5941
5942         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5943                 ret = false;
5944
5945 out_unlock:
5946         spin_unlock_irq(&mchdev_lock);
5947
5948         return ret;
5949 }
5950 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5951
5952 /**
5953  * Tells the intel_ips driver that the i915 driver is now loaded, if
5954  * IPS got loaded first.
5955  *
5956  * This awkward dance is so that neither module has to depend on the
5957  * other in order for IPS to do the appropriate communication of
5958  * GPU turbo limits to i915.
5959  */
5960 static void
5961 ips_ping_for_i915_load(void)
5962 {
5963         void (*link)(void);
5964
5965         link = symbol_get(ips_link_to_i915_driver);
5966         if (link) {
5967                 link();
5968                 symbol_put(ips_link_to_i915_driver);
5969         }
5970 }
5971
5972 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5973 {
5974         /* We only register the i915 ips part with intel-ips once everything is
5975          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5976         spin_lock_irq(&mchdev_lock);
5977         i915_mch_dev = dev_priv;
5978         spin_unlock_irq(&mchdev_lock);
5979
5980         ips_ping_for_i915_load();
5981 }
5982
5983 void intel_gpu_ips_teardown(void)
5984 {
5985         spin_lock_irq(&mchdev_lock);
5986         i915_mch_dev = NULL;
5987         spin_unlock_irq(&mchdev_lock);
5988 }
5989
5990 static void intel_init_emon(struct drm_device *dev)
5991 {
5992         struct drm_i915_private *dev_priv = dev->dev_private;
5993         u32 lcfuse;
5994         u8 pxw[16];
5995         int i;
5996
5997         /* Disable to program */
5998         I915_WRITE(ECR, 0);
5999         POSTING_READ(ECR);
6000
6001         /* Program energy weights for various events */
6002         I915_WRITE(SDEW, 0x15040d00);
6003         I915_WRITE(CSIEW0, 0x007f0000);
6004         I915_WRITE(CSIEW1, 0x1e220004);
6005         I915_WRITE(CSIEW2, 0x04000004);
6006
6007         for (i = 0; i < 5; i++)
6008                 I915_WRITE(PEW(i), 0);
6009         for (i = 0; i < 3; i++)
6010                 I915_WRITE(DEW(i), 0);
6011
6012         /* Program P-state weights to account for frequency power adjustment */
6013         for (i = 0; i < 16; i++) {
6014                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6015                 unsigned long freq = intel_pxfreq(pxvidfreq);
6016                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6017                         PXVFREQ_PX_SHIFT;
6018                 unsigned long val;
6019
6020                 val = vid * vid;
6021                 val *= (freq / 1000);
6022                 val *= 255;
6023                 val /= (127*127*900);
6024                 if (val > 0xff)
6025                         DRM_ERROR("bad pxval: %ld\n", val);
6026                 pxw[i] = val;
6027         }
6028         /* Render standby states get 0 weight */
6029         pxw[14] = 0;
6030         pxw[15] = 0;
6031
6032         for (i = 0; i < 4; i++) {
6033                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6034                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6035                 I915_WRITE(PXW(i), val);
6036         }
6037
6038         /* Adjust magic regs to magic values (more experimental results) */
6039         I915_WRITE(OGW0, 0);
6040         I915_WRITE(OGW1, 0);
6041         I915_WRITE(EG0, 0x00007f00);
6042         I915_WRITE(EG1, 0x0000000e);
6043         I915_WRITE(EG2, 0x000e0000);
6044         I915_WRITE(EG3, 0x68000300);
6045         I915_WRITE(EG4, 0x42000000);
6046         I915_WRITE(EG5, 0x00140031);
6047         I915_WRITE(EG6, 0);
6048         I915_WRITE(EG7, 0);
6049
6050         for (i = 0; i < 8; i++)
6051                 I915_WRITE(PXWL(i), 0);
6052
6053         /* Enable PMON + select events */
6054         I915_WRITE(ECR, 0x80000019);
6055
6056         lcfuse = I915_READ(LCFUSE02);
6057
6058         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6059 }
6060
6061 void intel_init_gt_powersave(struct drm_device *dev)
6062 {
6063         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6064
6065         if (IS_CHERRYVIEW(dev))
6066                 cherryview_init_gt_powersave(dev);
6067         else if (IS_VALLEYVIEW(dev))
6068                 valleyview_init_gt_powersave(dev);
6069 }
6070
6071 void intel_cleanup_gt_powersave(struct drm_device *dev)
6072 {
6073         if (IS_CHERRYVIEW(dev))
6074                 return;
6075         else if (IS_VALLEYVIEW(dev))
6076                 valleyview_cleanup_gt_powersave(dev);
6077 }
6078
6079 static void gen6_suspend_rps(struct drm_device *dev)
6080 {
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082
6083         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6084
6085         gen6_disable_rps_interrupts(dev);
6086 }
6087
6088 /**
6089  * intel_suspend_gt_powersave - suspend PM work and helper threads
6090  * @dev: drm device
6091  *
6092  * We don't want to disable RC6 or other features here, we just want
6093  * to make sure any work we've queued has finished and won't bother
6094  * us while we're suspended.
6095  */
6096 void intel_suspend_gt_powersave(struct drm_device *dev)
6097 {
6098         struct drm_i915_private *dev_priv = dev->dev_private;
6099
6100         if (INTEL_INFO(dev)->gen < 6)
6101                 return;
6102
6103         gen6_suspend_rps(dev);
6104
6105         /* Force GPU to min freq during suspend */
6106         gen6_rps_idle(dev_priv);
6107 }
6108
6109 void intel_disable_gt_powersave(struct drm_device *dev)
6110 {
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112
6113         if (IS_IRONLAKE_M(dev)) {
6114                 ironlake_disable_drps(dev);
6115         } else if (INTEL_INFO(dev)->gen >= 6) {
6116                 intel_suspend_gt_powersave(dev);
6117
6118                 mutex_lock(&dev_priv->rps.hw_lock);
6119                 if (INTEL_INFO(dev)->gen >= 9)
6120                         gen9_disable_rps(dev);
6121                 else if (IS_CHERRYVIEW(dev))
6122                         cherryview_disable_rps(dev);
6123                 else if (IS_VALLEYVIEW(dev))
6124                         valleyview_disable_rps(dev);
6125                 else
6126                         gen6_disable_rps(dev);
6127
6128                 dev_priv->rps.enabled = false;
6129                 mutex_unlock(&dev_priv->rps.hw_lock);
6130         }
6131 }
6132
6133 static void intel_gen6_powersave_work(struct work_struct *work)
6134 {
6135         struct drm_i915_private *dev_priv =
6136                 container_of(work, struct drm_i915_private,
6137                              rps.delayed_resume_work.work);
6138         struct drm_device *dev = dev_priv->dev;
6139
6140         mutex_lock(&dev_priv->rps.hw_lock);
6141
6142         gen6_reset_rps_interrupts(dev);
6143
6144         if (IS_CHERRYVIEW(dev)) {
6145                 cherryview_enable_rps(dev);
6146         } else if (IS_VALLEYVIEW(dev)) {
6147                 valleyview_enable_rps(dev);
6148         } else if (INTEL_INFO(dev)->gen >= 9) {
6149                 gen9_enable_rc6(dev);
6150                 gen9_enable_rps(dev);
6151                 if (IS_SKYLAKE(dev))
6152                         __gen6_update_ring_freq(dev);
6153         } else if (IS_BROADWELL(dev)) {
6154                 gen8_enable_rps(dev);
6155                 __gen6_update_ring_freq(dev);
6156         } else {
6157                 gen6_enable_rps(dev);
6158                 __gen6_update_ring_freq(dev);
6159         }
6160
6161         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6162         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6163
6164         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6165         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6166
6167         dev_priv->rps.enabled = true;
6168
6169         gen6_enable_rps_interrupts(dev);
6170
6171         mutex_unlock(&dev_priv->rps.hw_lock);
6172
6173         intel_runtime_pm_put(dev_priv);
6174 }
6175
6176 void intel_enable_gt_powersave(struct drm_device *dev)
6177 {
6178         struct drm_i915_private *dev_priv = dev->dev_private;
6179
6180         /* Powersaving is controlled by the host when inside a VM */
6181         if (intel_vgpu_active(dev))
6182                 return;
6183
6184         if (IS_IRONLAKE_M(dev)) {
6185                 mutex_lock(&dev->struct_mutex);
6186                 ironlake_enable_drps(dev);
6187                 intel_init_emon(dev);
6188                 mutex_unlock(&dev->struct_mutex);
6189         } else if (INTEL_INFO(dev)->gen >= 6) {
6190                 /*
6191                  * PCU communication is slow and this doesn't need to be
6192                  * done at any specific time, so do this out of our fast path
6193                  * to make resume and init faster.
6194                  *
6195                  * We depend on the HW RC6 power context save/restore
6196                  * mechanism when entering D3 through runtime PM suspend. So
6197                  * disable RPM until RPS/RC6 is properly setup. We can only
6198                  * get here via the driver load/system resume/runtime resume
6199                  * paths, so the _noresume version is enough (and in case of
6200                  * runtime resume it's necessary).
6201                  */
6202                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6203                                            round_jiffies_up_relative(HZ)))
6204                         intel_runtime_pm_get_noresume(dev_priv);
6205         }
6206 }
6207
6208 void intel_reset_gt_powersave(struct drm_device *dev)
6209 {
6210         struct drm_i915_private *dev_priv = dev->dev_private;
6211
6212         if (INTEL_INFO(dev)->gen < 6)
6213                 return;
6214
6215         gen6_suspend_rps(dev);
6216         dev_priv->rps.enabled = false;
6217 }
6218
6219 static void ibx_init_clock_gating(struct drm_device *dev)
6220 {
6221         struct drm_i915_private *dev_priv = dev->dev_private;
6222
6223         /*
6224          * On Ibex Peak and Cougar Point, we need to disable clock
6225          * gating for the panel power sequencer or it will fail to
6226          * start up when no ports are active.
6227          */
6228         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6229 }
6230
6231 static void g4x_disable_trickle_feed(struct drm_device *dev)
6232 {
6233         struct drm_i915_private *dev_priv = dev->dev_private;
6234         enum pipe pipe;
6235
6236         for_each_pipe(dev_priv, pipe) {
6237                 I915_WRITE(DSPCNTR(pipe),
6238                            I915_READ(DSPCNTR(pipe)) |
6239                            DISPPLANE_TRICKLE_FEED_DISABLE);
6240
6241                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6242                 POSTING_READ(DSPSURF(pipe));
6243         }
6244 }
6245
6246 static void ilk_init_lp_watermarks(struct drm_device *dev)
6247 {
6248         struct drm_i915_private *dev_priv = dev->dev_private;
6249
6250         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6251         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6252         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6253
6254         /*
6255          * Don't touch WM1S_LP_EN here.
6256          * Doing so could cause underruns.
6257          */
6258 }
6259
6260 static void ironlake_init_clock_gating(struct drm_device *dev)
6261 {
6262         struct drm_i915_private *dev_priv = dev->dev_private;
6263         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6264
6265         /*
6266          * Required for FBC
6267          * WaFbcDisableDpfcClockGating:ilk
6268          */
6269         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6270                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6271                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6272
6273         I915_WRITE(PCH_3DCGDIS0,
6274                    MARIUNIT_CLOCK_GATE_DISABLE |
6275                    SVSMUNIT_CLOCK_GATE_DISABLE);
6276         I915_WRITE(PCH_3DCGDIS1,
6277                    VFMUNIT_CLOCK_GATE_DISABLE);
6278
6279         /*
6280          * According to the spec the following bits should be set in
6281          * order to enable memory self-refresh
6282          * The bit 22/21 of 0x42004
6283          * The bit 5 of 0x42020
6284          * The bit 15 of 0x45000
6285          */
6286         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6287                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6288                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6289         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6290         I915_WRITE(DISP_ARB_CTL,
6291                    (I915_READ(DISP_ARB_CTL) |
6292                     DISP_FBC_WM_DIS));
6293
6294         ilk_init_lp_watermarks(dev);
6295
6296         /*
6297          * Based on the document from hardware guys the following bits
6298          * should be set unconditionally in order to enable FBC.
6299          * The bit 22 of 0x42000
6300          * The bit 22 of 0x42004
6301          * The bit 7,8,9 of 0x42020.
6302          */
6303         if (IS_IRONLAKE_M(dev)) {
6304                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6305                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6306                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6307                            ILK_FBCQ_DIS);
6308                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6309                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6310                            ILK_DPARB_GATE);
6311         }
6312
6313         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6314
6315         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6316                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6317                    ILK_ELPIN_409_SELECT);
6318         I915_WRITE(_3D_CHICKEN2,
6319                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6320                    _3D_CHICKEN2_WM_READ_PIPELINED);
6321
6322         /* WaDisableRenderCachePipelinedFlush:ilk */
6323         I915_WRITE(CACHE_MODE_0,
6324                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6325
6326         /* WaDisable_RenderCache_OperationalFlush:ilk */
6327         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6328
6329         g4x_disable_trickle_feed(dev);
6330
6331         ibx_init_clock_gating(dev);
6332 }
6333
6334 static void cpt_init_clock_gating(struct drm_device *dev)
6335 {
6336         struct drm_i915_private *dev_priv = dev->dev_private;
6337         int pipe;
6338         uint32_t val;
6339
6340         /*
6341          * On Ibex Peak and Cougar Point, we need to disable clock
6342          * gating for the panel power sequencer or it will fail to
6343          * start up when no ports are active.
6344          */
6345         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6346                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6347                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6348         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6349                    DPLS_EDP_PPS_FIX_DIS);
6350         /* The below fixes the weird display corruption, a few pixels shifted
6351          * downward, on (only) LVDS of some HP laptops with IVY.
6352          */
6353         for_each_pipe(dev_priv, pipe) {
6354                 val = I915_READ(TRANS_CHICKEN2(pipe));
6355                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6356                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6357                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6358                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6359                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6360                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6361                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6362                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6363         }
6364         /* WADP0ClockGatingDisable */
6365         for_each_pipe(dev_priv, pipe) {
6366                 I915_WRITE(TRANS_CHICKEN1(pipe),
6367                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6368         }
6369 }
6370
6371 static void gen6_check_mch_setup(struct drm_device *dev)
6372 {
6373         struct drm_i915_private *dev_priv = dev->dev_private;
6374         uint32_t tmp;
6375
6376         tmp = I915_READ(MCH_SSKPD);
6377         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6378                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6379                               tmp);
6380 }
6381
6382 static void gen6_init_clock_gating(struct drm_device *dev)
6383 {
6384         struct drm_i915_private *dev_priv = dev->dev_private;
6385         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6386
6387         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6388
6389         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6390                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6391                    ILK_ELPIN_409_SELECT);
6392
6393         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6394         I915_WRITE(_3D_CHICKEN,
6395                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6396
6397         /* WaDisable_RenderCache_OperationalFlush:snb */
6398         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6399
6400         /*
6401          * BSpec recoomends 8x4 when MSAA is used,
6402          * however in practice 16x4 seems fastest.
6403          *
6404          * Note that PS/WM thread counts depend on the WIZ hashing
6405          * disable bit, which we don't touch here, but it's good
6406          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6407          */
6408         I915_WRITE(GEN6_GT_MODE,
6409                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6410
6411         ilk_init_lp_watermarks(dev);
6412
6413         I915_WRITE(CACHE_MODE_0,
6414                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6415
6416         I915_WRITE(GEN6_UCGCTL1,
6417                    I915_READ(GEN6_UCGCTL1) |
6418                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6419                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6420
6421         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6422          * gating disable must be set.  Failure to set it results in
6423          * flickering pixels due to Z write ordering failures after
6424          * some amount of runtime in the Mesa "fire" demo, and Unigine
6425          * Sanctuary and Tropics, and apparently anything else with
6426          * alpha test or pixel discard.
6427          *
6428          * According to the spec, bit 11 (RCCUNIT) must also be set,
6429          * but we didn't debug actual testcases to find it out.
6430          *
6431          * WaDisableRCCUnitClockGating:snb
6432          * WaDisableRCPBUnitClockGating:snb
6433          */
6434         I915_WRITE(GEN6_UCGCTL2,
6435                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6436                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6437
6438         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6439         I915_WRITE(_3D_CHICKEN3,
6440                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6441
6442         /*
6443          * Bspec says:
6444          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6445          * 3DSTATE_SF number of SF output attributes is more than 16."
6446          */
6447         I915_WRITE(_3D_CHICKEN3,
6448                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6449
6450         /*
6451          * According to the spec the following bits should be
6452          * set in order to enable memory self-refresh and fbc:
6453          * The bit21 and bit22 of 0x42000
6454          * The bit21 and bit22 of 0x42004
6455          * The bit5 and bit7 of 0x42020
6456          * The bit14 of 0x70180
6457          * The bit14 of 0x71180
6458          *
6459          * WaFbcAsynchFlipDisableFbcQueue:snb
6460          */
6461         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6462                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6463                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6464         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6465                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6466                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6467         I915_WRITE(ILK_DSPCLK_GATE_D,
6468                    I915_READ(ILK_DSPCLK_GATE_D) |
6469                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6470                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6471
6472         g4x_disable_trickle_feed(dev);
6473
6474         cpt_init_clock_gating(dev);
6475
6476         gen6_check_mch_setup(dev);
6477 }
6478
6479 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6480 {
6481         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6482
6483         /*
6484          * WaVSThreadDispatchOverride:ivb,vlv
6485          *
6486          * This actually overrides the dispatch
6487          * mode for all thread types.
6488          */
6489         reg &= ~GEN7_FF_SCHED_MASK;
6490         reg |= GEN7_FF_TS_SCHED_HW;
6491         reg |= GEN7_FF_VS_SCHED_HW;
6492         reg |= GEN7_FF_DS_SCHED_HW;
6493
6494         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6495 }
6496
6497 static void lpt_init_clock_gating(struct drm_device *dev)
6498 {
6499         struct drm_i915_private *dev_priv = dev->dev_private;
6500
6501         /*
6502          * TODO: this bit should only be enabled when really needed, then
6503          * disabled when not needed anymore in order to save power.
6504          */
6505         if (HAS_PCH_LPT_LP(dev))
6506                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6507                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6508                            PCH_LP_PARTITION_LEVEL_DISABLE);
6509
6510         /* WADPOClockGatingDisable:hsw */
6511         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6512                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6513                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6514 }
6515
6516 static void lpt_suspend_hw(struct drm_device *dev)
6517 {
6518         struct drm_i915_private *dev_priv = dev->dev_private;
6519
6520         if (HAS_PCH_LPT_LP(dev)) {
6521                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6522
6523                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6524                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6525         }
6526 }
6527
6528 static void broadwell_init_clock_gating(struct drm_device *dev)
6529 {
6530         struct drm_i915_private *dev_priv = dev->dev_private;
6531         enum pipe pipe;
6532         uint32_t misccpctl;
6533
6534         ilk_init_lp_watermarks(dev);
6535
6536         /* WaSwitchSolVfFArbitrationPriority:bdw */
6537         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6538
6539         /* WaPsrDPAMaskVBlankInSRD:bdw */
6540         I915_WRITE(CHICKEN_PAR1_1,
6541                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6542
6543         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6544         for_each_pipe(dev_priv, pipe) {
6545                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6546                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6547                            BDW_DPRS_MASK_VBLANK_SRD);
6548         }
6549
6550         /* WaVSRefCountFullforceMissDisable:bdw */
6551         /* WaDSRefCountFullforceMissDisable:bdw */
6552         I915_WRITE(GEN7_FF_THREAD_MODE,
6553                    I915_READ(GEN7_FF_THREAD_MODE) &
6554                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6555
6556         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6557                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6558
6559         /* WaDisableSDEUnitClockGating:bdw */
6560         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6561                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6562
6563         /*
6564          * WaProgramL3SqcReg1Default:bdw
6565          * WaTempDisableDOPClkGating:bdw
6566          */
6567         misccpctl = I915_READ(GEN7_MISCCPCTL);
6568         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6569         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6570         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6571
6572         /*
6573          * WaGttCachingOffByDefault:bdw
6574          * GTT cache may not work with big pages, so if those
6575          * are ever enabled GTT cache may need to be disabled.
6576          */
6577         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6578
6579         lpt_init_clock_gating(dev);
6580 }
6581
6582 static void haswell_init_clock_gating(struct drm_device *dev)
6583 {
6584         struct drm_i915_private *dev_priv = dev->dev_private;
6585
6586         ilk_init_lp_watermarks(dev);
6587
6588         /* L3 caching of data atomics doesn't work -- disable it. */
6589         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6590         I915_WRITE(HSW_ROW_CHICKEN3,
6591                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6592
6593         /* This is required by WaCatErrorRejectionIssue:hsw */
6594         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6595                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6596                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6597
6598         /* WaVSRefCountFullforceMissDisable:hsw */
6599         I915_WRITE(GEN7_FF_THREAD_MODE,
6600                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6601
6602         /* WaDisable_RenderCache_OperationalFlush:hsw */
6603         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6604
6605         /* enable HiZ Raw Stall Optimization */
6606         I915_WRITE(CACHE_MODE_0_GEN7,
6607                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6608
6609         /* WaDisable4x2SubspanOptimization:hsw */
6610         I915_WRITE(CACHE_MODE_1,
6611                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6612
6613         /*
6614          * BSpec recommends 8x4 when MSAA is used,
6615          * however in practice 16x4 seems fastest.
6616          *
6617          * Note that PS/WM thread counts depend on the WIZ hashing
6618          * disable bit, which we don't touch here, but it's good
6619          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6620          */
6621         I915_WRITE(GEN7_GT_MODE,
6622                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6623
6624         /* WaSampleCChickenBitEnable:hsw */
6625         I915_WRITE(HALF_SLICE_CHICKEN3,
6626                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6627
6628         /* WaSwitchSolVfFArbitrationPriority:hsw */
6629         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6630
6631         /* WaRsPkgCStateDisplayPMReq:hsw */
6632         I915_WRITE(CHICKEN_PAR1_1,
6633                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6634
6635         lpt_init_clock_gating(dev);
6636 }
6637
6638 static void ivybridge_init_clock_gating(struct drm_device *dev)
6639 {
6640         struct drm_i915_private *dev_priv = dev->dev_private;
6641         uint32_t snpcr;
6642
6643         ilk_init_lp_watermarks(dev);
6644
6645         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6646
6647         /* WaDisableEarlyCull:ivb */
6648         I915_WRITE(_3D_CHICKEN3,
6649                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6650
6651         /* WaDisableBackToBackFlipFix:ivb */
6652         I915_WRITE(IVB_CHICKEN3,
6653                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6654                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6655
6656         /* WaDisablePSDDualDispatchEnable:ivb */
6657         if (IS_IVB_GT1(dev))
6658                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6659                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6660
6661         /* WaDisable_RenderCache_OperationalFlush:ivb */
6662         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6663
6664         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6665         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6666                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6667
6668         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6669         I915_WRITE(GEN7_L3CNTLREG1,
6670                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6671         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6672                    GEN7_WA_L3_CHICKEN_MODE);
6673         if (IS_IVB_GT1(dev))
6674                 I915_WRITE(GEN7_ROW_CHICKEN2,
6675                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6676         else {
6677                 /* must write both registers */
6678                 I915_WRITE(GEN7_ROW_CHICKEN2,
6679                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6680                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6681                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6682         }
6683
6684         /* WaForceL3Serialization:ivb */
6685         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6686                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6687
6688         /*
6689          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6690          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6691          */
6692         I915_WRITE(GEN6_UCGCTL2,
6693                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6694
6695         /* This is required by WaCatErrorRejectionIssue:ivb */
6696         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6697                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6698                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6699
6700         g4x_disable_trickle_feed(dev);
6701
6702         gen7_setup_fixed_func_scheduler(dev_priv);
6703
6704         if (0) { /* causes HiZ corruption on ivb:gt1 */
6705                 /* enable HiZ Raw Stall Optimization */
6706                 I915_WRITE(CACHE_MODE_0_GEN7,
6707                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6708         }
6709
6710         /* WaDisable4x2SubspanOptimization:ivb */
6711         I915_WRITE(CACHE_MODE_1,
6712                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6713
6714         /*
6715          * BSpec recommends 8x4 when MSAA is used,
6716          * however in practice 16x4 seems fastest.
6717          *
6718          * Note that PS/WM thread counts depend on the WIZ hashing
6719          * disable bit, which we don't touch here, but it's good
6720          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6721          */
6722         I915_WRITE(GEN7_GT_MODE,
6723                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6724
6725         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6726         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6727         snpcr |= GEN6_MBC_SNPCR_MED;
6728         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6729
6730         if (!HAS_PCH_NOP(dev))
6731                 cpt_init_clock_gating(dev);
6732
6733         gen6_check_mch_setup(dev);
6734 }
6735
6736 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6737 {
6738         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6739
6740         /*
6741          * Disable trickle feed and enable pnd deadline calculation
6742          */
6743         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6744         I915_WRITE(CBR1_VLV, 0);
6745 }
6746
6747 static void valleyview_init_clock_gating(struct drm_device *dev)
6748 {
6749         struct drm_i915_private *dev_priv = dev->dev_private;
6750
6751         vlv_init_display_clock_gating(dev_priv);
6752
6753         /* WaDisableEarlyCull:vlv */
6754         I915_WRITE(_3D_CHICKEN3,
6755                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6756
6757         /* WaDisableBackToBackFlipFix:vlv */
6758         I915_WRITE(IVB_CHICKEN3,
6759                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6760                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6761
6762         /* WaPsdDispatchEnable:vlv */
6763         /* WaDisablePSDDualDispatchEnable:vlv */
6764         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6765                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6766                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6767
6768         /* WaDisable_RenderCache_OperationalFlush:vlv */
6769         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6770
6771         /* WaForceL3Serialization:vlv */
6772         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6773                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6774
6775         /* WaDisableDopClockGating:vlv */
6776         I915_WRITE(GEN7_ROW_CHICKEN2,
6777                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6778
6779         /* This is required by WaCatErrorRejectionIssue:vlv */
6780         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6781                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6782                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6783
6784         gen7_setup_fixed_func_scheduler(dev_priv);
6785
6786         /*
6787          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6788          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6789          */
6790         I915_WRITE(GEN6_UCGCTL2,
6791                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6792
6793         /* WaDisableL3Bank2xClockGate:vlv
6794          * Disabling L3 clock gating- MMIO 940c[25] = 1
6795          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6796         I915_WRITE(GEN7_UCGCTL4,
6797                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6798
6799         /*
6800          * BSpec says this must be set, even though
6801          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6802          */
6803         I915_WRITE(CACHE_MODE_1,
6804                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6805
6806         /*
6807          * BSpec recommends 8x4 when MSAA is used,
6808          * however in practice 16x4 seems fastest.
6809          *
6810          * Note that PS/WM thread counts depend on the WIZ hashing
6811          * disable bit, which we don't touch here, but it's good
6812          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6813          */
6814         I915_WRITE(GEN7_GT_MODE,
6815                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6816
6817         /*
6818          * WaIncreaseL3CreditsForVLVB0:vlv
6819          * This is the hardware default actually.
6820          */
6821         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6822
6823         /*
6824          * WaDisableVLVClockGating_VBIIssue:vlv
6825          * Disable clock gating on th GCFG unit to prevent a delay
6826          * in the reporting of vblank events.
6827          */
6828         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6829 }
6830
6831 static void cherryview_init_clock_gating(struct drm_device *dev)
6832 {
6833         struct drm_i915_private *dev_priv = dev->dev_private;
6834
6835         vlv_init_display_clock_gating(dev_priv);
6836
6837         /* WaVSRefCountFullforceMissDisable:chv */
6838         /* WaDSRefCountFullforceMissDisable:chv */
6839         I915_WRITE(GEN7_FF_THREAD_MODE,
6840                    I915_READ(GEN7_FF_THREAD_MODE) &
6841                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6842
6843         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6844         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6845                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6846
6847         /* WaDisableCSUnitClockGating:chv */
6848         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6849                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6850
6851         /* WaDisableSDEUnitClockGating:chv */
6852         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6853                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6854
6855         /*
6856          * GTT cache may not work with big pages, so if those
6857          * are ever enabled GTT cache may need to be disabled.
6858          */
6859         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6860 }
6861
6862 static void g4x_init_clock_gating(struct drm_device *dev)
6863 {
6864         struct drm_i915_private *dev_priv = dev->dev_private;
6865         uint32_t dspclk_gate;
6866
6867         I915_WRITE(RENCLK_GATE_D1, 0);
6868         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6869                    GS_UNIT_CLOCK_GATE_DISABLE |
6870                    CL_UNIT_CLOCK_GATE_DISABLE);
6871         I915_WRITE(RAMCLK_GATE_D, 0);
6872         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6873                 OVRUNIT_CLOCK_GATE_DISABLE |
6874                 OVCUNIT_CLOCK_GATE_DISABLE;
6875         if (IS_GM45(dev))
6876                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6877         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6878
6879         /* WaDisableRenderCachePipelinedFlush */
6880         I915_WRITE(CACHE_MODE_0,
6881                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6882
6883         /* WaDisable_RenderCache_OperationalFlush:g4x */
6884         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6885
6886         g4x_disable_trickle_feed(dev);
6887 }
6888
6889 static void crestline_init_clock_gating(struct drm_device *dev)
6890 {
6891         struct drm_i915_private *dev_priv = dev->dev_private;
6892
6893         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6894         I915_WRITE(RENCLK_GATE_D2, 0);
6895         I915_WRITE(DSPCLK_GATE_D, 0);
6896         I915_WRITE(RAMCLK_GATE_D, 0);
6897         I915_WRITE16(DEUC, 0);
6898         I915_WRITE(MI_ARB_STATE,
6899                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6900
6901         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6902         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6903 }
6904
6905 static void broadwater_init_clock_gating(struct drm_device *dev)
6906 {
6907         struct drm_i915_private *dev_priv = dev->dev_private;
6908
6909         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6910                    I965_RCC_CLOCK_GATE_DISABLE |
6911                    I965_RCPB_CLOCK_GATE_DISABLE |
6912                    I965_ISC_CLOCK_GATE_DISABLE |
6913                    I965_FBC_CLOCK_GATE_DISABLE);
6914         I915_WRITE(RENCLK_GATE_D2, 0);
6915         I915_WRITE(MI_ARB_STATE,
6916                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6917
6918         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6919         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6920 }
6921
6922 static void gen3_init_clock_gating(struct drm_device *dev)
6923 {
6924         struct drm_i915_private *dev_priv = dev->dev_private;
6925         u32 dstate = I915_READ(D_STATE);
6926
6927         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6928                 DSTATE_DOT_CLOCK_GATING;
6929         I915_WRITE(D_STATE, dstate);
6930
6931         if (IS_PINEVIEW(dev))
6932                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6933
6934         /* IIR "flip pending" means done if this bit is set */
6935         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6936
6937         /* interrupts should cause a wake up from C3 */
6938         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6939
6940         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6941         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6942
6943         I915_WRITE(MI_ARB_STATE,
6944                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6945 }
6946
6947 static void i85x_init_clock_gating(struct drm_device *dev)
6948 {
6949         struct drm_i915_private *dev_priv = dev->dev_private;
6950
6951         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6952
6953         /* interrupts should cause a wake up from C3 */
6954         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6955                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6956
6957         I915_WRITE(MEM_MODE,
6958                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6959 }
6960
6961 static void i830_init_clock_gating(struct drm_device *dev)
6962 {
6963         struct drm_i915_private *dev_priv = dev->dev_private;
6964
6965         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6966
6967         I915_WRITE(MEM_MODE,
6968                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6969                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6970 }
6971
6972 void intel_init_clock_gating(struct drm_device *dev)
6973 {
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975
6976         if (dev_priv->display.init_clock_gating)
6977                 dev_priv->display.init_clock_gating(dev);
6978 }
6979
6980 void intel_suspend_hw(struct drm_device *dev)
6981 {
6982         if (HAS_PCH_LPT(dev))
6983                 lpt_suspend_hw(dev);
6984 }
6985
6986 /* Set up chip specific power management-related functions */
6987 void intel_init_pm(struct drm_device *dev)
6988 {
6989         struct drm_i915_private *dev_priv = dev->dev_private;
6990
6991         intel_fbc_init(dev_priv);
6992
6993         /* For cxsr */
6994         if (IS_PINEVIEW(dev))
6995                 i915_pineview_get_mem_freq(dev);
6996         else if (IS_GEN5(dev))
6997                 i915_ironlake_get_mem_freq(dev);
6998
6999         /* For FIFO watermark updates */
7000         if (INTEL_INFO(dev)->gen >= 9) {
7001                 skl_setup_wm_latency(dev);
7002
7003                 if (IS_BROXTON(dev))
7004                         dev_priv->display.init_clock_gating =
7005                                 bxt_init_clock_gating;
7006                 else if (IS_SKYLAKE(dev))
7007                         dev_priv->display.init_clock_gating =
7008                                 skl_init_clock_gating;
7009                 dev_priv->display.update_wm = skl_update_wm;
7010         } else if (HAS_PCH_SPLIT(dev)) {
7011                 ilk_setup_wm_latency(dev);
7012
7013                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7014                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7015                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7016                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7017                         dev_priv->display.update_wm = ilk_update_wm;
7018                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7019                 } else {
7020                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7021                                       "Disable CxSR\n");
7022                 }
7023
7024                 if (IS_GEN5(dev))
7025                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7026                 else if (IS_GEN6(dev))
7027                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7028                 else if (IS_IVYBRIDGE(dev))
7029                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7030                 else if (IS_HASWELL(dev))
7031                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7032                 else if (INTEL_INFO(dev)->gen == 8)
7033                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7034         } else if (IS_CHERRYVIEW(dev)) {
7035                 vlv_setup_wm_latency(dev);
7036
7037                 dev_priv->display.update_wm = vlv_update_wm;
7038                 dev_priv->display.init_clock_gating =
7039                         cherryview_init_clock_gating;
7040         } else if (IS_VALLEYVIEW(dev)) {
7041                 vlv_setup_wm_latency(dev);
7042
7043                 dev_priv->display.update_wm = vlv_update_wm;
7044                 dev_priv->display.init_clock_gating =
7045                         valleyview_init_clock_gating;
7046         } else if (IS_PINEVIEW(dev)) {
7047                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7048                                             dev_priv->is_ddr3,
7049                                             dev_priv->fsb_freq,
7050                                             dev_priv->mem_freq)) {
7051                         DRM_INFO("failed to find known CxSR latency "
7052                                  "(found ddr%s fsb freq %d, mem freq %d), "
7053                                  "disabling CxSR\n",
7054                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7055                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7056                         /* Disable CxSR and never update its watermark again */
7057                         intel_set_memory_cxsr(dev_priv, false);
7058                         dev_priv->display.update_wm = NULL;
7059                 } else
7060                         dev_priv->display.update_wm = pineview_update_wm;
7061                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7062         } else if (IS_G4X(dev)) {
7063                 dev_priv->display.update_wm = g4x_update_wm;
7064                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7065         } else if (IS_GEN4(dev)) {
7066                 dev_priv->display.update_wm = i965_update_wm;
7067                 if (IS_CRESTLINE(dev))
7068                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7069                 else if (IS_BROADWATER(dev))
7070                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7071         } else if (IS_GEN3(dev)) {
7072                 dev_priv->display.update_wm = i9xx_update_wm;
7073                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7074                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7075         } else if (IS_GEN2(dev)) {
7076                 if (INTEL_INFO(dev)->num_pipes == 1) {
7077                         dev_priv->display.update_wm = i845_update_wm;
7078                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7079                 } else {
7080                         dev_priv->display.update_wm = i9xx_update_wm;
7081                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7082                 }
7083
7084                 if (IS_I85X(dev) || IS_I865G(dev))
7085                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7086                 else
7087                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7088         } else {
7089                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7090         }
7091 }
7092
7093 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7094 {
7095         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7096
7097         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7098                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7099                 return -EAGAIN;
7100         }
7101
7102         I915_WRITE(GEN6_PCODE_DATA, *val);
7103         I915_WRITE(GEN6_PCODE_DATA1, 0);
7104         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7105
7106         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7107                      500)) {
7108                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7109                 return -ETIMEDOUT;
7110         }
7111
7112         *val = I915_READ(GEN6_PCODE_DATA);
7113         I915_WRITE(GEN6_PCODE_DATA, 0);
7114
7115         return 0;
7116 }
7117
7118 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7119 {
7120         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7121
7122         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7123                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7124                 return -EAGAIN;
7125         }
7126
7127         I915_WRITE(GEN6_PCODE_DATA, val);
7128         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7129
7130         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7131                      500)) {
7132                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7133                 return -ETIMEDOUT;
7134         }
7135
7136         I915_WRITE(GEN6_PCODE_DATA, 0);
7137
7138         return 0;
7139 }
7140
7141 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7142 {
7143         switch (czclk_freq) {
7144         case 200:
7145                 return 10;
7146         case 267:
7147                 return 12;
7148         case 320:
7149         case 333:
7150                 return 16;
7151         case 400:
7152                 return 20;
7153         default:
7154                 return -1;
7155         }
7156 }
7157
7158 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7159 {
7160         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7161
7162         div = vlv_gpu_freq_div(czclk_freq);
7163         if (div < 0)
7164                 return div;
7165
7166         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7167 }
7168
7169 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7170 {
7171         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7172
7173         mul = vlv_gpu_freq_div(czclk_freq);
7174         if (mul < 0)
7175                 return mul;
7176
7177         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7178 }
7179
7180 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7181 {
7182         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7183
7184         div = vlv_gpu_freq_div(czclk_freq) / 2;
7185         if (div < 0)
7186                 return div;
7187
7188         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7189 }
7190
7191 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7192 {
7193         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7194
7195         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7196         if (mul < 0)
7197                 return mul;
7198
7199         /* CHV needs even values */
7200         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7201 }
7202
7203 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7204 {
7205         if (IS_GEN9(dev_priv->dev))
7206                 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7207         else if (IS_CHERRYVIEW(dev_priv->dev))
7208                 return chv_gpu_freq(dev_priv, val);
7209         else if (IS_VALLEYVIEW(dev_priv->dev))
7210                 return byt_gpu_freq(dev_priv, val);
7211         else
7212                 return val * GT_FREQUENCY_MULTIPLIER;
7213 }
7214
7215 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7216 {
7217         if (IS_GEN9(dev_priv->dev))
7218                 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7219         else if (IS_CHERRYVIEW(dev_priv->dev))
7220                 return chv_freq_opcode(dev_priv, val);
7221         else if (IS_VALLEYVIEW(dev_priv->dev))
7222                 return byt_freq_opcode(dev_priv, val);
7223         else
7224                 return val / GT_FREQUENCY_MULTIPLIER;
7225 }
7226
7227 struct request_boost {
7228         struct work_struct work;
7229         struct drm_i915_gem_request *req;
7230 };
7231
7232 static void __intel_rps_boost_work(struct work_struct *work)
7233 {
7234         struct request_boost *boost = container_of(work, struct request_boost, work);
7235         struct drm_i915_gem_request *req = boost->req;
7236
7237         if (!i915_gem_request_completed(req, true))
7238                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7239                                req->emitted_jiffies);
7240
7241         i915_gem_request_unreference__unlocked(req);
7242         kfree(boost);
7243 }
7244
7245 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7246                                        struct drm_i915_gem_request *req)
7247 {
7248         struct request_boost *boost;
7249
7250         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7251                 return;
7252
7253         if (i915_gem_request_completed(req, true))
7254                 return;
7255
7256         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7257         if (boost == NULL)
7258                 return;
7259
7260         i915_gem_request_reference(req);
7261         boost->req = req;
7262
7263         INIT_WORK(&boost->work, __intel_rps_boost_work);
7264         queue_work(to_i915(dev)->wq, &boost->work);
7265 }
7266
7267 void intel_pm_setup(struct drm_device *dev)
7268 {
7269         struct drm_i915_private *dev_priv = dev->dev_private;
7270
7271         mutex_init(&dev_priv->rps.hw_lock);
7272         spin_lock_init(&dev_priv->rps.client_lock);
7273
7274         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7275                           intel_gen6_powersave_work);
7276         INIT_LIST_HEAD(&dev_priv->rps.clients);
7277         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7278         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7279
7280         dev_priv->pm.suspended = false;
7281 }