drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static bool intel_crtc_active(struct drm_crtc *crtc)
  48 {
  49         /* Be paranoid as we can arrive here with only partial
  50          * state retrieved from the hardware during setup.
  51          */
  52         return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  53 }
  54
  55 static void i8xx_disable_fbc(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         u32 fbc_ctl;
  59
  60         /* Disable compression */
  61         fbc_ctl = I915_READ(FBC_CONTROL);
  62         if ((fbc_ctl & FBC_CTL_EN) == 0)
  63                 return;
  64
  65         fbc_ctl &= ~FBC_CTL_EN;
  66         I915_WRITE(FBC_CONTROL, fbc_ctl);
  67
  68         /* Wait for compressing bit to clear */
  69         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  70                 DRM_DEBUG_KMS("FBC idle timed out\n");
  71                 return;
  72         }
  73
  74         DRM_DEBUG_KMS("disabled FBC\n");
  75 }
  76
  77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  78 {
  79         struct drm_device *dev = crtc->dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct drm_framebuffer *fb = crtc->fb;
  82         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  83         struct drm_i915_gem_object *obj = intel_fb->obj;
  84         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  85         int cfb_pitch;
  86         int plane, i;
  87         u32 fbc_ctl, fbc_ctl2;
  88
  89         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  90         if (fb->pitches[0] < cfb_pitch)
  91                 cfb_pitch = fb->pitches[0];
  92
  93         /* FBC_CTL wants 64B units */
  94         cfb_pitch = (cfb_pitch / 64) - 1;
  95         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  96
  97         /* Clear old tags */
  98         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  99                 I915_WRITE(FBC_TAG + (i * 4), 0);
 100
 101         /* Set it up... */
 102         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 103         fbc_ctl2 |= plane;
 104         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 105         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 106
 107         /* enable it... */
 108         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 109         if (IS_I945GM(dev))
 110                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 111         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 112         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 113         fbc_ctl |= obj->fence_reg;
 114         I915_WRITE(FBC_CONTROL, fbc_ctl);
 115
 116         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 117                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 118 }
 119
 120 static bool i8xx_fbc_enabled(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123
 124         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 125 }
 126
 127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 128 {
 129         struct drm_device *dev = crtc->dev;
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         struct drm_framebuffer *fb = crtc->fb;
 132         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 133         struct drm_i915_gem_object *obj = intel_fb->obj;
 134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 135         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 136         unsigned long stall_watermark = 200;
 137         u32 dpfc_ctl;
 138
 139         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 140         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 141         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 142
 143         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 144                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 145                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 146         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 147
 148         /* enable it... */
 149         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 150
 151         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 152 }
 153
 154 static void g4x_disable_fbc(struct drm_device *dev)
 155 {
 156         struct drm_i915_private *dev_priv = dev->dev_private;
 157         u32 dpfc_ctl;
 158
 159         /* Disable compression */
 160         dpfc_ctl = I915_READ(DPFC_CONTROL);
 161         if (dpfc_ctl & DPFC_CTL_EN) {
 162                 dpfc_ctl &= ~DPFC_CTL_EN;
 163                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 164
 165                 DRM_DEBUG_KMS("disabled FBC\n");
 166         }
 167 }
 168
 169 static bool g4x_fbc_enabled(struct drm_device *dev)
 170 {
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172
 173         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 174 }
 175
 176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 177 {
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         u32 blt_ecoskpd;
 180
 181         /* Make sure blitter notifies FBC of writes */
 182         gen6_gt_force_wake_get(dev_priv);
 183         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 184         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 185                 GEN6_BLITTER_LOCK_SHIFT;
 186         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 187         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 188         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 189         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 190                          GEN6_BLITTER_LOCK_SHIFT);
 191         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 192         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 193         gen6_gt_force_wake_put(dev_priv);
 194 }
 195
 196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 197 {
 198         struct drm_device *dev = crtc->dev;
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         struct drm_framebuffer *fb = crtc->fb;
 201         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 202         struct drm_i915_gem_object *obj = intel_fb->obj;
 203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 204         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 205         unsigned long stall_watermark = 200;
 206         u32 dpfc_ctl;
 207
 208         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 209         dpfc_ctl &= DPFC_RESERVED;
 210         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 211         /* Set persistent mode for front-buffer rendering, ala X. */
 212         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 213         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 214         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 215
 216         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 217                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 218                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 219         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 220         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 221         /* enable it... */
 222         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 223
 224         if (IS_GEN6(dev)) {
 225                 I915_WRITE(SNB_DPFC_CTL_SA,
 226                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 227                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 228                 sandybridge_blit_fbc_update(dev);
 229         }
 230
 231         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 232 }
 233
 234 static void ironlake_disable_fbc(struct drm_device *dev)
 235 {
 236         struct drm_i915_private *dev_priv = dev->dev_private;
 237         u32 dpfc_ctl;
 238
 239         /* Disable compression */
 240         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 241         if (dpfc_ctl & DPFC_CTL_EN) {
 242                 dpfc_ctl &= ~DPFC_CTL_EN;
 243                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 244
 245                 DRM_DEBUG_KMS("disabled FBC\n");
 246         }
 247 }
 248
 249 static bool ironlake_fbc_enabled(struct drm_device *dev)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252
 253         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 254 }
 255
 256 bool intel_fbc_enabled(struct drm_device *dev)
 257 {
 258         struct drm_i915_private *dev_priv = dev->dev_private;
 259
 260         if (!dev_priv->display.fbc_enabled)
 261                 return false;
 262
 263         return dev_priv->display.fbc_enabled(dev);
 264 }
 265
 266 static void intel_fbc_work_fn(struct work_struct *__work)
 267 {
 268         struct intel_fbc_work *work =
 269                 container_of(to_delayed_work(__work),
 270                              struct intel_fbc_work, work);
 271         struct drm_device *dev = work->crtc->dev;
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         mutex_lock(&dev->struct_mutex);
 275         if (work == dev_priv->fbc_work) {
 276                 /* Double check that we haven't switched fb without cancelling
 277                  * the prior work.
 278                  */
 279                 if (work->crtc->fb == work->fb) {
 280                         dev_priv->display.enable_fbc(work->crtc,
 281                                                      work->interval);
 282
 283                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 284                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 285                         dev_priv->cfb_y = work->crtc->y;
 286                 }
 287
 288                 dev_priv->fbc_work = NULL;
 289         }
 290         mutex_unlock(&dev->struct_mutex);
 291
 292         kfree(work);
 293 }
 294
 295 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 296 {
 297         if (dev_priv->fbc_work == NULL)
 298                 return;
 299
 300         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 301
 302         /* Synchronisation is provided by struct_mutex and checking of
 303          * dev_priv->fbc_work, so we can perform the cancellation
 304          * entirely asynchronously.
 305          */
 306         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 307                 /* tasklet was killed before being run, clean up */
 308                 kfree(dev_priv->fbc_work);
 309
 310         /* Mark the work as no longer wanted so that if it does
 311          * wake-up (because the work was already running and waiting
 312          * for our mutex), it will discover that is no longer
 313          * necessary to run.
 314          */
 315         dev_priv->fbc_work = NULL;
 316 }
 317
 318 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 319 {
 320         struct intel_fbc_work *work;
 321         struct drm_device *dev = crtc->dev;
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         if (!dev_priv->display.enable_fbc)
 325                 return;
 326
 327         intel_cancel_fbc_work(dev_priv);
 328
 329         work = kzalloc(sizeof *work, GFP_KERNEL);
 330         if (work == NULL) {
 331                 dev_priv->display.enable_fbc(crtc, interval);
 332                 return;
 333         }
 334
 335         work->crtc = crtc;
 336         work->fb = crtc->fb;
 337         work->interval = interval;
 338         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 339
 340         dev_priv->fbc_work = work;
 341
 342         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 343
 344         /* Delay the actual enabling to let pageflipping cease and the
 345          * display to settle before starting the compression. Note that
 346          * this delay also serves a second purpose: it allows for a
 347          * vblank to pass after disabling the FBC before we attempt
 348          * to modify the control registers.
 349          *
 350          * A more complicated solution would involve tracking vblanks
 351          * following the termination of the page-flipping sequence
 352          * and indeed performing the enable as a co-routine and not
 353          * waiting synchronously upon the vblank.
 354          */
 355         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 356 }
 357
 358 void intel_disable_fbc(struct drm_device *dev)
 359 {
 360         struct drm_i915_private *dev_priv = dev->dev_private;
 361
 362         intel_cancel_fbc_work(dev_priv);
 363
 364         if (!dev_priv->display.disable_fbc)
 365                 return;
 366
 367         dev_priv->display.disable_fbc(dev);
 368         dev_priv->cfb_plane = -1;
 369 }
 370
 371 /**
 372  * intel_update_fbc - enable/disable FBC as needed
 373  * @dev: the drm_device
 374  *
 375  * Set up the framebuffer compression hardware at mode set time.  We
 376  * enable it if possible:
 377  *   - plane A only (on pre-965)
 378  *   - no pixel mulitply/line duplication
 379  *   - no alpha buffer discard
 380  *   - no dual wide
 381  *   - framebuffer <= 2048 in width, 1536 in height
 382  *
 383  * We can't assume that any compression will take place (worst case),
 384  * so the compressed buffer has to be the same size as the uncompressed
 385  * one.  It also must reside (along with the line length buffer) in
 386  * stolen memory.
 387  *
 388  * We need to enable/disable FBC on a global basis.
 389  */
 390 void intel_update_fbc(struct drm_device *dev)
 391 {
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         struct drm_crtc *crtc = NULL, *tmp_crtc;
 394         struct intel_crtc *intel_crtc;
 395         struct drm_framebuffer *fb;
 396         struct intel_framebuffer *intel_fb;
 397         struct drm_i915_gem_object *obj;
 398         int enable_fbc;
 399
 400         if (!i915_powersave)
 401                 return;
 402
 403         if (!I915_HAS_FBC(dev))
 404                 return;
 405
 406         /*
 407          * If FBC is already on, we just have to verify that we can
 408          * keep it that way...
 409          * Need to disable if:
 410          *   - more than one pipe is active
 411          *   - changing FBC params (stride, fence, mode)
 412          *   - new fb is too large to fit in compressed buffer
 413          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 414          */
 415         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 416                 if (intel_crtc_active(tmp_crtc) &&
 417                     !to_intel_crtc(tmp_crtc)->primary_disabled) {
 418                         if (crtc) {
 419                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 420                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 421                                 goto out_disable;
 422                         }
 423                         crtc = tmp_crtc;
 424                 }
 425         }
 426
 427         if (!crtc || crtc->fb == NULL) {
 428                 DRM_DEBUG_KMS("no output, disabling\n");
 429                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 430                 goto out_disable;
 431         }
 432
 433         intel_crtc = to_intel_crtc(crtc);
 434         fb = crtc->fb;
 435         intel_fb = to_intel_framebuffer(fb);
 436         obj = intel_fb->obj;
 437
 438         enable_fbc = i915_enable_fbc;
 439         if (enable_fbc < 0) {
 440                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 441                 enable_fbc = 1;
 442                 if (INTEL_INFO(dev)->gen <= 6)
 443                         enable_fbc = 0;
 444         }
 445         if (!enable_fbc) {
 446                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 447                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 448                 goto out_disable;
 449         }
 450         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 451             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 452                 DRM_DEBUG_KMS("mode incompatible with compression, "
 453                               "disabling\n");
 454                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 455                 goto out_disable;
 456         }
 457         if ((crtc->mode.hdisplay > 2048) ||
 458             (crtc->mode.vdisplay > 1536)) {
 459                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 460                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 461                 goto out_disable;
 462         }
 463         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 464                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 465                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 466                 goto out_disable;
 467         }
 468
 469         /* The use of a CPU fence is mandatory in order to detect writes
 470          * by the CPU to the scanout and trigger updates to the FBC.
 471          */
 472         if (obj->tiling_mode != I915_TILING_X ||
 473             obj->fence_reg == I915_FENCE_REG_NONE) {
 474                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 475                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 476                 goto out_disable;
 477         }
 478
 479         /* If the kernel debugger is active, always disable compression */
 480         if (in_dbg_master())
 481                 goto out_disable;
 482
 483         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 484                 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 485                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 486                 goto out_disable;
 487         }
 488
 489         /* If the scanout has not changed, don't modify the FBC settings.
 490          * Note that we make the fundamental assumption that the fb->obj
 491          * cannot be unpinned (and have its GTT offset and fence revoked)
 492          * without first being decoupled from the scanout and FBC disabled.
 493          */
 494         if (dev_priv->cfb_plane == intel_crtc->plane &&
 495             dev_priv->cfb_fb == fb->base.id &&
 496             dev_priv->cfb_y == crtc->y)
 497                 return;
 498
 499         if (intel_fbc_enabled(dev)) {
 500                 /* We update FBC along two paths, after changing fb/crtc
 501                  * configuration (modeswitching) and after page-flipping
 502                  * finishes. For the latter, we know that not only did
 503                  * we disable the FBC at the start of the page-flip
 504                  * sequence, but also more than one vblank has passed.
 505                  *
 506                  * For the former case of modeswitching, it is possible
 507                  * to switch between two FBC valid configurations
 508                  * instantaneously so we do need to disable the FBC
 509                  * before we can modify its control registers. We also
 510                  * have to wait for the next vblank for that to take
 511                  * effect. However, since we delay enabling FBC we can
 512                  * assume that a vblank has passed since disabling and
 513                  * that we can safely alter the registers in the deferred
 514                  * callback.
 515                  *
 516                  * In the scenario that we go from a valid to invalid
 517                  * and then back to valid FBC configuration we have
 518                  * no strict enforcement that a vblank occurred since
 519                  * disabling the FBC. However, along all current pipe
 520                  * disabling paths we do need to wait for a vblank at
 521                  * some point. And we wait before enabling FBC anyway.
 522                  */
 523                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 524                 intel_disable_fbc(dev);
 525         }
 526
 527         intel_enable_fbc(crtc, 500);
 528         return;
 529
 530 out_disable:
 531         /* Multiple disables should be harmless */
 532         if (intel_fbc_enabled(dev)) {
 533                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 534                 intel_disable_fbc(dev);
 535         }
 536         i915_gem_stolen_cleanup_compression(dev);
 537 }
 538
 539 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 540 {
 541         drm_i915_private_t *dev_priv = dev->dev_private;
 542         u32 tmp;
 543
 544         tmp = I915_READ(CLKCFG);
 545
 546         switch (tmp & CLKCFG_FSB_MASK) {
 547         case CLKCFG_FSB_533:
 548                 dev_priv->fsb_freq = 533; /* 133*4 */
 549                 break;
 550         case CLKCFG_FSB_800:
 551                 dev_priv->fsb_freq = 800; /* 200*4 */
 552                 break;
 553         case CLKCFG_FSB_667:
 554                 dev_priv->fsb_freq =  667; /* 167*4 */
 555                 break;
 556         case CLKCFG_FSB_400:
 557                 dev_priv->fsb_freq = 400; /* 100*4 */
 558                 break;
 559         }
 560
 561         switch (tmp & CLKCFG_MEM_MASK) {
 562         case CLKCFG_MEM_533:
 563                 dev_priv->mem_freq = 533;
 564                 break;
 565         case CLKCFG_MEM_667:
 566                 dev_priv->mem_freq = 667;
 567                 break;
 568         case CLKCFG_MEM_800:
 569                 dev_priv->mem_freq = 800;
 570                 break;
 571         }
 572
 573         /* detect pineview DDR3 setting */
 574         tmp = I915_READ(CSHRDDR3CTL);
 575         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 576 }
 577
 578 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 579 {
 580         drm_i915_private_t *dev_priv = dev->dev_private;
 581         u16 ddrpll, csipll;
 582
 583         ddrpll = I915_READ16(DDRMPLL1);
 584         csipll = I915_READ16(CSIPLL0);
 585
 586         switch (ddrpll & 0xff) {
 587         case 0xc:
 588                 dev_priv->mem_freq = 800;
 589                 break;
 590         case 0x10:
 591                 dev_priv->mem_freq = 1066;
 592                 break;
 593         case 0x14:
 594                 dev_priv->mem_freq = 1333;
 595                 break;
 596         case 0x18:
 597                 dev_priv->mem_freq = 1600;
 598                 break;
 599         default:
 600                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 601                                  ddrpll & 0xff);
 602                 dev_priv->mem_freq = 0;
 603                 break;
 604         }
 605
 606         dev_priv->ips.r_t = dev_priv->mem_freq;
 607
 608         switch (csipll & 0x3ff) {
 609         case 0x00c:
 610                 dev_priv->fsb_freq = 3200;
 611                 break;
 612         case 0x00e:
 613                 dev_priv->fsb_freq = 3733;
 614                 break;
 615         case 0x010:
 616                 dev_priv->fsb_freq = 4266;
 617                 break;
 618         case 0x012:
 619                 dev_priv->fsb_freq = 4800;
 620                 break;
 621         case 0x014:
 622                 dev_priv->fsb_freq = 5333;
 623                 break;
 624         case 0x016:
 625                 dev_priv->fsb_freq = 5866;
 626                 break;
 627         case 0x018:
 628                 dev_priv->fsb_freq = 6400;
 629                 break;
 630         default:
 631                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 632                                  csipll & 0x3ff);
 633                 dev_priv->fsb_freq = 0;
 634                 break;
 635         }
 636
 637         if (dev_priv->fsb_freq == 3200) {
 638                 dev_priv->ips.c_m = 0;
 639         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 640                 dev_priv->ips.c_m = 1;
 641         } else {
 642                 dev_priv->ips.c_m = 2;
 643         }
 644 }
 645
 646 static const struct cxsr_latency cxsr_latency_table[] = {
 647         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 648         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 649         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 650         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 651         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 652
 653         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 654         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 655         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 656         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 657         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 658
 659         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 660         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 661         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 662         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 663         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 664
 665         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 666         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 667         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 668         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 669         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 670
 671         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 672         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 673         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 674         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 675         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 676
 677         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 678         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 679         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 680         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 681         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 682 };
 683
 684 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 685                                                          int is_ddr3,
 686                                                          int fsb,
 687                                                          int mem)
 688 {
 689         const struct cxsr_latency *latency;
 690         int i;
 691
 692         if (fsb == 0 || mem == 0)
 693                 return NULL;
 694
 695         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 696                 latency = &cxsr_latency_table[i];
 697                 if (is_desktop == latency->is_desktop &&
 698                     is_ddr3 == latency->is_ddr3 &&
 699                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 700                         return latency;
 701         }
 702
 703         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 704
 705         return NULL;
 706 }
 707
 708 static void pineview_disable_cxsr(struct drm_device *dev)
 709 {
 710         struct drm_i915_private *dev_priv = dev->dev_private;
 711
 712         /* deactivate cxsr */
 713         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 714 }
 715
 716 /*
 717  * Latency for FIFO fetches is dependent on several factors:
 718  *   - memory configuration (speed, channels)
 719  *   - chipset
 720  *   - current MCH state
 721  * It can be fairly high in some situations, so here we assume a fairly
 722  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 723  * set this value too high, the FIFO will fetch frequently to stay full)
 724  * and power consumption (set it too low to save power and we might see
 725  * FIFO underruns and display "flicker").
 726  *
 727  * A value of 5us seems to be a good balance; safe for very low end
 728  * platforms but not overly aggressive on lower latency configs.
 729  */
 730 static const int latency_ns = 5000;
 731
 732 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 733 {
 734         struct drm_i915_private *dev_priv = dev->dev_private;
 735         uint32_t dsparb = I915_READ(DSPARB);
 736         int size;
 737
 738         size = dsparb & 0x7f;
 739         if (plane)
 740                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 741
 742         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 743                       plane ? "B" : "A", size);
 744
 745         return size;
 746 }
 747
 748 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 749 {
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751         uint32_t dsparb = I915_READ(DSPARB);
 752         int size;
 753
 754         size = dsparb & 0x1ff;
 755         if (plane)
 756                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 757         size >>= 1; /* Convert to cachelines */
 758
 759         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 760                       plane ? "B" : "A", size);
 761
 762         return size;
 763 }
 764
 765 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 766 {
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         uint32_t dsparb = I915_READ(DSPARB);
 769         int size;
 770
 771         size = dsparb & 0x7f;
 772         size >>= 2; /* Convert to cachelines */
 773
 774         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 775                       plane ? "B" : "A",
 776                       size);
 777
 778         return size;
 779 }
 780
 781 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         uint32_t dsparb = I915_READ(DSPARB);
 785         int size;
 786
 787         size = dsparb & 0x7f;
 788         size >>= 1; /* Convert to cachelines */
 789
 790         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 791                       plane ? "B" : "A", size);
 792
 793         return size;
 794 }
 795
 796 /* Pineview has different values for various configs */
 797 static const struct intel_watermark_params pineview_display_wm = {
 798         PINEVIEW_DISPLAY_FIFO,
 799         PINEVIEW_MAX_WM,
 800         PINEVIEW_DFT_WM,
 801         PINEVIEW_GUARD_WM,
 802         PINEVIEW_FIFO_LINE_SIZE
 803 };
 804 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 805         PINEVIEW_DISPLAY_FIFO,
 806         PINEVIEW_MAX_WM,
 807         PINEVIEW_DFT_HPLLOFF_WM,
 808         PINEVIEW_GUARD_WM,
 809         PINEVIEW_FIFO_LINE_SIZE
 810 };
 811 static const struct intel_watermark_params pineview_cursor_wm = {
 812         PINEVIEW_CURSOR_FIFO,
 813         PINEVIEW_CURSOR_MAX_WM,
 814         PINEVIEW_CURSOR_DFT_WM,
 815         PINEVIEW_CURSOR_GUARD_WM,
 816         PINEVIEW_FIFO_LINE_SIZE,
 817 };
 818 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 819         PINEVIEW_CURSOR_FIFO,
 820         PINEVIEW_CURSOR_MAX_WM,
 821         PINEVIEW_CURSOR_DFT_WM,
 822         PINEVIEW_CURSOR_GUARD_WM,
 823         PINEVIEW_FIFO_LINE_SIZE
 824 };
 825 static const struct intel_watermark_params g4x_wm_info = {
 826         G4X_FIFO_SIZE,
 827         G4X_MAX_WM,
 828         G4X_MAX_WM,
 829         2,
 830         G4X_FIFO_LINE_SIZE,
 831 };
 832 static const struct intel_watermark_params g4x_cursor_wm_info = {
 833         I965_CURSOR_FIFO,
 834         I965_CURSOR_MAX_WM,
 835         I965_CURSOR_DFT_WM,
 836         2,
 837         G4X_FIFO_LINE_SIZE,
 838 };
 839 static const struct intel_watermark_params valleyview_wm_info = {
 840         VALLEYVIEW_FIFO_SIZE,
 841         VALLEYVIEW_MAX_WM,
 842         VALLEYVIEW_MAX_WM,
 843         2,
 844         G4X_FIFO_LINE_SIZE,
 845 };
 846 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 847         I965_CURSOR_FIFO,
 848         VALLEYVIEW_CURSOR_MAX_WM,
 849         I965_CURSOR_DFT_WM,
 850         2,
 851         G4X_FIFO_LINE_SIZE,
 852 };
 853 static const struct intel_watermark_params i965_cursor_wm_info = {
 854         I965_CURSOR_FIFO,
 855         I965_CURSOR_MAX_WM,
 856         I965_CURSOR_DFT_WM,
 857         2,
 858         I915_FIFO_LINE_SIZE,
 859 };
 860 static const struct intel_watermark_params i945_wm_info = {
 861         I945_FIFO_SIZE,
 862         I915_MAX_WM,
 863         1,
 864         2,
 865         I915_FIFO_LINE_SIZE
 866 };
 867 static const struct intel_watermark_params i915_wm_info = {
 868         I915_FIFO_SIZE,
 869         I915_MAX_WM,
 870         1,
 871         2,
 872         I915_FIFO_LINE_SIZE
 873 };
 874 static const struct intel_watermark_params i855_wm_info = {
 875         I855GM_FIFO_SIZE,
 876         I915_MAX_WM,
 877         1,
 878         2,
 879         I830_FIFO_LINE_SIZE
 880 };
 881 static const struct intel_watermark_params i830_wm_info = {
 882         I830_FIFO_SIZE,
 883         I915_MAX_WM,
 884         1,
 885         2,
 886         I830_FIFO_LINE_SIZE
 887 };
 888
 889 static const struct intel_watermark_params ironlake_display_wm_info = {
 890         ILK_DISPLAY_FIFO,
 891         ILK_DISPLAY_MAXWM,
 892         ILK_DISPLAY_DFTWM,
 893         2,
 894         ILK_FIFO_LINE_SIZE
 895 };
 896 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 897         ILK_CURSOR_FIFO,
 898         ILK_CURSOR_MAXWM,
 899         ILK_CURSOR_DFTWM,
 900         2,
 901         ILK_FIFO_LINE_SIZE
 902 };
 903 static const struct intel_watermark_params ironlake_display_srwm_info = {
 904         ILK_DISPLAY_SR_FIFO,
 905         ILK_DISPLAY_MAX_SRWM,
 906         ILK_DISPLAY_DFT_SRWM,
 907         2,
 908         ILK_FIFO_LINE_SIZE
 909 };
 910 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 911         ILK_CURSOR_SR_FIFO,
 912         ILK_CURSOR_MAX_SRWM,
 913         ILK_CURSOR_DFT_SRWM,
 914         2,
 915         ILK_FIFO_LINE_SIZE
 916 };
 917
 918 static const struct intel_watermark_params sandybridge_display_wm_info = {
 919         SNB_DISPLAY_FIFO,
 920         SNB_DISPLAY_MAXWM,
 921         SNB_DISPLAY_DFTWM,
 922         2,
 923         SNB_FIFO_LINE_SIZE
 924 };
 925 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 926         SNB_CURSOR_FIFO,
 927         SNB_CURSOR_MAXWM,
 928         SNB_CURSOR_DFTWM,
 929         2,
 930         SNB_FIFO_LINE_SIZE
 931 };
 932 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 933         SNB_DISPLAY_SR_FIFO,
 934         SNB_DISPLAY_MAX_SRWM,
 935         SNB_DISPLAY_DFT_SRWM,
 936         2,
 937         SNB_FIFO_LINE_SIZE
 938 };
 939 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 940         SNB_CURSOR_SR_FIFO,
 941         SNB_CURSOR_MAX_SRWM,
 942         SNB_CURSOR_DFT_SRWM,
 943         2,
 944         SNB_FIFO_LINE_SIZE
 945 };
 946
 947
 948 /**
 949  * intel_calculate_wm - calculate watermark level
 950  * @clock_in_khz: pixel clock
 951  * @wm: chip FIFO params
 952  * @pixel_size: display pixel size
 953  * @latency_ns: memory latency for the platform
 954  *
 955  * Calculate the watermark level (the level at which the display plane will
 956  * start fetching from memory again).  Each chip has a different display
 957  * FIFO size and allocation, so the caller needs to figure that out and pass
 958  * in the correct intel_watermark_params structure.
 959  *
 960  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 961  * on the pixel size.  When it reaches the watermark level, it'll start
 962  * fetching FIFO line sized based chunks from memory until the FIFO fills
 963  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 964  * will occur, and a display engine hang could result.
 965  */
 966 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 967                                         const struct intel_watermark_params *wm,
 968                                         int fifo_size,
 969                                         int pixel_size,
 970                                         unsigned long latency_ns)
 971 {
 972         long entries_required, wm_size;
 973
 974         /*
 975          * Note: we need to make sure we don't overflow for various clock &
 976          * latency values.
 977          * clocks go from a few thousand to several hundred thousand.
 978          * latency is usually a few thousand
 979          */
 980         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 981                 1000;
 982         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 983
 984         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 985
 986         wm_size = fifo_size - (entries_required + wm->guard_size);
 987
 988         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 989
 990         /* Don't promote wm_size to unsigned... */
 991         if (wm_size > (long)wm->max_wm)
 992                 wm_size = wm->max_wm;
 993         if (wm_size <= 0)
 994                 wm_size = wm->default_wm;
 995         return wm_size;
 996 }
 997
 998 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 999 {
1000         struct drm_crtc *crtc, *enabled = NULL;
1001
1002         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1003                 if (intel_crtc_active(crtc)) {
1004                         if (enabled)
1005                                 return NULL;
1006                         enabled = crtc;
1007                 }
1008         }
1009
1010         return enabled;
1011 }
1012
1013 static void pineview_update_wm(struct drm_device *dev)
1014 {
1015         struct drm_i915_private *dev_priv = dev->dev_private;
1016         struct drm_crtc *crtc;
1017         const struct cxsr_latency *latency;
1018         u32 reg;
1019         unsigned long wm;
1020
1021         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1022                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1023         if (!latency) {
1024                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1025                 pineview_disable_cxsr(dev);
1026                 return;
1027         }
1028
1029         crtc = single_enabled_crtc(dev);
1030         if (crtc) {
1031                 int clock = crtc->mode.clock;
1032                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1033
1034                 /* Display SR */
1035                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1036                                         pineview_display_wm.fifo_size,
1037                                         pixel_size, latency->display_sr);
1038                 reg = I915_READ(DSPFW1);
1039                 reg &= ~DSPFW_SR_MASK;
1040                 reg |= wm << DSPFW_SR_SHIFT;
1041                 I915_WRITE(DSPFW1, reg);
1042                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1043
1044                 /* cursor SR */
1045                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1046                                         pineview_display_wm.fifo_size,
1047                                         pixel_size, latency->cursor_sr);
1048                 reg = I915_READ(DSPFW3);
1049                 reg &= ~DSPFW_CURSOR_SR_MASK;
1050                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1051                 I915_WRITE(DSPFW3, reg);
1052
1053                 /* Display HPLL off SR */
1054                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1055                                         pineview_display_hplloff_wm.fifo_size,
1056                                         pixel_size, latency->display_hpll_disable);
1057                 reg = I915_READ(DSPFW3);
1058                 reg &= ~DSPFW_HPLL_SR_MASK;
1059                 reg |= wm & DSPFW_HPLL_SR_MASK;
1060                 I915_WRITE(DSPFW3, reg);
1061
1062                 /* cursor HPLL off SR */
1063                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1064                                         pineview_display_hplloff_wm.fifo_size,
1065                                         pixel_size, latency->cursor_hpll_disable);
1066                 reg = I915_READ(DSPFW3);
1067                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1068                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1069                 I915_WRITE(DSPFW3, reg);
1070                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1071
1072                 /* activate cxsr */
1073                 I915_WRITE(DSPFW3,
1074                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1075                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1076         } else {
1077                 pineview_disable_cxsr(dev);
1078                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1079         }
1080 }
1081
1082 static bool g4x_compute_wm0(struct drm_device *dev,
1083                             int plane,
1084                             const struct intel_watermark_params *display,
1085                             int display_latency_ns,
1086                             const struct intel_watermark_params *cursor,
1087                             int cursor_latency_ns,
1088                             int *plane_wm,
1089                             int *cursor_wm)
1090 {
1091         struct drm_crtc *crtc;
1092         int htotal, hdisplay, clock, pixel_size;
1093         int line_time_us, line_count;
1094         int entries, tlb_miss;
1095
1096         crtc = intel_get_crtc_for_plane(dev, plane);
1097         if (!intel_crtc_active(crtc)) {
1098                 *cursor_wm = cursor->guard_size;
1099                 *plane_wm = display->guard_size;
1100                 return false;
1101         }
1102
1103         htotal = crtc->mode.htotal;
1104         hdisplay = crtc->mode.hdisplay;
1105         clock = crtc->mode.clock;
1106         pixel_size = crtc->fb->bits_per_pixel / 8;
1107
1108         /* Use the small buffer method to calculate plane watermark */
1109         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1110         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1111         if (tlb_miss > 0)
1112                 entries += tlb_miss;
1113         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1114         *plane_wm = entries + display->guard_size;
1115         if (*plane_wm > (int)display->max_wm)
1116                 *plane_wm = display->max_wm;
1117
1118         /* Use the large buffer method to calculate cursor watermark */
1119         line_time_us = ((htotal * 1000) / clock);
1120         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1121         entries = line_count * 64 * pixel_size;
1122         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1123         if (tlb_miss > 0)
1124                 entries += tlb_miss;
1125         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1126         *cursor_wm = entries + cursor->guard_size;
1127         if (*cursor_wm > (int)cursor->max_wm)
1128                 *cursor_wm = (int)cursor->max_wm;
1129
1130         return true;
1131 }
1132
1133 /*
1134  * Check the wm result.
1135  *
1136  * If any calculated watermark values is larger than the maximum value that
1137  * can be programmed into the associated watermark register, that watermark
1138  * must be disabled.
1139  */
1140 static bool g4x_check_srwm(struct drm_device *dev,
1141                            int display_wm, int cursor_wm,
1142                            const struct intel_watermark_params *display,
1143                            const struct intel_watermark_params *cursor)
1144 {
1145         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1146                       display_wm, cursor_wm);
1147
1148         if (display_wm > display->max_wm) {
1149                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1150                               display_wm, display->max_wm);
1151                 return false;
1152         }
1153
1154         if (cursor_wm > cursor->max_wm) {
1155                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1156                               cursor_wm, cursor->max_wm);
1157                 return false;
1158         }
1159
1160         if (!(display_wm || cursor_wm)) {
1161                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1162                 return false;
1163         }
1164
1165         return true;
1166 }
1167
1168 static bool g4x_compute_srwm(struct drm_device *dev,
1169                              int plane,
1170                              int latency_ns,
1171                              const struct intel_watermark_params *display,
1172                              const struct intel_watermark_params *cursor,
1173                              int *display_wm, int *cursor_wm)
1174 {
1175         struct drm_crtc *crtc;
1176         int hdisplay, htotal, pixel_size, clock;
1177         unsigned long line_time_us;
1178         int line_count, line_size;
1179         int small, large;
1180         int entries;
1181
1182         if (!latency_ns) {
1183                 *display_wm = *cursor_wm = 0;
1184                 return false;
1185         }
1186
1187         crtc = intel_get_crtc_for_plane(dev, plane);
1188         hdisplay = crtc->mode.hdisplay;
1189         htotal = crtc->mode.htotal;
1190         clock = crtc->mode.clock;
1191         pixel_size = crtc->fb->bits_per_pixel / 8;
1192
1193         line_time_us = (htotal * 1000) / clock;
1194         line_count = (latency_ns / line_time_us + 1000) / 1000;
1195         line_size = hdisplay * pixel_size;
1196
1197         /* Use the minimum of the small and large buffer method for primary */
1198         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1199         large = line_count * line_size;
1200
1201         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1202         *display_wm = entries + display->guard_size;
1203
1204         /* calculate the self-refresh watermark for display cursor */
1205         entries = line_count * pixel_size * 64;
1206         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1207         *cursor_wm = entries + cursor->guard_size;
1208
1209         return g4x_check_srwm(dev,
1210                               *display_wm, *cursor_wm,
1211                               display, cursor);
1212 }
1213
1214 static bool vlv_compute_drain_latency(struct drm_device *dev,
1215                                      int plane,
1216                                      int *plane_prec_mult,
1217                                      int *plane_dl,
1218                                      int *cursor_prec_mult,
1219                                      int *cursor_dl)
1220 {
1221         struct drm_crtc *crtc;
1222         int clock, pixel_size;
1223         int entries;
1224
1225         crtc = intel_get_crtc_for_plane(dev, plane);
1226         if (!intel_crtc_active(crtc))
1227                 return false;
1228
1229         clock = crtc->mode.clock;       /* VESA DOT Clock */
1230         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1231
1232         entries = (clock / 1000) * pixel_size;
1233         *plane_prec_mult = (entries > 256) ?
1234                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1235         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1236                                                      pixel_size);
1237
1238         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1239         *cursor_prec_mult = (entries > 256) ?
1240                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1241         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1242
1243         return true;
1244 }
1245
1246 /*
1247  * Update drain latency registers of memory arbiter
1248  *
1249  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1250  * to be programmed. Each plane has a drain latency multiplier and a drain
1251  * latency value.
1252  */
1253
1254 static void vlv_update_drain_latency(struct drm_device *dev)
1255 {
1256         struct drm_i915_private *dev_priv = dev->dev_private;
1257         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1258         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1259         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1260                                                         either 16 or 32 */
1261
1262         /* For plane A, Cursor A */
1263         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1264                                       &cursor_prec_mult, &cursora_dl)) {
1265                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1266                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1267                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1268                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1269
1270                 I915_WRITE(VLV_DDL1, cursora_prec |
1271                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1272                                 planea_prec | planea_dl);
1273         }
1274
1275         /* For plane B, Cursor B */
1276         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1277                                       &cursor_prec_mult, &cursorb_dl)) {
1278                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1279                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1280                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1281                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1282
1283                 I915_WRITE(VLV_DDL2, cursorb_prec |
1284                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1285                                 planeb_prec | planeb_dl);
1286         }
1287 }
1288
1289 #define single_plane_enabled(mask) is_power_of_2(mask)
1290
1291 static void valleyview_update_wm(struct drm_device *dev)
1292 {
1293         static const int sr_latency_ns = 12000;
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1296         int plane_sr, cursor_sr;
1297         int ignore_plane_sr, ignore_cursor_sr;
1298         unsigned int enabled = 0;
1299
1300         vlv_update_drain_latency(dev);
1301
1302         if (g4x_compute_wm0(dev, 0,
1303                             &valleyview_wm_info, latency_ns,
1304                             &valleyview_cursor_wm_info, latency_ns,
1305                             &planea_wm, &cursora_wm))
1306                 enabled |= 1;
1307
1308         if (g4x_compute_wm0(dev, 1,
1309                             &valleyview_wm_info, latency_ns,
1310                             &valleyview_cursor_wm_info, latency_ns,
1311                             &planeb_wm, &cursorb_wm))
1312                 enabled |= 2;
1313
1314         if (single_plane_enabled(enabled) &&
1315             g4x_compute_srwm(dev, ffs(enabled) - 1,
1316                              sr_latency_ns,
1317                              &valleyview_wm_info,
1318                              &valleyview_cursor_wm_info,
1319                              &plane_sr, &ignore_cursor_sr) &&
1320             g4x_compute_srwm(dev, ffs(enabled) - 1,
1321                              2*sr_latency_ns,
1322                              &valleyview_wm_info,
1323                              &valleyview_cursor_wm_info,
1324                              &ignore_plane_sr, &cursor_sr)) {
1325                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1326         } else {
1327                 I915_WRITE(FW_BLC_SELF_VLV,
1328                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1329                 plane_sr = cursor_sr = 0;
1330         }
1331
1332         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1333                       planea_wm, cursora_wm,
1334                       planeb_wm, cursorb_wm,
1335                       plane_sr, cursor_sr);
1336
1337         I915_WRITE(DSPFW1,
1338                    (plane_sr << DSPFW_SR_SHIFT) |
1339                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1340                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1341                    planea_wm);
1342         I915_WRITE(DSPFW2,
1343                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1344                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1345         I915_WRITE(DSPFW3,
1346                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1347                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1348 }
1349
1350 static void g4x_update_wm(struct drm_device *dev)
1351 {
1352         static const int sr_latency_ns = 12000;
1353         struct drm_i915_private *dev_priv = dev->dev_private;
1354         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1355         int plane_sr, cursor_sr;
1356         unsigned int enabled = 0;
1357
1358         if (g4x_compute_wm0(dev, 0,
1359                             &g4x_wm_info, latency_ns,
1360                             &g4x_cursor_wm_info, latency_ns,
1361                             &planea_wm, &cursora_wm))
1362                 enabled |= 1;
1363
1364         if (g4x_compute_wm0(dev, 1,
1365                             &g4x_wm_info, latency_ns,
1366                             &g4x_cursor_wm_info, latency_ns,
1367                             &planeb_wm, &cursorb_wm))
1368                 enabled |= 2;
1369
1370         if (single_plane_enabled(enabled) &&
1371             g4x_compute_srwm(dev, ffs(enabled) - 1,
1372                              sr_latency_ns,
1373                              &g4x_wm_info,
1374                              &g4x_cursor_wm_info,
1375                              &plane_sr, &cursor_sr)) {
1376                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1377         } else {
1378                 I915_WRITE(FW_BLC_SELF,
1379                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1380                 plane_sr = cursor_sr = 0;
1381         }
1382
1383         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1384                       planea_wm, cursora_wm,
1385                       planeb_wm, cursorb_wm,
1386                       plane_sr, cursor_sr);
1387
1388         I915_WRITE(DSPFW1,
1389                    (plane_sr << DSPFW_SR_SHIFT) |
1390                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1391                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1392                    planea_wm);
1393         I915_WRITE(DSPFW2,
1394                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1395                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1396         /* HPLL off in SR has some issues on G4x... disable it */
1397         I915_WRITE(DSPFW3,
1398                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1399                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1400 }
1401
1402 static void i965_update_wm(struct drm_device *dev)
1403 {
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         struct drm_crtc *crtc;
1406         int srwm = 1;
1407         int cursor_sr = 16;
1408
1409         /* Calc sr entries for one plane configs */
1410         crtc = single_enabled_crtc(dev);
1411         if (crtc) {
1412                 /* self-refresh has much higher latency */
1413                 static const int sr_latency_ns = 12000;
1414                 int clock = crtc->mode.clock;
1415                 int htotal = crtc->mode.htotal;
1416                 int hdisplay = crtc->mode.hdisplay;
1417                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1418                 unsigned long line_time_us;
1419                 int entries;
1420
1421                 line_time_us = ((htotal * 1000) / clock);
1422
1423                 /* Use ns/us then divide to preserve precision */
1424                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1425                         pixel_size * hdisplay;
1426                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1427                 srwm = I965_FIFO_SIZE - entries;
1428                 if (srwm < 0)
1429                         srwm = 1;
1430                 srwm &= 0x1ff;
1431                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1432                               entries, srwm);
1433
1434                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1435                         pixel_size * 64;
1436                 entries = DIV_ROUND_UP(entries,
1437                                           i965_cursor_wm_info.cacheline_size);
1438                 cursor_sr = i965_cursor_wm_info.fifo_size -
1439                         (entries + i965_cursor_wm_info.guard_size);
1440
1441                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1442                         cursor_sr = i965_cursor_wm_info.max_wm;
1443
1444                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1445                               "cursor %d\n", srwm, cursor_sr);
1446
1447                 if (IS_CRESTLINE(dev))
1448                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1449         } else {
1450                 /* Turn off self refresh if both pipes are enabled */
1451                 if (IS_CRESTLINE(dev))
1452                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1453                                    & ~FW_BLC_SELF_EN);
1454         }
1455
1456         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1457                       srwm);
1458
1459         /* 965 has limitations... */
1460         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1461                    (8 << 16) | (8 << 8) | (8 << 0));
1462         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1463         /* update cursor SR watermark */
1464         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1465 }
1466
1467 static void i9xx_update_wm(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470         const struct intel_watermark_params *wm_info;
1471         uint32_t fwater_lo;
1472         uint32_t fwater_hi;
1473         int cwm, srwm = 1;
1474         int fifo_size;
1475         int planea_wm, planeb_wm;
1476         struct drm_crtc *crtc, *enabled = NULL;
1477
1478         if (IS_I945GM(dev))
1479                 wm_info = &i945_wm_info;
1480         else if (!IS_GEN2(dev))
1481                 wm_info = &i915_wm_info;
1482         else
1483                 wm_info = &i855_wm_info;
1484
1485         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1486         crtc = intel_get_crtc_for_plane(dev, 0);
1487         if (intel_crtc_active(crtc)) {
1488                 int cpp = crtc->fb->bits_per_pixel / 8;
1489                 if (IS_GEN2(dev))
1490                         cpp = 4;
1491
1492                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1493                                                wm_info, fifo_size, cpp,
1494                                                latency_ns);
1495                 enabled = crtc;
1496         } else
1497                 planea_wm = fifo_size - wm_info->guard_size;
1498
1499         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1500         crtc = intel_get_crtc_for_plane(dev, 1);
1501         if (intel_crtc_active(crtc)) {
1502                 int cpp = crtc->fb->bits_per_pixel / 8;
1503                 if (IS_GEN2(dev))
1504                         cpp = 4;
1505
1506                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1507                                                wm_info, fifo_size, cpp,
1508                                                latency_ns);
1509                 if (enabled == NULL)
1510                         enabled = crtc;
1511                 else
1512                         enabled = NULL;
1513         } else
1514                 planeb_wm = fifo_size - wm_info->guard_size;
1515
1516         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1517
1518         /*
1519          * Overlay gets an aggressive default since video jitter is bad.
1520          */
1521         cwm = 2;
1522
1523         /* Play safe and disable self-refresh before adjusting watermarks. */
1524         if (IS_I945G(dev) || IS_I945GM(dev))
1525                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1526         else if (IS_I915GM(dev))
1527                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1528
1529         /* Calc sr entries for one plane configs */
1530         if (HAS_FW_BLC(dev) && enabled) {
1531                 /* self-refresh has much higher latency */
1532                 static const int sr_latency_ns = 6000;
1533                 int clock = enabled->mode.clock;
1534                 int htotal = enabled->mode.htotal;
1535                 int hdisplay = enabled->mode.hdisplay;
1536                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1537                 unsigned long line_time_us;
1538                 int entries;
1539
1540                 line_time_us = (htotal * 1000) / clock;
1541
1542                 /* Use ns/us then divide to preserve precision */
1543                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1544                         pixel_size * hdisplay;
1545                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1546                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1547                 srwm = wm_info->fifo_size - entries;
1548                 if (srwm < 0)
1549                         srwm = 1;
1550
1551                 if (IS_I945G(dev) || IS_I945GM(dev))
1552                         I915_WRITE(FW_BLC_SELF,
1553                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1554                 else if (IS_I915GM(dev))
1555                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1556         }
1557
1558         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1559                       planea_wm, planeb_wm, cwm, srwm);
1560
1561         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1562         fwater_hi = (cwm & 0x1f);
1563
1564         /* Set request length to 8 cachelines per fetch */
1565         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1566         fwater_hi = fwater_hi | (1 << 8);
1567
1568         I915_WRITE(FW_BLC, fwater_lo);
1569         I915_WRITE(FW_BLC2, fwater_hi);
1570
1571         if (HAS_FW_BLC(dev)) {
1572                 if (enabled) {
1573                         if (IS_I945G(dev) || IS_I945GM(dev))
1574                                 I915_WRITE(FW_BLC_SELF,
1575                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1576                         else if (IS_I915GM(dev))
1577                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1578                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1579                 } else
1580                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1581         }
1582 }
1583
1584 static void i830_update_wm(struct drm_device *dev)
1585 {
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct drm_crtc *crtc;
1588         uint32_t fwater_lo;
1589         int planea_wm;
1590
1591         crtc = single_enabled_crtc(dev);
1592         if (crtc == NULL)
1593                 return;
1594
1595         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1596                                        dev_priv->display.get_fifo_size(dev, 0),
1597                                        4, latency_ns);
1598         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1599         fwater_lo |= (3<<8) | planea_wm;
1600
1601         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1602
1603         I915_WRITE(FW_BLC, fwater_lo);
1604 }
1605
1606 #define ILK_LP0_PLANE_LATENCY           700
1607 #define ILK_LP0_CURSOR_LATENCY          1300
1608
1609 /*
1610  * Check the wm result.
1611  *
1612  * If any calculated watermark values is larger than the maximum value that
1613  * can be programmed into the associated watermark register, that watermark
1614  * must be disabled.
1615  */
1616 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1617                                 int fbc_wm, int display_wm, int cursor_wm,
1618                                 const struct intel_watermark_params *display,
1619                                 const struct intel_watermark_params *cursor)
1620 {
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622
1623         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1624                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1625
1626         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1627                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1628                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1629
1630                 /* fbc has it's own way to disable FBC WM */
1631                 I915_WRITE(DISP_ARB_CTL,
1632                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1633                 return false;
1634         } else if (INTEL_INFO(dev)->gen >= 6) {
1635                 /* enable FBC WM (except on ILK, where it must remain off) */
1636                 I915_WRITE(DISP_ARB_CTL,
1637                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1638         }
1639
1640         if (display_wm > display->max_wm) {
1641                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1642                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1643                 return false;
1644         }
1645
1646         if (cursor_wm > cursor->max_wm) {
1647                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1648                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1649                 return false;
1650         }
1651
1652         if (!(fbc_wm || display_wm || cursor_wm)) {
1653                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1654                 return false;
1655         }
1656
1657         return true;
1658 }
1659
1660 /*
1661  * Compute watermark values of WM[1-3],
1662  */
1663 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1664                                   int latency_ns,
1665                                   const struct intel_watermark_params *display,
1666                                   const struct intel_watermark_params *cursor,
1667                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1668 {
1669         struct drm_crtc *crtc;
1670         unsigned long line_time_us;
1671         int hdisplay, htotal, pixel_size, clock;
1672         int line_count, line_size;
1673         int small, large;
1674         int entries;
1675
1676         if (!latency_ns) {
1677                 *fbc_wm = *display_wm = *cursor_wm = 0;
1678                 return false;
1679         }
1680
1681         crtc = intel_get_crtc_for_plane(dev, plane);
1682         hdisplay = crtc->mode.hdisplay;
1683         htotal = crtc->mode.htotal;
1684         clock = crtc->mode.clock;
1685         pixel_size = crtc->fb->bits_per_pixel / 8;
1686
1687         line_time_us = (htotal * 1000) / clock;
1688         line_count = (latency_ns / line_time_us + 1000) / 1000;
1689         line_size = hdisplay * pixel_size;
1690
1691         /* Use the minimum of the small and large buffer method for primary */
1692         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1693         large = line_count * line_size;
1694
1695         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1696         *display_wm = entries + display->guard_size;
1697
1698         /*
1699          * Spec says:
1700          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1701          */
1702         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1703
1704         /* calculate the self-refresh watermark for display cursor */
1705         entries = line_count * pixel_size * 64;
1706         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1707         *cursor_wm = entries + cursor->guard_size;
1708
1709         return ironlake_check_srwm(dev, level,
1710                                    *fbc_wm, *display_wm, *cursor_wm,
1711                                    display, cursor);
1712 }
1713
1714 static void ironlake_update_wm(struct drm_device *dev)
1715 {
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         int fbc_wm, plane_wm, cursor_wm;
1718         unsigned int enabled;
1719
1720         enabled = 0;
1721         if (g4x_compute_wm0(dev, 0,
1722                             &ironlake_display_wm_info,
1723                             ILK_LP0_PLANE_LATENCY,
1724                             &ironlake_cursor_wm_info,
1725                             ILK_LP0_CURSOR_LATENCY,
1726                             &plane_wm, &cursor_wm)) {
1727                 I915_WRITE(WM0_PIPEA_ILK,
1728                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1729                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1730                               " plane %d, " "cursor: %d\n",
1731                               plane_wm, cursor_wm);
1732                 enabled |= 1;
1733         }
1734
1735         if (g4x_compute_wm0(dev, 1,
1736                             &ironlake_display_wm_info,
1737                             ILK_LP0_PLANE_LATENCY,
1738                             &ironlake_cursor_wm_info,
1739                             ILK_LP0_CURSOR_LATENCY,
1740                             &plane_wm, &cursor_wm)) {
1741                 I915_WRITE(WM0_PIPEB_ILK,
1742                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1743                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1744                               " plane %d, cursor: %d\n",
1745                               plane_wm, cursor_wm);
1746                 enabled |= 2;
1747         }
1748
1749         /*
1750          * Calculate and update the self-refresh watermark only when one
1751          * display plane is used.
1752          */
1753         I915_WRITE(WM3_LP_ILK, 0);
1754         I915_WRITE(WM2_LP_ILK, 0);
1755         I915_WRITE(WM1_LP_ILK, 0);
1756
1757         if (!single_plane_enabled(enabled))
1758                 return;
1759         enabled = ffs(enabled) - 1;
1760
1761         /* WM1 */
1762         if (!ironlake_compute_srwm(dev, 1, enabled,
1763                                    ILK_READ_WM1_LATENCY() * 500,
1764                                    &ironlake_display_srwm_info,
1765                                    &ironlake_cursor_srwm_info,
1766                                    &fbc_wm, &plane_wm, &cursor_wm))
1767                 return;
1768
1769         I915_WRITE(WM1_LP_ILK,
1770                    WM1_LP_SR_EN |
1771                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1772                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1773                    (plane_wm << WM1_LP_SR_SHIFT) |
1774                    cursor_wm);
1775
1776         /* WM2 */
1777         if (!ironlake_compute_srwm(dev, 2, enabled,
1778                                    ILK_READ_WM2_LATENCY() * 500,
1779                                    &ironlake_display_srwm_info,
1780                                    &ironlake_cursor_srwm_info,
1781                                    &fbc_wm, &plane_wm, &cursor_wm))
1782                 return;
1783
1784         I915_WRITE(WM2_LP_ILK,
1785                    WM2_LP_EN |
1786                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1787                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1788                    (plane_wm << WM1_LP_SR_SHIFT) |
1789                    cursor_wm);
1790
1791         /*
1792          * WM3 is unsupported on ILK, probably because we don't have latency
1793          * data for that power state
1794          */
1795 }
1796
1797 static void sandybridge_update_wm(struct drm_device *dev)
1798 {
1799         struct drm_i915_private *dev_priv = dev->dev_private;
1800         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1801         u32 val;
1802         int fbc_wm, plane_wm, cursor_wm;
1803         unsigned int enabled;
1804
1805         enabled = 0;
1806         if (g4x_compute_wm0(dev, 0,
1807                             &sandybridge_display_wm_info, latency,
1808                             &sandybridge_cursor_wm_info, latency,
1809                             &plane_wm, &cursor_wm)) {
1810                 val = I915_READ(WM0_PIPEA_ILK);
1811                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1812                 I915_WRITE(WM0_PIPEA_ILK, val |
1813                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1814                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1815                               " plane %d, " "cursor: %d\n",
1816                               plane_wm, cursor_wm);
1817                 enabled |= 1;
1818         }
1819
1820         if (g4x_compute_wm0(dev, 1,
1821                             &sandybridge_display_wm_info, latency,
1822                             &sandybridge_cursor_wm_info, latency,
1823                             &plane_wm, &cursor_wm)) {
1824                 val = I915_READ(WM0_PIPEB_ILK);
1825                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1826                 I915_WRITE(WM0_PIPEB_ILK, val |
1827                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1828                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1829                               " plane %d, cursor: %d\n",
1830                               plane_wm, cursor_wm);
1831                 enabled |= 2;
1832         }
1833
1834         /*
1835          * Calculate and update the self-refresh watermark only when one
1836          * display plane is used.
1837          *
1838          * SNB support 3 levels of watermark.
1839          *
1840          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1841          * and disabled in the descending order
1842          *
1843          */
1844         I915_WRITE(WM3_LP_ILK, 0);
1845         I915_WRITE(WM2_LP_ILK, 0);
1846         I915_WRITE(WM1_LP_ILK, 0);
1847
1848         if (!single_plane_enabled(enabled) ||
1849             dev_priv->sprite_scaling_enabled)
1850                 return;
1851         enabled = ffs(enabled) - 1;
1852
1853         /* WM1 */
1854         if (!ironlake_compute_srwm(dev, 1, enabled,
1855                                    SNB_READ_WM1_LATENCY() * 500,
1856                                    &sandybridge_display_srwm_info,
1857                                    &sandybridge_cursor_srwm_info,
1858                                    &fbc_wm, &plane_wm, &cursor_wm))
1859                 return;
1860
1861         I915_WRITE(WM1_LP_ILK,
1862                    WM1_LP_SR_EN |
1863                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1864                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1865                    (plane_wm << WM1_LP_SR_SHIFT) |
1866                    cursor_wm);
1867
1868         /* WM2 */
1869         if (!ironlake_compute_srwm(dev, 2, enabled,
1870                                    SNB_READ_WM2_LATENCY() * 500,
1871                                    &sandybridge_display_srwm_info,
1872                                    &sandybridge_cursor_srwm_info,
1873                                    &fbc_wm, &plane_wm, &cursor_wm))
1874                 return;
1875
1876         I915_WRITE(WM2_LP_ILK,
1877                    WM2_LP_EN |
1878                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1879                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1880                    (plane_wm << WM1_LP_SR_SHIFT) |
1881                    cursor_wm);
1882
1883         /* WM3 */
1884         if (!ironlake_compute_srwm(dev, 3, enabled,
1885                                    SNB_READ_WM3_LATENCY() * 500,
1886                                    &sandybridge_display_srwm_info,
1887                                    &sandybridge_cursor_srwm_info,
1888                                    &fbc_wm, &plane_wm, &cursor_wm))
1889                 return;
1890
1891         I915_WRITE(WM3_LP_ILK,
1892                    WM3_LP_EN |
1893                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1894                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1895                    (plane_wm << WM1_LP_SR_SHIFT) |
1896                    cursor_wm);
1897 }
1898
1899 static void ivybridge_update_wm(struct drm_device *dev)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1903         u32 val;
1904         int fbc_wm, plane_wm, cursor_wm;
1905         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1906         unsigned int enabled;
1907
1908         enabled = 0;
1909         if (g4x_compute_wm0(dev, 0,
1910                             &sandybridge_display_wm_info, latency,
1911                             &sandybridge_cursor_wm_info, latency,
1912                             &plane_wm, &cursor_wm)) {
1913                 val = I915_READ(WM0_PIPEA_ILK);
1914                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1915                 I915_WRITE(WM0_PIPEA_ILK, val |
1916                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1917                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1918                               " plane %d, " "cursor: %d\n",
1919                               plane_wm, cursor_wm);
1920                 enabled |= 1;
1921         }
1922
1923         if (g4x_compute_wm0(dev, 1,
1924                             &sandybridge_display_wm_info, latency,
1925                             &sandybridge_cursor_wm_info, latency,
1926                             &plane_wm, &cursor_wm)) {
1927                 val = I915_READ(WM0_PIPEB_ILK);
1928                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1929                 I915_WRITE(WM0_PIPEB_ILK, val |
1930                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1931                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1932                               " plane %d, cursor: %d\n",
1933                               plane_wm, cursor_wm);
1934                 enabled |= 2;
1935         }
1936
1937         if (g4x_compute_wm0(dev, 2,
1938                             &sandybridge_display_wm_info, latency,
1939                             &sandybridge_cursor_wm_info, latency,
1940                             &plane_wm, &cursor_wm)) {
1941                 val = I915_READ(WM0_PIPEC_IVB);
1942                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1943                 I915_WRITE(WM0_PIPEC_IVB, val |
1944                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1945                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1946                               " plane %d, cursor: %d\n",
1947                               plane_wm, cursor_wm);
1948                 enabled |= 3;
1949         }
1950
1951         /*
1952          * Calculate and update the self-refresh watermark only when one
1953          * display plane is used.
1954          *
1955          * SNB support 3 levels of watermark.
1956          *
1957          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1958          * and disabled in the descending order
1959          *
1960          */
1961         I915_WRITE(WM3_LP_ILK, 0);
1962         I915_WRITE(WM2_LP_ILK, 0);
1963         I915_WRITE(WM1_LP_ILK, 0);
1964
1965         if (!single_plane_enabled(enabled) ||
1966             dev_priv->sprite_scaling_enabled)
1967                 return;
1968         enabled = ffs(enabled) - 1;
1969
1970         /* WM1 */
1971         if (!ironlake_compute_srwm(dev, 1, enabled,
1972                                    SNB_READ_WM1_LATENCY() * 500,
1973                                    &sandybridge_display_srwm_info,
1974                                    &sandybridge_cursor_srwm_info,
1975                                    &fbc_wm, &plane_wm, &cursor_wm))
1976                 return;
1977
1978         I915_WRITE(WM1_LP_ILK,
1979                    WM1_LP_SR_EN |
1980                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1981                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1982                    (plane_wm << WM1_LP_SR_SHIFT) |
1983                    cursor_wm);
1984
1985         /* WM2 */
1986         if (!ironlake_compute_srwm(dev, 2, enabled,
1987                                    SNB_READ_WM2_LATENCY() * 500,
1988                                    &sandybridge_display_srwm_info,
1989                                    &sandybridge_cursor_srwm_info,
1990                                    &fbc_wm, &plane_wm, &cursor_wm))
1991                 return;
1992
1993         I915_WRITE(WM2_LP_ILK,
1994                    WM2_LP_EN |
1995                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1996                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1997                    (plane_wm << WM1_LP_SR_SHIFT) |
1998                    cursor_wm);
1999
2000         /* WM3, note we have to correct the cursor latency */
2001         if (!ironlake_compute_srwm(dev, 3, enabled,
2002                                    SNB_READ_WM3_LATENCY() * 500,
2003                                    &sandybridge_display_srwm_info,
2004                                    &sandybridge_cursor_srwm_info,
2005                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2006             !ironlake_compute_srwm(dev, 3, enabled,
2007                                    2 * SNB_READ_WM3_LATENCY() * 500,
2008                                    &sandybridge_display_srwm_info,
2009                                    &sandybridge_cursor_srwm_info,
2010                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2011                 return;
2012
2013         I915_WRITE(WM3_LP_ILK,
2014                    WM3_LP_EN |
2015                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2016                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2017                    (plane_wm << WM1_LP_SR_SHIFT) |
2018                    cursor_wm);
2019 }
2020
2021 static void
2022 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2023                                  struct drm_display_mode *mode)
2024 {
2025         struct drm_i915_private *dev_priv = dev->dev_private;
2026         u32 temp;
2027
2028         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2029         temp &= ~PIPE_WM_LINETIME_MASK;
2030
2031         /* The WM are computed with base on how long it takes to fill a single
2032          * row at the given clock rate, multiplied by 8.
2033          * */
2034         temp |= PIPE_WM_LINETIME_TIME(
2035                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2036
2037         /* IPS watermarks are only used by pipe A, and are ignored by
2038          * pipes B and C.  They are calculated similarly to the common
2039          * linetime values, except that we are using CD clock frequency
2040          * in MHz instead of pixel rate for the division.
2041          *
2042          * This is a placeholder for the IPS watermark calculation code.
2043          */
2044
2045         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2046 }
2047
2048 static bool
2049 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2050                               uint32_t sprite_width, int pixel_size,
2051                               const struct intel_watermark_params *display,
2052                               int display_latency_ns, int *sprite_wm)
2053 {
2054         struct drm_crtc *crtc;
2055         int clock;
2056         int entries, tlb_miss;
2057
2058         crtc = intel_get_crtc_for_plane(dev, plane);
2059         if (!intel_crtc_active(crtc)) {
2060                 *sprite_wm = display->guard_size;
2061                 return false;
2062         }
2063
2064         clock = crtc->mode.clock;
2065
2066         /* Use the small buffer method to calculate the sprite watermark */
2067         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2068         tlb_miss = display->fifo_size*display->cacheline_size -
2069                 sprite_width * 8;
2070         if (tlb_miss > 0)
2071                 entries += tlb_miss;
2072         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2073         *sprite_wm = entries + display->guard_size;
2074         if (*sprite_wm > (int)display->max_wm)
2075                 *sprite_wm = display->max_wm;
2076
2077         return true;
2078 }
2079
2080 static bool
2081 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2082                                 uint32_t sprite_width, int pixel_size,
2083                                 const struct intel_watermark_params *display,
2084                                 int latency_ns, int *sprite_wm)
2085 {
2086         struct drm_crtc *crtc;
2087         unsigned long line_time_us;
2088         int clock;
2089         int line_count, line_size;
2090         int small, large;
2091         int entries;
2092
2093         if (!latency_ns) {
2094                 *sprite_wm = 0;
2095                 return false;
2096         }
2097
2098         crtc = intel_get_crtc_for_plane(dev, plane);
2099         clock = crtc->mode.clock;
2100         if (!clock) {
2101                 *sprite_wm = 0;
2102                 return false;
2103         }
2104
2105         line_time_us = (sprite_width * 1000) / clock;
2106         if (!line_time_us) {
2107                 *sprite_wm = 0;
2108                 return false;
2109         }
2110
2111         line_count = (latency_ns / line_time_us + 1000) / 1000;
2112         line_size = sprite_width * pixel_size;
2113
2114         /* Use the minimum of the small and large buffer method for primary */
2115         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2116         large = line_count * line_size;
2117
2118         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2119         *sprite_wm = entries + display->guard_size;
2120
2121         return *sprite_wm > 0x3ff ? false : true;
2122 }
2123
2124 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2125                                          uint32_t sprite_width, int pixel_size)
2126 {
2127         struct drm_i915_private *dev_priv = dev->dev_private;
2128         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2129         u32 val;
2130         int sprite_wm, reg;
2131         int ret;
2132
2133         switch (pipe) {
2134         case 0:
2135                 reg = WM0_PIPEA_ILK;
2136                 break;
2137         case 1:
2138                 reg = WM0_PIPEB_ILK;
2139                 break;
2140         case 2:
2141                 reg = WM0_PIPEC_IVB;
2142                 break;
2143         default:
2144                 return; /* bad pipe */
2145         }
2146
2147         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2148                                             &sandybridge_display_wm_info,
2149                                             latency, &sprite_wm);
2150         if (!ret) {
2151                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2152                               pipe_name(pipe));
2153                 return;
2154         }
2155
2156         val = I915_READ(reg);
2157         val &= ~WM0_PIPE_SPRITE_MASK;
2158         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2159         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2160
2161
2162         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2163                                               pixel_size,
2164                                               &sandybridge_display_srwm_info,
2165                                               SNB_READ_WM1_LATENCY() * 500,
2166                                               &sprite_wm);
2167         if (!ret) {
2168                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2169                               pipe_name(pipe));
2170                 return;
2171         }
2172         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2173
2174         /* Only IVB has two more LP watermarks for sprite */
2175         if (!IS_IVYBRIDGE(dev))
2176                 return;
2177
2178         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2179                                               pixel_size,
2180                                               &sandybridge_display_srwm_info,
2181                                               SNB_READ_WM2_LATENCY() * 500,
2182                                               &sprite_wm);
2183         if (!ret) {
2184                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2185                               pipe_name(pipe));
2186                 return;
2187         }
2188         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2189
2190         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2191                                               pixel_size,
2192                                               &sandybridge_display_srwm_info,
2193                                               SNB_READ_WM3_LATENCY() * 500,
2194                                               &sprite_wm);
2195         if (!ret) {
2196                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2197                               pipe_name(pipe));
2198                 return;
2199         }
2200         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2201 }
2202
2203 /**
2204  * intel_update_watermarks - update FIFO watermark values based on current modes
2205  *
2206  * Calculate watermark values for the various WM regs based on current mode
2207  * and plane configuration.
2208  *
2209  * There are several cases to deal with here:
2210  *   - normal (i.e. non-self-refresh)
2211  *   - self-refresh (SR) mode
2212  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2213  *   - lines are small relative to FIFO size (buffer can hold more than 2
2214  *     lines), so need to account for TLB latency
2215  *
2216  *   The normal calculation is:
2217  *     watermark = dotclock * bytes per pixel * latency
2218  *   where latency is platform & configuration dependent (we assume pessimal
2219  *   values here).
2220  *
2221  *   The SR calculation is:
2222  *     watermark = (trunc(latency/line time)+1) * surface width *
2223  *       bytes per pixel
2224  *   where
2225  *     line time = htotal / dotclock
2226  *     surface width = hdisplay for normal plane and 64 for cursor
2227  *   and latency is assumed to be high, as above.
2228  *
2229  * The final value programmed to the register should always be rounded up,
2230  * and include an extra 2 entries to account for clock crossings.
2231  *
2232  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2233  * to set the non-SR watermarks to 8.
2234  */
2235 void intel_update_watermarks(struct drm_device *dev)
2236 {
2237         struct drm_i915_private *dev_priv = dev->dev_private;
2238
2239         if (dev_priv->display.update_wm)
2240                 dev_priv->display.update_wm(dev);
2241 }
2242
2243 void intel_update_linetime_watermarks(struct drm_device *dev,
2244                 int pipe, struct drm_display_mode *mode)
2245 {
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248         if (dev_priv->display.update_linetime_wm)
2249                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2250 }
2251
2252 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2253                                     uint32_t sprite_width, int pixel_size)
2254 {
2255         struct drm_i915_private *dev_priv = dev->dev_private;
2256
2257         if (dev_priv->display.update_sprite_wm)
2258                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2259                                                    pixel_size);
2260 }
2261
2262 static struct drm_i915_gem_object *
2263 intel_alloc_context_page(struct drm_device *dev)
2264 {
2265         struct drm_i915_gem_object *ctx;
2266         int ret;
2267
2268         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2269
2270         ctx = i915_gem_alloc_object(dev, 4096);
2271         if (!ctx) {
2272                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2273                 return NULL;
2274         }
2275
2276         ret = i915_gem_object_pin(ctx, 4096, true, false);
2277         if (ret) {
2278                 DRM_ERROR("failed to pin power context: %d\n", ret);
2279                 goto err_unref;
2280         }
2281
2282         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2283         if (ret) {
2284                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2285                 goto err_unpin;
2286         }
2287
2288         return ctx;
2289
2290 err_unpin:
2291         i915_gem_object_unpin(ctx);
2292 err_unref:
2293         drm_gem_object_unreference(&ctx->base);
2294         return NULL;
2295 }
2296
2297 /**
2298  * Lock protecting IPS related data structures
2299  */
2300 DEFINE_SPINLOCK(mchdev_lock);
2301
2302 /* Global for IPS driver to get at the current i915 device. Protected by
2303  * mchdev_lock. */
2304 static struct drm_i915_private *i915_mch_dev;
2305
2306 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2307 {
2308         struct drm_i915_private *dev_priv = dev->dev_private;
2309         u16 rgvswctl;
2310
2311         assert_spin_locked(&mchdev_lock);
2312
2313         rgvswctl = I915_READ16(MEMSWCTL);
2314         if (rgvswctl & MEMCTL_CMD_STS) {
2315                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2316                 return false; /* still busy with another command */
2317         }
2318
2319         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2320                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2321         I915_WRITE16(MEMSWCTL, rgvswctl);
2322         POSTING_READ16(MEMSWCTL);
2323
2324         rgvswctl |= MEMCTL_CMD_STS;
2325         I915_WRITE16(MEMSWCTL, rgvswctl);
2326
2327         return true;
2328 }
2329
2330 static void ironlake_enable_drps(struct drm_device *dev)
2331 {
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         u32 rgvmodectl = I915_READ(MEMMODECTL);
2334         u8 fmax, fmin, fstart, vstart;
2335
2336         spin_lock_irq(&mchdev_lock);
2337
2338         /* Enable temp reporting */
2339         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2340         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2341
2342         /* 100ms RC evaluation intervals */
2343         I915_WRITE(RCUPEI, 100000);
2344         I915_WRITE(RCDNEI, 100000);
2345
2346         /* Set max/min thresholds to 90ms and 80ms respectively */
2347         I915_WRITE(RCBMAXAVG, 90000);
2348         I915_WRITE(RCBMINAVG, 80000);
2349
2350         I915_WRITE(MEMIHYST, 1);
2351
2352         /* Set up min, max, and cur for interrupt handling */
2353         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2354         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2355         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2356                 MEMMODE_FSTART_SHIFT;
2357
2358         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2359                 PXVFREQ_PX_SHIFT;
2360
2361         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2362         dev_priv->ips.fstart = fstart;
2363
2364         dev_priv->ips.max_delay = fstart;
2365         dev_priv->ips.min_delay = fmin;
2366         dev_priv->ips.cur_delay = fstart;
2367
2368         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2369                          fmax, fmin, fstart);
2370
2371         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2372
2373         /*
2374          * Interrupts will be enabled in ironlake_irq_postinstall
2375          */
2376
2377         I915_WRITE(VIDSTART, vstart);
2378         POSTING_READ(VIDSTART);
2379
2380         rgvmodectl |= MEMMODE_SWMODE_EN;
2381         I915_WRITE(MEMMODECTL, rgvmodectl);
2382
2383         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2384                 DRM_ERROR("stuck trying to change perf mode\n");
2385         mdelay(1);
2386
2387         ironlake_set_drps(dev, fstart);
2388
2389         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2390                 I915_READ(0x112e0);
2391         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2392         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2393         getrawmonotonic(&dev_priv->ips.last_time2);
2394
2395         spin_unlock_irq(&mchdev_lock);
2396 }
2397
2398 static void ironlake_disable_drps(struct drm_device *dev)
2399 {
2400         struct drm_i915_private *dev_priv = dev->dev_private;
2401         u16 rgvswctl;
2402
2403         spin_lock_irq(&mchdev_lock);
2404
2405         rgvswctl = I915_READ16(MEMSWCTL);
2406
2407         /* Ack interrupts, disable EFC interrupt */
2408         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2409         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2410         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2411         I915_WRITE(DEIIR, DE_PCU_EVENT);
2412         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2413
2414         /* Go back to the starting frequency */
2415         ironlake_set_drps(dev, dev_priv->ips.fstart);
2416         mdelay(1);
2417         rgvswctl |= MEMCTL_CMD_STS;
2418         I915_WRITE(MEMSWCTL, rgvswctl);
2419         mdelay(1);
2420
2421         spin_unlock_irq(&mchdev_lock);
2422 }
2423
2424 /* There's a funny hw issue where the hw returns all 0 when reading from
2425  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2426  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2427  * all limits and the gpu stuck at whatever frequency it is at atm).
2428  */
2429 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2430 {
2431         u32 limits;
2432
2433         limits = 0;
2434
2435         if (*val >= dev_priv->rps.max_delay)
2436                 *val = dev_priv->rps.max_delay;
2437         limits |= dev_priv->rps.max_delay << 24;
2438
2439         /* Only set the down limit when we've reached the lowest level to avoid
2440          * getting more interrupts, otherwise leave this clear. This prevents a
2441          * race in the hw when coming out of rc6: There's a tiny window where
2442          * the hw runs at the minimal clock before selecting the desired
2443          * frequency, if the down threshold expires in that window we will not
2444          * receive a down interrupt. */
2445         if (*val <= dev_priv->rps.min_delay) {
2446                 *val = dev_priv->rps.min_delay;
2447                 limits |= dev_priv->rps.min_delay << 16;
2448         }
2449
2450         return limits;
2451 }
2452
2453 void gen6_set_rps(struct drm_device *dev, u8 val)
2454 {
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         u32 limits = gen6_rps_limits(dev_priv, &val);
2457
2458         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2459         WARN_ON(val > dev_priv->rps.max_delay);
2460         WARN_ON(val < dev_priv->rps.min_delay);
2461
2462         if (val == dev_priv->rps.cur_delay)
2463                 return;
2464
2465         if (IS_HASWELL(dev))
2466                 I915_WRITE(GEN6_RPNSWREQ,
2467                            HSW_FREQUENCY(val));
2468         else
2469                 I915_WRITE(GEN6_RPNSWREQ,
2470                            GEN6_FREQUENCY(val) |
2471                            GEN6_OFFSET(0) |
2472                            GEN6_AGGRESSIVE_TURBO);
2473
2474         /* Make sure we continue to get interrupts
2475          * until we hit the minimum or maximum frequencies.
2476          */
2477         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2478
2479         POSTING_READ(GEN6_RPNSWREQ);
2480
2481         dev_priv->rps.cur_delay = val;
2482
2483         trace_intel_gpu_freq_change(val * 50);
2484 }
2485
2486 void valleyview_set_rps(struct drm_device *dev, u8 val)
2487 {
2488         struct drm_i915_private *dev_priv = dev->dev_private;
2489         unsigned long timeout = jiffies + msecs_to_jiffies(10);
2490         u32 limits = gen6_rps_limits(dev_priv, &val);
2491         u32 pval;
2492
2493         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2494         WARN_ON(val > dev_priv->rps.max_delay);
2495         WARN_ON(val < dev_priv->rps.min_delay);
2496
2497         DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2498                          vlv_gpu_freq(dev_priv->mem_freq,
2499                                       dev_priv->rps.cur_delay),
2500                          vlv_gpu_freq(dev_priv->mem_freq, val));
2501
2502         if (val == dev_priv->rps.cur_delay)
2503                 return;
2504
2505         valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2506
2507         do {
2508                 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2509                 if (time_after(jiffies, timeout)) {
2510                         DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2511                         break;
2512                 }
2513                 udelay(10);
2514         } while (pval & 1);
2515
2516         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2517         if ((pval >> 8) != val)
2518                 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2519                           val, pval >> 8);
2520
2521         /* Make sure we continue to get interrupts
2522          * until we hit the minimum or maximum frequencies.
2523          */
2524         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2525
2526         dev_priv->rps.cur_delay = pval >> 8;
2527
2528         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2529 }
2530
2531
2532 static void gen6_disable_rps(struct drm_device *dev)
2533 {
2534         struct drm_i915_private *dev_priv = dev->dev_private;
2535
2536         I915_WRITE(GEN6_RC_CONTROL, 0);
2537         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2538         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2539         I915_WRITE(GEN6_PMIER, 0);
2540         /* Complete PM interrupt masking here doesn't race with the rps work
2541          * item again unmasking PM interrupts because that is using a different
2542          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2543          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2544
2545         spin_lock_irq(&dev_priv->rps.lock);
2546         dev_priv->rps.pm_iir = 0;
2547         spin_unlock_irq(&dev_priv->rps.lock);
2548
2549         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2550 }
2551
2552 static void valleyview_disable_rps(struct drm_device *dev)
2553 {
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555
2556         I915_WRITE(GEN6_RC_CONTROL, 0);
2557         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2558         I915_WRITE(GEN6_PMIER, 0);
2559         /* Complete PM interrupt masking here doesn't race with the rps work
2560          * item again unmasking PM interrupts because that is using a different
2561          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2562          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2563
2564         spin_lock_irq(&dev_priv->rps.lock);
2565         dev_priv->rps.pm_iir = 0;
2566         spin_unlock_irq(&dev_priv->rps.lock);
2567
2568         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2569
2570         if (dev_priv->vlv_pctx) {
2571                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2572                 dev_priv->vlv_pctx = NULL;
2573         }
2574 }
2575
2576 int intel_enable_rc6(const struct drm_device *dev)
2577 {
2578         /* Respect the kernel parameter if it is set */
2579         if (i915_enable_rc6 >= 0)
2580                 return i915_enable_rc6;
2581
2582         /* Disable RC6 on Ironlake */
2583         if (INTEL_INFO(dev)->gen == 5)
2584                 return 0;
2585
2586         if (IS_HASWELL(dev)) {
2587                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2588                 return INTEL_RC6_ENABLE;
2589         }
2590
2591         /* snb/ivb have more than one rc6 state. */
2592         if (INTEL_INFO(dev)->gen == 6) {
2593                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2594                 return INTEL_RC6_ENABLE;
2595         }
2596
2597         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2598         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2599 }
2600
2601 static void gen6_enable_rps(struct drm_device *dev)
2602 {
2603         struct drm_i915_private *dev_priv = dev->dev_private;
2604         struct intel_ring_buffer *ring;
2605         u32 rp_state_cap;
2606         u32 gt_perf_status;
2607         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2608         u32 gtfifodbg;
2609         int rc6_mode;
2610         int i, ret;
2611
2612         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2613
2614         /* Here begins a magic sequence of register writes to enable
2615          * auto-downclocking.
2616          *
2617          * Perhaps there might be some value in exposing these to
2618          * userspace...
2619          */
2620         I915_WRITE(GEN6_RC_STATE, 0);
2621
2622         /* Clear the DBG now so we don't confuse earlier errors */
2623         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2624                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2625                 I915_WRITE(GTFIFODBG, gtfifodbg);
2626         }
2627
2628         gen6_gt_force_wake_get(dev_priv);
2629
2630         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2631         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2632
2633         /* In units of 50MHz */
2634         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
2635         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2636         dev_priv->rps.cur_delay = 0;
2637
2638         /* disable the counters and set deterministic thresholds */
2639         I915_WRITE(GEN6_RC_CONTROL, 0);
2640
2641         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2642         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2643         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2644         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2645         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2646
2647         for_each_ring(ring, dev_priv, i)
2648                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2649
2650         I915_WRITE(GEN6_RC_SLEEP, 0);
2651         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2652         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2653         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2654         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2655
2656         /* Check if we are enabling RC6 */
2657         rc6_mode = intel_enable_rc6(dev_priv->dev);
2658         if (rc6_mode & INTEL_RC6_ENABLE)
2659                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2660
2661         /* We don't use those on Haswell */
2662         if (!IS_HASWELL(dev)) {
2663                 if (rc6_mode & INTEL_RC6p_ENABLE)
2664                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2665
2666                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2667                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2668         }
2669
2670         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2671                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2672                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2673                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2674
2675         I915_WRITE(GEN6_RC_CONTROL,
2676                    rc6_mask |
2677                    GEN6_RC_CTL_EI_MODE(1) |
2678                    GEN6_RC_CTL_HW_ENABLE);
2679
2680         if (IS_HASWELL(dev)) {
2681                 I915_WRITE(GEN6_RPNSWREQ,
2682                            HSW_FREQUENCY(10));
2683                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2684                            HSW_FREQUENCY(12));
2685         } else {
2686                 I915_WRITE(GEN6_RPNSWREQ,
2687                            GEN6_FREQUENCY(10) |
2688                            GEN6_OFFSET(0) |
2689                            GEN6_AGGRESSIVE_TURBO);
2690                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2691                            GEN6_FREQUENCY(12));
2692         }
2693
2694         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2695         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2696                    dev_priv->rps.max_delay << 24 |
2697                    dev_priv->rps.min_delay << 16);
2698
2699         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2700         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2701         I915_WRITE(GEN6_RP_UP_EI, 66000);
2702         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2703
2704         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2705         I915_WRITE(GEN6_RP_CONTROL,
2706                    GEN6_RP_MEDIA_TURBO |
2707                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2708                    GEN6_RP_MEDIA_IS_GFX |
2709                    GEN6_RP_ENABLE |
2710                    GEN6_RP_UP_BUSY_AVG |
2711                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2712
2713         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2714         if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
2715                 pcu_mbox = 0;
2716                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2717                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2718                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
2719                                          (dev_priv->rps.max_delay & 0xff) * 50,
2720                                          (pcu_mbox & 0xff) * 50);
2721                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
2722                 }
2723         } else {
2724                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2725         }
2726
2727         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2728
2729         /* requires MSI enabled */
2730         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2731         spin_lock_irq(&dev_priv->rps.lock);
2732         WARN_ON(dev_priv->rps.pm_iir != 0);
2733         I915_WRITE(GEN6_PMIMR, 0);
2734         spin_unlock_irq(&dev_priv->rps.lock);
2735         /* enable all PM interrupts */
2736         I915_WRITE(GEN6_PMINTRMSK, 0);
2737
2738         rc6vids = 0;
2739         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2740         if (IS_GEN6(dev) && ret) {
2741                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2742         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2743                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2744                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2745                 rc6vids &= 0xffff00;
2746                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2747                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2748                 if (ret)
2749                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2750         }
2751
2752         gen6_gt_force_wake_put(dev_priv);
2753 }
2754
2755 static void gen6_update_ring_freq(struct drm_device *dev)
2756 {
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         int min_freq = 15;
2759         unsigned int gpu_freq;
2760         unsigned int max_ia_freq, min_ring_freq;
2761         int scaling_factor = 180;
2762
2763         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2764
2765         max_ia_freq = cpufreq_quick_get_max(0);
2766         /*
2767          * Default to measured freq if none found, PCU will ensure we don't go
2768          * over
2769          */
2770         if (!max_ia_freq)
2771                 max_ia_freq = tsc_khz;
2772
2773         /* Convert from kHz to MHz */
2774         max_ia_freq /= 1000;
2775
2776         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2777         /* convert DDR frequency from units of 133.3MHz to bandwidth */
2778         min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2779
2780         /*
2781          * For each potential GPU frequency, load a ring frequency we'd like
2782          * to use for memory access.  We do this by specifying the IA frequency
2783          * the PCU should use as a reference to determine the ring frequency.
2784          */
2785         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2786              gpu_freq--) {
2787                 int diff = dev_priv->rps.max_delay - gpu_freq;
2788                 unsigned int ia_freq = 0, ring_freq = 0;
2789
2790                 if (IS_HASWELL(dev)) {
2791                         ring_freq = (gpu_freq * 5 + 3) / 4;
2792                         ring_freq = max(min_ring_freq, ring_freq);
2793                         /* leave ia_freq as the default, chosen by cpufreq */
2794                 } else {
2795                         /* On older processors, there is no separate ring
2796                          * clock domain, so in order to boost the bandwidth
2797                          * of the ring, we need to upclock the CPU (ia_freq).
2798                          *
2799                          * For GPU frequencies less than 750MHz,
2800                          * just use the lowest ring freq.
2801                          */
2802                         if (gpu_freq < min_freq)
2803                                 ia_freq = 800;
2804                         else
2805                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2806                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2807                 }
2808
2809                 sandybridge_pcode_write(dev_priv,
2810                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2811                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2812                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2813                                         gpu_freq);
2814         }
2815 }
2816
2817 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2818 {
2819         u32 val, rp0;
2820
2821         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2822
2823         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2824         /* Clamp to max */
2825         rp0 = min_t(u32, rp0, 0xea);
2826
2827         return rp0;
2828 }
2829
2830 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2831 {
2832         u32 val, rpe;
2833
2834         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2835         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2836         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2837         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2838
2839         return rpe;
2840 }
2841
2842 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2843 {
2844         u32 val;
2845
2846         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2847
2848         return val & 0xff;
2849 }
2850
2851 static void vlv_rps_timer_work(struct work_struct *work)
2852 {
2853         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
2854                                                     rps.vlv_work.work);
2855
2856         /*
2857          * Timer fired, we must be idle.  Drop to min voltage state.
2858          * Note: we use RPe here since it should match the
2859          * Vmin we were shooting for.  That should give us better
2860          * perf when we come back out of RC6 than if we used the
2861          * min freq available.
2862          */
2863         mutex_lock(&dev_priv->rps.hw_lock);
2864         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
2865         mutex_unlock(&dev_priv->rps.hw_lock);
2866 }
2867
2868 static void valleyview_setup_pctx(struct drm_device *dev)
2869 {
2870         struct drm_i915_private *dev_priv = dev->dev_private;
2871         struct drm_i915_gem_object *pctx;
2872         unsigned long pctx_paddr;
2873         u32 pcbr;
2874         int pctx_size = 24*1024;
2875
2876         pcbr = I915_READ(VLV_PCBR);
2877         if (pcbr) {
2878                 /* BIOS set it up already, grab the pre-alloc'd space */
2879                 int pcbr_offset;
2880
2881                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
2882                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
2883                                                                       pcbr_offset,
2884                                                                       -1,
2885                                                                       pctx_size);
2886                 goto out;
2887         }
2888
2889         /*
2890          * From the Gunit register HAS:
2891          * The Gfx driver is expected to program this register and ensure
2892          * proper allocation within Gfx stolen memory.  For example, this
2893          * register should be programmed such than the PCBR range does not
2894          * overlap with other ranges, such as the frame buffer, protected
2895          * memory, or any other relevant ranges.
2896          */
2897         pctx = i915_gem_object_create_stolen(dev, pctx_size);
2898         if (!pctx) {
2899                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
2900                 return;
2901         }
2902
2903         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
2904         I915_WRITE(VLV_PCBR, pctx_paddr);
2905
2906 out:
2907         dev_priv->vlv_pctx = pctx;
2908 }
2909
2910 static void valleyview_enable_rps(struct drm_device *dev)
2911 {
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         struct intel_ring_buffer *ring;
2914         u32 gtfifodbg, val, rpe;
2915         int i;
2916
2917         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2918
2919         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2920                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2921                 I915_WRITE(GTFIFODBG, gtfifodbg);
2922         }
2923
2924         valleyview_setup_pctx(dev);
2925
2926         gen6_gt_force_wake_get(dev_priv);
2927
2928         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2929         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2930         I915_WRITE(GEN6_RP_UP_EI, 66000);
2931         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2932
2933         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2934
2935         I915_WRITE(GEN6_RP_CONTROL,
2936                    GEN6_RP_MEDIA_TURBO |
2937                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2938                    GEN6_RP_MEDIA_IS_GFX |
2939                    GEN6_RP_ENABLE |
2940                    GEN6_RP_UP_BUSY_AVG |
2941                    GEN6_RP_DOWN_IDLE_CONT);
2942
2943         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
2944         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2945         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2946
2947         for_each_ring(ring, dev_priv, i)
2948                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2949
2950         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
2951
2952         /* allows RC6 residency counter to work */
2953         I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
2954         I915_WRITE(GEN6_RC_CONTROL,
2955                    GEN7_RC_CTL_TO_MODE);
2956
2957         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
2958         switch ((val >> 6) & 3) {
2959         case 0:
2960         case 1:
2961                 dev_priv->mem_freq = 800;
2962                 break;
2963         case 2:
2964                 dev_priv->mem_freq = 1066;
2965                 break;
2966         case 3:
2967                 dev_priv->mem_freq = 1333;
2968                 break;
2969         }
2970         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
2971
2972         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
2973         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
2974
2975         DRM_DEBUG_DRIVER("current GPU freq: %d\n",
2976                          vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
2977         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
2978
2979         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
2980         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
2981         DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
2982                                                      dev_priv->rps.max_delay));
2983
2984         rpe = valleyview_rps_rpe_freq(dev_priv);
2985         DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
2986                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
2987         dev_priv->rps.rpe_delay = rpe;
2988
2989         val = valleyview_rps_min_freq(dev_priv);
2990         DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
2991                                                             val));
2992         dev_priv->rps.min_delay = val;
2993
2994         DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
2995                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
2996
2997         INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
2998
2999         valleyview_set_rps(dev_priv->dev, rpe);
3000
3001         /* requires MSI enabled */
3002         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3003         spin_lock_irq(&dev_priv->rps.lock);
3004         WARN_ON(dev_priv->rps.pm_iir != 0);
3005         I915_WRITE(GEN6_PMIMR, 0);
3006         spin_unlock_irq(&dev_priv->rps.lock);
3007         /* enable all PM interrupts */
3008         I915_WRITE(GEN6_PMINTRMSK, 0);
3009
3010         gen6_gt_force_wake_put(dev_priv);
3011 }
3012
3013 void ironlake_teardown_rc6(struct drm_device *dev)
3014 {
3015         struct drm_i915_private *dev_priv = dev->dev_private;
3016
3017         if (dev_priv->ips.renderctx) {
3018                 i915_gem_object_unpin(dev_priv->ips.renderctx);
3019                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3020                 dev_priv->ips.renderctx = NULL;
3021         }
3022
3023         if (dev_priv->ips.pwrctx) {
3024                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3025                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3026                 dev_priv->ips.pwrctx = NULL;
3027         }
3028 }
3029
3030 static void ironlake_disable_rc6(struct drm_device *dev)
3031 {
3032         struct drm_i915_private *dev_priv = dev->dev_private;
3033
3034         if (I915_READ(PWRCTXA)) {
3035                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3036                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3037                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3038                          50);
3039
3040                 I915_WRITE(PWRCTXA, 0);
3041                 POSTING_READ(PWRCTXA);
3042
3043                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3044                 POSTING_READ(RSTDBYCTL);
3045         }
3046 }
3047
3048 static int ironlake_setup_rc6(struct drm_device *dev)
3049 {
3050         struct drm_i915_private *dev_priv = dev->dev_private;
3051
3052         if (dev_priv->ips.renderctx == NULL)
3053                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3054         if (!dev_priv->ips.renderctx)
3055                 return -ENOMEM;
3056
3057         if (dev_priv->ips.pwrctx == NULL)
3058                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3059         if (!dev_priv->ips.pwrctx) {
3060                 ironlake_teardown_rc6(dev);
3061                 return -ENOMEM;
3062         }
3063
3064         return 0;
3065 }
3066
3067 static void ironlake_enable_rc6(struct drm_device *dev)
3068 {
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3071         bool was_interruptible;
3072         int ret;
3073
3074         /* rc6 disabled by default due to repeated reports of hanging during
3075          * boot and resume.
3076          */
3077         if (!intel_enable_rc6(dev))
3078                 return;
3079
3080         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3081
3082         ret = ironlake_setup_rc6(dev);
3083         if (ret)
3084                 return;
3085
3086         was_interruptible = dev_priv->mm.interruptible;
3087         dev_priv->mm.interruptible = false;
3088
3089         /*
3090          * GPU can automatically power down the render unit if given a page
3091          * to save state.
3092          */
3093         ret = intel_ring_begin(ring, 6);
3094         if (ret) {
3095                 ironlake_teardown_rc6(dev);
3096                 dev_priv->mm.interruptible = was_interruptible;
3097                 return;
3098         }
3099
3100         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3101         intel_ring_emit(ring, MI_SET_CONTEXT);
3102         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3103                         MI_MM_SPACE_GTT |
3104                         MI_SAVE_EXT_STATE_EN |
3105                         MI_RESTORE_EXT_STATE_EN |
3106                         MI_RESTORE_INHIBIT);
3107         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3108         intel_ring_emit(ring, MI_NOOP);
3109         intel_ring_emit(ring, MI_FLUSH);
3110         intel_ring_advance(ring);
3111
3112         /*
3113          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3114          * does an implicit flush, combined with MI_FLUSH above, it should be
3115          * safe to assume that renderctx is valid
3116          */
3117         ret = intel_ring_idle(ring);
3118         dev_priv->mm.interruptible = was_interruptible;
3119         if (ret) {
3120                 DRM_ERROR("failed to enable ironlake power savings\n");
3121                 ironlake_teardown_rc6(dev);
3122                 return;
3123         }
3124
3125         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3126         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3127 }
3128
3129 static unsigned long intel_pxfreq(u32 vidfreq)
3130 {
3131         unsigned long freq;
3132         int div = (vidfreq & 0x3f0000) >> 16;
3133         int post = (vidfreq & 0x3000) >> 12;
3134         int pre = (vidfreq & 0x7);
3135
3136         if (!pre)
3137                 return 0;
3138
3139         freq = ((div * 133333) / ((1<<post) * pre));
3140
3141         return freq;
3142 }
3143
3144 static const struct cparams {
3145         u16 i;
3146         u16 t;
3147         u16 m;
3148         u16 c;
3149 } cparams[] = {
3150         { 1, 1333, 301, 28664 },
3151         { 1, 1066, 294, 24460 },
3152         { 1, 800, 294, 25192 },
3153         { 0, 1333, 276, 27605 },
3154         { 0, 1066, 276, 27605 },
3155         { 0, 800, 231, 23784 },
3156 };
3157
3158 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3159 {
3160         u64 total_count, diff, ret;
3161         u32 count1, count2, count3, m = 0, c = 0;
3162         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3163         int i;
3164
3165         assert_spin_locked(&mchdev_lock);
3166
3167         diff1 = now - dev_priv->ips.last_time1;
3168
3169         /* Prevent division-by-zero if we are asking too fast.
3170          * Also, we don't get interesting results if we are polling
3171          * faster than once in 10ms, so just return the saved value
3172          * in such cases.
3173          */
3174         if (diff1 <= 10)
3175                 return dev_priv->ips.chipset_power;
3176
3177         count1 = I915_READ(DMIEC);
3178         count2 = I915_READ(DDREC);
3179         count3 = I915_READ(CSIEC);
3180
3181         total_count = count1 + count2 + count3;
3182
3183         /* FIXME: handle per-counter overflow */
3184         if (total_count < dev_priv->ips.last_count1) {
3185                 diff = ~0UL - dev_priv->ips.last_count1;
3186                 diff += total_count;
3187         } else {
3188                 diff = total_count - dev_priv->ips.last_count1;
3189         }
3190
3191         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3192                 if (cparams[i].i == dev_priv->ips.c_m &&
3193                     cparams[i].t == dev_priv->ips.r_t) {
3194                         m = cparams[i].m;
3195                         c = cparams[i].c;
3196                         break;
3197                 }
3198         }
3199
3200         diff = div_u64(diff, diff1);
3201         ret = ((m * diff) + c);
3202         ret = div_u64(ret, 10);
3203
3204         dev_priv->ips.last_count1 = total_count;
3205         dev_priv->ips.last_time1 = now;
3206
3207         dev_priv->ips.chipset_power = ret;
3208
3209         return ret;
3210 }
3211
3212 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3213 {
3214         unsigned long val;
3215
3216         if (dev_priv->info->gen != 5)
3217                 return 0;
3218
3219         spin_lock_irq(&mchdev_lock);
3220
3221         val = __i915_chipset_val(dev_priv);
3222
3223         spin_unlock_irq(&mchdev_lock);
3224
3225         return val;
3226 }
3227
3228 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3229 {
3230         unsigned long m, x, b;
3231         u32 tsfs;
3232
3233         tsfs = I915_READ(TSFS);
3234
3235         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3236         x = I915_READ8(TR1);
3237
3238         b = tsfs & TSFS_INTR_MASK;
3239
3240         return ((m * x) / 127) - b;
3241 }
3242
3243 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3244 {
3245         static const struct v_table {
3246                 u16 vd; /* in .1 mil */
3247                 u16 vm; /* in .1 mil */
3248         } v_table[] = {
3249                 { 0, 0, },
3250                 { 375, 0, },
3251                 { 500, 0, },
3252                 { 625, 0, },
3253                 { 750, 0, },
3254                 { 875, 0, },
3255                 { 1000, 0, },
3256                 { 1125, 0, },
3257                 { 4125, 3000, },
3258                 { 4125, 3000, },
3259                 { 4125, 3000, },
3260                 { 4125, 3000, },
3261                 { 4125, 3000, },
3262                 { 4125, 3000, },
3263                 { 4125, 3000, },
3264                 { 4125, 3000, },
3265                 { 4125, 3000, },
3266                 { 4125, 3000, },
3267                 { 4125, 3000, },
3268                 { 4125, 3000, },
3269                 { 4125, 3000, },
3270                 { 4125, 3000, },
3271                 { 4125, 3000, },
3272                 { 4125, 3000, },
3273                 { 4125, 3000, },
3274                 { 4125, 3000, },
3275                 { 4125, 3000, },
3276                 { 4125, 3000, },
3277                 { 4125, 3000, },
3278                 { 4125, 3000, },
3279                 { 4125, 3000, },
3280                 { 4125, 3000, },
3281                 { 4250, 3125, },
3282                 { 4375, 3250, },
3283                 { 4500, 3375, },
3284                 { 4625, 3500, },
3285                 { 4750, 3625, },
3286                 { 4875, 3750, },
3287                 { 5000, 3875, },
3288                 { 5125, 4000, },
3289                 { 5250, 4125, },
3290                 { 5375, 4250, },
3291                 { 5500, 4375, },
3292                 { 5625, 4500, },
3293                 { 5750, 4625, },
3294                 { 5875, 4750, },
3295                 { 6000, 4875, },
3296                 { 6125, 5000, },
3297                 { 6250, 5125, },
3298                 { 6375, 5250, },
3299                 { 6500, 5375, },
3300                 { 6625, 5500, },
3301                 { 6750, 5625, },
3302                 { 6875, 5750, },
3303                 { 7000, 5875, },
3304                 { 7125, 6000, },
3305                 { 7250, 6125, },
3306                 { 7375, 6250, },
3307                 { 7500, 6375, },
3308                 { 7625, 6500, },
3309                 { 7750, 6625, },
3310                 { 7875, 6750, },
3311                 { 8000, 6875, },
3312                 { 8125, 7000, },
3313                 { 8250, 7125, },
3314                 { 8375, 7250, },
3315                 { 8500, 7375, },
3316                 { 8625, 7500, },
3317                 { 8750, 7625, },
3318                 { 8875, 7750, },
3319                 { 9000, 7875, },
3320                 { 9125, 8000, },
3321                 { 9250, 8125, },
3322                 { 9375, 8250, },
3323                 { 9500, 8375, },
3324                 { 9625, 8500, },
3325                 { 9750, 8625, },
3326                 { 9875, 8750, },
3327                 { 10000, 8875, },
3328                 { 10125, 9000, },
3329                 { 10250, 9125, },
3330                 { 10375, 9250, },
3331                 { 10500, 9375, },
3332                 { 10625, 9500, },
3333                 { 10750, 9625, },
3334                 { 10875, 9750, },
3335                 { 11000, 9875, },
3336                 { 11125, 10000, },
3337                 { 11250, 10125, },
3338                 { 11375, 10250, },
3339                 { 11500, 10375, },
3340                 { 11625, 10500, },
3341                 { 11750, 10625, },
3342                 { 11875, 10750, },
3343                 { 12000, 10875, },
3344                 { 12125, 11000, },
3345                 { 12250, 11125, },
3346                 { 12375, 11250, },
3347                 { 12500, 11375, },
3348                 { 12625, 11500, },
3349                 { 12750, 11625, },
3350                 { 12875, 11750, },
3351                 { 13000, 11875, },
3352                 { 13125, 12000, },
3353                 { 13250, 12125, },
3354                 { 13375, 12250, },
3355                 { 13500, 12375, },
3356                 { 13625, 12500, },
3357                 { 13750, 12625, },
3358                 { 13875, 12750, },
3359                 { 14000, 12875, },
3360                 { 14125, 13000, },
3361                 { 14250, 13125, },
3362                 { 14375, 13250, },
3363                 { 14500, 13375, },
3364                 { 14625, 13500, },
3365                 { 14750, 13625, },
3366                 { 14875, 13750, },
3367                 { 15000, 13875, },
3368                 { 15125, 14000, },
3369                 { 15250, 14125, },
3370                 { 15375, 14250, },
3371                 { 15500, 14375, },
3372                 { 15625, 14500, },
3373                 { 15750, 14625, },
3374                 { 15875, 14750, },
3375                 { 16000, 14875, },
3376                 { 16125, 15000, },
3377         };
3378         if (dev_priv->info->is_mobile)
3379                 return v_table[pxvid].vm;
3380         else
3381                 return v_table[pxvid].vd;
3382 }
3383
3384 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3385 {
3386         struct timespec now, diff1;
3387         u64 diff;
3388         unsigned long diffms;
3389         u32 count;
3390
3391         assert_spin_locked(&mchdev_lock);
3392
3393         getrawmonotonic(&now);
3394         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3395
3396         /* Don't divide by 0 */
3397         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3398         if (!diffms)
3399                 return;
3400
3401         count = I915_READ(GFXEC);
3402
3403         if (count < dev_priv->ips.last_count2) {
3404                 diff = ~0UL - dev_priv->ips.last_count2;
3405                 diff += count;
3406         } else {
3407                 diff = count - dev_priv->ips.last_count2;
3408         }
3409
3410         dev_priv->ips.last_count2 = count;
3411         dev_priv->ips.last_time2 = now;
3412
3413         /* More magic constants... */
3414         diff = diff * 1181;
3415         diff = div_u64(diff, diffms * 10);
3416         dev_priv->ips.gfx_power = diff;
3417 }
3418
3419 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3420 {
3421         if (dev_priv->info->gen != 5)
3422                 return;
3423
3424         spin_lock_irq(&mchdev_lock);
3425
3426         __i915_update_gfx_val(dev_priv);
3427
3428         spin_unlock_irq(&mchdev_lock);
3429 }
3430
3431 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3432 {
3433         unsigned long t, corr, state1, corr2, state2;
3434         u32 pxvid, ext_v;
3435
3436         assert_spin_locked(&mchdev_lock);
3437
3438         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3439         pxvid = (pxvid >> 24) & 0x7f;
3440         ext_v = pvid_to_extvid(dev_priv, pxvid);
3441
3442         state1 = ext_v;
3443
3444         t = i915_mch_val(dev_priv);
3445
3446         /* Revel in the empirically derived constants */
3447
3448         /* Correction factor in 1/100000 units */
3449         if (t > 80)
3450                 corr = ((t * 2349) + 135940);
3451         else if (t >= 50)
3452                 corr = ((t * 964) + 29317);
3453         else /* < 50 */
3454                 corr = ((t * 301) + 1004);
3455
3456         corr = corr * ((150142 * state1) / 10000 - 78642);
3457         corr /= 100000;
3458         corr2 = (corr * dev_priv->ips.corr);
3459
3460         state2 = (corr2 * state1) / 10000;
3461         state2 /= 100; /* convert to mW */
3462
3463         __i915_update_gfx_val(dev_priv);
3464
3465         return dev_priv->ips.gfx_power + state2;
3466 }
3467
3468 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3469 {
3470         unsigned long val;
3471
3472         if (dev_priv->info->gen != 5)
3473                 return 0;
3474
3475         spin_lock_irq(&mchdev_lock);
3476
3477         val = __i915_gfx_val(dev_priv);
3478
3479         spin_unlock_irq(&mchdev_lock);
3480
3481         return val;
3482 }
3483
3484 /**
3485  * i915_read_mch_val - return value for IPS use
3486  *
3487  * Calculate and return a value for the IPS driver to use when deciding whether
3488  * we have thermal and power headroom to increase CPU or GPU power budget.
3489  */
3490 unsigned long i915_read_mch_val(void)
3491 {
3492         struct drm_i915_private *dev_priv;
3493         unsigned long chipset_val, graphics_val, ret = 0;
3494
3495         spin_lock_irq(&mchdev_lock);
3496         if (!i915_mch_dev)
3497                 goto out_unlock;
3498         dev_priv = i915_mch_dev;
3499
3500         chipset_val = __i915_chipset_val(dev_priv);
3501         graphics_val = __i915_gfx_val(dev_priv);
3502
3503         ret = chipset_val + graphics_val;
3504
3505 out_unlock:
3506         spin_unlock_irq(&mchdev_lock);
3507
3508         return ret;
3509 }
3510 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3511
3512 /**
3513  * i915_gpu_raise - raise GPU frequency limit
3514  *
3515  * Raise the limit; IPS indicates we have thermal headroom.
3516  */
3517 bool i915_gpu_raise(void)
3518 {
3519         struct drm_i915_private *dev_priv;
3520         bool ret = true;
3521
3522         spin_lock_irq(&mchdev_lock);
3523         if (!i915_mch_dev) {
3524                 ret = false;
3525                 goto out_unlock;
3526         }
3527         dev_priv = i915_mch_dev;
3528
3529         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3530                 dev_priv->ips.max_delay--;
3531
3532 out_unlock:
3533         spin_unlock_irq(&mchdev_lock);
3534
3535         return ret;
3536 }
3537 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3538
3539 /**
3540  * i915_gpu_lower - lower GPU frequency limit
3541  *
3542  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3543  * frequency maximum.
3544  */
3545 bool i915_gpu_lower(void)
3546 {
3547         struct drm_i915_private *dev_priv;
3548         bool ret = true;
3549
3550         spin_lock_irq(&mchdev_lock);
3551         if (!i915_mch_dev) {
3552                 ret = false;
3553                 goto out_unlock;
3554         }
3555         dev_priv = i915_mch_dev;
3556
3557         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3558                 dev_priv->ips.max_delay++;
3559
3560 out_unlock:
3561         spin_unlock_irq(&mchdev_lock);
3562
3563         return ret;
3564 }
3565 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3566
3567 /**
3568  * i915_gpu_busy - indicate GPU business to IPS
3569  *
3570  * Tell the IPS driver whether or not the GPU is busy.
3571  */
3572 bool i915_gpu_busy(void)
3573 {
3574         struct drm_i915_private *dev_priv;
3575         struct intel_ring_buffer *ring;
3576         bool ret = false;
3577         int i;
3578
3579         spin_lock_irq(&mchdev_lock);
3580         if (!i915_mch_dev)
3581                 goto out_unlock;
3582         dev_priv = i915_mch_dev;
3583
3584         for_each_ring(ring, dev_priv, i)
3585                 ret |= !list_empty(&ring->request_list);
3586
3587 out_unlock:
3588         spin_unlock_irq(&mchdev_lock);
3589
3590         return ret;
3591 }
3592 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3593
3594 /**
3595  * i915_gpu_turbo_disable - disable graphics turbo
3596  *
3597  * Disable graphics turbo by resetting the max frequency and setting the
3598  * current frequency to the default.
3599  */
3600 bool i915_gpu_turbo_disable(void)
3601 {
3602         struct drm_i915_private *dev_priv;
3603         bool ret = true;
3604
3605         spin_lock_irq(&mchdev_lock);
3606         if (!i915_mch_dev) {
3607                 ret = false;
3608                 goto out_unlock;
3609         }
3610         dev_priv = i915_mch_dev;
3611
3612         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3613
3614         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3615                 ret = false;
3616
3617 out_unlock:
3618         spin_unlock_irq(&mchdev_lock);
3619
3620         return ret;
3621 }
3622 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3623
3624 /**
3625  * Tells the intel_ips driver that the i915 driver is now loaded, if
3626  * IPS got loaded first.
3627  *
3628  * This awkward dance is so that neither module has to depend on the
3629  * other in order for IPS to do the appropriate communication of
3630  * GPU turbo limits to i915.
3631  */
3632 static void
3633 ips_ping_for_i915_load(void)
3634 {
3635         void (*link)(void);
3636
3637         link = symbol_get(ips_link_to_i915_driver);
3638         if (link) {
3639                 link();
3640                 symbol_put(ips_link_to_i915_driver);
3641         }
3642 }
3643
3644 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3645 {
3646         /* We only register the i915 ips part with intel-ips once everything is
3647          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3648         spin_lock_irq(&mchdev_lock);
3649         i915_mch_dev = dev_priv;
3650         spin_unlock_irq(&mchdev_lock);
3651
3652         ips_ping_for_i915_load();
3653 }
3654
3655 void intel_gpu_ips_teardown(void)
3656 {
3657         spin_lock_irq(&mchdev_lock);
3658         i915_mch_dev = NULL;
3659         spin_unlock_irq(&mchdev_lock);
3660 }
3661 static void intel_init_emon(struct drm_device *dev)
3662 {
3663         struct drm_i915_private *dev_priv = dev->dev_private;
3664         u32 lcfuse;
3665         u8 pxw[16];
3666         int i;
3667
3668         /* Disable to program */
3669         I915_WRITE(ECR, 0);
3670         POSTING_READ(ECR);
3671
3672         /* Program energy weights for various events */
3673         I915_WRITE(SDEW, 0x15040d00);
3674         I915_WRITE(CSIEW0, 0x007f0000);
3675         I915_WRITE(CSIEW1, 0x1e220004);
3676         I915_WRITE(CSIEW2, 0x04000004);
3677
3678         for (i = 0; i < 5; i++)
3679                 I915_WRITE(PEW + (i * 4), 0);
3680         for (i = 0; i < 3; i++)
3681                 I915_WRITE(DEW + (i * 4), 0);
3682
3683         /* Program P-state weights to account for frequency power adjustment */
3684         for (i = 0; i < 16; i++) {
3685                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3686                 unsigned long freq = intel_pxfreq(pxvidfreq);
3687                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3688                         PXVFREQ_PX_SHIFT;
3689                 unsigned long val;
3690
3691                 val = vid * vid;
3692                 val *= (freq / 1000);
3693                 val *= 255;
3694                 val /= (127*127*900);
3695                 if (val > 0xff)
3696                         DRM_ERROR("bad pxval: %ld\n", val);
3697                 pxw[i] = val;
3698         }
3699         /* Render standby states get 0 weight */
3700         pxw[14] = 0;
3701         pxw[15] = 0;
3702
3703         for (i = 0; i < 4; i++) {
3704                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3705                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3706                 I915_WRITE(PXW + (i * 4), val);
3707         }
3708
3709         /* Adjust magic regs to magic values (more experimental results) */
3710         I915_WRITE(OGW0, 0);
3711         I915_WRITE(OGW1, 0);
3712         I915_WRITE(EG0, 0x00007f00);
3713         I915_WRITE(EG1, 0x0000000e);
3714         I915_WRITE(EG2, 0x000e0000);
3715         I915_WRITE(EG3, 0x68000300);
3716         I915_WRITE(EG4, 0x42000000);
3717         I915_WRITE(EG5, 0x00140031);
3718         I915_WRITE(EG6, 0);
3719         I915_WRITE(EG7, 0);
3720
3721         for (i = 0; i < 8; i++)
3722                 I915_WRITE(PXWL + (i * 4), 0);
3723
3724         /* Enable PMON + select events */
3725         I915_WRITE(ECR, 0x80000019);
3726
3727         lcfuse = I915_READ(LCFUSE02);
3728
3729         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3730 }
3731
3732 void intel_disable_gt_powersave(struct drm_device *dev)
3733 {
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735
3736         /* Interrupts should be disabled already to avoid re-arming. */
3737         WARN_ON(dev->irq_enabled);
3738
3739         if (IS_IRONLAKE_M(dev)) {
3740                 ironlake_disable_drps(dev);
3741                 ironlake_disable_rc6(dev);
3742         } else if (INTEL_INFO(dev)->gen >= 6) {
3743                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3744                 cancel_work_sync(&dev_priv->rps.work);
3745                 if (IS_VALLEYVIEW(dev))
3746                         cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
3747                 mutex_lock(&dev_priv->rps.hw_lock);
3748                 if (IS_VALLEYVIEW(dev))
3749                         valleyview_disable_rps(dev);
3750                 else
3751                         gen6_disable_rps(dev);
3752                 mutex_unlock(&dev_priv->rps.hw_lock);
3753         }
3754 }
3755
3756 static void intel_gen6_powersave_work(struct work_struct *work)
3757 {
3758         struct drm_i915_private *dev_priv =
3759                 container_of(work, struct drm_i915_private,
3760                              rps.delayed_resume_work.work);
3761         struct drm_device *dev = dev_priv->dev;
3762
3763         mutex_lock(&dev_priv->rps.hw_lock);
3764
3765         if (IS_VALLEYVIEW(dev)) {
3766                 valleyview_enable_rps(dev);
3767         } else {
3768                 gen6_enable_rps(dev);
3769                 gen6_update_ring_freq(dev);
3770         }
3771         mutex_unlock(&dev_priv->rps.hw_lock);
3772 }
3773
3774 void intel_enable_gt_powersave(struct drm_device *dev)
3775 {
3776         struct drm_i915_private *dev_priv = dev->dev_private;
3777
3778         if (IS_IRONLAKE_M(dev)) {
3779                 ironlake_enable_drps(dev);
3780                 ironlake_enable_rc6(dev);
3781                 intel_init_emon(dev);
3782         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3783                 /*
3784                  * PCU communication is slow and this doesn't need to be
3785                  * done at any specific time, so do this out of our fast path
3786                  * to make resume and init faster.
3787                  */
3788                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3789                                       round_jiffies_up_relative(HZ));
3790         }
3791 }
3792
3793 static void ibx_init_clock_gating(struct drm_device *dev)
3794 {
3795         struct drm_i915_private *dev_priv = dev->dev_private;
3796
3797         /*
3798          * On Ibex Peak and Cougar Point, we need to disable clock
3799          * gating for the panel power sequencer or it will fail to
3800          * start up when no ports are active.
3801          */
3802         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3803 }
3804
3805 static void ironlake_init_clock_gating(struct drm_device *dev)
3806 {
3807         struct drm_i915_private *dev_priv = dev->dev_private;
3808         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3809
3810         /* Required for FBC */
3811         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3812                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3813                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3814
3815         I915_WRITE(PCH_3DCGDIS0,
3816                    MARIUNIT_CLOCK_GATE_DISABLE |
3817                    SVSMUNIT_CLOCK_GATE_DISABLE);
3818         I915_WRITE(PCH_3DCGDIS1,
3819                    VFMUNIT_CLOCK_GATE_DISABLE);
3820
3821         /*
3822          * According to the spec the following bits should be set in
3823          * order to enable memory self-refresh
3824          * The bit 22/21 of 0x42004
3825          * The bit 5 of 0x42020
3826          * The bit 15 of 0x45000
3827          */
3828         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3829                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3830                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3831         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3832         I915_WRITE(DISP_ARB_CTL,
3833                    (I915_READ(DISP_ARB_CTL) |
3834                     DISP_FBC_WM_DIS));
3835         I915_WRITE(WM3_LP_ILK, 0);
3836         I915_WRITE(WM2_LP_ILK, 0);
3837         I915_WRITE(WM1_LP_ILK, 0);
3838
3839         /*
3840          * Based on the document from hardware guys the following bits
3841          * should be set unconditionally in order to enable FBC.
3842          * The bit 22 of 0x42000
3843          * The bit 22 of 0x42004
3844          * The bit 7,8,9 of 0x42020.
3845          */
3846         if (IS_IRONLAKE_M(dev)) {
3847                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3848                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3849                            ILK_FBCQ_DIS);
3850                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3851                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3852                            ILK_DPARB_GATE);
3853         }
3854
3855         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3856
3857         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3858                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3859                    ILK_ELPIN_409_SELECT);
3860         I915_WRITE(_3D_CHICKEN2,
3861                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3862                    _3D_CHICKEN2_WM_READ_PIPELINED);
3863
3864         /* WaDisableRenderCachePipelinedFlush:ilk */
3865         I915_WRITE(CACHE_MODE_0,
3866                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3867
3868         ibx_init_clock_gating(dev);
3869 }
3870
3871 static void cpt_init_clock_gating(struct drm_device *dev)
3872 {
3873         struct drm_i915_private *dev_priv = dev->dev_private;
3874         int pipe;
3875         uint32_t val;
3876
3877         /*
3878          * On Ibex Peak and Cougar Point, we need to disable clock
3879          * gating for the panel power sequencer or it will fail to
3880          * start up when no ports are active.
3881          */
3882         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3883         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3884                    DPLS_EDP_PPS_FIX_DIS);
3885         /* The below fixes the weird display corruption, a few pixels shifted
3886          * downward, on (only) LVDS of some HP laptops with IVY.
3887          */
3888         for_each_pipe(pipe) {
3889                 val = I915_READ(TRANS_CHICKEN2(pipe));
3890                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3891                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3892                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3893                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3894                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3895                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3896                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3897                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3898         }
3899         /* WADP0ClockGatingDisable */
3900         for_each_pipe(pipe) {
3901                 I915_WRITE(TRANS_CHICKEN1(pipe),
3902                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3903         }
3904 }
3905
3906 static void gen6_check_mch_setup(struct drm_device *dev)
3907 {
3908         struct drm_i915_private *dev_priv = dev->dev_private;
3909         uint32_t tmp;
3910
3911         tmp = I915_READ(MCH_SSKPD);
3912         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3913                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3914                 DRM_INFO("This can cause pipe underruns and display issues.\n");
3915                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3916         }
3917 }
3918
3919 static void gen6_init_clock_gating(struct drm_device *dev)
3920 {
3921         struct drm_i915_private *dev_priv = dev->dev_private;
3922         int pipe;
3923         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3924
3925         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3926
3927         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3928                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3929                    ILK_ELPIN_409_SELECT);
3930
3931         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
3932         I915_WRITE(_3D_CHICKEN,
3933                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3934
3935         /* WaSetupGtModeTdRowDispatch:snb */
3936         if (IS_SNB_GT1(dev))
3937                 I915_WRITE(GEN6_GT_MODE,
3938                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3939
3940         I915_WRITE(WM3_LP_ILK, 0);
3941         I915_WRITE(WM2_LP_ILK, 0);
3942         I915_WRITE(WM1_LP_ILK, 0);
3943
3944         I915_WRITE(CACHE_MODE_0,
3945                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3946
3947         I915_WRITE(GEN6_UCGCTL1,
3948                    I915_READ(GEN6_UCGCTL1) |
3949                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3950                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3951
3952         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3953          * gating disable must be set.  Failure to set it results in
3954          * flickering pixels due to Z write ordering failures after
3955          * some amount of runtime in the Mesa "fire" demo, and Unigine
3956          * Sanctuary and Tropics, and apparently anything else with
3957          * alpha test or pixel discard.
3958          *
3959          * According to the spec, bit 11 (RCCUNIT) must also be set,
3960          * but we didn't debug actual testcases to find it out.
3961          *
3962          * Also apply WaDisableVDSUnitClockGating:snb and
3963          * WaDisableRCPBUnitClockGating:snb.
3964          */
3965         I915_WRITE(GEN6_UCGCTL2,
3966                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3967                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3968                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3969
3970         /* Bspec says we need to always set all mask bits. */
3971         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3972                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3973
3974         /*
3975          * According to the spec the following bits should be
3976          * set in order to enable memory self-refresh and fbc:
3977          * The bit21 and bit22 of 0x42000
3978          * The bit21 and bit22 of 0x42004
3979          * The bit5 and bit7 of 0x42020
3980          * The bit14 of 0x70180
3981          * The bit14 of 0x71180
3982          */
3983         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3984                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3985                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3986         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3987                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3988                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3989         I915_WRITE(ILK_DSPCLK_GATE_D,
3990                    I915_READ(ILK_DSPCLK_GATE_D) |
3991                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
3992                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3993
3994         /* WaMbcDriverBootEnable:snb */
3995         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3996                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3997
3998         for_each_pipe(pipe) {
3999                 I915_WRITE(DSPCNTR(pipe),
4000                            I915_READ(DSPCNTR(pipe)) |
4001                            DISPPLANE_TRICKLE_FEED_DISABLE);
4002                 intel_flush_display_plane(dev_priv, pipe);
4003         }
4004
4005         /* The default value should be 0x200 according to docs, but the two
4006          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4007         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4008         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4009
4010         cpt_init_clock_gating(dev);
4011
4012         gen6_check_mch_setup(dev);
4013 }
4014
4015 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4016 {
4017         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4018
4019         reg &= ~GEN7_FF_SCHED_MASK;
4020         reg |= GEN7_FF_TS_SCHED_HW;
4021         reg |= GEN7_FF_VS_SCHED_HW;
4022         reg |= GEN7_FF_DS_SCHED_HW;
4023
4024         if (IS_HASWELL(dev_priv->dev))
4025                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4026
4027         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4028 }
4029
4030 static void lpt_init_clock_gating(struct drm_device *dev)
4031 {
4032         struct drm_i915_private *dev_priv = dev->dev_private;
4033
4034         /*
4035          * TODO: this bit should only be enabled when really needed, then
4036          * disabled when not needed anymore in order to save power.
4037          */
4038         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4039                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4040                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4041                            PCH_LP_PARTITION_LEVEL_DISABLE);
4042 }
4043
4044 static void lpt_suspend_hw(struct drm_device *dev)
4045 {
4046         struct drm_i915_private *dev_priv = dev->dev_private;
4047
4048         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4049                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4050
4051                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4052                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4053         }
4054 }
4055
4056 static void haswell_init_clock_gating(struct drm_device *dev)
4057 {
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059         int pipe;
4060
4061         I915_WRITE(WM3_LP_ILK, 0);
4062         I915_WRITE(WM2_LP_ILK, 0);
4063         I915_WRITE(WM1_LP_ILK, 0);
4064
4065         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4066          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4067          */
4068         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4069
4070         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4071         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4072                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4073
4074         /* WaApplyL3ControlAndL3ChickenMode:hsw */
4075         I915_WRITE(GEN7_L3CNTLREG1,
4076                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4077         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4078                         GEN7_WA_L3_CHICKEN_MODE);
4079
4080         /* This is required by WaCatErrorRejectionIssue:hsw */
4081         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4082                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4083                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4084
4085         for_each_pipe(pipe) {
4086                 I915_WRITE(DSPCNTR(pipe),
4087                            I915_READ(DSPCNTR(pipe)) |
4088                            DISPPLANE_TRICKLE_FEED_DISABLE);
4089                 intel_flush_display_plane(dev_priv, pipe);
4090         }
4091
4092         /* WaVSRefCountFullforceMissDisable:hsw */
4093         gen7_setup_fixed_func_scheduler(dev_priv);
4094
4095         /* WaDisable4x2SubspanOptimization:hsw */
4096         I915_WRITE(CACHE_MODE_1,
4097                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4098
4099         /* WaMbcDriverBootEnable:hsw */
4100         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4101                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4102
4103         /* WaSwitchSolVfFArbitrationPriority:hsw */
4104         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4105
4106         /* XXX: This is a workaround for early silicon revisions and should be
4107          * removed later.
4108          */
4109         I915_WRITE(WM_DBG,
4110                         I915_READ(WM_DBG) |
4111                         WM_DBG_DISALLOW_MULTIPLE_LP |
4112                         WM_DBG_DISALLOW_SPRITE |
4113                         WM_DBG_DISALLOW_MAXFIFO);
4114
4115         lpt_init_clock_gating(dev);
4116 }
4117
4118 static void ivybridge_init_clock_gating(struct drm_device *dev)
4119 {
4120         struct drm_i915_private *dev_priv = dev->dev_private;
4121         int pipe;
4122         uint32_t snpcr;
4123
4124         I915_WRITE(WM3_LP_ILK, 0);
4125         I915_WRITE(WM2_LP_ILK, 0);
4126         I915_WRITE(WM1_LP_ILK, 0);
4127
4128         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4129
4130         /* WaDisableEarlyCull:ivb */
4131         I915_WRITE(_3D_CHICKEN3,
4132                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4133
4134         /* WaDisableBackToBackFlipFix:ivb */
4135         I915_WRITE(IVB_CHICKEN3,
4136                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4137                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4138
4139         /* WaDisablePSDDualDispatchEnable:ivb */
4140         if (IS_IVB_GT1(dev))
4141                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4142                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4143         else
4144                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4145                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4146
4147         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4148         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4149                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4150
4151         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4152         I915_WRITE(GEN7_L3CNTLREG1,
4153                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4154         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4155                    GEN7_WA_L3_CHICKEN_MODE);
4156         if (IS_IVB_GT1(dev))
4157                 I915_WRITE(GEN7_ROW_CHICKEN2,
4158                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4159         else
4160                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4161                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4162
4163
4164         /* WaForceL3Serialization:ivb */
4165         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4166                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4167
4168         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4169          * gating disable must be set.  Failure to set it results in
4170          * flickering pixels due to Z write ordering failures after
4171          * some amount of runtime in the Mesa "fire" demo, and Unigine
4172          * Sanctuary and Tropics, and apparently anything else with
4173          * alpha test or pixel discard.
4174          *
4175          * According to the spec, bit 11 (RCCUNIT) must also be set,
4176          * but we didn't debug actual testcases to find it out.
4177          *
4178          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4179          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4180          */
4181         I915_WRITE(GEN6_UCGCTL2,
4182                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4183                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4184
4185         /* This is required by WaCatErrorRejectionIssue:ivb */
4186         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4187                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4188                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4189
4190         for_each_pipe(pipe) {
4191                 I915_WRITE(DSPCNTR(pipe),
4192                            I915_READ(DSPCNTR(pipe)) |
4193                            DISPPLANE_TRICKLE_FEED_DISABLE);
4194                 intel_flush_display_plane(dev_priv, pipe);
4195         }
4196
4197         /* WaMbcDriverBootEnable:ivb */
4198         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4199                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4200
4201         /* WaVSRefCountFullforceMissDisable:ivb */
4202         gen7_setup_fixed_func_scheduler(dev_priv);
4203
4204         /* WaDisable4x2SubspanOptimization:ivb */
4205         I915_WRITE(CACHE_MODE_1,
4206                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4207
4208         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4209         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4210         snpcr |= GEN6_MBC_SNPCR_MED;
4211         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4212
4213         if (!HAS_PCH_NOP(dev))
4214                 cpt_init_clock_gating(dev);
4215
4216         gen6_check_mch_setup(dev);
4217 }
4218
4219 static void valleyview_init_clock_gating(struct drm_device *dev)
4220 {
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222         int pipe;
4223
4224         I915_WRITE(WM3_LP_ILK, 0);
4225         I915_WRITE(WM2_LP_ILK, 0);
4226         I915_WRITE(WM1_LP_ILK, 0);
4227
4228         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4229
4230         /* WaDisableEarlyCull:vlv */
4231         I915_WRITE(_3D_CHICKEN3,
4232                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4233
4234         /* WaDisableBackToBackFlipFix:vlv */
4235         I915_WRITE(IVB_CHICKEN3,
4236                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4237                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4238
4239         /* WaDisablePSDDualDispatchEnable:vlv */
4240         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4241                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4242                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4243
4244         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4245         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4246                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4247
4248         /* WaApplyL3ControlAndL3ChickenMode:vlv */
4249         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4250         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4251
4252         /* WaForceL3Serialization:vlv */
4253         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4254                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4255
4256         /* WaDisableDopClockGating:vlv */
4257         I915_WRITE(GEN7_ROW_CHICKEN2,
4258                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4259
4260         /* WaForceL3Serialization:vlv */
4261         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4262                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4263
4264         /* This is required by WaCatErrorRejectionIssue:vlv */
4265         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4266                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4267                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4268
4269         /* WaMbcDriverBootEnable:vlv */
4270         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4271                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4272
4273
4274         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4275          * gating disable must be set.  Failure to set it results in
4276          * flickering pixels due to Z write ordering failures after
4277          * some amount of runtime in the Mesa "fire" demo, and Unigine
4278          * Sanctuary and Tropics, and apparently anything else with
4279          * alpha test or pixel discard.
4280          *
4281          * According to the spec, bit 11 (RCCUNIT) must also be set,
4282          * but we didn't debug actual testcases to find it out.
4283          *
4284          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4285          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4286          *
4287          * Also apply WaDisableVDSUnitClockGating:vlv and
4288          * WaDisableRCPBUnitClockGating:vlv.
4289          */
4290         I915_WRITE(GEN6_UCGCTL2,
4291                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4292                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4293                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4294                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4295                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4296
4297         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4298
4299         for_each_pipe(pipe) {
4300                 I915_WRITE(DSPCNTR(pipe),
4301                            I915_READ(DSPCNTR(pipe)) |
4302                            DISPPLANE_TRICKLE_FEED_DISABLE);
4303                 intel_flush_display_plane(dev_priv, pipe);
4304         }
4305
4306         I915_WRITE(CACHE_MODE_1,
4307                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4308
4309         /*
4310          * WaDisableVLVClockGating_VBIIssue:vlv
4311          * Disable clock gating on th GCFG unit to prevent a delay
4312          * in the reporting of vblank events.
4313          */
4314         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4315
4316         /* Conservative clock gating settings for now */
4317         I915_WRITE(0x9400, 0xffffffff);
4318         I915_WRITE(0x9404, 0xffffffff);
4319         I915_WRITE(0x9408, 0xffffffff);
4320         I915_WRITE(0x940c, 0xffffffff);
4321         I915_WRITE(0x9410, 0xffffffff);
4322         I915_WRITE(0x9414, 0xffffffff);
4323         I915_WRITE(0x9418, 0xffffffff);
4324 }
4325
4326 static void g4x_init_clock_gating(struct drm_device *dev)
4327 {
4328         struct drm_i915_private *dev_priv = dev->dev_private;
4329         uint32_t dspclk_gate;
4330
4331         I915_WRITE(RENCLK_GATE_D1, 0);
4332         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4333                    GS_UNIT_CLOCK_GATE_DISABLE |
4334                    CL_UNIT_CLOCK_GATE_DISABLE);
4335         I915_WRITE(RAMCLK_GATE_D, 0);
4336         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4337                 OVRUNIT_CLOCK_GATE_DISABLE |
4338                 OVCUNIT_CLOCK_GATE_DISABLE;
4339         if (IS_GM45(dev))
4340                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4341         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4342
4343         /* WaDisableRenderCachePipelinedFlush */
4344         I915_WRITE(CACHE_MODE_0,
4345                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4346 }
4347
4348 static void crestline_init_clock_gating(struct drm_device *dev)
4349 {
4350         struct drm_i915_private *dev_priv = dev->dev_private;
4351
4352         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4353         I915_WRITE(RENCLK_GATE_D2, 0);
4354         I915_WRITE(DSPCLK_GATE_D, 0);
4355         I915_WRITE(RAMCLK_GATE_D, 0);
4356         I915_WRITE16(DEUC, 0);
4357 }
4358
4359 static void broadwater_init_clock_gating(struct drm_device *dev)
4360 {
4361         struct drm_i915_private *dev_priv = dev->dev_private;
4362
4363         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4364                    I965_RCC_CLOCK_GATE_DISABLE |
4365                    I965_RCPB_CLOCK_GATE_DISABLE |
4366                    I965_ISC_CLOCK_GATE_DISABLE |
4367                    I965_FBC_CLOCK_GATE_DISABLE);
4368         I915_WRITE(RENCLK_GATE_D2, 0);
4369 }
4370
4371 static void gen3_init_clock_gating(struct drm_device *dev)
4372 {
4373         struct drm_i915_private *dev_priv = dev->dev_private;
4374         u32 dstate = I915_READ(D_STATE);
4375
4376         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4377                 DSTATE_DOT_CLOCK_GATING;
4378         I915_WRITE(D_STATE, dstate);
4379
4380         if (IS_PINEVIEW(dev))
4381                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4382
4383         /* IIR "flip pending" means done if this bit is set */
4384         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4385 }
4386
4387 static void i85x_init_clock_gating(struct drm_device *dev)
4388 {
4389         struct drm_i915_private *dev_priv = dev->dev_private;
4390
4391         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4392 }
4393
4394 static void i830_init_clock_gating(struct drm_device *dev)
4395 {
4396         struct drm_i915_private *dev_priv = dev->dev_private;
4397
4398         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4399 }
4400
4401 void intel_init_clock_gating(struct drm_device *dev)
4402 {
4403         struct drm_i915_private *dev_priv = dev->dev_private;
4404
4405         dev_priv->display.init_clock_gating(dev);
4406 }
4407
4408 void intel_suspend_hw(struct drm_device *dev)
4409 {
4410         if (HAS_PCH_LPT(dev))
4411                 lpt_suspend_hw(dev);
4412 }
4413
4414 /**
4415  * We should only use the power well if we explicitly asked the hardware to
4416  * enable it, so check if it's enabled and also check if we've requested it to
4417  * be enabled.
4418  */
4419 bool intel_display_power_enabled(struct drm_device *dev,
4420                                  enum intel_display_power_domain domain)
4421 {
4422         struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424         if (!HAS_POWER_WELL(dev))
4425                 return true;
4426
4427         switch (domain) {
4428         case POWER_DOMAIN_PIPE_A:
4429         case POWER_DOMAIN_TRANSCODER_EDP:
4430                 return true;
4431         case POWER_DOMAIN_PIPE_B:
4432         case POWER_DOMAIN_PIPE_C:
4433         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4434         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4435         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4436         case POWER_DOMAIN_TRANSCODER_A:
4437         case POWER_DOMAIN_TRANSCODER_B:
4438         case POWER_DOMAIN_TRANSCODER_C:
4439                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4440                        (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4441         default:
4442                 BUG();
4443         }
4444 }
4445
4446 void intel_set_power_well(struct drm_device *dev, bool enable)
4447 {
4448         struct drm_i915_private *dev_priv = dev->dev_private;
4449         bool is_enabled, enable_requested;
4450         uint32_t tmp;
4451
4452         if (!HAS_POWER_WELL(dev))
4453                 return;
4454
4455         if (!i915_disable_power_well && !enable)
4456                 return;
4457
4458         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4459         is_enabled = tmp & HSW_PWR_WELL_STATE;
4460         enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4461
4462         if (enable) {
4463                 if (!enable_requested)
4464                         I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4465
4466                 if (!is_enabled) {
4467                         DRM_DEBUG_KMS("Enabling power well\n");
4468                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4469                                       HSW_PWR_WELL_STATE), 20))
4470                                 DRM_ERROR("Timeout enabling power well\n");
4471                 }
4472         } else {
4473                 if (enable_requested) {
4474                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4475                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
4476                 }
4477         }
4478 }
4479
4480 /*
4481  * Starting with Haswell, we have a "Power Down Well" that can be turned off
4482  * when not needed anymore. We have 4 registers that can request the power well
4483  * to be enabled, and it will only be disabled if none of the registers is
4484  * requesting it to be enabled.
4485  */
4486 void intel_init_power_well(struct drm_device *dev)
4487 {
4488         struct drm_i915_private *dev_priv = dev->dev_private;
4489
4490         if (!HAS_POWER_WELL(dev))
4491                 return;
4492
4493         /* For now, we need the power well to be always enabled. */
4494         intel_set_power_well(dev, true);
4495
4496         /* We're taking over the BIOS, so clear any requests made by it since
4497          * the driver is in charge now. */
4498         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4499                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4500 }
4501
4502 /* Set up chip specific power management-related functions */
4503 void intel_init_pm(struct drm_device *dev)
4504 {
4505         struct drm_i915_private *dev_priv = dev->dev_private;
4506
4507         if (I915_HAS_FBC(dev)) {
4508                 if (HAS_PCH_SPLIT(dev)) {
4509                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4510                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
4511                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4512                 } else if (IS_GM45(dev)) {
4513                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4514                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4515                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4516                 } else if (IS_CRESTLINE(dev)) {
4517                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4518                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4519                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4520                 }
4521                 /* 855GM needs testing */
4522         }
4523
4524         /* For cxsr */
4525         if (IS_PINEVIEW(dev))
4526                 i915_pineview_get_mem_freq(dev);
4527         else if (IS_GEN5(dev))
4528                 i915_ironlake_get_mem_freq(dev);
4529
4530         /* For FIFO watermark updates */
4531         if (HAS_PCH_SPLIT(dev)) {
4532                 if (IS_GEN5(dev)) {
4533                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4534                                 dev_priv->display.update_wm = ironlake_update_wm;
4535                         else {
4536                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4537                                               "Disable CxSR\n");
4538                                 dev_priv->display.update_wm = NULL;
4539                         }
4540                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4541                 } else if (IS_GEN6(dev)) {
4542                         if (SNB_READ_WM0_LATENCY()) {
4543                                 dev_priv->display.update_wm = sandybridge_update_wm;
4544                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4545                         } else {
4546                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4547                                               "Disable CxSR\n");
4548                                 dev_priv->display.update_wm = NULL;
4549                         }
4550                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4551                 } else if (IS_IVYBRIDGE(dev)) {
4552                         if (SNB_READ_WM0_LATENCY()) {
4553                                 dev_priv->display.update_wm = ivybridge_update_wm;
4554                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4555                         } else {
4556                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4557                                               "Disable CxSR\n");
4558                                 dev_priv->display.update_wm = NULL;
4559                         }
4560                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4561                 } else if (IS_HASWELL(dev)) {
4562                         if (SNB_READ_WM0_LATENCY()) {
4563                                 dev_priv->display.update_wm = sandybridge_update_wm;
4564                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4565                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4566                         } else {
4567                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4568                                               "Disable CxSR\n");
4569                                 dev_priv->display.update_wm = NULL;
4570                         }
4571                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4572                 } else
4573                         dev_priv->display.update_wm = NULL;
4574         } else if (IS_VALLEYVIEW(dev)) {
4575                 dev_priv->display.update_wm = valleyview_update_wm;
4576                 dev_priv->display.init_clock_gating =
4577                         valleyview_init_clock_gating;
4578         } else if (IS_PINEVIEW(dev)) {
4579                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4580                                             dev_priv->is_ddr3,
4581                                             dev_priv->fsb_freq,
4582                                             dev_priv->mem_freq)) {
4583                         DRM_INFO("failed to find known CxSR latency "
4584                                  "(found ddr%s fsb freq %d, mem freq %d), "
4585                                  "disabling CxSR\n",
4586                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4587                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4588                         /* Disable CxSR and never update its watermark again */
4589                         pineview_disable_cxsr(dev);
4590                         dev_priv->display.update_wm = NULL;
4591                 } else
4592                         dev_priv->display.update_wm = pineview_update_wm;
4593                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4594         } else if (IS_G4X(dev)) {
4595                 dev_priv->display.update_wm = g4x_update_wm;
4596                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4597         } else if (IS_GEN4(dev)) {
4598                 dev_priv->display.update_wm = i965_update_wm;
4599                 if (IS_CRESTLINE(dev))
4600                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4601                 else if (IS_BROADWATER(dev))
4602                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4603         } else if (IS_GEN3(dev)) {
4604                 dev_priv->display.update_wm = i9xx_update_wm;
4605                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4606                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4607         } else if (IS_I865G(dev)) {
4608                 dev_priv->display.update_wm = i830_update_wm;
4609                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4610                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4611         } else if (IS_I85X(dev)) {
4612                 dev_priv->display.update_wm = i9xx_update_wm;
4613                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4614                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4615         } else {
4616                 dev_priv->display.update_wm = i830_update_wm;
4617                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4618                 if (IS_845G(dev))
4619                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4620                 else
4621                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4622         }
4623 }
4624
4625 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4626 {
4627         u32 gt_thread_status_mask;
4628
4629         if (IS_HASWELL(dev_priv->dev))
4630                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4631         else
4632                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4633
4634         /* w/a for a sporadic read returning 0 by waiting for the GT
4635          * thread to wake up.
4636          */
4637         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4638                 DRM_ERROR("GT thread status wait timed out\n");
4639 }
4640
4641 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4642 {
4643         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4644         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4645 }
4646
4647 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4648 {
4649         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
4650                             FORCEWAKE_ACK_TIMEOUT_MS))
4651                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4652
4653         I915_WRITE_NOTRACE(FORCEWAKE, 1);
4654         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4655
4656         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
4657                             FORCEWAKE_ACK_TIMEOUT_MS))
4658                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4659
4660         /* WaRsForcewakeWaitTC0:snb */
4661         __gen6_gt_wait_for_thread_c0(dev_priv);
4662 }
4663
4664 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4665 {
4666         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4667         /* something from same cacheline, but !FORCEWAKE_MT */
4668         POSTING_READ(ECOBUS);
4669 }
4670
4671 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4672 {
4673         u32 forcewake_ack;
4674
4675         if (IS_HASWELL(dev_priv->dev))
4676                 forcewake_ack = FORCEWAKE_ACK_HSW;
4677         else
4678                 forcewake_ack = FORCEWAKE_MT_ACK;
4679
4680         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
4681                             FORCEWAKE_ACK_TIMEOUT_MS))
4682                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4683
4684         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4685         /* something from same cacheline, but !FORCEWAKE_MT */
4686         POSTING_READ(ECOBUS);
4687
4688         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
4689                             FORCEWAKE_ACK_TIMEOUT_MS))
4690                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4691
4692         /* WaRsForcewakeWaitTC0:ivb,hsw */
4693         __gen6_gt_wait_for_thread_c0(dev_priv);
4694 }
4695
4696 /*
4697  * Generally this is called implicitly by the register read function. However,
4698  * if some sequence requires the GT to not power down then this function should
4699  * be called at the beginning of the sequence followed by a call to
4700  * gen6_gt_force_wake_put() at the end of the sequence.
4701  */
4702 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4703 {
4704         unsigned long irqflags;
4705
4706         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4707         if (dev_priv->forcewake_count++ == 0)
4708                 dev_priv->gt.force_wake_get(dev_priv);
4709         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4710 }
4711
4712 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4713 {
4714         u32 gtfifodbg;
4715         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4716         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4717              "MMIO read or write has been dropped %x\n", gtfifodbg))
4718                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4719 }
4720
4721 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4722 {
4723         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4724         /* something from same cacheline, but !FORCEWAKE */
4725         POSTING_READ(ECOBUS);
4726         gen6_gt_check_fifodbg(dev_priv);
4727 }
4728
4729 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4730 {
4731         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4732         /* something from same cacheline, but !FORCEWAKE_MT */
4733         POSTING_READ(ECOBUS);
4734         gen6_gt_check_fifodbg(dev_priv);
4735 }
4736
4737 /*
4738  * see gen6_gt_force_wake_get()
4739  */
4740 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4741 {
4742         unsigned long irqflags;
4743
4744         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4745         if (--dev_priv->forcewake_count == 0)
4746                 dev_priv->gt.force_wake_put(dev_priv);
4747         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4748 }
4749
4750 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4751 {
4752         int ret = 0;
4753
4754         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4755                 int loop = 500;
4756                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4757                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4758                         udelay(10);
4759                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4760                 }
4761                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4762                         ++ret;
4763                 dev_priv->gt_fifo_count = fifo;
4764         }
4765         dev_priv->gt_fifo_count--;
4766
4767         return ret;
4768 }
4769
4770 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4771 {
4772         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4773         /* something from same cacheline, but !FORCEWAKE_VLV */
4774         POSTING_READ(FORCEWAKE_ACK_VLV);
4775 }
4776
4777 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4778 {
4779         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
4780                             FORCEWAKE_ACK_TIMEOUT_MS))
4781                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4782
4783         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4784         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4785                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4786
4787         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
4788                             FORCEWAKE_ACK_TIMEOUT_MS))
4789                 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4790
4791         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4792                              FORCEWAKE_KERNEL),
4793                             FORCEWAKE_ACK_TIMEOUT_MS))
4794                 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
4795
4796         /* WaRsForcewakeWaitTC0:vlv */
4797         __gen6_gt_wait_for_thread_c0(dev_priv);
4798 }
4799
4800 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4801 {
4802         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4803         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4804                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4805         /* The below doubles as a POSTING_READ */
4806         gen6_gt_check_fifodbg(dev_priv);
4807 }
4808
4809 void intel_gt_reset(struct drm_device *dev)
4810 {
4811         struct drm_i915_private *dev_priv = dev->dev_private;
4812
4813         if (IS_VALLEYVIEW(dev)) {
4814                 vlv_force_wake_reset(dev_priv);
4815         } else if (INTEL_INFO(dev)->gen >= 6) {
4816                 __gen6_gt_force_wake_reset(dev_priv);
4817                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4818                         __gen6_gt_force_wake_mt_reset(dev_priv);
4819         }
4820 }
4821
4822 void intel_gt_init(struct drm_device *dev)
4823 {
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825
4826         spin_lock_init(&dev_priv->gt_lock);
4827
4828         intel_gt_reset(dev);
4829
4830         if (IS_VALLEYVIEW(dev)) {
4831                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4832                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4833         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4834                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4835                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4836         } else if (IS_GEN6(dev)) {
4837                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4838                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4839         }
4840         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4841                           intel_gen6_powersave_work);
4842 }
4843
4844 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4845 {
4846         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4847
4848         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4849                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4850                 return -EAGAIN;
4851         }
4852
4853         I915_WRITE(GEN6_PCODE_DATA, *val);
4854         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4855
4856         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4857                      500)) {
4858                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4859                 return -ETIMEDOUT;
4860         }
4861
4862         *val = I915_READ(GEN6_PCODE_DATA);
4863         I915_WRITE(GEN6_PCODE_DATA, 0);
4864
4865         return 0;
4866 }
4867
4868 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4869 {
4870         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4871
4872         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4873                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4874                 return -EAGAIN;
4875         }
4876
4877         I915_WRITE(GEN6_PCODE_DATA, val);
4878         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4879
4880         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4881                      500)) {
4882                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4883                 return -ETIMEDOUT;
4884         }
4885
4886         I915_WRITE(GEN6_PCODE_DATA, 0);
4887
4888         return 0;
4889 }
4890
4891 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
4892                         u8 addr, u32 *val)
4893 {
4894         u32 cmd, devfn, be, bar;
4895
4896         bar = 0;
4897         be = 0xf;
4898         devfn = PCI_DEVFN(2, 0);
4899
4900         cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4901                 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4902                 (bar << IOSF_BAR_SHIFT);
4903
4904         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4905
4906         if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4907                 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4908                                  opcode == PUNIT_OPCODE_REG_READ ?
4909                                  "read" : "write");
4910                 return -EAGAIN;
4911         }
4912
4913         I915_WRITE(VLV_IOSF_ADDR, addr);
4914         if (opcode == PUNIT_OPCODE_REG_WRITE)
4915                 I915_WRITE(VLV_IOSF_DATA, *val);
4916         I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4917
4918         if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4919                      5)) {
4920                 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4921                           opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4922                           addr);
4923                 return -ETIMEDOUT;
4924         }
4925
4926         if (opcode == PUNIT_OPCODE_REG_READ)
4927                 *val = I915_READ(VLV_IOSF_DATA);
4928         I915_WRITE(VLV_IOSF_DATA, 0);
4929
4930         return 0;
4931 }
4932
4933 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4934 {
4935         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
4936                             addr, val);
4937 }
4938
4939 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
4940 {
4941         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
4942                             addr, &val);
4943 }
4944
4945 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4946 {
4947         return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
4948                             addr, val);
4949 }
4950
4951 int vlv_gpu_freq(int ddr_freq, int val)
4952 {
4953         int mult, base;
4954
4955         switch (ddr_freq) {
4956         case 800:
4957                 mult = 20;
4958                 base = 120;
4959                 break;
4960         case 1066:
4961                 mult = 22;
4962                 base = 133;
4963                 break;
4964         case 1333:
4965                 mult = 21;
4966                 base = 125;
4967                 break;
4968         default:
4969                 return -1;
4970         }
4971
4972         return ((val - 0xbd) * mult) + base;
4973 }
4974
4975 int vlv_freq_opcode(int ddr_freq, int val)
4976 {
4977         int mult, base;
4978
4979         switch (ddr_freq) {
4980         case 800:
4981                 mult = 20;
4982                 base = 120;
4983                 break;
4984         case 1066:
4985                 mult = 22;
4986                 base = 133;
4987                 break;
4988         case 1333:
4989                 mult = 21;
4990                 base = 125;
4991                 break;
4992         default:
4993                 return -1;
4994         }
4995
4996         val /= mult;
4997         val -= base / mult;
4998         val += 0xbd;
4999
5000         if (val > 0xea)
5001                 val = 0xea;
5002
5003         return val;
5004 }
5005