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1 /*
2  * Copyright © 2012 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
25  *
26  */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
35
36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
38  * during in-memory transfers and, therefore, reduce the power packet.
39  *
40  * The benefits of FBC are mostly visible with solid backgrounds and
41  * variation-less patterns.
42  *
43  * FBC-related functionality can be enabled by the means of the
44  * i915.i915_enable_fbc parameter
45  */
46
47 static bool intel_crtc_active(struct drm_crtc *crtc)
48 {
49         /* Be paranoid as we can arrive here with only partial
50          * state retrieved from the hardware during setup.
51          */
52         return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53 }
54
55 static void i8xx_disable_fbc(struct drm_device *dev)
56 {
57         struct drm_i915_private *dev_priv = dev->dev_private;
58         u32 fbc_ctl;
59
60         /* Disable compression */
61         fbc_ctl = I915_READ(FBC_CONTROL);
62         if ((fbc_ctl & FBC_CTL_EN) == 0)
63                 return;
64
65         fbc_ctl &= ~FBC_CTL_EN;
66         I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68         /* Wait for compressing bit to clear */
69         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70                 DRM_DEBUG_KMS("FBC idle timed out\n");
71                 return;
72         }
73
74         DRM_DEBUG_KMS("disabled FBC\n");
75 }
76
77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
78 {
79         struct drm_device *dev = crtc->dev;
80         struct drm_i915_private *dev_priv = dev->dev_private;
81         struct drm_framebuffer *fb = crtc->fb;
82         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83         struct drm_i915_gem_object *obj = intel_fb->obj;
84         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85         int cfb_pitch;
86         int plane, i;
87         u32 fbc_ctl, fbc_ctl2;
88
89         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90         if (fb->pitches[0] < cfb_pitch)
91                 cfb_pitch = fb->pitches[0];
92
93         /* FBC_CTL wants 64B units */
94         cfb_pitch = (cfb_pitch / 64) - 1;
95         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97         /* Clear old tags */
98         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99                 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101         /* Set it up... */
102         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103         fbc_ctl2 |= plane;
104         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105         I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107         /* enable it... */
108         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109         if (IS_I945GM(dev))
110                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113         fbc_ctl |= obj->fence_reg;
114         I915_WRITE(FBC_CONTROL, fbc_ctl);
115
116         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
118 }
119
120 static bool i8xx_fbc_enabled(struct drm_device *dev)
121 {
122         struct drm_i915_private *dev_priv = dev->dev_private;
123
124         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125 }
126
127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
128 {
129         struct drm_device *dev = crtc->dev;
130         struct drm_i915_private *dev_priv = dev->dev_private;
131         struct drm_framebuffer *fb = crtc->fb;
132         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133         struct drm_i915_gem_object *obj = intel_fb->obj;
134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136         unsigned long stall_watermark = 200;
137         u32 dpfc_ctl;
138
139         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148         /* enable it... */
149         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
151         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
152 }
153
154 static void g4x_disable_fbc(struct drm_device *dev)
155 {
156         struct drm_i915_private *dev_priv = dev->dev_private;
157         u32 dpfc_ctl;
158
159         /* Disable compression */
160         dpfc_ctl = I915_READ(DPFC_CONTROL);
161         if (dpfc_ctl & DPFC_CTL_EN) {
162                 dpfc_ctl &= ~DPFC_CTL_EN;
163                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165                 DRM_DEBUG_KMS("disabled FBC\n");
166         }
167 }
168
169 static bool g4x_fbc_enabled(struct drm_device *dev)
170 {
171         struct drm_i915_private *dev_priv = dev->dev_private;
172
173         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174 }
175
176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
177 {
178         struct drm_i915_private *dev_priv = dev->dev_private;
179         u32 blt_ecoskpd;
180
181         /* Make sure blitter notifies FBC of writes */
182         gen6_gt_force_wake_get(dev_priv);
183         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185                 GEN6_BLITTER_LOCK_SHIFT;
186         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190                          GEN6_BLITTER_LOCK_SHIFT);
191         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192         POSTING_READ(GEN6_BLITTER_ECOSKPD);
193         gen6_gt_force_wake_put(dev_priv);
194 }
195
196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
197 {
198         struct drm_device *dev = crtc->dev;
199         struct drm_i915_private *dev_priv = dev->dev_private;
200         struct drm_framebuffer *fb = crtc->fb;
201         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202         struct drm_i915_gem_object *obj = intel_fb->obj;
203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205         unsigned long stall_watermark = 200;
206         u32 dpfc_ctl;
207
208         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209         dpfc_ctl &= DPFC_RESERVED;
210         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211         /* Set persistent mode for front-buffer rendering, ala X. */
212         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221         /* enable it... */
222         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224         if (IS_GEN6(dev)) {
225                 I915_WRITE(SNB_DPFC_CTL_SA,
226                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228                 sandybridge_blit_fbc_update(dev);
229         }
230
231         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
232 }
233
234 static void ironlake_disable_fbc(struct drm_device *dev)
235 {
236         struct drm_i915_private *dev_priv = dev->dev_private;
237         u32 dpfc_ctl;
238
239         /* Disable compression */
240         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241         if (dpfc_ctl & DPFC_CTL_EN) {
242                 dpfc_ctl &= ~DPFC_CTL_EN;
243                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
245                 if (IS_IVYBRIDGE(dev))
246                         /* WaFbcDisableDpfcClockGating:ivb */
247                         I915_WRITE(ILK_DSPCLK_GATE_D,
248                                    I915_READ(ILK_DSPCLK_GATE_D) &
249                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
250
251                 if (IS_HASWELL(dev))
252                         /* WaFbcDisableDpfcClockGating:hsw */
253                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
254                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
255                                    ~HSW_DPFC_GATING_DISABLE);
256
257                 DRM_DEBUG_KMS("disabled FBC\n");
258         }
259 }
260
261 static bool ironlake_fbc_enabled(struct drm_device *dev)
262 {
263         struct drm_i915_private *dev_priv = dev->dev_private;
264
265         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
266 }
267
268 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269 {
270         struct drm_device *dev = crtc->dev;
271         struct drm_i915_private *dev_priv = dev->dev_private;
272         struct drm_framebuffer *fb = crtc->fb;
273         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274         struct drm_i915_gem_object *obj = intel_fb->obj;
275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276
277         I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
278
279         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280                    IVB_DPFC_CTL_FENCE_EN |
281                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282
283         if (IS_IVYBRIDGE(dev)) {
284                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
285                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
286                 /* WaFbcDisableDpfcClockGating:ivb */
287                 I915_WRITE(ILK_DSPCLK_GATE_D,
288                            I915_READ(ILK_DSPCLK_GATE_D) |
289                            ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
290         } else {
291                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
292                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
293                            HSW_BYPASS_FBC_QUEUE);
294                 /* WaFbcDisableDpfcClockGating:hsw */
295                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
296                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
297                            HSW_DPFC_GATING_DISABLE);
298         }
299
300         I915_WRITE(SNB_DPFC_CTL_SA,
301                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
302         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
303
304         sandybridge_blit_fbc_update(dev);
305
306         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
307 }
308
309 bool intel_fbc_enabled(struct drm_device *dev)
310 {
311         struct drm_i915_private *dev_priv = dev->dev_private;
312
313         if (!dev_priv->display.fbc_enabled)
314                 return false;
315
316         return dev_priv->display.fbc_enabled(dev);
317 }
318
319 static void intel_fbc_work_fn(struct work_struct *__work)
320 {
321         struct intel_fbc_work *work =
322                 container_of(to_delayed_work(__work),
323                              struct intel_fbc_work, work);
324         struct drm_device *dev = work->crtc->dev;
325         struct drm_i915_private *dev_priv = dev->dev_private;
326
327         mutex_lock(&dev->struct_mutex);
328         if (work == dev_priv->fbc_work) {
329                 /* Double check that we haven't switched fb without cancelling
330                  * the prior work.
331                  */
332                 if (work->crtc->fb == work->fb) {
333                         dev_priv->display.enable_fbc(work->crtc,
334                                                      work->interval);
335
336                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
337                         dev_priv->cfb_fb = work->crtc->fb->base.id;
338                         dev_priv->cfb_y = work->crtc->y;
339                 }
340
341                 dev_priv->fbc_work = NULL;
342         }
343         mutex_unlock(&dev->struct_mutex);
344
345         kfree(work);
346 }
347
348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349 {
350         if (dev_priv->fbc_work == NULL)
351                 return;
352
353         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355         /* Synchronisation is provided by struct_mutex and checking of
356          * dev_priv->fbc_work, so we can perform the cancellation
357          * entirely asynchronously.
358          */
359         if (cancel_delayed_work(&dev_priv->fbc_work->work))
360                 /* tasklet was killed before being run, clean up */
361                 kfree(dev_priv->fbc_work);
362
363         /* Mark the work as no longer wanted so that if it does
364          * wake-up (because the work was already running and waiting
365          * for our mutex), it will discover that is no longer
366          * necessary to run.
367          */
368         dev_priv->fbc_work = NULL;
369 }
370
371 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
372 {
373         struct intel_fbc_work *work;
374         struct drm_device *dev = crtc->dev;
375         struct drm_i915_private *dev_priv = dev->dev_private;
376
377         if (!dev_priv->display.enable_fbc)
378                 return;
379
380         intel_cancel_fbc_work(dev_priv);
381
382         work = kzalloc(sizeof *work, GFP_KERNEL);
383         if (work == NULL) {
384                 dev_priv->display.enable_fbc(crtc, interval);
385                 return;
386         }
387
388         work->crtc = crtc;
389         work->fb = crtc->fb;
390         work->interval = interval;
391         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
393         dev_priv->fbc_work = work;
394
395         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
396
397         /* Delay the actual enabling to let pageflipping cease and the
398          * display to settle before starting the compression. Note that
399          * this delay also serves a second purpose: it allows for a
400          * vblank to pass after disabling the FBC before we attempt
401          * to modify the control registers.
402          *
403          * A more complicated solution would involve tracking vblanks
404          * following the termination of the page-flipping sequence
405          * and indeed performing the enable as a co-routine and not
406          * waiting synchronously upon the vblank.
407          */
408         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409 }
410
411 void intel_disable_fbc(struct drm_device *dev)
412 {
413         struct drm_i915_private *dev_priv = dev->dev_private;
414
415         intel_cancel_fbc_work(dev_priv);
416
417         if (!dev_priv->display.disable_fbc)
418                 return;
419
420         dev_priv->display.disable_fbc(dev);
421         dev_priv->cfb_plane = -1;
422 }
423
424 /**
425  * intel_update_fbc - enable/disable FBC as needed
426  * @dev: the drm_device
427  *
428  * Set up the framebuffer compression hardware at mode set time.  We
429  * enable it if possible:
430  *   - plane A only (on pre-965)
431  *   - no pixel mulitply/line duplication
432  *   - no alpha buffer discard
433  *   - no dual wide
434  *   - framebuffer <= 2048 in width, 1536 in height
435  *
436  * We can't assume that any compression will take place (worst case),
437  * so the compressed buffer has to be the same size as the uncompressed
438  * one.  It also must reside (along with the line length buffer) in
439  * stolen memory.
440  *
441  * We need to enable/disable FBC on a global basis.
442  */
443 void intel_update_fbc(struct drm_device *dev)
444 {
445         struct drm_i915_private *dev_priv = dev->dev_private;
446         struct drm_crtc *crtc = NULL, *tmp_crtc;
447         struct intel_crtc *intel_crtc;
448         struct drm_framebuffer *fb;
449         struct intel_framebuffer *intel_fb;
450         struct drm_i915_gem_object *obj;
451         int enable_fbc;
452
453         if (!i915_powersave)
454                 return;
455
456         if (!I915_HAS_FBC(dev))
457                 return;
458
459         /*
460          * If FBC is already on, we just have to verify that we can
461          * keep it that way...
462          * Need to disable if:
463          *   - more than one pipe is active
464          *   - changing FBC params (stride, fence, mode)
465          *   - new fb is too large to fit in compressed buffer
466          *   - going to an unsupported config (interlace, pixel multiply, etc.)
467          */
468         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
469                 if (intel_crtc_active(tmp_crtc) &&
470                     !to_intel_crtc(tmp_crtc)->primary_disabled) {
471                         if (crtc) {
472                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
473                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
474                                 goto out_disable;
475                         }
476                         crtc = tmp_crtc;
477                 }
478         }
479
480         if (!crtc || crtc->fb == NULL) {
481                 DRM_DEBUG_KMS("no output, disabling\n");
482                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
483                 goto out_disable;
484         }
485
486         intel_crtc = to_intel_crtc(crtc);
487         fb = crtc->fb;
488         intel_fb = to_intel_framebuffer(fb);
489         obj = intel_fb->obj;
490
491         enable_fbc = i915_enable_fbc;
492         if (enable_fbc < 0) {
493                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
494                 enable_fbc = 1;
495                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
496                         enable_fbc = 0;
497         }
498         if (!enable_fbc) {
499                 DRM_DEBUG_KMS("fbc disabled per module param\n");
500                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
501                 goto out_disable;
502         }
503         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
504             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
505                 DRM_DEBUG_KMS("mode incompatible with compression, "
506                               "disabling\n");
507                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
508                 goto out_disable;
509         }
510         if ((crtc->mode.hdisplay > 2048) ||
511             (crtc->mode.vdisplay > 1536)) {
512                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
513                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
514                 goto out_disable;
515         }
516         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
517             intel_crtc->plane != 0) {
518                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
519                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
520                 goto out_disable;
521         }
522
523         /* The use of a CPU fence is mandatory in order to detect writes
524          * by the CPU to the scanout and trigger updates to the FBC.
525          */
526         if (obj->tiling_mode != I915_TILING_X ||
527             obj->fence_reg == I915_FENCE_REG_NONE) {
528                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
529                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
530                 goto out_disable;
531         }
532
533         /* If the kernel debugger is active, always disable compression */
534         if (in_dbg_master())
535                 goto out_disable;
536
537         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
538                 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
539                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
540                 goto out_disable;
541         }
542
543         /* If the scanout has not changed, don't modify the FBC settings.
544          * Note that we make the fundamental assumption that the fb->obj
545          * cannot be unpinned (and have its GTT offset and fence revoked)
546          * without first being decoupled from the scanout and FBC disabled.
547          */
548         if (dev_priv->cfb_plane == intel_crtc->plane &&
549             dev_priv->cfb_fb == fb->base.id &&
550             dev_priv->cfb_y == crtc->y)
551                 return;
552
553         if (intel_fbc_enabled(dev)) {
554                 /* We update FBC along two paths, after changing fb/crtc
555                  * configuration (modeswitching) and after page-flipping
556                  * finishes. For the latter, we know that not only did
557                  * we disable the FBC at the start of the page-flip
558                  * sequence, but also more than one vblank has passed.
559                  *
560                  * For the former case of modeswitching, it is possible
561                  * to switch between two FBC valid configurations
562                  * instantaneously so we do need to disable the FBC
563                  * before we can modify its control registers. We also
564                  * have to wait for the next vblank for that to take
565                  * effect. However, since we delay enabling FBC we can
566                  * assume that a vblank has passed since disabling and
567                  * that we can safely alter the registers in the deferred
568                  * callback.
569                  *
570                  * In the scenario that we go from a valid to invalid
571                  * and then back to valid FBC configuration we have
572                  * no strict enforcement that a vblank occurred since
573                  * disabling the FBC. However, along all current pipe
574                  * disabling paths we do need to wait for a vblank at
575                  * some point. And we wait before enabling FBC anyway.
576                  */
577                 DRM_DEBUG_KMS("disabling active FBC for update\n");
578                 intel_disable_fbc(dev);
579         }
580
581         intel_enable_fbc(crtc, 500);
582         return;
583
584 out_disable:
585         /* Multiple disables should be harmless */
586         if (intel_fbc_enabled(dev)) {
587                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
588                 intel_disable_fbc(dev);
589         }
590         i915_gem_stolen_cleanup_compression(dev);
591 }
592
593 static void i915_pineview_get_mem_freq(struct drm_device *dev)
594 {
595         drm_i915_private_t *dev_priv = dev->dev_private;
596         u32 tmp;
597
598         tmp = I915_READ(CLKCFG);
599
600         switch (tmp & CLKCFG_FSB_MASK) {
601         case CLKCFG_FSB_533:
602                 dev_priv->fsb_freq = 533; /* 133*4 */
603                 break;
604         case CLKCFG_FSB_800:
605                 dev_priv->fsb_freq = 800; /* 200*4 */
606                 break;
607         case CLKCFG_FSB_667:
608                 dev_priv->fsb_freq =  667; /* 167*4 */
609                 break;
610         case CLKCFG_FSB_400:
611                 dev_priv->fsb_freq = 400; /* 100*4 */
612                 break;
613         }
614
615         switch (tmp & CLKCFG_MEM_MASK) {
616         case CLKCFG_MEM_533:
617                 dev_priv->mem_freq = 533;
618                 break;
619         case CLKCFG_MEM_667:
620                 dev_priv->mem_freq = 667;
621                 break;
622         case CLKCFG_MEM_800:
623                 dev_priv->mem_freq = 800;
624                 break;
625         }
626
627         /* detect pineview DDR3 setting */
628         tmp = I915_READ(CSHRDDR3CTL);
629         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
630 }
631
632 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
633 {
634         drm_i915_private_t *dev_priv = dev->dev_private;
635         u16 ddrpll, csipll;
636
637         ddrpll = I915_READ16(DDRMPLL1);
638         csipll = I915_READ16(CSIPLL0);
639
640         switch (ddrpll & 0xff) {
641         case 0xc:
642                 dev_priv->mem_freq = 800;
643                 break;
644         case 0x10:
645                 dev_priv->mem_freq = 1066;
646                 break;
647         case 0x14:
648                 dev_priv->mem_freq = 1333;
649                 break;
650         case 0x18:
651                 dev_priv->mem_freq = 1600;
652                 break;
653         default:
654                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
655                                  ddrpll & 0xff);
656                 dev_priv->mem_freq = 0;
657                 break;
658         }
659
660         dev_priv->ips.r_t = dev_priv->mem_freq;
661
662         switch (csipll & 0x3ff) {
663         case 0x00c:
664                 dev_priv->fsb_freq = 3200;
665                 break;
666         case 0x00e:
667                 dev_priv->fsb_freq = 3733;
668                 break;
669         case 0x010:
670                 dev_priv->fsb_freq = 4266;
671                 break;
672         case 0x012:
673                 dev_priv->fsb_freq = 4800;
674                 break;
675         case 0x014:
676                 dev_priv->fsb_freq = 5333;
677                 break;
678         case 0x016:
679                 dev_priv->fsb_freq = 5866;
680                 break;
681         case 0x018:
682                 dev_priv->fsb_freq = 6400;
683                 break;
684         default:
685                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
686                                  csipll & 0x3ff);
687                 dev_priv->fsb_freq = 0;
688                 break;
689         }
690
691         if (dev_priv->fsb_freq == 3200) {
692                 dev_priv->ips.c_m = 0;
693         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
694                 dev_priv->ips.c_m = 1;
695         } else {
696                 dev_priv->ips.c_m = 2;
697         }
698 }
699
700 static const struct cxsr_latency cxsr_latency_table[] = {
701         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
702         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
703         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
704         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
705         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
706
707         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
708         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
709         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
710         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
711         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
712
713         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
714         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
715         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
716         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
717         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
718
719         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
720         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
721         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
722         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
723         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
724
725         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
726         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
727         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
728         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
729         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
730
731         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
732         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
733         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
734         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
735         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
736 };
737
738 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
739                                                          int is_ddr3,
740                                                          int fsb,
741                                                          int mem)
742 {
743         const struct cxsr_latency *latency;
744         int i;
745
746         if (fsb == 0 || mem == 0)
747                 return NULL;
748
749         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
750                 latency = &cxsr_latency_table[i];
751                 if (is_desktop == latency->is_desktop &&
752                     is_ddr3 == latency->is_ddr3 &&
753                     fsb == latency->fsb_freq && mem == latency->mem_freq)
754                         return latency;
755         }
756
757         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
758
759         return NULL;
760 }
761
762 static void pineview_disable_cxsr(struct drm_device *dev)
763 {
764         struct drm_i915_private *dev_priv = dev->dev_private;
765
766         /* deactivate cxsr */
767         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
768 }
769
770 /*
771  * Latency for FIFO fetches is dependent on several factors:
772  *   - memory configuration (speed, channels)
773  *   - chipset
774  *   - current MCH state
775  * It can be fairly high in some situations, so here we assume a fairly
776  * pessimal value.  It's a tradeoff between extra memory fetches (if we
777  * set this value too high, the FIFO will fetch frequently to stay full)
778  * and power consumption (set it too low to save power and we might see
779  * FIFO underruns and display "flicker").
780  *
781  * A value of 5us seems to be a good balance; safe for very low end
782  * platforms but not overly aggressive on lower latency configs.
783  */
784 static const int latency_ns = 5000;
785
786 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
787 {
788         struct drm_i915_private *dev_priv = dev->dev_private;
789         uint32_t dsparb = I915_READ(DSPARB);
790         int size;
791
792         size = dsparb & 0x7f;
793         if (plane)
794                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
795
796         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
797                       plane ? "B" : "A", size);
798
799         return size;
800 }
801
802 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
803 {
804         struct drm_i915_private *dev_priv = dev->dev_private;
805         uint32_t dsparb = I915_READ(DSPARB);
806         int size;
807
808         size = dsparb & 0x1ff;
809         if (plane)
810                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
811         size >>= 1; /* Convert to cachelines */
812
813         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814                       plane ? "B" : "A", size);
815
816         return size;
817 }
818
819 static int i845_get_fifo_size(struct drm_device *dev, int plane)
820 {
821         struct drm_i915_private *dev_priv = dev->dev_private;
822         uint32_t dsparb = I915_READ(DSPARB);
823         int size;
824
825         size = dsparb & 0x7f;
826         size >>= 2; /* Convert to cachelines */
827
828         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
829                       plane ? "B" : "A",
830                       size);
831
832         return size;
833 }
834
835 static int i830_get_fifo_size(struct drm_device *dev, int plane)
836 {
837         struct drm_i915_private *dev_priv = dev->dev_private;
838         uint32_t dsparb = I915_READ(DSPARB);
839         int size;
840
841         size = dsparb & 0x7f;
842         size >>= 1; /* Convert to cachelines */
843
844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845                       plane ? "B" : "A", size);
846
847         return size;
848 }
849
850 /* Pineview has different values for various configs */
851 static const struct intel_watermark_params pineview_display_wm = {
852         PINEVIEW_DISPLAY_FIFO,
853         PINEVIEW_MAX_WM,
854         PINEVIEW_DFT_WM,
855         PINEVIEW_GUARD_WM,
856         PINEVIEW_FIFO_LINE_SIZE
857 };
858 static const struct intel_watermark_params pineview_display_hplloff_wm = {
859         PINEVIEW_DISPLAY_FIFO,
860         PINEVIEW_MAX_WM,
861         PINEVIEW_DFT_HPLLOFF_WM,
862         PINEVIEW_GUARD_WM,
863         PINEVIEW_FIFO_LINE_SIZE
864 };
865 static const struct intel_watermark_params pineview_cursor_wm = {
866         PINEVIEW_CURSOR_FIFO,
867         PINEVIEW_CURSOR_MAX_WM,
868         PINEVIEW_CURSOR_DFT_WM,
869         PINEVIEW_CURSOR_GUARD_WM,
870         PINEVIEW_FIFO_LINE_SIZE,
871 };
872 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
873         PINEVIEW_CURSOR_FIFO,
874         PINEVIEW_CURSOR_MAX_WM,
875         PINEVIEW_CURSOR_DFT_WM,
876         PINEVIEW_CURSOR_GUARD_WM,
877         PINEVIEW_FIFO_LINE_SIZE
878 };
879 static const struct intel_watermark_params g4x_wm_info = {
880         G4X_FIFO_SIZE,
881         G4X_MAX_WM,
882         G4X_MAX_WM,
883         2,
884         G4X_FIFO_LINE_SIZE,
885 };
886 static const struct intel_watermark_params g4x_cursor_wm_info = {
887         I965_CURSOR_FIFO,
888         I965_CURSOR_MAX_WM,
889         I965_CURSOR_DFT_WM,
890         2,
891         G4X_FIFO_LINE_SIZE,
892 };
893 static const struct intel_watermark_params valleyview_wm_info = {
894         VALLEYVIEW_FIFO_SIZE,
895         VALLEYVIEW_MAX_WM,
896         VALLEYVIEW_MAX_WM,
897         2,
898         G4X_FIFO_LINE_SIZE,
899 };
900 static const struct intel_watermark_params valleyview_cursor_wm_info = {
901         I965_CURSOR_FIFO,
902         VALLEYVIEW_CURSOR_MAX_WM,
903         I965_CURSOR_DFT_WM,
904         2,
905         G4X_FIFO_LINE_SIZE,
906 };
907 static const struct intel_watermark_params i965_cursor_wm_info = {
908         I965_CURSOR_FIFO,
909         I965_CURSOR_MAX_WM,
910         I965_CURSOR_DFT_WM,
911         2,
912         I915_FIFO_LINE_SIZE,
913 };
914 static const struct intel_watermark_params i945_wm_info = {
915         I945_FIFO_SIZE,
916         I915_MAX_WM,
917         1,
918         2,
919         I915_FIFO_LINE_SIZE
920 };
921 static const struct intel_watermark_params i915_wm_info = {
922         I915_FIFO_SIZE,
923         I915_MAX_WM,
924         1,
925         2,
926         I915_FIFO_LINE_SIZE
927 };
928 static const struct intel_watermark_params i855_wm_info = {
929         I855GM_FIFO_SIZE,
930         I915_MAX_WM,
931         1,
932         2,
933         I830_FIFO_LINE_SIZE
934 };
935 static const struct intel_watermark_params i830_wm_info = {
936         I830_FIFO_SIZE,
937         I915_MAX_WM,
938         1,
939         2,
940         I830_FIFO_LINE_SIZE
941 };
942
943 static const struct intel_watermark_params ironlake_display_wm_info = {
944         ILK_DISPLAY_FIFO,
945         ILK_DISPLAY_MAXWM,
946         ILK_DISPLAY_DFTWM,
947         2,
948         ILK_FIFO_LINE_SIZE
949 };
950 static const struct intel_watermark_params ironlake_cursor_wm_info = {
951         ILK_CURSOR_FIFO,
952         ILK_CURSOR_MAXWM,
953         ILK_CURSOR_DFTWM,
954         2,
955         ILK_FIFO_LINE_SIZE
956 };
957 static const struct intel_watermark_params ironlake_display_srwm_info = {
958         ILK_DISPLAY_SR_FIFO,
959         ILK_DISPLAY_MAX_SRWM,
960         ILK_DISPLAY_DFT_SRWM,
961         2,
962         ILK_FIFO_LINE_SIZE
963 };
964 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
965         ILK_CURSOR_SR_FIFO,
966         ILK_CURSOR_MAX_SRWM,
967         ILK_CURSOR_DFT_SRWM,
968         2,
969         ILK_FIFO_LINE_SIZE
970 };
971
972 static const struct intel_watermark_params sandybridge_display_wm_info = {
973         SNB_DISPLAY_FIFO,
974         SNB_DISPLAY_MAXWM,
975         SNB_DISPLAY_DFTWM,
976         2,
977         SNB_FIFO_LINE_SIZE
978 };
979 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
980         SNB_CURSOR_FIFO,
981         SNB_CURSOR_MAXWM,
982         SNB_CURSOR_DFTWM,
983         2,
984         SNB_FIFO_LINE_SIZE
985 };
986 static const struct intel_watermark_params sandybridge_display_srwm_info = {
987         SNB_DISPLAY_SR_FIFO,
988         SNB_DISPLAY_MAX_SRWM,
989         SNB_DISPLAY_DFT_SRWM,
990         2,
991         SNB_FIFO_LINE_SIZE
992 };
993 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
994         SNB_CURSOR_SR_FIFO,
995         SNB_CURSOR_MAX_SRWM,
996         SNB_CURSOR_DFT_SRWM,
997         2,
998         SNB_FIFO_LINE_SIZE
999 };
1000
1001
1002 /**
1003  * intel_calculate_wm - calculate watermark level
1004  * @clock_in_khz: pixel clock
1005  * @wm: chip FIFO params
1006  * @pixel_size: display pixel size
1007  * @latency_ns: memory latency for the platform
1008  *
1009  * Calculate the watermark level (the level at which the display plane will
1010  * start fetching from memory again).  Each chip has a different display
1011  * FIFO size and allocation, so the caller needs to figure that out and pass
1012  * in the correct intel_watermark_params structure.
1013  *
1014  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1015  * on the pixel size.  When it reaches the watermark level, it'll start
1016  * fetching FIFO line sized based chunks from memory until the FIFO fills
1017  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1018  * will occur, and a display engine hang could result.
1019  */
1020 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1021                                         const struct intel_watermark_params *wm,
1022                                         int fifo_size,
1023                                         int pixel_size,
1024                                         unsigned long latency_ns)
1025 {
1026         long entries_required, wm_size;
1027
1028         /*
1029          * Note: we need to make sure we don't overflow for various clock &
1030          * latency values.
1031          * clocks go from a few thousand to several hundred thousand.
1032          * latency is usually a few thousand
1033          */
1034         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1035                 1000;
1036         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1037
1038         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1039
1040         wm_size = fifo_size - (entries_required + wm->guard_size);
1041
1042         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1043
1044         /* Don't promote wm_size to unsigned... */
1045         if (wm_size > (long)wm->max_wm)
1046                 wm_size = wm->max_wm;
1047         if (wm_size <= 0)
1048                 wm_size = wm->default_wm;
1049         return wm_size;
1050 }
1051
1052 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1053 {
1054         struct drm_crtc *crtc, *enabled = NULL;
1055
1056         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1057                 if (intel_crtc_active(crtc)) {
1058                         if (enabled)
1059                                 return NULL;
1060                         enabled = crtc;
1061                 }
1062         }
1063
1064         return enabled;
1065 }
1066
1067 static void pineview_update_wm(struct drm_device *dev)
1068 {
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         struct drm_crtc *crtc;
1071         const struct cxsr_latency *latency;
1072         u32 reg;
1073         unsigned long wm;
1074
1075         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1076                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1077         if (!latency) {
1078                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1079                 pineview_disable_cxsr(dev);
1080                 return;
1081         }
1082
1083         crtc = single_enabled_crtc(dev);
1084         if (crtc) {
1085                 int clock = crtc->mode.clock;
1086                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1087
1088                 /* Display SR */
1089                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1090                                         pineview_display_wm.fifo_size,
1091                                         pixel_size, latency->display_sr);
1092                 reg = I915_READ(DSPFW1);
1093                 reg &= ~DSPFW_SR_MASK;
1094                 reg |= wm << DSPFW_SR_SHIFT;
1095                 I915_WRITE(DSPFW1, reg);
1096                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1097
1098                 /* cursor SR */
1099                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1100                                         pineview_display_wm.fifo_size,
1101                                         pixel_size, latency->cursor_sr);
1102                 reg = I915_READ(DSPFW3);
1103                 reg &= ~DSPFW_CURSOR_SR_MASK;
1104                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1105                 I915_WRITE(DSPFW3, reg);
1106
1107                 /* Display HPLL off SR */
1108                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1109                                         pineview_display_hplloff_wm.fifo_size,
1110                                         pixel_size, latency->display_hpll_disable);
1111                 reg = I915_READ(DSPFW3);
1112                 reg &= ~DSPFW_HPLL_SR_MASK;
1113                 reg |= wm & DSPFW_HPLL_SR_MASK;
1114                 I915_WRITE(DSPFW3, reg);
1115
1116                 /* cursor HPLL off SR */
1117                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1118                                         pineview_display_hplloff_wm.fifo_size,
1119                                         pixel_size, latency->cursor_hpll_disable);
1120                 reg = I915_READ(DSPFW3);
1121                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1122                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1123                 I915_WRITE(DSPFW3, reg);
1124                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1125
1126                 /* activate cxsr */
1127                 I915_WRITE(DSPFW3,
1128                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1129                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1130         } else {
1131                 pineview_disable_cxsr(dev);
1132                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1133         }
1134 }
1135
1136 static bool g4x_compute_wm0(struct drm_device *dev,
1137                             int plane,
1138                             const struct intel_watermark_params *display,
1139                             int display_latency_ns,
1140                             const struct intel_watermark_params *cursor,
1141                             int cursor_latency_ns,
1142                             int *plane_wm,
1143                             int *cursor_wm)
1144 {
1145         struct drm_crtc *crtc;
1146         int htotal, hdisplay, clock, pixel_size;
1147         int line_time_us, line_count;
1148         int entries, tlb_miss;
1149
1150         crtc = intel_get_crtc_for_plane(dev, plane);
1151         if (!intel_crtc_active(crtc)) {
1152                 *cursor_wm = cursor->guard_size;
1153                 *plane_wm = display->guard_size;
1154                 return false;
1155         }
1156
1157         htotal = crtc->mode.htotal;
1158         hdisplay = crtc->mode.hdisplay;
1159         clock = crtc->mode.clock;
1160         pixel_size = crtc->fb->bits_per_pixel / 8;
1161
1162         /* Use the small buffer method to calculate plane watermark */
1163         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1164         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1165         if (tlb_miss > 0)
1166                 entries += tlb_miss;
1167         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1168         *plane_wm = entries + display->guard_size;
1169         if (*plane_wm > (int)display->max_wm)
1170                 *plane_wm = display->max_wm;
1171
1172         /* Use the large buffer method to calculate cursor watermark */
1173         line_time_us = ((htotal * 1000) / clock);
1174         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1175         entries = line_count * 64 * pixel_size;
1176         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1177         if (tlb_miss > 0)
1178                 entries += tlb_miss;
1179         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1180         *cursor_wm = entries + cursor->guard_size;
1181         if (*cursor_wm > (int)cursor->max_wm)
1182                 *cursor_wm = (int)cursor->max_wm;
1183
1184         return true;
1185 }
1186
1187 /*
1188  * Check the wm result.
1189  *
1190  * If any calculated watermark values is larger than the maximum value that
1191  * can be programmed into the associated watermark register, that watermark
1192  * must be disabled.
1193  */
1194 static bool g4x_check_srwm(struct drm_device *dev,
1195                            int display_wm, int cursor_wm,
1196                            const struct intel_watermark_params *display,
1197                            const struct intel_watermark_params *cursor)
1198 {
1199         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1200                       display_wm, cursor_wm);
1201
1202         if (display_wm > display->max_wm) {
1203                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1204                               display_wm, display->max_wm);
1205                 return false;
1206         }
1207
1208         if (cursor_wm > cursor->max_wm) {
1209                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1210                               cursor_wm, cursor->max_wm);
1211                 return false;
1212         }
1213
1214         if (!(display_wm || cursor_wm)) {
1215                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1216                 return false;
1217         }
1218
1219         return true;
1220 }
1221
1222 static bool g4x_compute_srwm(struct drm_device *dev,
1223                              int plane,
1224                              int latency_ns,
1225                              const struct intel_watermark_params *display,
1226                              const struct intel_watermark_params *cursor,
1227                              int *display_wm, int *cursor_wm)
1228 {
1229         struct drm_crtc *crtc;
1230         int hdisplay, htotal, pixel_size, clock;
1231         unsigned long line_time_us;
1232         int line_count, line_size;
1233         int small, large;
1234         int entries;
1235
1236         if (!latency_ns) {
1237                 *display_wm = *cursor_wm = 0;
1238                 return false;
1239         }
1240
1241         crtc = intel_get_crtc_for_plane(dev, plane);
1242         hdisplay = crtc->mode.hdisplay;
1243         htotal = crtc->mode.htotal;
1244         clock = crtc->mode.clock;
1245         pixel_size = crtc->fb->bits_per_pixel / 8;
1246
1247         line_time_us = (htotal * 1000) / clock;
1248         line_count = (latency_ns / line_time_us + 1000) / 1000;
1249         line_size = hdisplay * pixel_size;
1250
1251         /* Use the minimum of the small and large buffer method for primary */
1252         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1253         large = line_count * line_size;
1254
1255         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1256         *display_wm = entries + display->guard_size;
1257
1258         /* calculate the self-refresh watermark for display cursor */
1259         entries = line_count * pixel_size * 64;
1260         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1261         *cursor_wm = entries + cursor->guard_size;
1262
1263         return g4x_check_srwm(dev,
1264                               *display_wm, *cursor_wm,
1265                               display, cursor);
1266 }
1267
1268 static bool vlv_compute_drain_latency(struct drm_device *dev,
1269                                      int plane,
1270                                      int *plane_prec_mult,
1271                                      int *plane_dl,
1272                                      int *cursor_prec_mult,
1273                                      int *cursor_dl)
1274 {
1275         struct drm_crtc *crtc;
1276         int clock, pixel_size;
1277         int entries;
1278
1279         crtc = intel_get_crtc_for_plane(dev, plane);
1280         if (!intel_crtc_active(crtc))
1281                 return false;
1282
1283         clock = crtc->mode.clock;       /* VESA DOT Clock */
1284         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1285
1286         entries = (clock / 1000) * pixel_size;
1287         *plane_prec_mult = (entries > 256) ?
1288                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1289         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1290                                                      pixel_size);
1291
1292         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1293         *cursor_prec_mult = (entries > 256) ?
1294                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1295         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1296
1297         return true;
1298 }
1299
1300 /*
1301  * Update drain latency registers of memory arbiter
1302  *
1303  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1304  * to be programmed. Each plane has a drain latency multiplier and a drain
1305  * latency value.
1306  */
1307
1308 static void vlv_update_drain_latency(struct drm_device *dev)
1309 {
1310         struct drm_i915_private *dev_priv = dev->dev_private;
1311         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1312         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1313         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1314                                                         either 16 or 32 */
1315
1316         /* For plane A, Cursor A */
1317         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1318                                       &cursor_prec_mult, &cursora_dl)) {
1319                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1320                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1321                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1322                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1323
1324                 I915_WRITE(VLV_DDL1, cursora_prec |
1325                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1326                                 planea_prec | planea_dl);
1327         }
1328
1329         /* For plane B, Cursor B */
1330         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1331                                       &cursor_prec_mult, &cursorb_dl)) {
1332                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1333                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1334                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1335                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1336
1337                 I915_WRITE(VLV_DDL2, cursorb_prec |
1338                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1339                                 planeb_prec | planeb_dl);
1340         }
1341 }
1342
1343 #define single_plane_enabled(mask) is_power_of_2(mask)
1344
1345 static void valleyview_update_wm(struct drm_device *dev)
1346 {
1347         static const int sr_latency_ns = 12000;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350         int plane_sr, cursor_sr;
1351         int ignore_plane_sr, ignore_cursor_sr;
1352         unsigned int enabled = 0;
1353
1354         vlv_update_drain_latency(dev);
1355
1356         if (g4x_compute_wm0(dev, PIPE_A,
1357                             &valleyview_wm_info, latency_ns,
1358                             &valleyview_cursor_wm_info, latency_ns,
1359                             &planea_wm, &cursora_wm))
1360                 enabled |= 1 << PIPE_A;
1361
1362         if (g4x_compute_wm0(dev, PIPE_B,
1363                             &valleyview_wm_info, latency_ns,
1364                             &valleyview_cursor_wm_info, latency_ns,
1365                             &planeb_wm, &cursorb_wm))
1366                 enabled |= 1 << PIPE_B;
1367
1368         if (single_plane_enabled(enabled) &&
1369             g4x_compute_srwm(dev, ffs(enabled) - 1,
1370                              sr_latency_ns,
1371                              &valleyview_wm_info,
1372                              &valleyview_cursor_wm_info,
1373                              &plane_sr, &ignore_cursor_sr) &&
1374             g4x_compute_srwm(dev, ffs(enabled) - 1,
1375                              2*sr_latency_ns,
1376                              &valleyview_wm_info,
1377                              &valleyview_cursor_wm_info,
1378                              &ignore_plane_sr, &cursor_sr)) {
1379                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1380         } else {
1381                 I915_WRITE(FW_BLC_SELF_VLV,
1382                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1383                 plane_sr = cursor_sr = 0;
1384         }
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387                       planea_wm, cursora_wm,
1388                       planeb_wm, cursorb_wm,
1389                       plane_sr, cursor_sr);
1390
1391         I915_WRITE(DSPFW1,
1392                    (plane_sr << DSPFW_SR_SHIFT) |
1393                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1395                    planea_wm);
1396         I915_WRITE(DSPFW2,
1397                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1398                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1399         I915_WRITE(DSPFW3,
1400                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1401                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1402 }
1403
1404 static void g4x_update_wm(struct drm_device *dev)
1405 {
1406         static const int sr_latency_ns = 12000;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1409         int plane_sr, cursor_sr;
1410         unsigned int enabled = 0;
1411
1412         if (g4x_compute_wm0(dev, PIPE_A,
1413                             &g4x_wm_info, latency_ns,
1414                             &g4x_cursor_wm_info, latency_ns,
1415                             &planea_wm, &cursora_wm))
1416                 enabled |= 1 << PIPE_A;
1417
1418         if (g4x_compute_wm0(dev, PIPE_B,
1419                             &g4x_wm_info, latency_ns,
1420                             &g4x_cursor_wm_info, latency_ns,
1421                             &planeb_wm, &cursorb_wm))
1422                 enabled |= 1 << PIPE_B;
1423
1424         if (single_plane_enabled(enabled) &&
1425             g4x_compute_srwm(dev, ffs(enabled) - 1,
1426                              sr_latency_ns,
1427                              &g4x_wm_info,
1428                              &g4x_cursor_wm_info,
1429                              &plane_sr, &cursor_sr)) {
1430                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1431         } else {
1432                 I915_WRITE(FW_BLC_SELF,
1433                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1434                 plane_sr = cursor_sr = 0;
1435         }
1436
1437         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1438                       planea_wm, cursora_wm,
1439                       planeb_wm, cursorb_wm,
1440                       plane_sr, cursor_sr);
1441
1442         I915_WRITE(DSPFW1,
1443                    (plane_sr << DSPFW_SR_SHIFT) |
1444                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1445                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1446                    planea_wm);
1447         I915_WRITE(DSPFW2,
1448                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1449                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1450         /* HPLL off in SR has some issues on G4x... disable it */
1451         I915_WRITE(DSPFW3,
1452                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1453                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1454 }
1455
1456 static void i965_update_wm(struct drm_device *dev)
1457 {
1458         struct drm_i915_private *dev_priv = dev->dev_private;
1459         struct drm_crtc *crtc;
1460         int srwm = 1;
1461         int cursor_sr = 16;
1462
1463         /* Calc sr entries for one plane configs */
1464         crtc = single_enabled_crtc(dev);
1465         if (crtc) {
1466                 /* self-refresh has much higher latency */
1467                 static const int sr_latency_ns = 12000;
1468                 int clock = crtc->mode.clock;
1469                 int htotal = crtc->mode.htotal;
1470                 int hdisplay = crtc->mode.hdisplay;
1471                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1472                 unsigned long line_time_us;
1473                 int entries;
1474
1475                 line_time_us = ((htotal * 1000) / clock);
1476
1477                 /* Use ns/us then divide to preserve precision */
1478                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479                         pixel_size * hdisplay;
1480                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1481                 srwm = I965_FIFO_SIZE - entries;
1482                 if (srwm < 0)
1483                         srwm = 1;
1484                 srwm &= 0x1ff;
1485                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1486                               entries, srwm);
1487
1488                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1489                         pixel_size * 64;
1490                 entries = DIV_ROUND_UP(entries,
1491                                           i965_cursor_wm_info.cacheline_size);
1492                 cursor_sr = i965_cursor_wm_info.fifo_size -
1493                         (entries + i965_cursor_wm_info.guard_size);
1494
1495                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1496                         cursor_sr = i965_cursor_wm_info.max_wm;
1497
1498                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499                               "cursor %d\n", srwm, cursor_sr);
1500
1501                 if (IS_CRESTLINE(dev))
1502                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1503         } else {
1504                 /* Turn off self refresh if both pipes are enabled */
1505                 if (IS_CRESTLINE(dev))
1506                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1507                                    & ~FW_BLC_SELF_EN);
1508         }
1509
1510         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1511                       srwm);
1512
1513         /* 965 has limitations... */
1514         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1515                    (8 << 16) | (8 << 8) | (8 << 0));
1516         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1517         /* update cursor SR watermark */
1518         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1519 }
1520
1521 static void i9xx_update_wm(struct drm_device *dev)
1522 {
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         const struct intel_watermark_params *wm_info;
1525         uint32_t fwater_lo;
1526         uint32_t fwater_hi;
1527         int cwm, srwm = 1;
1528         int fifo_size;
1529         int planea_wm, planeb_wm;
1530         struct drm_crtc *crtc, *enabled = NULL;
1531
1532         if (IS_I945GM(dev))
1533                 wm_info = &i945_wm_info;
1534         else if (!IS_GEN2(dev))
1535                 wm_info = &i915_wm_info;
1536         else
1537                 wm_info = &i855_wm_info;
1538
1539         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540         crtc = intel_get_crtc_for_plane(dev, 0);
1541         if (intel_crtc_active(crtc)) {
1542                 int cpp = crtc->fb->bits_per_pixel / 8;
1543                 if (IS_GEN2(dev))
1544                         cpp = 4;
1545
1546                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1547                                                wm_info, fifo_size, cpp,
1548                                                latency_ns);
1549                 enabled = crtc;
1550         } else
1551                 planea_wm = fifo_size - wm_info->guard_size;
1552
1553         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554         crtc = intel_get_crtc_for_plane(dev, 1);
1555         if (intel_crtc_active(crtc)) {
1556                 int cpp = crtc->fb->bits_per_pixel / 8;
1557                 if (IS_GEN2(dev))
1558                         cpp = 4;
1559
1560                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1561                                                wm_info, fifo_size, cpp,
1562                                                latency_ns);
1563                 if (enabled == NULL)
1564                         enabled = crtc;
1565                 else
1566                         enabled = NULL;
1567         } else
1568                 planeb_wm = fifo_size - wm_info->guard_size;
1569
1570         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1571
1572         /*
1573          * Overlay gets an aggressive default since video jitter is bad.
1574          */
1575         cwm = 2;
1576
1577         /* Play safe and disable self-refresh before adjusting watermarks. */
1578         if (IS_I945G(dev) || IS_I945GM(dev))
1579                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1580         else if (IS_I915GM(dev))
1581                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1582
1583         /* Calc sr entries for one plane configs */
1584         if (HAS_FW_BLC(dev) && enabled) {
1585                 /* self-refresh has much higher latency */
1586                 static const int sr_latency_ns = 6000;
1587                 int clock = enabled->mode.clock;
1588                 int htotal = enabled->mode.htotal;
1589                 int hdisplay = enabled->mode.hdisplay;
1590                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1591                 unsigned long line_time_us;
1592                 int entries;
1593
1594                 line_time_us = (htotal * 1000) / clock;
1595
1596                 /* Use ns/us then divide to preserve precision */
1597                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1598                         pixel_size * hdisplay;
1599                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1600                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1601                 srwm = wm_info->fifo_size - entries;
1602                 if (srwm < 0)
1603                         srwm = 1;
1604
1605                 if (IS_I945G(dev) || IS_I945GM(dev))
1606                         I915_WRITE(FW_BLC_SELF,
1607                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1608                 else if (IS_I915GM(dev))
1609                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1610         }
1611
1612         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613                       planea_wm, planeb_wm, cwm, srwm);
1614
1615         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1616         fwater_hi = (cwm & 0x1f);
1617
1618         /* Set request length to 8 cachelines per fetch */
1619         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1620         fwater_hi = fwater_hi | (1 << 8);
1621
1622         I915_WRITE(FW_BLC, fwater_lo);
1623         I915_WRITE(FW_BLC2, fwater_hi);
1624
1625         if (HAS_FW_BLC(dev)) {
1626                 if (enabled) {
1627                         if (IS_I945G(dev) || IS_I945GM(dev))
1628                                 I915_WRITE(FW_BLC_SELF,
1629                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1630                         else if (IS_I915GM(dev))
1631                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1632                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1633                 } else
1634                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1635         }
1636 }
1637
1638 static void i830_update_wm(struct drm_device *dev)
1639 {
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         struct drm_crtc *crtc;
1642         uint32_t fwater_lo;
1643         int planea_wm;
1644
1645         crtc = single_enabled_crtc(dev);
1646         if (crtc == NULL)
1647                 return;
1648
1649         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1650                                        dev_priv->display.get_fifo_size(dev, 0),
1651                                        4, latency_ns);
1652         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1653         fwater_lo |= (3<<8) | planea_wm;
1654
1655         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1656
1657         I915_WRITE(FW_BLC, fwater_lo);
1658 }
1659
1660 #define ILK_LP0_PLANE_LATENCY           700
1661 #define ILK_LP0_CURSOR_LATENCY          1300
1662
1663 /*
1664  * Check the wm result.
1665  *
1666  * If any calculated watermark values is larger than the maximum value that
1667  * can be programmed into the associated watermark register, that watermark
1668  * must be disabled.
1669  */
1670 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1671                                 int fbc_wm, int display_wm, int cursor_wm,
1672                                 const struct intel_watermark_params *display,
1673                                 const struct intel_watermark_params *cursor)
1674 {
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1678                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1679
1680         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1681                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1682                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1683
1684                 /* fbc has it's own way to disable FBC WM */
1685                 I915_WRITE(DISP_ARB_CTL,
1686                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1687                 return false;
1688         } else if (INTEL_INFO(dev)->gen >= 6) {
1689                 /* enable FBC WM (except on ILK, where it must remain off) */
1690                 I915_WRITE(DISP_ARB_CTL,
1691                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1692         }
1693
1694         if (display_wm > display->max_wm) {
1695                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1696                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1697                 return false;
1698         }
1699
1700         if (cursor_wm > cursor->max_wm) {
1701                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1702                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1703                 return false;
1704         }
1705
1706         if (!(fbc_wm || display_wm || cursor_wm)) {
1707                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1708                 return false;
1709         }
1710
1711         return true;
1712 }
1713
1714 /*
1715  * Compute watermark values of WM[1-3],
1716  */
1717 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1718                                   int latency_ns,
1719                                   const struct intel_watermark_params *display,
1720                                   const struct intel_watermark_params *cursor,
1721                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1722 {
1723         struct drm_crtc *crtc;
1724         unsigned long line_time_us;
1725         int hdisplay, htotal, pixel_size, clock;
1726         int line_count, line_size;
1727         int small, large;
1728         int entries;
1729
1730         if (!latency_ns) {
1731                 *fbc_wm = *display_wm = *cursor_wm = 0;
1732                 return false;
1733         }
1734
1735         crtc = intel_get_crtc_for_plane(dev, plane);
1736         hdisplay = crtc->mode.hdisplay;
1737         htotal = crtc->mode.htotal;
1738         clock = crtc->mode.clock;
1739         pixel_size = crtc->fb->bits_per_pixel / 8;
1740
1741         line_time_us = (htotal * 1000) / clock;
1742         line_count = (latency_ns / line_time_us + 1000) / 1000;
1743         line_size = hdisplay * pixel_size;
1744
1745         /* Use the minimum of the small and large buffer method for primary */
1746         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1747         large = line_count * line_size;
1748
1749         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1750         *display_wm = entries + display->guard_size;
1751
1752         /*
1753          * Spec says:
1754          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1755          */
1756         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1757
1758         /* calculate the self-refresh watermark for display cursor */
1759         entries = line_count * pixel_size * 64;
1760         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1761         *cursor_wm = entries + cursor->guard_size;
1762
1763         return ironlake_check_srwm(dev, level,
1764                                    *fbc_wm, *display_wm, *cursor_wm,
1765                                    display, cursor);
1766 }
1767
1768 static void ironlake_update_wm(struct drm_device *dev)
1769 {
1770         struct drm_i915_private *dev_priv = dev->dev_private;
1771         int fbc_wm, plane_wm, cursor_wm;
1772         unsigned int enabled;
1773
1774         enabled = 0;
1775         if (g4x_compute_wm0(dev, PIPE_A,
1776                             &ironlake_display_wm_info,
1777                             ILK_LP0_PLANE_LATENCY,
1778                             &ironlake_cursor_wm_info,
1779                             ILK_LP0_CURSOR_LATENCY,
1780                             &plane_wm, &cursor_wm)) {
1781                 I915_WRITE(WM0_PIPEA_ILK,
1782                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1783                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1784                               " plane %d, " "cursor: %d\n",
1785                               plane_wm, cursor_wm);
1786                 enabled |= 1 << PIPE_A;
1787         }
1788
1789         if (g4x_compute_wm0(dev, PIPE_B,
1790                             &ironlake_display_wm_info,
1791                             ILK_LP0_PLANE_LATENCY,
1792                             &ironlake_cursor_wm_info,
1793                             ILK_LP0_CURSOR_LATENCY,
1794                             &plane_wm, &cursor_wm)) {
1795                 I915_WRITE(WM0_PIPEB_ILK,
1796                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1797                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1798                               " plane %d, cursor: %d\n",
1799                               plane_wm, cursor_wm);
1800                 enabled |= 1 << PIPE_B;
1801         }
1802
1803         /*
1804          * Calculate and update the self-refresh watermark only when one
1805          * display plane is used.
1806          */
1807         I915_WRITE(WM3_LP_ILK, 0);
1808         I915_WRITE(WM2_LP_ILK, 0);
1809         I915_WRITE(WM1_LP_ILK, 0);
1810
1811         if (!single_plane_enabled(enabled))
1812                 return;
1813         enabled = ffs(enabled) - 1;
1814
1815         /* WM1 */
1816         if (!ironlake_compute_srwm(dev, 1, enabled,
1817                                    ILK_READ_WM1_LATENCY() * 500,
1818                                    &ironlake_display_srwm_info,
1819                                    &ironlake_cursor_srwm_info,
1820                                    &fbc_wm, &plane_wm, &cursor_wm))
1821                 return;
1822
1823         I915_WRITE(WM1_LP_ILK,
1824                    WM1_LP_SR_EN |
1825                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1826                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1827                    (plane_wm << WM1_LP_SR_SHIFT) |
1828                    cursor_wm);
1829
1830         /* WM2 */
1831         if (!ironlake_compute_srwm(dev, 2, enabled,
1832                                    ILK_READ_WM2_LATENCY() * 500,
1833                                    &ironlake_display_srwm_info,
1834                                    &ironlake_cursor_srwm_info,
1835                                    &fbc_wm, &plane_wm, &cursor_wm))
1836                 return;
1837
1838         I915_WRITE(WM2_LP_ILK,
1839                    WM2_LP_EN |
1840                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1841                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1842                    (plane_wm << WM1_LP_SR_SHIFT) |
1843                    cursor_wm);
1844
1845         /*
1846          * WM3 is unsupported on ILK, probably because we don't have latency
1847          * data for that power state
1848          */
1849 }
1850
1851 static void sandybridge_update_wm(struct drm_device *dev)
1852 {
1853         struct drm_i915_private *dev_priv = dev->dev_private;
1854         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1855         u32 val;
1856         int fbc_wm, plane_wm, cursor_wm;
1857         unsigned int enabled;
1858
1859         enabled = 0;
1860         if (g4x_compute_wm0(dev, PIPE_A,
1861                             &sandybridge_display_wm_info, latency,
1862                             &sandybridge_cursor_wm_info, latency,
1863                             &plane_wm, &cursor_wm)) {
1864                 val = I915_READ(WM0_PIPEA_ILK);
1865                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1866                 I915_WRITE(WM0_PIPEA_ILK, val |
1867                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1868                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1869                               " plane %d, " "cursor: %d\n",
1870                               plane_wm, cursor_wm);
1871                 enabled |= 1 << PIPE_A;
1872         }
1873
1874         if (g4x_compute_wm0(dev, PIPE_B,
1875                             &sandybridge_display_wm_info, latency,
1876                             &sandybridge_cursor_wm_info, latency,
1877                             &plane_wm, &cursor_wm)) {
1878                 val = I915_READ(WM0_PIPEB_ILK);
1879                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1880                 I915_WRITE(WM0_PIPEB_ILK, val |
1881                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1882                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1883                               " plane %d, cursor: %d\n",
1884                               plane_wm, cursor_wm);
1885                 enabled |= 1 << PIPE_B;
1886         }
1887
1888         /*
1889          * Calculate and update the self-refresh watermark only when one
1890          * display plane is used.
1891          *
1892          * SNB support 3 levels of watermark.
1893          *
1894          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1895          * and disabled in the descending order
1896          *
1897          */
1898         I915_WRITE(WM3_LP_ILK, 0);
1899         I915_WRITE(WM2_LP_ILK, 0);
1900         I915_WRITE(WM1_LP_ILK, 0);
1901
1902         if (!single_plane_enabled(enabled) ||
1903             dev_priv->sprite_scaling_enabled)
1904                 return;
1905         enabled = ffs(enabled) - 1;
1906
1907         /* WM1 */
1908         if (!ironlake_compute_srwm(dev, 1, enabled,
1909                                    SNB_READ_WM1_LATENCY() * 500,
1910                                    &sandybridge_display_srwm_info,
1911                                    &sandybridge_cursor_srwm_info,
1912                                    &fbc_wm, &plane_wm, &cursor_wm))
1913                 return;
1914
1915         I915_WRITE(WM1_LP_ILK,
1916                    WM1_LP_SR_EN |
1917                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1918                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1919                    (plane_wm << WM1_LP_SR_SHIFT) |
1920                    cursor_wm);
1921
1922         /* WM2 */
1923         if (!ironlake_compute_srwm(dev, 2, enabled,
1924                                    SNB_READ_WM2_LATENCY() * 500,
1925                                    &sandybridge_display_srwm_info,
1926                                    &sandybridge_cursor_srwm_info,
1927                                    &fbc_wm, &plane_wm, &cursor_wm))
1928                 return;
1929
1930         I915_WRITE(WM2_LP_ILK,
1931                    WM2_LP_EN |
1932                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1933                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1934                    (plane_wm << WM1_LP_SR_SHIFT) |
1935                    cursor_wm);
1936
1937         /* WM3 */
1938         if (!ironlake_compute_srwm(dev, 3, enabled,
1939                                    SNB_READ_WM3_LATENCY() * 500,
1940                                    &sandybridge_display_srwm_info,
1941                                    &sandybridge_cursor_srwm_info,
1942                                    &fbc_wm, &plane_wm, &cursor_wm))
1943                 return;
1944
1945         I915_WRITE(WM3_LP_ILK,
1946                    WM3_LP_EN |
1947                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1948                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1949                    (plane_wm << WM1_LP_SR_SHIFT) |
1950                    cursor_wm);
1951 }
1952
1953 static void ivybridge_update_wm(struct drm_device *dev)
1954 {
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1957         u32 val;
1958         int fbc_wm, plane_wm, cursor_wm;
1959         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1960         unsigned int enabled;
1961
1962         enabled = 0;
1963         if (g4x_compute_wm0(dev, PIPE_A,
1964                             &sandybridge_display_wm_info, latency,
1965                             &sandybridge_cursor_wm_info, latency,
1966                             &plane_wm, &cursor_wm)) {
1967                 val = I915_READ(WM0_PIPEA_ILK);
1968                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1969                 I915_WRITE(WM0_PIPEA_ILK, val |
1970                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1971                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1972                               " plane %d, " "cursor: %d\n",
1973                               plane_wm, cursor_wm);
1974                 enabled |= 1 << PIPE_A;
1975         }
1976
1977         if (g4x_compute_wm0(dev, PIPE_B,
1978                             &sandybridge_display_wm_info, latency,
1979                             &sandybridge_cursor_wm_info, latency,
1980                             &plane_wm, &cursor_wm)) {
1981                 val = I915_READ(WM0_PIPEB_ILK);
1982                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1983                 I915_WRITE(WM0_PIPEB_ILK, val |
1984                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1985                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1986                               " plane %d, cursor: %d\n",
1987                               plane_wm, cursor_wm);
1988                 enabled |= 1 << PIPE_B;
1989         }
1990
1991         if (g4x_compute_wm0(dev, PIPE_C,
1992                             &sandybridge_display_wm_info, latency,
1993                             &sandybridge_cursor_wm_info, latency,
1994                             &plane_wm, &cursor_wm)) {
1995                 val = I915_READ(WM0_PIPEC_IVB);
1996                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1997                 I915_WRITE(WM0_PIPEC_IVB, val |
1998                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1999                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2000                               " plane %d, cursor: %d\n",
2001                               plane_wm, cursor_wm);
2002                 enabled |= 1 << PIPE_C;
2003         }
2004
2005         /*
2006          * Calculate and update the self-refresh watermark only when one
2007          * display plane is used.
2008          *
2009          * SNB support 3 levels of watermark.
2010          *
2011          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2012          * and disabled in the descending order
2013          *
2014          */
2015         I915_WRITE(WM3_LP_ILK, 0);
2016         I915_WRITE(WM2_LP_ILK, 0);
2017         I915_WRITE(WM1_LP_ILK, 0);
2018
2019         if (!single_plane_enabled(enabled) ||
2020             dev_priv->sprite_scaling_enabled)
2021                 return;
2022         enabled = ffs(enabled) - 1;
2023
2024         /* WM1 */
2025         if (!ironlake_compute_srwm(dev, 1, enabled,
2026                                    SNB_READ_WM1_LATENCY() * 500,
2027                                    &sandybridge_display_srwm_info,
2028                                    &sandybridge_cursor_srwm_info,
2029                                    &fbc_wm, &plane_wm, &cursor_wm))
2030                 return;
2031
2032         I915_WRITE(WM1_LP_ILK,
2033                    WM1_LP_SR_EN |
2034                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2035                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2036                    (plane_wm << WM1_LP_SR_SHIFT) |
2037                    cursor_wm);
2038
2039         /* WM2 */
2040         if (!ironlake_compute_srwm(dev, 2, enabled,
2041                                    SNB_READ_WM2_LATENCY() * 500,
2042                                    &sandybridge_display_srwm_info,
2043                                    &sandybridge_cursor_srwm_info,
2044                                    &fbc_wm, &plane_wm, &cursor_wm))
2045                 return;
2046
2047         I915_WRITE(WM2_LP_ILK,
2048                    WM2_LP_EN |
2049                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2050                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2051                    (plane_wm << WM1_LP_SR_SHIFT) |
2052                    cursor_wm);
2053
2054         /* WM3, note we have to correct the cursor latency */
2055         if (!ironlake_compute_srwm(dev, 3, enabled,
2056                                    SNB_READ_WM3_LATENCY() * 500,
2057                                    &sandybridge_display_srwm_info,
2058                                    &sandybridge_cursor_srwm_info,
2059                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2060             !ironlake_compute_srwm(dev, 3, enabled,
2061                                    2 * SNB_READ_WM3_LATENCY() * 500,
2062                                    &sandybridge_display_srwm_info,
2063                                    &sandybridge_cursor_srwm_info,
2064                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2065                 return;
2066
2067         I915_WRITE(WM3_LP_ILK,
2068                    WM3_LP_EN |
2069                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2070                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2071                    (plane_wm << WM1_LP_SR_SHIFT) |
2072                    cursor_wm);
2073 }
2074
2075 static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2076                                       struct drm_crtc *crtc)
2077 {
2078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079         uint32_t pixel_rate, pfit_size;
2080
2081         if (intel_crtc->config.pixel_target_clock)
2082                 pixel_rate = intel_crtc->config.pixel_target_clock;
2083         else
2084                 pixel_rate = intel_crtc->config.adjusted_mode.clock;
2085
2086         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2087          * adjust the pixel_rate here. */
2088
2089         pfit_size = intel_crtc->config.pch_pfit.size;
2090         if (pfit_size) {
2091                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2092
2093                 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2094                 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2095                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2096                 pfit_h = pfit_size & 0xFFFF;
2097                 if (pipe_w < pfit_w)
2098                         pipe_w = pfit_w;
2099                 if (pipe_h < pfit_h)
2100                         pipe_h = pfit_h;
2101
2102                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2103                                      pfit_w * pfit_h);
2104         }
2105
2106         return pixel_rate;
2107 }
2108
2109 static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2110                                uint32_t latency)
2111 {
2112         uint64_t ret;
2113
2114         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2115         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2116
2117         return ret;
2118 }
2119
2120 static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2121                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2122                                uint32_t latency)
2123 {
2124         uint32_t ret;
2125
2126         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2127         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2128         ret = DIV_ROUND_UP(ret, 64) + 2;
2129         return ret;
2130 }
2131
2132 static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2133                            uint8_t bytes_per_pixel)
2134 {
2135         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2136 }
2137
2138 struct hsw_pipe_wm_parameters {
2139         bool active;
2140         bool sprite_enabled;
2141         uint8_t pri_bytes_per_pixel;
2142         uint8_t spr_bytes_per_pixel;
2143         uint8_t cur_bytes_per_pixel;
2144         uint32_t pri_horiz_pixels;
2145         uint32_t spr_horiz_pixels;
2146         uint32_t cur_horiz_pixels;
2147         uint32_t pipe_htotal;
2148         uint32_t pixel_rate;
2149 };
2150
2151 struct hsw_wm_maximums {
2152         uint16_t pri;
2153         uint16_t spr;
2154         uint16_t cur;
2155         uint16_t fbc;
2156 };
2157
2158 struct hsw_lp_wm_result {
2159         bool enable;
2160         bool fbc_enable;
2161         uint32_t pri_val;
2162         uint32_t spr_val;
2163         uint32_t cur_val;
2164         uint32_t fbc_val;
2165 };
2166
2167 struct hsw_wm_values {
2168         uint32_t wm_pipe[3];
2169         uint32_t wm_lp[3];
2170         uint32_t wm_lp_spr[3];
2171         uint32_t wm_linetime[3];
2172         bool enable_fbc_wm;
2173 };
2174
2175 enum hsw_data_buf_partitioning {
2176         HSW_DATA_BUF_PART_1_2,
2177         HSW_DATA_BUF_PART_5_6,
2178 };
2179
2180 /* For both WM_PIPE and WM_LP. */
2181 static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2182                                    uint32_t mem_value,
2183                                    bool is_lp)
2184 {
2185         uint32_t method1, method2;
2186
2187         /* TODO: for now, assume the primary plane is always enabled. */
2188         if (!params->active)
2189                 return 0;
2190
2191         method1 = hsw_wm_method1(params->pixel_rate,
2192                                  params->pri_bytes_per_pixel,
2193                                  mem_value);
2194
2195         if (!is_lp)
2196                 return method1;
2197
2198         method2 = hsw_wm_method2(params->pixel_rate,
2199                                  params->pipe_htotal,
2200                                  params->pri_horiz_pixels,
2201                                  params->pri_bytes_per_pixel,
2202                                  mem_value);
2203
2204         return min(method1, method2);
2205 }
2206
2207 /* For both WM_PIPE and WM_LP. */
2208 static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2209                                    uint32_t mem_value)
2210 {
2211         uint32_t method1, method2;
2212
2213         if (!params->active || !params->sprite_enabled)
2214                 return 0;
2215
2216         method1 = hsw_wm_method1(params->pixel_rate,
2217                                  params->spr_bytes_per_pixel,
2218                                  mem_value);
2219         method2 = hsw_wm_method2(params->pixel_rate,
2220                                  params->pipe_htotal,
2221                                  params->spr_horiz_pixels,
2222                                  params->spr_bytes_per_pixel,
2223                                  mem_value);
2224         return min(method1, method2);
2225 }
2226
2227 /* For both WM_PIPE and WM_LP. */
2228 static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2229                                    uint32_t mem_value)
2230 {
2231         if (!params->active)
2232                 return 0;
2233
2234         return hsw_wm_method2(params->pixel_rate,
2235                               params->pipe_htotal,
2236                               params->cur_horiz_pixels,
2237                               params->cur_bytes_per_pixel,
2238                               mem_value);
2239 }
2240
2241 /* Only for WM_LP. */
2242 static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2243                                    uint32_t pri_val,
2244                                    uint32_t mem_value)
2245 {
2246         if (!params->active)
2247                 return 0;
2248
2249         return hsw_wm_fbc(pri_val,
2250                           params->pri_horiz_pixels,
2251                           params->pri_bytes_per_pixel);
2252 }
2253
2254 static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
2255                               struct hsw_pipe_wm_parameters *params,
2256                               struct hsw_lp_wm_result *result)
2257 {
2258         enum pipe pipe;
2259         uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2260
2261         for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2262                 struct hsw_pipe_wm_parameters *p = &params[pipe];
2263
2264                 pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
2265                 spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
2266                 cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
2267                 fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
2268         }
2269
2270         result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2271         result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2272         result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2273         result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2274
2275         if (result->fbc_val > max->fbc) {
2276                 result->fbc_enable = false;
2277                 result->fbc_val = 0;
2278         } else {
2279                 result->fbc_enable = true;
2280         }
2281
2282         result->enable = result->pri_val <= max->pri &&
2283                          result->spr_val <= max->spr &&
2284                          result->cur_val <= max->cur;
2285         return result->enable;
2286 }
2287
2288 static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2289                                     uint32_t mem_value, enum pipe pipe,
2290                                     struct hsw_pipe_wm_parameters *params)
2291 {
2292         uint32_t pri_val, cur_val, spr_val;
2293
2294         pri_val = hsw_compute_pri_wm(params, mem_value, false);
2295         spr_val = hsw_compute_spr_wm(params, mem_value);
2296         cur_val = hsw_compute_cur_wm(params, mem_value);
2297
2298         WARN(pri_val > 127,
2299              "Primary WM error, mode not supported for pipe %c\n",
2300              pipe_name(pipe));
2301         WARN(spr_val > 127,
2302              "Sprite WM error, mode not supported for pipe %c\n",
2303              pipe_name(pipe));
2304         WARN(cur_val > 63,
2305              "Cursor WM error, mode not supported for pipe %c\n",
2306              pipe_name(pipe));
2307
2308         return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2309                (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2310                cur_val;
2311 }
2312
2313 static uint32_t
2314 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2315 {
2316         struct drm_i915_private *dev_priv = dev->dev_private;
2317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2319         u32 linetime, ips_linetime;
2320
2321         if (!intel_crtc_active(crtc))
2322                 return 0;
2323
2324         /* The WM are computed with base on how long it takes to fill a single
2325          * row at the given clock rate, multiplied by 8.
2326          * */
2327         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2328         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2329                                          intel_ddi_get_cdclk_freq(dev_priv));
2330
2331         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2332                PIPE_WM_LINETIME_TIME(linetime);
2333 }
2334
2335 static void hsw_compute_wm_parameters(struct drm_device *dev,
2336                                       struct hsw_pipe_wm_parameters *params,
2337                                       uint32_t *wm,
2338                                       struct hsw_wm_maximums *lp_max_1_2)
2339 {
2340         struct drm_i915_private *dev_priv = dev->dev_private;
2341         struct drm_crtc *crtc;
2342         struct drm_plane *plane;
2343         uint64_t sskpd = I915_READ64(MCH_SSKPD);
2344         enum pipe pipe;
2345         int pipes_active = 0, sprites_enabled = 0;
2346
2347         if ((sskpd >> 56) & 0xFF)
2348                 wm[0] = (sskpd >> 56) & 0xFF;
2349         else
2350                 wm[0] = sskpd & 0xF;
2351         wm[1] = ((sskpd >> 4) & 0xFF) * 5;
2352         wm[2] = ((sskpd >> 12) & 0xFF) * 5;
2353         wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
2354         wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
2355
2356         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2357                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2358                 struct hsw_pipe_wm_parameters *p;
2359
2360                 pipe = intel_crtc->pipe;
2361                 p = &params[pipe];
2362
2363                 p->active = intel_crtc_active(crtc);
2364                 if (!p->active)
2365                         continue;
2366
2367                 pipes_active++;
2368
2369                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2370                 p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2371                 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2372                 p->cur_bytes_per_pixel = 4;
2373                 p->pri_horiz_pixels =
2374                         intel_crtc->config.requested_mode.hdisplay;
2375                 p->cur_horiz_pixels = 64;
2376         }
2377
2378         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2379                 struct intel_plane *intel_plane = to_intel_plane(plane);
2380                 struct hsw_pipe_wm_parameters *p;
2381
2382                 pipe = intel_plane->pipe;
2383                 p = &params[pipe];
2384
2385                 p->sprite_enabled = intel_plane->wm.enable;
2386                 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2387                 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
2388
2389                 if (p->sprite_enabled)
2390                         sprites_enabled++;
2391         }
2392
2393         if (pipes_active > 1) {
2394                 lp_max_1_2->pri = sprites_enabled ? 128 : 256;
2395                 lp_max_1_2->spr = 128;
2396                 lp_max_1_2->cur = 64;
2397         } else {
2398                 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
2399                 lp_max_1_2->spr = 384;
2400                 lp_max_1_2->cur = 255;
2401         }
2402         lp_max_1_2->fbc = 15;
2403 }
2404
2405 static void hsw_compute_wm_results(struct drm_device *dev,
2406                                    struct hsw_pipe_wm_parameters *params,
2407                                    uint32_t *wm,
2408                                    struct hsw_wm_maximums *lp_maximums,
2409                                    struct hsw_wm_values *results)
2410 {
2411         struct drm_i915_private *dev_priv = dev->dev_private;
2412         struct drm_crtc *crtc;
2413         struct hsw_lp_wm_result lp_results[4] = {};
2414         enum pipe pipe;
2415         int level, max_level, wm_lp;
2416
2417         for (level = 1; level <= 4; level++)
2418                 if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
2419                                        &lp_results[level - 1]))
2420                         break;
2421         max_level = level - 1;
2422
2423         /* The spec says it is preferred to disable FBC WMs instead of disabling
2424          * a WM level. */
2425         results->enable_fbc_wm = true;
2426         for (level = 1; level <= max_level; level++) {
2427                 if (!lp_results[level - 1].fbc_enable) {
2428                         results->enable_fbc_wm = false;
2429                         break;
2430                 }
2431         }
2432
2433         memset(results, 0, sizeof(*results));
2434         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2435                 const struct hsw_lp_wm_result *r;
2436
2437                 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2438                 if (level > max_level)
2439                         break;
2440
2441                 r = &lp_results[level - 1];
2442                 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2443                                                           r->fbc_val,
2444                                                           r->pri_val,
2445                                                           r->cur_val);
2446                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2447         }
2448
2449         for_each_pipe(pipe)
2450                 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2451                                                              pipe,
2452                                                              &params[pipe]);
2453
2454         for_each_pipe(pipe) {
2455                 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2456                 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2457         }
2458 }
2459
2460 /*
2461  * The spec says we shouldn't write when we don't need, because every write
2462  * causes WMs to be re-evaluated, expending some power.
2463  */
2464 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2465                                 struct hsw_wm_values *results,
2466                                 enum hsw_data_buf_partitioning partitioning)
2467 {
2468         struct hsw_wm_values previous;
2469         uint32_t val;
2470         enum hsw_data_buf_partitioning prev_partitioning;
2471         bool prev_enable_fbc_wm;
2472
2473         previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2474         previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2475         previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2476         previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2477         previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2478         previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2479         previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2480         previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2481         previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2482         previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2483         previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2484         previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2485
2486         prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2487                             HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2488
2489         prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2490
2491         if (memcmp(results->wm_pipe, previous.wm_pipe,
2492                    sizeof(results->wm_pipe)) == 0 &&
2493             memcmp(results->wm_lp, previous.wm_lp,
2494                    sizeof(results->wm_lp)) == 0 &&
2495             memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2496                    sizeof(results->wm_lp_spr)) == 0 &&
2497             memcmp(results->wm_linetime, previous.wm_linetime,
2498                    sizeof(results->wm_linetime)) == 0 &&
2499             partitioning == prev_partitioning &&
2500             results->enable_fbc_wm == prev_enable_fbc_wm)
2501                 return;
2502
2503         if (previous.wm_lp[2] != 0)
2504                 I915_WRITE(WM3_LP_ILK, 0);
2505         if (previous.wm_lp[1] != 0)
2506                 I915_WRITE(WM2_LP_ILK, 0);
2507         if (previous.wm_lp[0] != 0)
2508                 I915_WRITE(WM1_LP_ILK, 0);
2509
2510         if (previous.wm_pipe[0] != results->wm_pipe[0])
2511                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2512         if (previous.wm_pipe[1] != results->wm_pipe[1])
2513                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2514         if (previous.wm_pipe[2] != results->wm_pipe[2])
2515                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2516
2517         if (previous.wm_linetime[0] != results->wm_linetime[0])
2518                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2519         if (previous.wm_linetime[1] != results->wm_linetime[1])
2520                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2521         if (previous.wm_linetime[2] != results->wm_linetime[2])
2522                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2523
2524         if (prev_partitioning != partitioning) {
2525                 val = I915_READ(WM_MISC);
2526                 if (partitioning == HSW_DATA_BUF_PART_1_2)
2527                         val &= ~WM_MISC_DATA_PARTITION_5_6;
2528                 else
2529                         val |= WM_MISC_DATA_PARTITION_5_6;
2530                 I915_WRITE(WM_MISC, val);
2531         }
2532
2533         if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2534                 val = I915_READ(DISP_ARB_CTL);
2535                 if (results->enable_fbc_wm)
2536                         val &= ~DISP_FBC_WM_DIS;
2537                 else
2538                         val |= DISP_FBC_WM_DIS;
2539                 I915_WRITE(DISP_ARB_CTL, val);
2540         }
2541
2542         if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2543                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2544         if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2545                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2546         if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2547                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2548
2549         if (results->wm_lp[0] != 0)
2550                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2551         if (results->wm_lp[1] != 0)
2552                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2553         if (results->wm_lp[2] != 0)
2554                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2555 }
2556
2557 static void haswell_update_wm(struct drm_device *dev)
2558 {
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         struct hsw_wm_maximums lp_max_1_2;
2561         struct hsw_pipe_wm_parameters params[3];
2562         struct hsw_wm_values results;
2563         uint32_t wm[5];
2564
2565         hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2);
2566         hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results);
2567         hsw_write_wm_values(dev_priv, &results, HSW_DATA_BUF_PART_1_2);
2568 }
2569
2570 static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2571                                      uint32_t sprite_width, int pixel_size,
2572                                      bool enable)
2573 {
2574         struct drm_plane *plane;
2575
2576         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2577                 struct intel_plane *intel_plane = to_intel_plane(plane);
2578
2579                 if (intel_plane->pipe == pipe) {
2580                         intel_plane->wm.enable = enable;
2581                         intel_plane->wm.horiz_pixels = sprite_width + 1;
2582                         intel_plane->wm.bytes_per_pixel = pixel_size;
2583                         break;
2584                 }
2585         }
2586
2587         haswell_update_wm(dev);
2588 }
2589
2590 static bool
2591 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2592                               uint32_t sprite_width, int pixel_size,
2593                               const struct intel_watermark_params *display,
2594                               int display_latency_ns, int *sprite_wm)
2595 {
2596         struct drm_crtc *crtc;
2597         int clock;
2598         int entries, tlb_miss;
2599
2600         crtc = intel_get_crtc_for_plane(dev, plane);
2601         if (!intel_crtc_active(crtc)) {
2602                 *sprite_wm = display->guard_size;
2603                 return false;
2604         }
2605
2606         clock = crtc->mode.clock;
2607
2608         /* Use the small buffer method to calculate the sprite watermark */
2609         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2610         tlb_miss = display->fifo_size*display->cacheline_size -
2611                 sprite_width * 8;
2612         if (tlb_miss > 0)
2613                 entries += tlb_miss;
2614         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2615         *sprite_wm = entries + display->guard_size;
2616         if (*sprite_wm > (int)display->max_wm)
2617                 *sprite_wm = display->max_wm;
2618
2619         return true;
2620 }
2621
2622 static bool
2623 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2624                                 uint32_t sprite_width, int pixel_size,
2625                                 const struct intel_watermark_params *display,
2626                                 int latency_ns, int *sprite_wm)
2627 {
2628         struct drm_crtc *crtc;
2629         unsigned long line_time_us;
2630         int clock;
2631         int line_count, line_size;
2632         int small, large;
2633         int entries;
2634
2635         if (!latency_ns) {
2636                 *sprite_wm = 0;
2637                 return false;
2638         }
2639
2640         crtc = intel_get_crtc_for_plane(dev, plane);
2641         clock = crtc->mode.clock;
2642         if (!clock) {
2643                 *sprite_wm = 0;
2644                 return false;
2645         }
2646
2647         line_time_us = (sprite_width * 1000) / clock;
2648         if (!line_time_us) {
2649                 *sprite_wm = 0;
2650                 return false;
2651         }
2652
2653         line_count = (latency_ns / line_time_us + 1000) / 1000;
2654         line_size = sprite_width * pixel_size;
2655
2656         /* Use the minimum of the small and large buffer method for primary */
2657         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2658         large = line_count * line_size;
2659
2660         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2661         *sprite_wm = entries + display->guard_size;
2662
2663         return *sprite_wm > 0x3ff ? false : true;
2664 }
2665
2666 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2667                                          uint32_t sprite_width, int pixel_size,
2668                                          bool enable)
2669 {
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2672         u32 val;
2673         int sprite_wm, reg;
2674         int ret;
2675
2676         if (!enable)
2677                 return;
2678
2679         switch (pipe) {
2680         case 0:
2681                 reg = WM0_PIPEA_ILK;
2682                 break;
2683         case 1:
2684                 reg = WM0_PIPEB_ILK;
2685                 break;
2686         case 2:
2687                 reg = WM0_PIPEC_IVB;
2688                 break;
2689         default:
2690                 return; /* bad pipe */
2691         }
2692
2693         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2694                                             &sandybridge_display_wm_info,
2695                                             latency, &sprite_wm);
2696         if (!ret) {
2697                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2698                               pipe_name(pipe));
2699                 return;
2700         }
2701
2702         val = I915_READ(reg);
2703         val &= ~WM0_PIPE_SPRITE_MASK;
2704         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2705         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2706
2707
2708         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2709                                               pixel_size,
2710                                               &sandybridge_display_srwm_info,
2711                                               SNB_READ_WM1_LATENCY() * 500,
2712                                               &sprite_wm);
2713         if (!ret) {
2714                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2715                               pipe_name(pipe));
2716                 return;
2717         }
2718         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2719
2720         /* Only IVB has two more LP watermarks for sprite */
2721         if (!IS_IVYBRIDGE(dev))
2722                 return;
2723
2724         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2725                                               pixel_size,
2726                                               &sandybridge_display_srwm_info,
2727                                               SNB_READ_WM2_LATENCY() * 500,
2728                                               &sprite_wm);
2729         if (!ret) {
2730                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2731                               pipe_name(pipe));
2732                 return;
2733         }
2734         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2735
2736         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2737                                               pixel_size,
2738                                               &sandybridge_display_srwm_info,
2739                                               SNB_READ_WM3_LATENCY() * 500,
2740                                               &sprite_wm);
2741         if (!ret) {
2742                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2743                               pipe_name(pipe));
2744                 return;
2745         }
2746         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2747 }
2748
2749 /**
2750  * intel_update_watermarks - update FIFO watermark values based on current modes
2751  *
2752  * Calculate watermark values for the various WM regs based on current mode
2753  * and plane configuration.
2754  *
2755  * There are several cases to deal with here:
2756  *   - normal (i.e. non-self-refresh)
2757  *   - self-refresh (SR) mode
2758  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2759  *   - lines are small relative to FIFO size (buffer can hold more than 2
2760  *     lines), so need to account for TLB latency
2761  *
2762  *   The normal calculation is:
2763  *     watermark = dotclock * bytes per pixel * latency
2764  *   where latency is platform & configuration dependent (we assume pessimal
2765  *   values here).
2766  *
2767  *   The SR calculation is:
2768  *     watermark = (trunc(latency/line time)+1) * surface width *
2769  *       bytes per pixel
2770  *   where
2771  *     line time = htotal / dotclock
2772  *     surface width = hdisplay for normal plane and 64 for cursor
2773  *   and latency is assumed to be high, as above.
2774  *
2775  * The final value programmed to the register should always be rounded up,
2776  * and include an extra 2 entries to account for clock crossings.
2777  *
2778  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2779  * to set the non-SR watermarks to 8.
2780  */
2781 void intel_update_watermarks(struct drm_device *dev)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784
2785         if (dev_priv->display.update_wm)
2786                 dev_priv->display.update_wm(dev);
2787 }
2788
2789 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2790                                     uint32_t sprite_width, int pixel_size,
2791                                     bool enable)
2792 {
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794
2795         if (dev_priv->display.update_sprite_wm)
2796                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2797                                                    pixel_size, enable);
2798 }
2799
2800 static struct drm_i915_gem_object *
2801 intel_alloc_context_page(struct drm_device *dev)
2802 {
2803         struct drm_i915_gem_object *ctx;
2804         int ret;
2805
2806         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2807
2808         ctx = i915_gem_alloc_object(dev, 4096);
2809         if (!ctx) {
2810                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2811                 return NULL;
2812         }
2813
2814         ret = i915_gem_object_pin(ctx, 4096, true, false);
2815         if (ret) {
2816                 DRM_ERROR("failed to pin power context: %d\n", ret);
2817                 goto err_unref;
2818         }
2819
2820         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2821         if (ret) {
2822                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2823                 goto err_unpin;
2824         }
2825
2826         return ctx;
2827
2828 err_unpin:
2829         i915_gem_object_unpin(ctx);
2830 err_unref:
2831         drm_gem_object_unreference(&ctx->base);
2832         return NULL;
2833 }
2834
2835 /**
2836  * Lock protecting IPS related data structures
2837  */
2838 DEFINE_SPINLOCK(mchdev_lock);
2839
2840 /* Global for IPS driver to get at the current i915 device. Protected by
2841  * mchdev_lock. */
2842 static struct drm_i915_private *i915_mch_dev;
2843
2844 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2845 {
2846         struct drm_i915_private *dev_priv = dev->dev_private;
2847         u16 rgvswctl;
2848
2849         assert_spin_locked(&mchdev_lock);
2850
2851         rgvswctl = I915_READ16(MEMSWCTL);
2852         if (rgvswctl & MEMCTL_CMD_STS) {
2853                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2854                 return false; /* still busy with another command */
2855         }
2856
2857         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2858                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2859         I915_WRITE16(MEMSWCTL, rgvswctl);
2860         POSTING_READ16(MEMSWCTL);
2861
2862         rgvswctl |= MEMCTL_CMD_STS;
2863         I915_WRITE16(MEMSWCTL, rgvswctl);
2864
2865         return true;
2866 }
2867
2868 static void ironlake_enable_drps(struct drm_device *dev)
2869 {
2870         struct drm_i915_private *dev_priv = dev->dev_private;
2871         u32 rgvmodectl = I915_READ(MEMMODECTL);
2872         u8 fmax, fmin, fstart, vstart;
2873
2874         spin_lock_irq(&mchdev_lock);
2875
2876         /* Enable temp reporting */
2877         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2878         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2879
2880         /* 100ms RC evaluation intervals */
2881         I915_WRITE(RCUPEI, 100000);
2882         I915_WRITE(RCDNEI, 100000);
2883
2884         /* Set max/min thresholds to 90ms and 80ms respectively */
2885         I915_WRITE(RCBMAXAVG, 90000);
2886         I915_WRITE(RCBMINAVG, 80000);
2887
2888         I915_WRITE(MEMIHYST, 1);
2889
2890         /* Set up min, max, and cur for interrupt handling */
2891         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2892         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2893         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2894                 MEMMODE_FSTART_SHIFT;
2895
2896         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2897                 PXVFREQ_PX_SHIFT;
2898
2899         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2900         dev_priv->ips.fstart = fstart;
2901
2902         dev_priv->ips.max_delay = fstart;
2903         dev_priv->ips.min_delay = fmin;
2904         dev_priv->ips.cur_delay = fstart;
2905
2906         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2907                          fmax, fmin, fstart);
2908
2909         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2910
2911         /*
2912          * Interrupts will be enabled in ironlake_irq_postinstall
2913          */
2914
2915         I915_WRITE(VIDSTART, vstart);
2916         POSTING_READ(VIDSTART);
2917
2918         rgvmodectl |= MEMMODE_SWMODE_EN;
2919         I915_WRITE(MEMMODECTL, rgvmodectl);
2920
2921         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2922                 DRM_ERROR("stuck trying to change perf mode\n");
2923         mdelay(1);
2924
2925         ironlake_set_drps(dev, fstart);
2926
2927         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2928                 I915_READ(0x112e0);
2929         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2930         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2931         getrawmonotonic(&dev_priv->ips.last_time2);
2932
2933         spin_unlock_irq(&mchdev_lock);
2934 }
2935
2936 static void ironlake_disable_drps(struct drm_device *dev)
2937 {
2938         struct drm_i915_private *dev_priv = dev->dev_private;
2939         u16 rgvswctl;
2940
2941         spin_lock_irq(&mchdev_lock);
2942
2943         rgvswctl = I915_READ16(MEMSWCTL);
2944
2945         /* Ack interrupts, disable EFC interrupt */
2946         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2947         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2948         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2949         I915_WRITE(DEIIR, DE_PCU_EVENT);
2950         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2951
2952         /* Go back to the starting frequency */
2953         ironlake_set_drps(dev, dev_priv->ips.fstart);
2954         mdelay(1);
2955         rgvswctl |= MEMCTL_CMD_STS;
2956         I915_WRITE(MEMSWCTL, rgvswctl);
2957         mdelay(1);
2958
2959         spin_unlock_irq(&mchdev_lock);
2960 }
2961
2962 /* There's a funny hw issue where the hw returns all 0 when reading from
2963  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2964  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2965  * all limits and the gpu stuck at whatever frequency it is at atm).
2966  */
2967 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2968 {
2969         u32 limits;
2970
2971         limits = 0;
2972
2973         if (*val >= dev_priv->rps.max_delay)
2974                 *val = dev_priv->rps.max_delay;
2975         limits |= dev_priv->rps.max_delay << 24;
2976
2977         /* Only set the down limit when we've reached the lowest level to avoid
2978          * getting more interrupts, otherwise leave this clear. This prevents a
2979          * race in the hw when coming out of rc6: There's a tiny window where
2980          * the hw runs at the minimal clock before selecting the desired
2981          * frequency, if the down threshold expires in that window we will not
2982          * receive a down interrupt. */
2983         if (*val <= dev_priv->rps.min_delay) {
2984                 *val = dev_priv->rps.min_delay;
2985                 limits |= dev_priv->rps.min_delay << 16;
2986         }
2987
2988         return limits;
2989 }
2990
2991 void gen6_set_rps(struct drm_device *dev, u8 val)
2992 {
2993         struct drm_i915_private *dev_priv = dev->dev_private;
2994         u32 limits = gen6_rps_limits(dev_priv, &val);
2995
2996         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2997         WARN_ON(val > dev_priv->rps.max_delay);
2998         WARN_ON(val < dev_priv->rps.min_delay);
2999
3000         if (val == dev_priv->rps.cur_delay)
3001                 return;
3002
3003         if (IS_HASWELL(dev))
3004                 I915_WRITE(GEN6_RPNSWREQ,
3005                            HSW_FREQUENCY(val));
3006         else
3007                 I915_WRITE(GEN6_RPNSWREQ,
3008                            GEN6_FREQUENCY(val) |
3009                            GEN6_OFFSET(0) |
3010                            GEN6_AGGRESSIVE_TURBO);
3011
3012         /* Make sure we continue to get interrupts
3013          * until we hit the minimum or maximum frequencies.
3014          */
3015         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3016
3017         POSTING_READ(GEN6_RPNSWREQ);
3018
3019         dev_priv->rps.cur_delay = val;
3020
3021         trace_intel_gpu_freq_change(val * 50);
3022 }
3023
3024 void valleyview_set_rps(struct drm_device *dev, u8 val)
3025 {
3026         struct drm_i915_private *dev_priv = dev->dev_private;
3027         unsigned long timeout = jiffies + msecs_to_jiffies(10);
3028         u32 limits = gen6_rps_limits(dev_priv, &val);
3029         u32 pval;
3030
3031         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3032         WARN_ON(val > dev_priv->rps.max_delay);
3033         WARN_ON(val < dev_priv->rps.min_delay);
3034
3035         DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
3036                          vlv_gpu_freq(dev_priv->mem_freq,
3037                                       dev_priv->rps.cur_delay),
3038                          vlv_gpu_freq(dev_priv->mem_freq, val));
3039
3040         if (val == dev_priv->rps.cur_delay)
3041                 return;
3042
3043         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3044
3045         do {
3046                 pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3047                 if (time_after(jiffies, timeout)) {
3048                         DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3049                         break;
3050                 }
3051                 udelay(10);
3052         } while (pval & 1);
3053
3054         pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3055         if ((pval >> 8) != val)
3056                 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
3057                           val, pval >> 8);
3058
3059         /* Make sure we continue to get interrupts
3060          * until we hit the minimum or maximum frequencies.
3061          */
3062         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3063
3064         dev_priv->rps.cur_delay = pval >> 8;
3065
3066         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3067 }
3068
3069
3070 static void gen6_disable_rps(struct drm_device *dev)
3071 {
3072         struct drm_i915_private *dev_priv = dev->dev_private;
3073
3074         I915_WRITE(GEN6_RC_CONTROL, 0);
3075         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3076         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3077         I915_WRITE(GEN6_PMIER, 0);
3078         /* Complete PM interrupt masking here doesn't race with the rps work
3079          * item again unmasking PM interrupts because that is using a different
3080          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3081          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3082
3083         spin_lock_irq(&dev_priv->rps.lock);
3084         dev_priv->rps.pm_iir = 0;
3085         spin_unlock_irq(&dev_priv->rps.lock);
3086
3087         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
3088 }
3089
3090 static void valleyview_disable_rps(struct drm_device *dev)
3091 {
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093
3094         I915_WRITE(GEN6_RC_CONTROL, 0);
3095         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3096         I915_WRITE(GEN6_PMIER, 0);
3097         /* Complete PM interrupt masking here doesn't race with the rps work
3098          * item again unmasking PM interrupts because that is using a different
3099          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3100          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3101
3102         spin_lock_irq(&dev_priv->rps.lock);
3103         dev_priv->rps.pm_iir = 0;
3104         spin_unlock_irq(&dev_priv->rps.lock);
3105
3106         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
3107
3108         if (dev_priv->vlv_pctx) {
3109                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3110                 dev_priv->vlv_pctx = NULL;
3111         }
3112 }
3113
3114 int intel_enable_rc6(const struct drm_device *dev)
3115 {
3116         /* Respect the kernel parameter if it is set */
3117         if (i915_enable_rc6 >= 0)
3118                 return i915_enable_rc6;
3119
3120         /* Disable RC6 on Ironlake */
3121         if (INTEL_INFO(dev)->gen == 5)
3122                 return 0;
3123
3124         if (IS_HASWELL(dev)) {
3125                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3126                 return INTEL_RC6_ENABLE;
3127         }
3128
3129         /* snb/ivb have more than one rc6 state. */
3130         if (INTEL_INFO(dev)->gen == 6) {
3131                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3132                 return INTEL_RC6_ENABLE;
3133         }
3134
3135         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3136         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3137 }
3138
3139 static void gen6_enable_rps(struct drm_device *dev)
3140 {
3141         struct drm_i915_private *dev_priv = dev->dev_private;
3142         struct intel_ring_buffer *ring;
3143         u32 rp_state_cap;
3144         u32 gt_perf_status;
3145         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3146         u32 gtfifodbg;
3147         int rc6_mode;
3148         int i, ret;
3149
3150         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3151
3152         /* Here begins a magic sequence of register writes to enable
3153          * auto-downclocking.
3154          *
3155          * Perhaps there might be some value in exposing these to
3156          * userspace...
3157          */
3158         I915_WRITE(GEN6_RC_STATE, 0);
3159
3160         /* Clear the DBG now so we don't confuse earlier errors */
3161         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3162                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3163                 I915_WRITE(GTFIFODBG, gtfifodbg);
3164         }
3165
3166         gen6_gt_force_wake_get(dev_priv);
3167
3168         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3169         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3170
3171         /* In units of 50MHz */
3172         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3173         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3174         dev_priv->rps.cur_delay = 0;
3175
3176         /* disable the counters and set deterministic thresholds */
3177         I915_WRITE(GEN6_RC_CONTROL, 0);
3178
3179         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3180         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3181         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3182         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3183         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3184
3185         for_each_ring(ring, dev_priv, i)
3186                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3187
3188         I915_WRITE(GEN6_RC_SLEEP, 0);
3189         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3190         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3191         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3192         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3193
3194         /* Check if we are enabling RC6 */
3195         rc6_mode = intel_enable_rc6(dev_priv->dev);
3196         if (rc6_mode & INTEL_RC6_ENABLE)
3197                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3198
3199         /* We don't use those on Haswell */
3200         if (!IS_HASWELL(dev)) {
3201                 if (rc6_mode & INTEL_RC6p_ENABLE)
3202                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3203
3204                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3205                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3206         }
3207
3208         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3209                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3210                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3211                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3212
3213         I915_WRITE(GEN6_RC_CONTROL,
3214                    rc6_mask |
3215                    GEN6_RC_CTL_EI_MODE(1) |
3216                    GEN6_RC_CTL_HW_ENABLE);
3217
3218         if (IS_HASWELL(dev)) {
3219                 I915_WRITE(GEN6_RPNSWREQ,
3220                            HSW_FREQUENCY(10));
3221                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3222                            HSW_FREQUENCY(12));
3223         } else {
3224                 I915_WRITE(GEN6_RPNSWREQ,
3225                            GEN6_FREQUENCY(10) |
3226                            GEN6_OFFSET(0) |
3227                            GEN6_AGGRESSIVE_TURBO);
3228                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3229                            GEN6_FREQUENCY(12));
3230         }
3231
3232         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3233         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3234                    dev_priv->rps.max_delay << 24 |
3235                    dev_priv->rps.min_delay << 16);
3236
3237         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3238         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3239         I915_WRITE(GEN6_RP_UP_EI, 66000);
3240         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3241
3242         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3243         I915_WRITE(GEN6_RP_CONTROL,
3244                    GEN6_RP_MEDIA_TURBO |
3245                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3246                    GEN6_RP_MEDIA_IS_GFX |
3247                    GEN6_RP_ENABLE |
3248                    GEN6_RP_UP_BUSY_AVG |
3249                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
3250
3251         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3252         if (!ret) {
3253                 pcu_mbox = 0;
3254                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3255                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3256                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3257                                          (dev_priv->rps.max_delay & 0xff) * 50,
3258                                          (pcu_mbox & 0xff) * 50);
3259                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3260                 }
3261         } else {
3262                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3263         }
3264
3265         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
3266
3267         /* requires MSI enabled */
3268         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3269         spin_lock_irq(&dev_priv->rps.lock);
3270         WARN_ON(dev_priv->rps.pm_iir != 0);
3271         I915_WRITE(GEN6_PMIMR, 0);
3272         spin_unlock_irq(&dev_priv->rps.lock);
3273         /* enable all PM interrupts */
3274         I915_WRITE(GEN6_PMINTRMSK, 0);
3275
3276         rc6vids = 0;
3277         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3278         if (IS_GEN6(dev) && ret) {
3279                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3280         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3281                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3282                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3283                 rc6vids &= 0xffff00;
3284                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3285                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3286                 if (ret)
3287                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3288         }
3289
3290         gen6_gt_force_wake_put(dev_priv);
3291 }
3292
3293 static void gen6_update_ring_freq(struct drm_device *dev)
3294 {
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296         int min_freq = 15;
3297         unsigned int gpu_freq;
3298         unsigned int max_ia_freq, min_ring_freq;
3299         int scaling_factor = 180;
3300
3301         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3302
3303         max_ia_freq = cpufreq_quick_get_max(0);
3304         /*
3305          * Default to measured freq if none found, PCU will ensure we don't go
3306          * over
3307          */
3308         if (!max_ia_freq)
3309                 max_ia_freq = tsc_khz;
3310
3311         /* Convert from kHz to MHz */
3312         max_ia_freq /= 1000;
3313
3314         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3315         /* convert DDR frequency from units of 133.3MHz to bandwidth */
3316         min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3317
3318         /*
3319          * For each potential GPU frequency, load a ring frequency we'd like
3320          * to use for memory access.  We do this by specifying the IA frequency
3321          * the PCU should use as a reference to determine the ring frequency.
3322          */
3323         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3324              gpu_freq--) {
3325                 int diff = dev_priv->rps.max_delay - gpu_freq;
3326                 unsigned int ia_freq = 0, ring_freq = 0;
3327
3328                 if (IS_HASWELL(dev)) {
3329                         ring_freq = (gpu_freq * 5 + 3) / 4;
3330                         ring_freq = max(min_ring_freq, ring_freq);
3331                         /* leave ia_freq as the default, chosen by cpufreq */
3332                 } else {
3333                         /* On older processors, there is no separate ring
3334                          * clock domain, so in order to boost the bandwidth
3335                          * of the ring, we need to upclock the CPU (ia_freq).
3336                          *
3337                          * For GPU frequencies less than 750MHz,
3338                          * just use the lowest ring freq.
3339                          */
3340                         if (gpu_freq < min_freq)
3341                                 ia_freq = 800;
3342                         else
3343                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3344                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3345                 }
3346
3347                 sandybridge_pcode_write(dev_priv,
3348                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3349                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3350                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3351                                         gpu_freq);
3352         }
3353 }
3354
3355 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3356 {
3357         u32 val, rp0;
3358
3359         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3360
3361         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3362         /* Clamp to max */
3363         rp0 = min_t(u32, rp0, 0xea);
3364
3365         return rp0;
3366 }
3367
3368 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3369 {
3370         u32 val, rpe;
3371
3372         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3373         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3374         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3375         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3376
3377         return rpe;
3378 }
3379
3380 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3381 {
3382         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3383 }
3384
3385 static void vlv_rps_timer_work(struct work_struct *work)
3386 {
3387         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3388                                                     rps.vlv_work.work);
3389
3390         /*
3391          * Timer fired, we must be idle.  Drop to min voltage state.
3392          * Note: we use RPe here since it should match the
3393          * Vmin we were shooting for.  That should give us better
3394          * perf when we come back out of RC6 than if we used the
3395          * min freq available.
3396          */
3397         mutex_lock(&dev_priv->rps.hw_lock);
3398         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3399         mutex_unlock(&dev_priv->rps.hw_lock);
3400 }
3401
3402 static void valleyview_setup_pctx(struct drm_device *dev)
3403 {
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         struct drm_i915_gem_object *pctx;
3406         unsigned long pctx_paddr;
3407         u32 pcbr;
3408         int pctx_size = 24*1024;
3409
3410         pcbr = I915_READ(VLV_PCBR);
3411         if (pcbr) {
3412                 /* BIOS set it up already, grab the pre-alloc'd space */
3413                 int pcbr_offset;
3414
3415                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3416                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3417                                                                       pcbr_offset,
3418                                                                       -1,
3419                                                                       pctx_size);
3420                 goto out;
3421         }
3422
3423         /*
3424          * From the Gunit register HAS:
3425          * The Gfx driver is expected to program this register and ensure
3426          * proper allocation within Gfx stolen memory.  For example, this
3427          * register should be programmed such than the PCBR range does not
3428          * overlap with other ranges, such as the frame buffer, protected
3429          * memory, or any other relevant ranges.
3430          */
3431         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3432         if (!pctx) {
3433                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3434                 return;
3435         }
3436
3437         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3438         I915_WRITE(VLV_PCBR, pctx_paddr);
3439
3440 out:
3441         dev_priv->vlv_pctx = pctx;
3442 }
3443
3444 static void valleyview_enable_rps(struct drm_device *dev)
3445 {
3446         struct drm_i915_private *dev_priv = dev->dev_private;
3447         struct intel_ring_buffer *ring;
3448         u32 gtfifodbg, val, rpe;
3449         int i;
3450
3451         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3452
3453         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3454                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3455                 I915_WRITE(GTFIFODBG, gtfifodbg);
3456         }
3457
3458         valleyview_setup_pctx(dev);
3459
3460         gen6_gt_force_wake_get(dev_priv);
3461
3462         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3463         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3464         I915_WRITE(GEN6_RP_UP_EI, 66000);
3465         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3466
3467         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3468
3469         I915_WRITE(GEN6_RP_CONTROL,
3470                    GEN6_RP_MEDIA_TURBO |
3471                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3472                    GEN6_RP_MEDIA_IS_GFX |
3473                    GEN6_RP_ENABLE |
3474                    GEN6_RP_UP_BUSY_AVG |
3475                    GEN6_RP_DOWN_IDLE_CONT);
3476
3477         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3478         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3479         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3480
3481         for_each_ring(ring, dev_priv, i)
3482                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3483
3484         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3485
3486         /* allows RC6 residency counter to work */
3487         I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3488         I915_WRITE(GEN6_RC_CONTROL,
3489                    GEN7_RC_CTL_TO_MODE);
3490
3491         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3492         switch ((val >> 6) & 3) {
3493         case 0:
3494         case 1:
3495                 dev_priv->mem_freq = 800;
3496                 break;
3497         case 2:
3498                 dev_priv->mem_freq = 1066;
3499                 break;
3500         case 3:
3501                 dev_priv->mem_freq = 1333;
3502                 break;
3503         }
3504         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3505
3506         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3507         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3508
3509         DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3510                          vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3511         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3512
3513         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3514         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3515         DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3516                                                      dev_priv->rps.max_delay));
3517
3518         rpe = valleyview_rps_rpe_freq(dev_priv);
3519         DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3520                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
3521         dev_priv->rps.rpe_delay = rpe;
3522
3523         val = valleyview_rps_min_freq(dev_priv);
3524         DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3525                                                             val));
3526         dev_priv->rps.min_delay = val;
3527
3528         DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3529                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
3530
3531         INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3532
3533         valleyview_set_rps(dev_priv->dev, rpe);
3534
3535         /* requires MSI enabled */
3536         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3537         spin_lock_irq(&dev_priv->rps.lock);
3538         WARN_ON(dev_priv->rps.pm_iir != 0);
3539         I915_WRITE(GEN6_PMIMR, 0);
3540         spin_unlock_irq(&dev_priv->rps.lock);
3541         /* enable all PM interrupts */
3542         I915_WRITE(GEN6_PMINTRMSK, 0);
3543
3544         gen6_gt_force_wake_put(dev_priv);
3545 }
3546
3547 void ironlake_teardown_rc6(struct drm_device *dev)
3548 {
3549         struct drm_i915_private *dev_priv = dev->dev_private;
3550
3551         if (dev_priv->ips.renderctx) {
3552                 i915_gem_object_unpin(dev_priv->ips.renderctx);
3553                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3554                 dev_priv->ips.renderctx = NULL;
3555         }
3556
3557         if (dev_priv->ips.pwrctx) {
3558                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3559                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3560                 dev_priv->ips.pwrctx = NULL;
3561         }
3562 }
3563
3564 static void ironlake_disable_rc6(struct drm_device *dev)
3565 {
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567
3568         if (I915_READ(PWRCTXA)) {
3569                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3570                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3571                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3572                          50);
3573
3574                 I915_WRITE(PWRCTXA, 0);
3575                 POSTING_READ(PWRCTXA);
3576
3577                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3578                 POSTING_READ(RSTDBYCTL);
3579         }
3580 }
3581
3582 static int ironlake_setup_rc6(struct drm_device *dev)
3583 {
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585
3586         if (dev_priv->ips.renderctx == NULL)
3587                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3588         if (!dev_priv->ips.renderctx)
3589                 return -ENOMEM;
3590
3591         if (dev_priv->ips.pwrctx == NULL)
3592                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3593         if (!dev_priv->ips.pwrctx) {
3594                 ironlake_teardown_rc6(dev);
3595                 return -ENOMEM;
3596         }
3597
3598         return 0;
3599 }
3600
3601 static void ironlake_enable_rc6(struct drm_device *dev)
3602 {
3603         struct drm_i915_private *dev_priv = dev->dev_private;
3604         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3605         bool was_interruptible;
3606         int ret;
3607
3608         /* rc6 disabled by default due to repeated reports of hanging during
3609          * boot and resume.
3610          */
3611         if (!intel_enable_rc6(dev))
3612                 return;
3613
3614         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3615
3616         ret = ironlake_setup_rc6(dev);
3617         if (ret)
3618                 return;
3619
3620         was_interruptible = dev_priv->mm.interruptible;
3621         dev_priv->mm.interruptible = false;
3622
3623         /*
3624          * GPU can automatically power down the render unit if given a page
3625          * to save state.
3626          */
3627         ret = intel_ring_begin(ring, 6);
3628         if (ret) {
3629                 ironlake_teardown_rc6(dev);
3630                 dev_priv->mm.interruptible = was_interruptible;
3631                 return;
3632         }
3633
3634         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3635         intel_ring_emit(ring, MI_SET_CONTEXT);
3636         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3637                         MI_MM_SPACE_GTT |
3638                         MI_SAVE_EXT_STATE_EN |
3639                         MI_RESTORE_EXT_STATE_EN |
3640                         MI_RESTORE_INHIBIT);
3641         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3642         intel_ring_emit(ring, MI_NOOP);
3643         intel_ring_emit(ring, MI_FLUSH);
3644         intel_ring_advance(ring);
3645
3646         /*
3647          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3648          * does an implicit flush, combined with MI_FLUSH above, it should be
3649          * safe to assume that renderctx is valid
3650          */
3651         ret = intel_ring_idle(ring);
3652         dev_priv->mm.interruptible = was_interruptible;
3653         if (ret) {
3654                 DRM_ERROR("failed to enable ironlake power savings\n");
3655                 ironlake_teardown_rc6(dev);
3656                 return;
3657         }
3658
3659         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3660         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3661 }
3662
3663 static unsigned long intel_pxfreq(u32 vidfreq)
3664 {
3665         unsigned long freq;
3666         int div = (vidfreq & 0x3f0000) >> 16;
3667         int post = (vidfreq & 0x3000) >> 12;
3668         int pre = (vidfreq & 0x7);
3669
3670         if (!pre)
3671                 return 0;
3672
3673         freq = ((div * 133333) / ((1<<post) * pre));
3674
3675         return freq;
3676 }
3677
3678 static const struct cparams {
3679         u16 i;
3680         u16 t;
3681         u16 m;
3682         u16 c;
3683 } cparams[] = {
3684         { 1, 1333, 301, 28664 },
3685         { 1, 1066, 294, 24460 },
3686         { 1, 800, 294, 25192 },
3687         { 0, 1333, 276, 27605 },
3688         { 0, 1066, 276, 27605 },
3689         { 0, 800, 231, 23784 },
3690 };
3691
3692 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3693 {
3694         u64 total_count, diff, ret;
3695         u32 count1, count2, count3, m = 0, c = 0;
3696         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3697         int i;
3698
3699         assert_spin_locked(&mchdev_lock);
3700
3701         diff1 = now - dev_priv->ips.last_time1;
3702
3703         /* Prevent division-by-zero if we are asking too fast.
3704          * Also, we don't get interesting results if we are polling
3705          * faster than once in 10ms, so just return the saved value
3706          * in such cases.
3707          */
3708         if (diff1 <= 10)
3709                 return dev_priv->ips.chipset_power;
3710
3711         count1 = I915_READ(DMIEC);
3712         count2 = I915_READ(DDREC);
3713         count3 = I915_READ(CSIEC);
3714
3715         total_count = count1 + count2 + count3;
3716
3717         /* FIXME: handle per-counter overflow */
3718         if (total_count < dev_priv->ips.last_count1) {
3719                 diff = ~0UL - dev_priv->ips.last_count1;
3720                 diff += total_count;
3721         } else {
3722                 diff = total_count - dev_priv->ips.last_count1;
3723         }
3724
3725         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3726                 if (cparams[i].i == dev_priv->ips.c_m &&
3727                     cparams[i].t == dev_priv->ips.r_t) {
3728                         m = cparams[i].m;
3729                         c = cparams[i].c;
3730                         break;
3731                 }
3732         }
3733
3734         diff = div_u64(diff, diff1);
3735         ret = ((m * diff) + c);
3736         ret = div_u64(ret, 10);
3737
3738         dev_priv->ips.last_count1 = total_count;
3739         dev_priv->ips.last_time1 = now;
3740
3741         dev_priv->ips.chipset_power = ret;
3742
3743         return ret;
3744 }
3745
3746 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3747 {
3748         unsigned long val;
3749
3750         if (dev_priv->info->gen != 5)
3751                 return 0;
3752
3753         spin_lock_irq(&mchdev_lock);
3754
3755         val = __i915_chipset_val(dev_priv);
3756
3757         spin_unlock_irq(&mchdev_lock);
3758
3759         return val;
3760 }
3761
3762 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3763 {
3764         unsigned long m, x, b;
3765         u32 tsfs;
3766
3767         tsfs = I915_READ(TSFS);
3768
3769         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3770         x = I915_READ8(TR1);
3771
3772         b = tsfs & TSFS_INTR_MASK;
3773
3774         return ((m * x) / 127) - b;
3775 }
3776
3777 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3778 {
3779         static const struct v_table {
3780                 u16 vd; /* in .1 mil */
3781                 u16 vm; /* in .1 mil */
3782         } v_table[] = {
3783                 { 0, 0, },
3784                 { 375, 0, },
3785                 { 500, 0, },
3786                 { 625, 0, },
3787                 { 750, 0, },
3788                 { 875, 0, },
3789                 { 1000, 0, },
3790                 { 1125, 0, },
3791                 { 4125, 3000, },
3792                 { 4125, 3000, },
3793                 { 4125, 3000, },
3794                 { 4125, 3000, },
3795                 { 4125, 3000, },
3796                 { 4125, 3000, },
3797                 { 4125, 3000, },
3798                 { 4125, 3000, },
3799                 { 4125, 3000, },
3800                 { 4125, 3000, },
3801                 { 4125, 3000, },
3802                 { 4125, 3000, },
3803                 { 4125, 3000, },
3804                 { 4125, 3000, },
3805                 { 4125, 3000, },
3806                 { 4125, 3000, },
3807                 { 4125, 3000, },
3808                 { 4125, 3000, },
3809                 { 4125, 3000, },
3810                 { 4125, 3000, },
3811                 { 4125, 3000, },
3812                 { 4125, 3000, },
3813                 { 4125, 3000, },
3814                 { 4125, 3000, },
3815                 { 4250, 3125, },
3816                 { 4375, 3250, },
3817                 { 4500, 3375, },
3818                 { 4625, 3500, },
3819                 { 4750, 3625, },
3820                 { 4875, 3750, },
3821                 { 5000, 3875, },
3822                 { 5125, 4000, },
3823                 { 5250, 4125, },
3824                 { 5375, 4250, },
3825                 { 5500, 4375, },
3826                 { 5625, 4500, },
3827                 { 5750, 4625, },
3828                 { 5875, 4750, },
3829                 { 6000, 4875, },
3830                 { 6125, 5000, },
3831                 { 6250, 5125, },
3832                 { 6375, 5250, },
3833                 { 6500, 5375, },
3834                 { 6625, 5500, },
3835                 { 6750, 5625, },
3836                 { 6875, 5750, },
3837                 { 7000, 5875, },
3838                 { 7125, 6000, },
3839                 { 7250, 6125, },
3840                 { 7375, 6250, },
3841                 { 7500, 6375, },
3842                 { 7625, 6500, },
3843                 { 7750, 6625, },
3844                 { 7875, 6750, },
3845                 { 8000, 6875, },
3846                 { 8125, 7000, },
3847                 { 8250, 7125, },
3848                 { 8375, 7250, },
3849                 { 8500, 7375, },
3850                 { 8625, 7500, },
3851                 { 8750, 7625, },
3852                 { 8875, 7750, },
3853                 { 9000, 7875, },
3854                 { 9125, 8000, },
3855                 { 9250, 8125, },
3856                 { 9375, 8250, },
3857                 { 9500, 8375, },
3858                 { 9625, 8500, },
3859                 { 9750, 8625, },
3860                 { 9875, 8750, },
3861                 { 10000, 8875, },
3862                 { 10125, 9000, },
3863                 { 10250, 9125, },
3864                 { 10375, 9250, },
3865                 { 10500, 9375, },
3866                 { 10625, 9500, },
3867                 { 10750, 9625, },
3868                 { 10875, 9750, },
3869                 { 11000, 9875, },
3870                 { 11125, 10000, },
3871                 { 11250, 10125, },
3872                 { 11375, 10250, },
3873                 { 11500, 10375, },
3874                 { 11625, 10500, },
3875                 { 11750, 10625, },
3876                 { 11875, 10750, },
3877                 { 12000, 10875, },
3878                 { 12125, 11000, },
3879                 { 12250, 11125, },
3880                 { 12375, 11250, },
3881                 { 12500, 11375, },
3882                 { 12625, 11500, },
3883                 { 12750, 11625, },
3884                 { 12875, 11750, },
3885                 { 13000, 11875, },
3886                 { 13125, 12000, },
3887                 { 13250, 12125, },
3888                 { 13375, 12250, },
3889                 { 13500, 12375, },
3890                 { 13625, 12500, },
3891                 { 13750, 12625, },
3892                 { 13875, 12750, },
3893                 { 14000, 12875, },
3894                 { 14125, 13000, },
3895                 { 14250, 13125, },
3896                 { 14375, 13250, },
3897                 { 14500, 13375, },
3898                 { 14625, 13500, },
3899                 { 14750, 13625, },
3900                 { 14875, 13750, },
3901                 { 15000, 13875, },
3902                 { 15125, 14000, },
3903                 { 15250, 14125, },
3904                 { 15375, 14250, },
3905                 { 15500, 14375, },
3906                 { 15625, 14500, },
3907                 { 15750, 14625, },
3908                 { 15875, 14750, },
3909                 { 16000, 14875, },
3910                 { 16125, 15000, },
3911         };
3912         if (dev_priv->info->is_mobile)
3913                 return v_table[pxvid].vm;
3914         else
3915                 return v_table[pxvid].vd;
3916 }
3917
3918 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3919 {
3920         struct timespec now, diff1;
3921         u64 diff;
3922         unsigned long diffms;
3923         u32 count;
3924
3925         assert_spin_locked(&mchdev_lock);
3926
3927         getrawmonotonic(&now);
3928         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3929
3930         /* Don't divide by 0 */
3931         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3932         if (!diffms)
3933                 return;
3934
3935         count = I915_READ(GFXEC);
3936
3937         if (count < dev_priv->ips.last_count2) {
3938                 diff = ~0UL - dev_priv->ips.last_count2;
3939                 diff += count;
3940         } else {
3941                 diff = count - dev_priv->ips.last_count2;
3942         }
3943
3944         dev_priv->ips.last_count2 = count;
3945         dev_priv->ips.last_time2 = now;
3946
3947         /* More magic constants... */
3948         diff = diff * 1181;
3949         diff = div_u64(diff, diffms * 10);
3950         dev_priv->ips.gfx_power = diff;
3951 }
3952
3953 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3954 {
3955         if (dev_priv->info->gen != 5)
3956                 return;
3957
3958         spin_lock_irq(&mchdev_lock);
3959
3960         __i915_update_gfx_val(dev_priv);
3961
3962         spin_unlock_irq(&mchdev_lock);
3963 }
3964
3965 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3966 {
3967         unsigned long t, corr, state1, corr2, state2;
3968         u32 pxvid, ext_v;
3969
3970         assert_spin_locked(&mchdev_lock);
3971
3972         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3973         pxvid = (pxvid >> 24) & 0x7f;
3974         ext_v = pvid_to_extvid(dev_priv, pxvid);
3975
3976         state1 = ext_v;
3977
3978         t = i915_mch_val(dev_priv);
3979
3980         /* Revel in the empirically derived constants */
3981
3982         /* Correction factor in 1/100000 units */
3983         if (t > 80)
3984                 corr = ((t * 2349) + 135940);
3985         else if (t >= 50)
3986                 corr = ((t * 964) + 29317);
3987         else /* < 50 */
3988                 corr = ((t * 301) + 1004);
3989
3990         corr = corr * ((150142 * state1) / 10000 - 78642);
3991         corr /= 100000;
3992         corr2 = (corr * dev_priv->ips.corr);
3993
3994         state2 = (corr2 * state1) / 10000;
3995         state2 /= 100; /* convert to mW */
3996
3997         __i915_update_gfx_val(dev_priv);
3998
3999         return dev_priv->ips.gfx_power + state2;
4000 }
4001
4002 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4003 {
4004         unsigned long val;
4005
4006         if (dev_priv->info->gen != 5)
4007                 return 0;
4008
4009         spin_lock_irq(&mchdev_lock);
4010
4011         val = __i915_gfx_val(dev_priv);
4012
4013         spin_unlock_irq(&mchdev_lock);
4014
4015         return val;
4016 }
4017
4018 /**
4019  * i915_read_mch_val - return value for IPS use
4020  *
4021  * Calculate and return a value for the IPS driver to use when deciding whether
4022  * we have thermal and power headroom to increase CPU or GPU power budget.
4023  */
4024 unsigned long i915_read_mch_val(void)
4025 {
4026         struct drm_i915_private *dev_priv;
4027         unsigned long chipset_val, graphics_val, ret = 0;
4028
4029         spin_lock_irq(&mchdev_lock);
4030         if (!i915_mch_dev)
4031                 goto out_unlock;
4032         dev_priv = i915_mch_dev;
4033
4034         chipset_val = __i915_chipset_val(dev_priv);
4035         graphics_val = __i915_gfx_val(dev_priv);
4036
4037         ret = chipset_val + graphics_val;
4038
4039 out_unlock:
4040         spin_unlock_irq(&mchdev_lock);
4041
4042         return ret;
4043 }
4044 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4045
4046 /**
4047  * i915_gpu_raise - raise GPU frequency limit
4048  *
4049  * Raise the limit; IPS indicates we have thermal headroom.
4050  */
4051 bool i915_gpu_raise(void)
4052 {
4053         struct drm_i915_private *dev_priv;
4054         bool ret = true;
4055
4056         spin_lock_irq(&mchdev_lock);
4057         if (!i915_mch_dev) {
4058                 ret = false;
4059                 goto out_unlock;
4060         }
4061         dev_priv = i915_mch_dev;
4062
4063         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4064                 dev_priv->ips.max_delay--;
4065
4066 out_unlock:
4067         spin_unlock_irq(&mchdev_lock);
4068
4069         return ret;
4070 }
4071 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4072
4073 /**
4074  * i915_gpu_lower - lower GPU frequency limit
4075  *
4076  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4077  * frequency maximum.
4078  */
4079 bool i915_gpu_lower(void)
4080 {
4081         struct drm_i915_private *dev_priv;
4082         bool ret = true;
4083
4084         spin_lock_irq(&mchdev_lock);
4085         if (!i915_mch_dev) {
4086                 ret = false;
4087                 goto out_unlock;
4088         }
4089         dev_priv = i915_mch_dev;
4090
4091         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4092                 dev_priv->ips.max_delay++;
4093
4094 out_unlock:
4095         spin_unlock_irq(&mchdev_lock);
4096
4097         return ret;
4098 }
4099 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4100
4101 /**
4102  * i915_gpu_busy - indicate GPU business to IPS
4103  *
4104  * Tell the IPS driver whether or not the GPU is busy.
4105  */
4106 bool i915_gpu_busy(void)
4107 {
4108         struct drm_i915_private *dev_priv;
4109         struct intel_ring_buffer *ring;
4110         bool ret = false;
4111         int i;
4112
4113         spin_lock_irq(&mchdev_lock);
4114         if (!i915_mch_dev)
4115                 goto out_unlock;
4116         dev_priv = i915_mch_dev;
4117
4118         for_each_ring(ring, dev_priv, i)
4119                 ret |= !list_empty(&ring->request_list);
4120
4121 out_unlock:
4122         spin_unlock_irq(&mchdev_lock);
4123
4124         return ret;
4125 }
4126 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4127
4128 /**
4129  * i915_gpu_turbo_disable - disable graphics turbo
4130  *
4131  * Disable graphics turbo by resetting the max frequency and setting the
4132  * current frequency to the default.
4133  */
4134 bool i915_gpu_turbo_disable(void)
4135 {
4136         struct drm_i915_private *dev_priv;
4137         bool ret = true;
4138
4139         spin_lock_irq(&mchdev_lock);
4140         if (!i915_mch_dev) {
4141                 ret = false;
4142                 goto out_unlock;
4143         }
4144         dev_priv = i915_mch_dev;
4145
4146         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4147
4148         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4149                 ret = false;
4150
4151 out_unlock:
4152         spin_unlock_irq(&mchdev_lock);
4153
4154         return ret;
4155 }
4156 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4157
4158 /**
4159  * Tells the intel_ips driver that the i915 driver is now loaded, if
4160  * IPS got loaded first.
4161  *
4162  * This awkward dance is so that neither module has to depend on the
4163  * other in order for IPS to do the appropriate communication of
4164  * GPU turbo limits to i915.
4165  */
4166 static void
4167 ips_ping_for_i915_load(void)
4168 {
4169         void (*link)(void);
4170
4171         link = symbol_get(ips_link_to_i915_driver);
4172         if (link) {
4173                 link();
4174                 symbol_put(ips_link_to_i915_driver);
4175         }
4176 }
4177
4178 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4179 {
4180         /* We only register the i915 ips part with intel-ips once everything is
4181          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4182         spin_lock_irq(&mchdev_lock);
4183         i915_mch_dev = dev_priv;
4184         spin_unlock_irq(&mchdev_lock);
4185
4186         ips_ping_for_i915_load();
4187 }
4188
4189 void intel_gpu_ips_teardown(void)
4190 {
4191         spin_lock_irq(&mchdev_lock);
4192         i915_mch_dev = NULL;
4193         spin_unlock_irq(&mchdev_lock);
4194 }
4195 static void intel_init_emon(struct drm_device *dev)
4196 {
4197         struct drm_i915_private *dev_priv = dev->dev_private;
4198         u32 lcfuse;
4199         u8 pxw[16];
4200         int i;
4201
4202         /* Disable to program */
4203         I915_WRITE(ECR, 0);
4204         POSTING_READ(ECR);
4205
4206         /* Program energy weights for various events */
4207         I915_WRITE(SDEW, 0x15040d00);
4208         I915_WRITE(CSIEW0, 0x007f0000);
4209         I915_WRITE(CSIEW1, 0x1e220004);
4210         I915_WRITE(CSIEW2, 0x04000004);
4211
4212         for (i = 0; i < 5; i++)
4213                 I915_WRITE(PEW + (i * 4), 0);
4214         for (i = 0; i < 3; i++)
4215                 I915_WRITE(DEW + (i * 4), 0);
4216
4217         /* Program P-state weights to account for frequency power adjustment */
4218         for (i = 0; i < 16; i++) {
4219                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4220                 unsigned long freq = intel_pxfreq(pxvidfreq);
4221                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4222                         PXVFREQ_PX_SHIFT;
4223                 unsigned long val;
4224
4225                 val = vid * vid;
4226                 val *= (freq / 1000);
4227                 val *= 255;
4228                 val /= (127*127*900);
4229                 if (val > 0xff)
4230                         DRM_ERROR("bad pxval: %ld\n", val);
4231                 pxw[i] = val;
4232         }
4233         /* Render standby states get 0 weight */
4234         pxw[14] = 0;
4235         pxw[15] = 0;
4236
4237         for (i = 0; i < 4; i++) {
4238                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4239                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4240                 I915_WRITE(PXW + (i * 4), val);
4241         }
4242
4243         /* Adjust magic regs to magic values (more experimental results) */
4244         I915_WRITE(OGW0, 0);
4245         I915_WRITE(OGW1, 0);
4246         I915_WRITE(EG0, 0x00007f00);
4247         I915_WRITE(EG1, 0x0000000e);
4248         I915_WRITE(EG2, 0x000e0000);
4249         I915_WRITE(EG3, 0x68000300);
4250         I915_WRITE(EG4, 0x42000000);
4251         I915_WRITE(EG5, 0x00140031);
4252         I915_WRITE(EG6, 0);
4253         I915_WRITE(EG7, 0);
4254
4255         for (i = 0; i < 8; i++)
4256                 I915_WRITE(PXWL + (i * 4), 0);
4257
4258         /* Enable PMON + select events */
4259         I915_WRITE(ECR, 0x80000019);
4260
4261         lcfuse = I915_READ(LCFUSE02);
4262
4263         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4264 }
4265
4266 void intel_disable_gt_powersave(struct drm_device *dev)
4267 {
4268         struct drm_i915_private *dev_priv = dev->dev_private;
4269
4270         /* Interrupts should be disabled already to avoid re-arming. */
4271         WARN_ON(dev->irq_enabled);
4272
4273         if (IS_IRONLAKE_M(dev)) {
4274                 ironlake_disable_drps(dev);
4275                 ironlake_disable_rc6(dev);
4276         } else if (INTEL_INFO(dev)->gen >= 6) {
4277                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4278                 cancel_work_sync(&dev_priv->rps.work);
4279                 if (IS_VALLEYVIEW(dev))
4280                         cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4281                 mutex_lock(&dev_priv->rps.hw_lock);
4282                 if (IS_VALLEYVIEW(dev))
4283                         valleyview_disable_rps(dev);
4284                 else
4285                         gen6_disable_rps(dev);
4286                 mutex_unlock(&dev_priv->rps.hw_lock);
4287         }
4288 }
4289
4290 static void intel_gen6_powersave_work(struct work_struct *work)
4291 {
4292         struct drm_i915_private *dev_priv =
4293                 container_of(work, struct drm_i915_private,
4294                              rps.delayed_resume_work.work);
4295         struct drm_device *dev = dev_priv->dev;
4296
4297         mutex_lock(&dev_priv->rps.hw_lock);
4298
4299         if (IS_VALLEYVIEW(dev)) {
4300                 valleyview_enable_rps(dev);
4301         } else {
4302                 gen6_enable_rps(dev);
4303                 gen6_update_ring_freq(dev);
4304         }
4305         mutex_unlock(&dev_priv->rps.hw_lock);
4306 }
4307
4308 void intel_enable_gt_powersave(struct drm_device *dev)
4309 {
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311
4312         if (IS_IRONLAKE_M(dev)) {
4313                 ironlake_enable_drps(dev);
4314                 ironlake_enable_rc6(dev);
4315                 intel_init_emon(dev);
4316         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4317                 /*
4318                  * PCU communication is slow and this doesn't need to be
4319                  * done at any specific time, so do this out of our fast path
4320                  * to make resume and init faster.
4321                  */
4322                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4323                                       round_jiffies_up_relative(HZ));
4324         }
4325 }
4326
4327 static void ibx_init_clock_gating(struct drm_device *dev)
4328 {
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330
4331         /*
4332          * On Ibex Peak and Cougar Point, we need to disable clock
4333          * gating for the panel power sequencer or it will fail to
4334          * start up when no ports are active.
4335          */
4336         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4337 }
4338
4339 static void ironlake_init_clock_gating(struct drm_device *dev)
4340 {
4341         struct drm_i915_private *dev_priv = dev->dev_private;
4342         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4343
4344         /* Required for FBC */
4345         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4346                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4347                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4348
4349         I915_WRITE(PCH_3DCGDIS0,
4350                    MARIUNIT_CLOCK_GATE_DISABLE |
4351                    SVSMUNIT_CLOCK_GATE_DISABLE);
4352         I915_WRITE(PCH_3DCGDIS1,
4353                    VFMUNIT_CLOCK_GATE_DISABLE);
4354
4355         /*
4356          * According to the spec the following bits should be set in
4357          * order to enable memory self-refresh
4358          * The bit 22/21 of 0x42004
4359          * The bit 5 of 0x42020
4360          * The bit 15 of 0x45000
4361          */
4362         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4363                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4364                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4365         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4366         I915_WRITE(DISP_ARB_CTL,
4367                    (I915_READ(DISP_ARB_CTL) |
4368                     DISP_FBC_WM_DIS));
4369         I915_WRITE(WM3_LP_ILK, 0);
4370         I915_WRITE(WM2_LP_ILK, 0);
4371         I915_WRITE(WM1_LP_ILK, 0);
4372
4373         /*
4374          * Based on the document from hardware guys the following bits
4375          * should be set unconditionally in order to enable FBC.
4376          * The bit 22 of 0x42000
4377          * The bit 22 of 0x42004
4378          * The bit 7,8,9 of 0x42020.
4379          */
4380         if (IS_IRONLAKE_M(dev)) {
4381                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4382                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4383                            ILK_FBCQ_DIS);
4384                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4385                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4386                            ILK_DPARB_GATE);
4387         }
4388
4389         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4390
4391         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4392                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4393                    ILK_ELPIN_409_SELECT);
4394         I915_WRITE(_3D_CHICKEN2,
4395                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4396                    _3D_CHICKEN2_WM_READ_PIPELINED);
4397
4398         /* WaDisableRenderCachePipelinedFlush:ilk */
4399         I915_WRITE(CACHE_MODE_0,
4400                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4401
4402         ibx_init_clock_gating(dev);
4403 }
4404
4405 static void cpt_init_clock_gating(struct drm_device *dev)
4406 {
4407         struct drm_i915_private *dev_priv = dev->dev_private;
4408         int pipe;
4409         uint32_t val;
4410
4411         /*
4412          * On Ibex Peak and Cougar Point, we need to disable clock
4413          * gating for the panel power sequencer or it will fail to
4414          * start up when no ports are active.
4415          */
4416         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4417         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4418                    DPLS_EDP_PPS_FIX_DIS);
4419         /* The below fixes the weird display corruption, a few pixels shifted
4420          * downward, on (only) LVDS of some HP laptops with IVY.
4421          */
4422         for_each_pipe(pipe) {
4423                 val = I915_READ(TRANS_CHICKEN2(pipe));
4424                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4425                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4426                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4427                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4428                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4429                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4430                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4431                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4432         }
4433         /* WADP0ClockGatingDisable */
4434         for_each_pipe(pipe) {
4435                 I915_WRITE(TRANS_CHICKEN1(pipe),
4436                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4437         }
4438 }
4439
4440 static void gen6_check_mch_setup(struct drm_device *dev)
4441 {
4442         struct drm_i915_private *dev_priv = dev->dev_private;
4443         uint32_t tmp;
4444
4445         tmp = I915_READ(MCH_SSKPD);
4446         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4447                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4448                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4449                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4450         }
4451 }
4452
4453 static void gen6_init_clock_gating(struct drm_device *dev)
4454 {
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456         int pipe;
4457         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4458
4459         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4460
4461         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4462                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4463                    ILK_ELPIN_409_SELECT);
4464
4465         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4466         I915_WRITE(_3D_CHICKEN,
4467                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4468
4469         /* WaSetupGtModeTdRowDispatch:snb */
4470         if (IS_SNB_GT1(dev))
4471                 I915_WRITE(GEN6_GT_MODE,
4472                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4473
4474         I915_WRITE(WM3_LP_ILK, 0);
4475         I915_WRITE(WM2_LP_ILK, 0);
4476         I915_WRITE(WM1_LP_ILK, 0);
4477
4478         I915_WRITE(CACHE_MODE_0,
4479                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4480
4481         I915_WRITE(GEN6_UCGCTL1,
4482                    I915_READ(GEN6_UCGCTL1) |
4483                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4484                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4485
4486         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4487          * gating disable must be set.  Failure to set it results in
4488          * flickering pixels due to Z write ordering failures after
4489          * some amount of runtime in the Mesa "fire" demo, and Unigine
4490          * Sanctuary and Tropics, and apparently anything else with
4491          * alpha test or pixel discard.
4492          *
4493          * According to the spec, bit 11 (RCCUNIT) must also be set,
4494          * but we didn't debug actual testcases to find it out.
4495          *
4496          * Also apply WaDisableVDSUnitClockGating:snb and
4497          * WaDisableRCPBUnitClockGating:snb.
4498          */
4499         I915_WRITE(GEN6_UCGCTL2,
4500                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4501                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4502                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4503
4504         /* Bspec says we need to always set all mask bits. */
4505         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4506                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4507
4508         /*
4509          * According to the spec the following bits should be
4510          * set in order to enable memory self-refresh and fbc:
4511          * The bit21 and bit22 of 0x42000
4512          * The bit21 and bit22 of 0x42004
4513          * The bit5 and bit7 of 0x42020
4514          * The bit14 of 0x70180
4515          * The bit14 of 0x71180
4516          */
4517         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4518                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4519                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4520         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4521                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4522                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4523         I915_WRITE(ILK_DSPCLK_GATE_D,
4524                    I915_READ(ILK_DSPCLK_GATE_D) |
4525                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4526                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4527
4528         /* WaMbcDriverBootEnable:snb */
4529         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4530                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4531
4532         for_each_pipe(pipe) {
4533                 I915_WRITE(DSPCNTR(pipe),
4534                            I915_READ(DSPCNTR(pipe)) |
4535                            DISPPLANE_TRICKLE_FEED_DISABLE);
4536                 intel_flush_display_plane(dev_priv, pipe);
4537         }
4538
4539         /* The default value should be 0x200 according to docs, but the two
4540          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4541         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4542         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4543
4544         cpt_init_clock_gating(dev);
4545
4546         gen6_check_mch_setup(dev);
4547 }
4548
4549 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4550 {
4551         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4552
4553         reg &= ~GEN7_FF_SCHED_MASK;
4554         reg |= GEN7_FF_TS_SCHED_HW;
4555         reg |= GEN7_FF_VS_SCHED_HW;
4556         reg |= GEN7_FF_DS_SCHED_HW;
4557
4558         if (IS_HASWELL(dev_priv->dev))
4559                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4560
4561         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4562 }
4563
4564 static void lpt_init_clock_gating(struct drm_device *dev)
4565 {
4566         struct drm_i915_private *dev_priv = dev->dev_private;
4567
4568         /*
4569          * TODO: this bit should only be enabled when really needed, then
4570          * disabled when not needed anymore in order to save power.
4571          */
4572         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4573                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4574                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4575                            PCH_LP_PARTITION_LEVEL_DISABLE);
4576
4577         /* WADPOClockGatingDisable:hsw */
4578         I915_WRITE(_TRANSA_CHICKEN1,
4579                    I915_READ(_TRANSA_CHICKEN1) |
4580                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4581 }
4582
4583 static void lpt_suspend_hw(struct drm_device *dev)
4584 {
4585         struct drm_i915_private *dev_priv = dev->dev_private;
4586
4587         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4588                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4589
4590                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4591                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4592         }
4593 }
4594
4595 static void haswell_init_clock_gating(struct drm_device *dev)
4596 {
4597         struct drm_i915_private *dev_priv = dev->dev_private;
4598         int pipe;
4599
4600         I915_WRITE(WM3_LP_ILK, 0);
4601         I915_WRITE(WM2_LP_ILK, 0);
4602         I915_WRITE(WM1_LP_ILK, 0);
4603
4604         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4605          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4606          */
4607         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4608
4609         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4610         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4611                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4612
4613         /* WaApplyL3ControlAndL3ChickenMode:hsw */
4614         I915_WRITE(GEN7_L3CNTLREG1,
4615                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4616         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4617                         GEN7_WA_L3_CHICKEN_MODE);
4618
4619         /* This is required by WaCatErrorRejectionIssue:hsw */
4620         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4621                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4622                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4623
4624         for_each_pipe(pipe) {
4625                 I915_WRITE(DSPCNTR(pipe),
4626                            I915_READ(DSPCNTR(pipe)) |
4627                            DISPPLANE_TRICKLE_FEED_DISABLE);
4628                 intel_flush_display_plane(dev_priv, pipe);
4629         }
4630
4631         /* WaVSRefCountFullforceMissDisable:hsw */
4632         gen7_setup_fixed_func_scheduler(dev_priv);
4633
4634         /* WaDisable4x2SubspanOptimization:hsw */
4635         I915_WRITE(CACHE_MODE_1,
4636                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4637
4638         /* WaMbcDriverBootEnable:hsw */
4639         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4640                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4641
4642         /* WaSwitchSolVfFArbitrationPriority:hsw */
4643         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4644
4645         /* WaRsPkgCStateDisplayPMReq:hsw */
4646         I915_WRITE(CHICKEN_PAR1_1,
4647                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4648
4649         lpt_init_clock_gating(dev);
4650 }
4651
4652 static void ivybridge_init_clock_gating(struct drm_device *dev)
4653 {
4654         struct drm_i915_private *dev_priv = dev->dev_private;
4655         int pipe;
4656         uint32_t snpcr;
4657
4658         I915_WRITE(WM3_LP_ILK, 0);
4659         I915_WRITE(WM2_LP_ILK, 0);
4660         I915_WRITE(WM1_LP_ILK, 0);
4661
4662         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4663
4664         /* WaDisableEarlyCull:ivb */
4665         I915_WRITE(_3D_CHICKEN3,
4666                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4667
4668         /* WaDisableBackToBackFlipFix:ivb */
4669         I915_WRITE(IVB_CHICKEN3,
4670                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4671                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4672
4673         /* WaDisablePSDDualDispatchEnable:ivb */
4674         if (IS_IVB_GT1(dev))
4675                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4676                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4677         else
4678                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4679                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4680
4681         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4682         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4683                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4684
4685         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4686         I915_WRITE(GEN7_L3CNTLREG1,
4687                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4688         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4689                    GEN7_WA_L3_CHICKEN_MODE);
4690         if (IS_IVB_GT1(dev))
4691                 I915_WRITE(GEN7_ROW_CHICKEN2,
4692                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4693         else
4694                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4695                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4696
4697
4698         /* WaForceL3Serialization:ivb */
4699         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4700                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4701
4702         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4703          * gating disable must be set.  Failure to set it results in
4704          * flickering pixels due to Z write ordering failures after
4705          * some amount of runtime in the Mesa "fire" demo, and Unigine
4706          * Sanctuary and Tropics, and apparently anything else with
4707          * alpha test or pixel discard.
4708          *
4709          * According to the spec, bit 11 (RCCUNIT) must also be set,
4710          * but we didn't debug actual testcases to find it out.
4711          *
4712          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4713          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4714          */
4715         I915_WRITE(GEN6_UCGCTL2,
4716                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4717                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4718
4719         /* This is required by WaCatErrorRejectionIssue:ivb */
4720         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4721                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4722                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4723
4724         for_each_pipe(pipe) {
4725                 I915_WRITE(DSPCNTR(pipe),
4726                            I915_READ(DSPCNTR(pipe)) |
4727                            DISPPLANE_TRICKLE_FEED_DISABLE);
4728                 intel_flush_display_plane(dev_priv, pipe);
4729         }
4730
4731         /* WaMbcDriverBootEnable:ivb */
4732         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4733                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4734
4735         /* WaVSRefCountFullforceMissDisable:ivb */
4736         gen7_setup_fixed_func_scheduler(dev_priv);
4737
4738         /* WaDisable4x2SubspanOptimization:ivb */
4739         I915_WRITE(CACHE_MODE_1,
4740                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4741
4742         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4743         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4744         snpcr |= GEN6_MBC_SNPCR_MED;
4745         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4746
4747         if (!HAS_PCH_NOP(dev))
4748                 cpt_init_clock_gating(dev);
4749
4750         gen6_check_mch_setup(dev);
4751 }
4752
4753 static void valleyview_init_clock_gating(struct drm_device *dev)
4754 {
4755         struct drm_i915_private *dev_priv = dev->dev_private;
4756         int pipe;
4757
4758         I915_WRITE(WM3_LP_ILK, 0);
4759         I915_WRITE(WM2_LP_ILK, 0);
4760         I915_WRITE(WM1_LP_ILK, 0);
4761
4762         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4763
4764         /* WaDisableEarlyCull:vlv */
4765         I915_WRITE(_3D_CHICKEN3,
4766                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4767
4768         /* WaDisableBackToBackFlipFix:vlv */
4769         I915_WRITE(IVB_CHICKEN3,
4770                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4771                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4772
4773         /* WaDisablePSDDualDispatchEnable:vlv */
4774         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4775                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4776                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4777
4778         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4779         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4780                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4781
4782         /* WaApplyL3ControlAndL3ChickenMode:vlv */
4783         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4784         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4785
4786         /* WaForceL3Serialization:vlv */
4787         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4788                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4789
4790         /* WaDisableDopClockGating:vlv */
4791         I915_WRITE(GEN7_ROW_CHICKEN2,
4792                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4793
4794         /* WaForceL3Serialization:vlv */
4795         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4796                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4797
4798         /* This is required by WaCatErrorRejectionIssue:vlv */
4799         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4800                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4801                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4802
4803         /* WaMbcDriverBootEnable:vlv */
4804         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4805                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4806
4807
4808         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4809          * gating disable must be set.  Failure to set it results in
4810          * flickering pixels due to Z write ordering failures after
4811          * some amount of runtime in the Mesa "fire" demo, and Unigine
4812          * Sanctuary and Tropics, and apparently anything else with
4813          * alpha test or pixel discard.
4814          *
4815          * According to the spec, bit 11 (RCCUNIT) must also be set,
4816          * but we didn't debug actual testcases to find it out.
4817          *
4818          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4819          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4820          *
4821          * Also apply WaDisableVDSUnitClockGating:vlv and
4822          * WaDisableRCPBUnitClockGating:vlv.
4823          */
4824         I915_WRITE(GEN6_UCGCTL2,
4825                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4826                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4827                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4828                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4829                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4830
4831         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4832
4833         for_each_pipe(pipe) {
4834                 I915_WRITE(DSPCNTR(pipe),
4835                            I915_READ(DSPCNTR(pipe)) |
4836                            DISPPLANE_TRICKLE_FEED_DISABLE);
4837                 intel_flush_display_plane(dev_priv, pipe);
4838         }
4839
4840         I915_WRITE(CACHE_MODE_1,
4841                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4842
4843         /*
4844          * WaDisableVLVClockGating_VBIIssue:vlv
4845          * Disable clock gating on th GCFG unit to prevent a delay
4846          * in the reporting of vblank events.
4847          */
4848         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4849
4850         /* Conservative clock gating settings for now */
4851         I915_WRITE(0x9400, 0xffffffff);
4852         I915_WRITE(0x9404, 0xffffffff);
4853         I915_WRITE(0x9408, 0xffffffff);
4854         I915_WRITE(0x940c, 0xffffffff);
4855         I915_WRITE(0x9410, 0xffffffff);
4856         I915_WRITE(0x9414, 0xffffffff);
4857         I915_WRITE(0x9418, 0xffffffff);
4858 }
4859
4860 static void g4x_init_clock_gating(struct drm_device *dev)
4861 {
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         uint32_t dspclk_gate;
4864
4865         I915_WRITE(RENCLK_GATE_D1, 0);
4866         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4867                    GS_UNIT_CLOCK_GATE_DISABLE |
4868                    CL_UNIT_CLOCK_GATE_DISABLE);
4869         I915_WRITE(RAMCLK_GATE_D, 0);
4870         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4871                 OVRUNIT_CLOCK_GATE_DISABLE |
4872                 OVCUNIT_CLOCK_GATE_DISABLE;
4873         if (IS_GM45(dev))
4874                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4875         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4876
4877         /* WaDisableRenderCachePipelinedFlush */
4878         I915_WRITE(CACHE_MODE_0,
4879                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4880 }
4881
4882 static void crestline_init_clock_gating(struct drm_device *dev)
4883 {
4884         struct drm_i915_private *dev_priv = dev->dev_private;
4885
4886         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4887         I915_WRITE(RENCLK_GATE_D2, 0);
4888         I915_WRITE(DSPCLK_GATE_D, 0);
4889         I915_WRITE(RAMCLK_GATE_D, 0);
4890         I915_WRITE16(DEUC, 0);
4891 }
4892
4893 static void broadwater_init_clock_gating(struct drm_device *dev)
4894 {
4895         struct drm_i915_private *dev_priv = dev->dev_private;
4896
4897         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4898                    I965_RCC_CLOCK_GATE_DISABLE |
4899                    I965_RCPB_CLOCK_GATE_DISABLE |
4900                    I965_ISC_CLOCK_GATE_DISABLE |
4901                    I965_FBC_CLOCK_GATE_DISABLE);
4902         I915_WRITE(RENCLK_GATE_D2, 0);
4903 }
4904
4905 static void gen3_init_clock_gating(struct drm_device *dev)
4906 {
4907         struct drm_i915_private *dev_priv = dev->dev_private;
4908         u32 dstate = I915_READ(D_STATE);
4909
4910         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4911                 DSTATE_DOT_CLOCK_GATING;
4912         I915_WRITE(D_STATE, dstate);
4913
4914         if (IS_PINEVIEW(dev))
4915                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4916
4917         /* IIR "flip pending" means done if this bit is set */
4918         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4919 }
4920
4921 static void i85x_init_clock_gating(struct drm_device *dev)
4922 {
4923         struct drm_i915_private *dev_priv = dev->dev_private;
4924
4925         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4926 }
4927
4928 static void i830_init_clock_gating(struct drm_device *dev)
4929 {
4930         struct drm_i915_private *dev_priv = dev->dev_private;
4931
4932         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4933 }
4934
4935 void intel_init_clock_gating(struct drm_device *dev)
4936 {
4937         struct drm_i915_private *dev_priv = dev->dev_private;
4938
4939         dev_priv->display.init_clock_gating(dev);
4940 }
4941
4942 void intel_suspend_hw(struct drm_device *dev)
4943 {
4944         if (HAS_PCH_LPT(dev))
4945                 lpt_suspend_hw(dev);
4946 }
4947
4948 /**
4949  * We should only use the power well if we explicitly asked the hardware to
4950  * enable it, so check if it's enabled and also check if we've requested it to
4951  * be enabled.
4952  */
4953 bool intel_display_power_enabled(struct drm_device *dev,
4954                                  enum intel_display_power_domain domain)
4955 {
4956         struct drm_i915_private *dev_priv = dev->dev_private;
4957
4958         if (!HAS_POWER_WELL(dev))
4959                 return true;
4960
4961         switch (domain) {
4962         case POWER_DOMAIN_PIPE_A:
4963         case POWER_DOMAIN_TRANSCODER_EDP:
4964                 return true;
4965         case POWER_DOMAIN_PIPE_B:
4966         case POWER_DOMAIN_PIPE_C:
4967         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4968         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4969         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4970         case POWER_DOMAIN_TRANSCODER_A:
4971         case POWER_DOMAIN_TRANSCODER_B:
4972         case POWER_DOMAIN_TRANSCODER_C:
4973                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4974                        (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4975         default:
4976                 BUG();
4977         }
4978 }
4979
4980 void intel_set_power_well(struct drm_device *dev, bool enable)
4981 {
4982         struct drm_i915_private *dev_priv = dev->dev_private;
4983         bool is_enabled, enable_requested;
4984         uint32_t tmp;
4985
4986         if (!HAS_POWER_WELL(dev))
4987                 return;
4988
4989         if (!i915_disable_power_well && !enable)
4990                 return;
4991
4992         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4993         is_enabled = tmp & HSW_PWR_WELL_STATE;
4994         enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4995
4996         if (enable) {
4997                 if (!enable_requested)
4998                         I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4999
5000                 if (!is_enabled) {
5001                         DRM_DEBUG_KMS("Enabling power well\n");
5002                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5003                                       HSW_PWR_WELL_STATE), 20))
5004                                 DRM_ERROR("Timeout enabling power well\n");
5005                 }
5006         } else {
5007                 if (enable_requested) {
5008                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5009                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5010                 }
5011         }
5012 }
5013
5014 /*
5015  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5016  * when not needed anymore. We have 4 registers that can request the power well
5017  * to be enabled, and it will only be disabled if none of the registers is
5018  * requesting it to be enabled.
5019  */
5020 void intel_init_power_well(struct drm_device *dev)
5021 {
5022         struct drm_i915_private *dev_priv = dev->dev_private;
5023
5024         if (!HAS_POWER_WELL(dev))
5025                 return;
5026
5027         /* For now, we need the power well to be always enabled. */
5028         intel_set_power_well(dev, true);
5029
5030         /* We're taking over the BIOS, so clear any requests made by it since
5031          * the driver is in charge now. */
5032         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5033                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5034 }
5035
5036 /* Set up chip specific power management-related functions */
5037 void intel_init_pm(struct drm_device *dev)
5038 {
5039         struct drm_i915_private *dev_priv = dev->dev_private;
5040
5041         if (I915_HAS_FBC(dev)) {
5042                 if (HAS_PCH_SPLIT(dev)) {
5043                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5044                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5045                                 dev_priv->display.enable_fbc =
5046                                         gen7_enable_fbc;
5047                         else
5048                                 dev_priv->display.enable_fbc =
5049                                         ironlake_enable_fbc;
5050                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5051                 } else if (IS_GM45(dev)) {
5052                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5053                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5054                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5055                 } else if (IS_CRESTLINE(dev)) {
5056                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5057                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5058                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5059                 }
5060                 /* 855GM needs testing */
5061         }
5062
5063         /* For cxsr */
5064         if (IS_PINEVIEW(dev))
5065                 i915_pineview_get_mem_freq(dev);
5066         else if (IS_GEN5(dev))
5067                 i915_ironlake_get_mem_freq(dev);
5068
5069         /* For FIFO watermark updates */
5070         if (HAS_PCH_SPLIT(dev)) {
5071                 if (IS_GEN5(dev)) {
5072                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5073                                 dev_priv->display.update_wm = ironlake_update_wm;
5074                         else {
5075                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5076                                               "Disable CxSR\n");
5077                                 dev_priv->display.update_wm = NULL;
5078                         }
5079                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5080                 } else if (IS_GEN6(dev)) {
5081                         if (SNB_READ_WM0_LATENCY()) {
5082                                 dev_priv->display.update_wm = sandybridge_update_wm;
5083                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5084                         } else {
5085                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5086                                               "Disable CxSR\n");
5087                                 dev_priv->display.update_wm = NULL;
5088                         }
5089                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5090                 } else if (IS_IVYBRIDGE(dev)) {
5091                         if (SNB_READ_WM0_LATENCY()) {
5092                                 dev_priv->display.update_wm = ivybridge_update_wm;
5093                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5094                         } else {
5095                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5096                                               "Disable CxSR\n");
5097                                 dev_priv->display.update_wm = NULL;
5098                         }
5099                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5100                 } else if (IS_HASWELL(dev)) {
5101                         if (I915_READ64(MCH_SSKPD)) {
5102                                 dev_priv->display.update_wm = haswell_update_wm;
5103                                 dev_priv->display.update_sprite_wm =
5104                                         haswell_update_sprite_wm;
5105                         } else {
5106                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5107                                               "Disable CxSR\n");
5108                                 dev_priv->display.update_wm = NULL;
5109                         }
5110                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5111                 } else
5112                         dev_priv->display.update_wm = NULL;
5113         } else if (IS_VALLEYVIEW(dev)) {
5114                 dev_priv->display.update_wm = valleyview_update_wm;
5115                 dev_priv->display.init_clock_gating =
5116                         valleyview_init_clock_gating;
5117         } else if (IS_PINEVIEW(dev)) {
5118                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5119                                             dev_priv->is_ddr3,
5120                                             dev_priv->fsb_freq,
5121                                             dev_priv->mem_freq)) {
5122                         DRM_INFO("failed to find known CxSR latency "
5123                                  "(found ddr%s fsb freq %d, mem freq %d), "
5124                                  "disabling CxSR\n",
5125                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5126                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5127                         /* Disable CxSR and never update its watermark again */
5128                         pineview_disable_cxsr(dev);
5129                         dev_priv->display.update_wm = NULL;
5130                 } else
5131                         dev_priv->display.update_wm = pineview_update_wm;
5132                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5133         } else if (IS_G4X(dev)) {
5134                 dev_priv->display.update_wm = g4x_update_wm;
5135                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5136         } else if (IS_GEN4(dev)) {
5137                 dev_priv->display.update_wm = i965_update_wm;
5138                 if (IS_CRESTLINE(dev))
5139                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5140                 else if (IS_BROADWATER(dev))
5141                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5142         } else if (IS_GEN3(dev)) {
5143                 dev_priv->display.update_wm = i9xx_update_wm;
5144                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5145                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5146         } else if (IS_I865G(dev)) {
5147                 dev_priv->display.update_wm = i830_update_wm;
5148                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5149                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5150         } else if (IS_I85X(dev)) {
5151                 dev_priv->display.update_wm = i9xx_update_wm;
5152                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5153                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5154         } else {
5155                 dev_priv->display.update_wm = i830_update_wm;
5156                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5157                 if (IS_845G(dev))
5158                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5159                 else
5160                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5161         }
5162 }
5163
5164 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
5165 {
5166         u32 gt_thread_status_mask;
5167
5168         if (IS_HASWELL(dev_priv->dev))
5169                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
5170         else
5171                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
5172
5173         /* w/a for a sporadic read returning 0 by waiting for the GT
5174          * thread to wake up.
5175          */
5176         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
5177                 DRM_ERROR("GT thread status wait timed out\n");
5178 }
5179
5180 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
5181 {
5182         I915_WRITE_NOTRACE(FORCEWAKE, 0);
5183         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
5184 }
5185
5186 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5187 {
5188         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
5189                             FORCEWAKE_ACK_TIMEOUT_MS))
5190                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5191
5192         I915_WRITE_NOTRACE(FORCEWAKE, 1);
5193         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
5194
5195         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
5196                             FORCEWAKE_ACK_TIMEOUT_MS))
5197                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
5198
5199         /* WaRsForcewakeWaitTC0:snb */
5200         __gen6_gt_wait_for_thread_c0(dev_priv);
5201 }
5202
5203 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
5204 {
5205         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
5206         /* something from same cacheline, but !FORCEWAKE_MT */
5207         POSTING_READ(ECOBUS);
5208 }
5209
5210 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
5211 {
5212         u32 forcewake_ack;
5213
5214         if (IS_HASWELL(dev_priv->dev))
5215                 forcewake_ack = FORCEWAKE_ACK_HSW;
5216         else
5217                 forcewake_ack = FORCEWAKE_MT_ACK;
5218
5219         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
5220                             FORCEWAKE_ACK_TIMEOUT_MS))
5221                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5222
5223         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
5224         /* something from same cacheline, but !FORCEWAKE_MT */
5225         POSTING_READ(ECOBUS);
5226
5227         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
5228                             FORCEWAKE_ACK_TIMEOUT_MS))
5229                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
5230
5231         /* WaRsForcewakeWaitTC0:ivb,hsw */
5232         __gen6_gt_wait_for_thread_c0(dev_priv);
5233 }
5234
5235 /*
5236  * Generally this is called implicitly by the register read function. However,
5237  * if some sequence requires the GT to not power down then this function should
5238  * be called at the beginning of the sequence followed by a call to
5239  * gen6_gt_force_wake_put() at the end of the sequence.
5240  */
5241 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5242 {
5243         unsigned long irqflags;
5244
5245         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5246         if (dev_priv->forcewake_count++ == 0)
5247                 dev_priv->gt.force_wake_get(dev_priv);
5248         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5249 }
5250
5251 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
5252 {
5253         u32 gtfifodbg;
5254         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
5255         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
5256              "MMIO read or write has been dropped %x\n", gtfifodbg))
5257                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
5258 }
5259
5260 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5261 {
5262         I915_WRITE_NOTRACE(FORCEWAKE, 0);
5263         /* something from same cacheline, but !FORCEWAKE */
5264         POSTING_READ(ECOBUS);
5265         gen6_gt_check_fifodbg(dev_priv);
5266 }
5267
5268 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
5269 {
5270         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5271         /* something from same cacheline, but !FORCEWAKE_MT */
5272         POSTING_READ(ECOBUS);
5273         gen6_gt_check_fifodbg(dev_priv);
5274 }
5275
5276 /*
5277  * see gen6_gt_force_wake_get()
5278  */
5279 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5280 {
5281         unsigned long irqflags;
5282
5283         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5284         if (--dev_priv->forcewake_count == 0)
5285                 dev_priv->gt.force_wake_put(dev_priv);
5286         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5287 }
5288
5289 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
5290 {
5291         int ret = 0;
5292
5293         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
5294                 int loop = 500;
5295                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5296                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
5297                         udelay(10);
5298                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5299                 }
5300                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
5301                         ++ret;
5302                 dev_priv->gt_fifo_count = fifo;
5303         }
5304         dev_priv->gt_fifo_count--;
5305
5306         return ret;
5307 }
5308
5309 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
5310 {
5311         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
5312         /* something from same cacheline, but !FORCEWAKE_VLV */
5313         POSTING_READ(FORCEWAKE_ACK_VLV);
5314 }
5315
5316 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
5317 {
5318         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
5319                             FORCEWAKE_ACK_TIMEOUT_MS))
5320                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5321
5322         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
5323         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5324                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
5325
5326         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
5327                             FORCEWAKE_ACK_TIMEOUT_MS))
5328                 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
5329
5330         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
5331                              FORCEWAKE_KERNEL),
5332                             FORCEWAKE_ACK_TIMEOUT_MS))
5333                 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
5334
5335         /* WaRsForcewakeWaitTC0:vlv */
5336         __gen6_gt_wait_for_thread_c0(dev_priv);
5337 }
5338
5339 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
5340 {
5341         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5342         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5343                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5344         /* The below doubles as a POSTING_READ */
5345         gen6_gt_check_fifodbg(dev_priv);
5346 }
5347
5348 void intel_gt_reset(struct drm_device *dev)
5349 {
5350         struct drm_i915_private *dev_priv = dev->dev_private;
5351
5352         if (IS_VALLEYVIEW(dev)) {
5353                 vlv_force_wake_reset(dev_priv);
5354         } else if (INTEL_INFO(dev)->gen >= 6) {
5355                 __gen6_gt_force_wake_reset(dev_priv);
5356                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5357                         __gen6_gt_force_wake_mt_reset(dev_priv);
5358         }
5359 }
5360
5361 void intel_gt_init(struct drm_device *dev)
5362 {
5363         struct drm_i915_private *dev_priv = dev->dev_private;
5364
5365         spin_lock_init(&dev_priv->gt_lock);
5366
5367         intel_gt_reset(dev);
5368
5369         if (IS_VALLEYVIEW(dev)) {
5370                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
5371                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
5372         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5373                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
5374                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
5375         } else if (IS_GEN6(dev)) {
5376                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
5377                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
5378         }
5379         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5380                           intel_gen6_powersave_work);
5381 }
5382
5383 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5384 {
5385         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5386
5387         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5388                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5389                 return -EAGAIN;
5390         }
5391
5392         I915_WRITE(GEN6_PCODE_DATA, *val);
5393         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5394
5395         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5396                      500)) {
5397                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5398                 return -ETIMEDOUT;
5399         }
5400
5401         *val = I915_READ(GEN6_PCODE_DATA);
5402         I915_WRITE(GEN6_PCODE_DATA, 0);
5403
5404         return 0;
5405 }
5406
5407 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5408 {
5409         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5410
5411         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5412                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5413                 return -EAGAIN;
5414         }
5415
5416         I915_WRITE(GEN6_PCODE_DATA, val);
5417         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5418
5419         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5420                      500)) {
5421                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5422                 return -ETIMEDOUT;
5423         }
5424
5425         I915_WRITE(GEN6_PCODE_DATA, 0);
5426
5427         return 0;
5428 }
5429
5430 int vlv_gpu_freq(int ddr_freq, int val)
5431 {
5432         int mult, base;
5433
5434         switch (ddr_freq) {
5435         case 800:
5436                 mult = 20;
5437                 base = 120;
5438                 break;
5439         case 1066:
5440                 mult = 22;
5441                 base = 133;
5442                 break;
5443         case 1333:
5444                 mult = 21;
5445                 base = 125;
5446                 break;
5447         default:
5448                 return -1;
5449         }
5450
5451         return ((val - 0xbd) * mult) + base;
5452 }
5453
5454 int vlv_freq_opcode(int ddr_freq, int val)
5455 {
5456         int mult, base;
5457
5458         switch (ddr_freq) {
5459         case 800:
5460                 mult = 20;
5461                 base = 120;
5462                 break;
5463         case 1066:
5464                 mult = 22;
5465                 base = 133;
5466                 break;
5467         case 1333:
5468                 mult = 21;
5469                 base = 125;
5470                 break;
5471         default:
5472                 return -1;
5473         }
5474
5475         val /= mult;
5476         val -= base / mult;
5477         val += 0xbd;
5478
5479         if (val > 0xea)
5480                 val = 0xea;
5481
5482         return val;
5483 }
5484