1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
6 #include "i915_gem_request.h"
7 #include "i915_gem_timeline.h"
8 #include "i915_selftest.h"
10 #define I915_CMD_HASH_ORDER 9
12 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
13 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
14 * to give some inclination as to some of the magic values used in the various
17 #define CACHELINE_BYTES 64
18 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
21 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
22 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
23 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
25 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
26 * cacheline, the Head Pointer must not be greater than the Tail
29 #define I915_RING_FREE_SPACE 64
31 struct intel_hw_status_page {
37 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
38 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
40 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
41 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
43 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
44 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
46 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
47 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
49 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
50 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
52 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
53 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
55 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
56 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
58 #define gen8_semaphore_seqno_size sizeof(uint64_t)
59 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \
60 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
61 #define GEN8_SIGNAL_OFFSET(__ring, to) \
62 (dev_priv->semaphore->node.start + \
63 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
64 #define GEN8_WAIT_OFFSET(__ring, from) \
65 (dev_priv->semaphore->node.start + \
66 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
68 enum intel_engine_hangcheck_action {
73 ENGINE_ACTIVE_SUBUNITS,
78 static inline const char *
79 hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
86 case ENGINE_ACTIVE_SEQNO:
87 return "active seqno";
88 case ENGINE_ACTIVE_HEAD:
90 case ENGINE_ACTIVE_SUBUNITS:
91 return "active subunits";
92 case ENGINE_WAIT_KICK:
101 #define I915_MAX_SLICES 3
102 #define I915_MAX_SUBSLICES 3
104 #define instdone_slice_mask(dev_priv__) \
105 (INTEL_GEN(dev_priv__) == 7 ? \
106 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
108 #define instdone_subslice_mask(dev_priv__) \
109 (INTEL_GEN(dev_priv__) == 7 ? \
110 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
112 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
113 for ((slice__) = 0, (subslice__) = 0; \
114 (slice__) < I915_MAX_SLICES; \
115 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
116 (slice__) += ((subslice__) == 0)) \
117 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
118 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
120 struct intel_instdone {
122 /* The following exist only in the RCS engine */
124 u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
125 u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
128 struct intel_engine_hangcheck {
131 enum intel_engine_hangcheck_action action;
132 unsigned long action_timestamp;
134 struct intel_instdone instdone;
139 struct i915_vma *vma;
142 struct intel_engine_cs *engine;
144 struct list_head request_list;
154 struct i915_gem_context;
155 struct drm_i915_reg_table;
158 * we use a single page to load ctx workarounds so all of these
159 * values are referred in terms of dwords
161 * struct i915_wa_ctx_bb:
162 * offset: specifies batch starting position, also helpful in case
163 * if we want to have multiple batches at different offsets based on
164 * some criteria. It is not a requirement at the moment but provides
165 * an option for future use.
166 * size: size of the batch in DWORDS
168 struct i915_ctx_workarounds {
169 struct i915_wa_ctx_bb {
172 } indirect_ctx, per_ctx;
173 struct i915_vma *vma;
176 struct drm_i915_gem_request;
177 struct intel_render_state;
180 * Engine IDs definitions.
181 * Keep instances of the same type engine together.
183 enum intel_engine_id {
188 #define _VCS(n) (VCS + (n))
192 struct intel_engine_cs {
193 struct drm_i915_private *i915;
195 enum intel_engine_id id;
196 unsigned int exec_id;
200 unsigned int irq_shift;
201 struct intel_ring *buffer;
202 struct intel_timeline *timeline;
204 struct intel_render_state *render_state;
207 unsigned long irq_posted;
208 #define ENGINE_IRQ_BREADCRUMB 0
209 #define ENGINE_IRQ_EXECLIST 1
211 /* Rather than have every client wait upon all user interrupts,
212 * with the herd waking after every interrupt and each doing the
213 * heavyweight seqno dance, we delegate the task (of being the
214 * bottom-half of the user interrupt) to the first client. After
215 * every interrupt, we wake up one client, who does the heavyweight
216 * coherent seqno read and either goes back to sleep (if incomplete),
217 * or wakes up all the completed clients in parallel, before then
218 * transferring the bottom-half status to the next client in the queue.
220 * Compared to walking the entire list of waiters in a single dedicated
221 * bottom-half, we reduce the latency of the first waiter by avoiding
222 * a context switch, but incur additional coherent seqno reads when
223 * following the chain of request breadcrumbs. Since it is most likely
224 * that we have a single client waiting on each seqno, then reducing
225 * the overhead of waking that client is much preferred.
227 struct intel_breadcrumbs {
228 spinlock_t irq_lock; /* protects irq_*; irqsafe */
229 struct intel_wait *irq_wait; /* oldest waiter by retirement */
231 spinlock_t rb_lock; /* protects the rb and wraps irq_lock */
232 struct rb_root waiters; /* sorted by retirement, priority */
233 struct rb_root signals; /* sorted by retirement */
234 struct task_struct *signaler; /* used for fence signalling */
235 struct drm_i915_gem_request __rcu *first_signal;
236 struct timer_list fake_irq; /* used after a missed interrupt */
237 struct timer_list hangcheck; /* detect missed interrupts */
239 unsigned int hangcheck_interrupts;
242 bool irq_enabled : 1;
243 I915_SELFTEST_DECLARE(bool mock : 1);
247 * A pool of objects to use as shadow copies of client batch buffers
248 * when the command parser is enabled. Prevents the client from
249 * modifying the batch contents after software parsing.
251 struct i915_gem_batch_pool batch_pool;
253 struct intel_hw_status_page status_page;
254 struct i915_ctx_workarounds wa_ctx;
255 struct i915_vma *scratch;
257 u32 irq_keep_mask; /* always keep these interrupts */
258 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
259 void (*irq_enable)(struct intel_engine_cs *engine);
260 void (*irq_disable)(struct intel_engine_cs *engine);
262 int (*init_hw)(struct intel_engine_cs *engine);
263 void (*reset_hw)(struct intel_engine_cs *engine,
264 struct drm_i915_gem_request *req);
266 void (*set_default_submission)(struct intel_engine_cs *engine);
268 int (*context_pin)(struct intel_engine_cs *engine,
269 struct i915_gem_context *ctx);
270 void (*context_unpin)(struct intel_engine_cs *engine,
271 struct i915_gem_context *ctx);
272 int (*request_alloc)(struct drm_i915_gem_request *req);
273 int (*init_context)(struct drm_i915_gem_request *req);
275 int (*emit_flush)(struct drm_i915_gem_request *request,
277 #define EMIT_INVALIDATE BIT(0)
278 #define EMIT_FLUSH BIT(1)
279 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
280 int (*emit_bb_start)(struct drm_i915_gem_request *req,
281 u64 offset, u32 length,
282 unsigned int dispatch_flags);
283 #define I915_DISPATCH_SECURE BIT(0)
284 #define I915_DISPATCH_PINNED BIT(1)
285 #define I915_DISPATCH_RS BIT(2)
286 void (*emit_breadcrumb)(struct drm_i915_gem_request *req,
288 int emit_breadcrumb_sz;
290 /* Pass the request to the hardware queue (e.g. directly into
291 * the legacy ringbuffer or to the end of an execlist).
293 * This is called from an atomic context with irqs disabled; must
296 void (*submit_request)(struct drm_i915_gem_request *req);
298 /* Call when the priority on a request has changed and it and its
299 * dependencies may need rescheduling. Note the request itself may
300 * not be ready to run!
302 * Called under the struct_mutex.
304 void (*schedule)(struct drm_i915_gem_request *request,
307 /* Some chipsets are not quite as coherent as advertised and need
308 * an expensive kick to force a true read of the up-to-date seqno.
309 * However, the up-to-date seqno is not always required and the last
310 * seen value is good enough. Note that the seqno will always be
311 * monotonic, even if not coherent.
313 void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
314 void (*cleanup)(struct intel_engine_cs *engine);
316 /* GEN8 signal/wait table - never trust comments!
317 * signal to signal to signal to signal to signal to
318 * RCS VCS BCS VECS VCS2
319 * --------------------------------------------------------------------
320 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
321 * |-------------------------------------------------------------------
322 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
323 * |-------------------------------------------------------------------
324 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
325 * |-------------------------------------------------------------------
326 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
327 * |-------------------------------------------------------------------
328 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
329 * |-------------------------------------------------------------------
332 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
333 * ie. transpose of g(x, y)
335 * sync from sync from sync from sync from sync from
336 * RCS VCS BCS VECS VCS2
337 * --------------------------------------------------------------------
338 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
339 * |-------------------------------------------------------------------
340 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
341 * |-------------------------------------------------------------------
342 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
343 * |-------------------------------------------------------------------
344 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
345 * |-------------------------------------------------------------------
346 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
347 * |-------------------------------------------------------------------
350 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
351 * ie. transpose of f(x, y)
355 #define GEN6_SEMAPHORE_LAST VECS_HW
356 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
357 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
359 /* our mbox written by others */
360 u32 wait[GEN6_NUM_SEMAPHORES];
361 /* mboxes this ring signals to */
362 i915_reg_t signal[GEN6_NUM_SEMAPHORES];
364 u64 signal_ggtt[I915_NUM_ENGINES];
368 int (*sync_to)(struct drm_i915_gem_request *req,
369 struct drm_i915_gem_request *signal);
370 u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
374 struct tasklet_struct irq_tasklet;
375 struct execlist_port {
376 struct drm_i915_gem_request *request;
378 GEM_DEBUG_DECL(u32 context_id);
380 struct rb_root execlist_queue;
381 struct rb_node *execlist_first;
382 unsigned int fw_domains;
384 /* Contexts are pinned whilst they are active on the GPU. The last
385 * context executed remains active whilst the GPU is idle - the
386 * switch away and write to the context object only occurs on the
387 * next execution. Contexts are only unpinned on retirement of the
388 * following request ensuring that we can always write to the object
389 * on the context switch even after idling. Across suspend, we switch
390 * to the kernel context and trash it as the save may not happen
391 * before the hardware is powered down.
393 struct i915_gem_context *last_retired_context;
395 /* We track the current MI_SET_CONTEXT in order to eliminate
396 * redudant context switches. This presumes that requests are not
397 * reordered! Or when they are the tracking is updated along with
398 * the emission of individual requests into the legacy command
401 struct i915_gem_context *legacy_active_context;
403 /* status_notifier: list of callbacks for context-switch changes */
404 struct atomic_notifier_head context_status_notifier;
406 struct intel_engine_hangcheck hangcheck;
408 bool needs_cmd_parser;
411 * Table of commands the command parser needs to know about
414 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
417 * Table of registers allowed in commands that read/write registers.
419 const struct drm_i915_reg_table *reg_tables;
423 * Returns the bitmask for the length field of the specified command.
424 * Return 0 for an unrecognized/invalid command.
426 * If the command parser finds an entry for a command in the engine's
427 * cmd_tables, it gets the command's length based on the table entry.
428 * If not, it calls this function to determine the per-engine length
429 * field encoding for the command (i.e. different opcode ranges use
430 * certain bits to encode the command length in the header).
432 u32 (*get_cmd_length_mask)(u32 cmd_header);
435 static inline unsigned int
436 intel_engine_flag(const struct intel_engine_cs *engine)
438 return BIT(engine->id);
442 intel_read_status_page(struct intel_engine_cs *engine, int reg)
444 /* Ensure that the compiler doesn't optimize away the load. */
445 return READ_ONCE(engine->status_page.page_addr[reg]);
449 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
451 /* Writing into the status page should be done sparingly. Since
452 * we do when we are uncertain of the device state, we take a bit
453 * of extra paranoia to try and ensure that the HWS takes the value
454 * we give and that it doesn't end up trapped inside the CPU!
456 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
458 clflush(&engine->status_page.page_addr[reg]);
459 engine->status_page.page_addr[reg] = value;
460 clflush(&engine->status_page.page_addr[reg]);
463 WRITE_ONCE(engine->status_page.page_addr[reg], value);
468 * Reads a dword out of the status page, which is written to from the command
469 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
472 * The following dwords have a reserved meaning:
473 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
474 * 0x04: ring 0 head pointer
475 * 0x05: ring 1 head pointer (915-class)
476 * 0x06: ring 2 head pointer (915-class)
477 * 0x10-0x1b: Context status DWords (GM45)
478 * 0x1f: Last written status offset. (GM45)
479 * 0x20-0x2f: Reserved (Gen6+)
481 * The area from dword 0x30 to 0x3ff is available for driver usage.
483 #define I915_GEM_HWS_INDEX 0x30
484 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
485 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
486 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
489 intel_engine_create_ring(struct intel_engine_cs *engine, int size);
490 int intel_ring_pin(struct intel_ring *ring, unsigned int offset_bias);
491 void intel_ring_unpin(struct intel_ring *ring);
492 void intel_ring_free(struct intel_ring *ring);
494 void intel_engine_stop(struct intel_engine_cs *engine);
495 void intel_engine_cleanup(struct intel_engine_cs *engine);
497 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
499 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
501 u32 __must_check *intel_ring_begin(struct drm_i915_gem_request *req, int n);
504 intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs)
508 * This serves as a placeholder in the code so that the reader
509 * can compare against the preceding intel_ring_begin() and
510 * check that the number of dwords emitted matches the space
511 * reserved for the command packet (i.e. the value passed to
512 * intel_ring_begin()).
514 GEM_BUG_ON((req->ring->vaddr + req->ring->tail) != cs);
518 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
520 return pos & (ring->size - 1);
524 intel_ring_offset(const struct drm_i915_gem_request *req, void *addr)
526 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
527 u32 offset = addr - req->ring->vaddr;
528 GEM_BUG_ON(offset > req->ring->size);
529 return intel_ring_wrap(req->ring, offset);
533 assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
535 /* We could combine these into a single tail operation, but keeping
536 * them as seperate tests will help identify the cause should one
539 GEM_BUG_ON(!IS_ALIGNED(tail, 8));
540 GEM_BUG_ON(tail >= ring->size);
543 void intel_ring_update_space(struct intel_ring *ring);
545 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
547 void intel_engine_setup_common(struct intel_engine_cs *engine);
548 int intel_engine_init_common(struct intel_engine_cs *engine);
549 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
550 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
552 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
553 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
554 int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
555 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
556 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
558 u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
559 u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine);
561 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
563 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
566 static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
568 /* We are only peeking at the tail of the submit queue (and not the
569 * queue itself) in order to gain a hint as to the current active
570 * state of the engine. Callers are not expected to be taking
571 * engine->timeline->lock, nor are they expected to be concerned
572 * wtih serialising this hint with anything, so document it as
573 * a hint and nothing more.
575 return READ_ONCE(engine->timeline->seqno);
578 int init_workarounds_ring(struct intel_engine_cs *engine);
579 int intel_ring_workarounds_emit(struct drm_i915_gem_request *req);
581 void intel_engine_get_instdone(struct intel_engine_cs *engine,
582 struct intel_instdone *instdone);
585 * Arbitrary size for largest possible 'add request' sequence. The code paths
586 * are complex and variable. Empirical measurement shows that the worst case
587 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
588 * we need to allocate double the largest single packet within that emission
589 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
591 #define MIN_SPACE_FOR_ADD_REQUEST 336
593 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
595 return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
598 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
599 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
601 static inline void intel_wait_init(struct intel_wait *wait,
602 struct drm_i915_gem_request *rq)
608 static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno)
614 static inline bool intel_wait_has_seqno(const struct intel_wait *wait)
620 intel_wait_update_seqno(struct intel_wait *wait, u32 seqno)
623 return intel_wait_has_seqno(wait);
627 intel_wait_update_request(struct intel_wait *wait,
628 const struct drm_i915_gem_request *rq)
630 return intel_wait_update_seqno(wait, i915_gem_request_global_seqno(rq));
634 intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno)
636 return wait->seqno == seqno;
640 intel_wait_check_request(const struct intel_wait *wait,
641 const struct drm_i915_gem_request *rq)
643 return intel_wait_check_seqno(wait, i915_gem_request_global_seqno(rq));
646 static inline bool intel_wait_complete(const struct intel_wait *wait)
648 return RB_EMPTY_NODE(&wait->node);
651 bool intel_engine_add_wait(struct intel_engine_cs *engine,
652 struct intel_wait *wait);
653 void intel_engine_remove_wait(struct intel_engine_cs *engine,
654 struct intel_wait *wait);
655 void intel_engine_enable_signaling(struct drm_i915_gem_request *request);
656 void intel_engine_cancel_signaling(struct drm_i915_gem_request *request);
658 static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
660 return READ_ONCE(engine->breadcrumbs.irq_wait);
663 unsigned int intel_engine_wakeup(struct intel_engine_cs *engine);
664 #define ENGINE_WAKEUP_WAITER BIT(0)
665 #define ENGINE_WAKEUP_ASLEEP BIT(1)
667 void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
668 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
670 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
671 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
672 bool intel_breadcrumbs_busy(struct intel_engine_cs *engine);
674 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
676 memset(batch, 0, 6 * sizeof(u32));
678 batch[0] = GFX_OP_PIPE_CONTROL(6);
685 bool intel_engine_is_idle(struct intel_engine_cs *engine);
686 bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
688 void intel_engines_reset_default_submission(struct drm_i915_private *i915);
690 #endif /* _INTEL_RINGBUFFER_H_ */