drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define GEN9_ENABLE_DC5(dev) 0
  53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
  54
  55 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  56         for (i = 0;                                                     \
  57              i < (power_domains)->power_well_count &&                   \
  58                  ((power_well) = &(power_domains)->power_wells[i]);     \
  59              i++)                                                       \
  60                 if ((power_well)->domains & (domain_mask))
  61
  62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  63         for (i = (power_domains)->power_well_count - 1;                  \
  64              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  65              i--)                                                        \
  66                 if ((power_well)->domains & (domain_mask))
  67
  68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  69                                     int power_well_id);
  70
  71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
  72                                     struct i915_power_well *power_well)
  73 {
  74         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
  75         power_well->ops->enable(dev_priv, power_well);
  76         power_well->hw_enabled = true;
  77 }
  78
  79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
  80                                      struct i915_power_well *power_well)
  81 {
  82         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
  83         power_well->hw_enabled = false;
  84         power_well->ops->disable(dev_priv, power_well);
  85 }
  86
  87 /*
  88  * We should only use the power well if we explicitly asked the hardware to
  89  * enable it, so check if it's enabled and also check if we've requested it to
  90  * be enabled.
  91  */
  92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
  93                                    struct i915_power_well *power_well)
  94 {
  95         return I915_READ(HSW_PWR_WELL_DRIVER) ==
  96                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
  97 }
  98
  99 /**
 100  * __intel_display_power_is_enabled - unlocked check for a power domain
 101  * @dev_priv: i915 device instance
 102  * @domain: power domain to check
 103  *
 104  * This is the unlocked version of intel_display_power_is_enabled() and should
 105  * only be used from error capture and recovery code where deadlocks are
 106  * possible.
 107  *
 108  * Returns:
 109  * True when the power domain is enabled, false otherwise.
 110  */
 111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 112                                       enum intel_display_power_domain domain)
 113 {
 114         struct i915_power_domains *power_domains;
 115         struct i915_power_well *power_well;
 116         bool is_enabled;
 117         int i;
 118
 119         if (dev_priv->pm.suspended)
 120                 return false;
 121
 122         power_domains = &dev_priv->power_domains;
 123
 124         is_enabled = true;
 125
 126         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 127                 if (power_well->always_on)
 128                         continue;
 129
 130                 if (!power_well->hw_enabled) {
 131                         is_enabled = false;
 132                         break;
 133                 }
 134         }
 135
 136         return is_enabled;
 137 }
 138
 139 /**
 140  * intel_display_power_is_enabled - check for a power domain
 141  * @dev_priv: i915 device instance
 142  * @domain: power domain to check
 143  *
 144  * This function can be used to check the hw power domain state. It is mostly
 145  * used in hardware state readout functions. Everywhere else code should rely
 146  * upon explicit power domain reference counting to ensure that the hardware
 147  * block is powered up before accessing it.
 148  *
 149  * Callers must hold the relevant modesetting locks to ensure that concurrent
 150  * threads can't disable the power well while the caller tries to read a few
 151  * registers.
 152  *
 153  * Returns:
 154  * True when the power domain is enabled, false otherwise.
 155  */
 156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 157                                     enum intel_display_power_domain domain)
 158 {
 159         struct i915_power_domains *power_domains;
 160         bool ret;
 161
 162         power_domains = &dev_priv->power_domains;
 163
 164         mutex_lock(&power_domains->lock);
 165         ret = __intel_display_power_is_enabled(dev_priv, domain);
 166         mutex_unlock(&power_domains->lock);
 167
 168         return ret;
 169 }
 170
 171 /**
 172  * intel_display_set_init_power - set the initial power domain state
 173  * @dev_priv: i915 device instance
 174  * @enable: whether to enable or disable the initial power domain state
 175  *
 176  * For simplicity our driver load/unload and system suspend/resume code assumes
 177  * that all power domains are always enabled. This functions controls the state
 178  * of this little hack. While the initial power domain state is enabled runtime
 179  * pm is effectively disabled.
 180  */
 181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 182                                   bool enable)
 183 {
 184         if (dev_priv->power_domains.init_power_on == enable)
 185                 return;
 186
 187         if (enable)
 188                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 189         else
 190                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 191
 192         dev_priv->power_domains.init_power_on = enable;
 193 }
 194
 195 /*
 196  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 197  * when not needed anymore. We have 4 registers that can request the power well
 198  * to be enabled, and it will only be disabled if none of the registers is
 199  * requesting it to be enabled.
 200  */
 201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 202 {
 203         struct drm_device *dev = dev_priv->dev;
 204
 205         /*
 206          * After we re-enable the power well, if we touch VGA register 0x3d5
 207          * we'll get unclaimed register interrupts. This stops after we write
 208          * anything to the VGA MSR register. The vgacon module uses this
 209          * register all the time, so if we unbind our driver and, as a
 210          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 211          * console_unlock(). So make here we touch the VGA MSR register, making
 212          * sure vgacon can keep working normally without triggering interrupts
 213          * and error messages.
 214          */
 215         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 216         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 217         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 218
 219         if (IS_BROADWELL(dev))
 220                 gen8_irq_power_well_post_enable(dev_priv,
 221                                                 1 << PIPE_C | 1 << PIPE_B);
 222 }
 223
 224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 225                                        struct i915_power_well *power_well)
 226 {
 227         struct drm_device *dev = dev_priv->dev;
 228
 229         /*
 230          * After we re-enable the power well, if we touch VGA register 0x3d5
 231          * we'll get unclaimed register interrupts. This stops after we write
 232          * anything to the VGA MSR register. The vgacon module uses this
 233          * register all the time, so if we unbind our driver and, as a
 234          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 235          * console_unlock(). So make here we touch the VGA MSR register, making
 236          * sure vgacon can keep working normally without triggering interrupts
 237          * and error messages.
 238          */
 239         if (power_well->data == SKL_DISP_PW_2) {
 240                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 241                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 242                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 243
 244                 gen8_irq_power_well_post_enable(dev_priv,
 245                                                 1 << PIPE_C | 1 << PIPE_B);
 246         }
 247
 248         if (power_well->data == SKL_DISP_PW_1) {
 249                 intel_prepare_ddi(dev);
 250                 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
 251         }
 252 }
 253
 254 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 255                                struct i915_power_well *power_well, bool enable)
 256 {
 257         bool is_enabled, enable_requested;
 258         uint32_t tmp;
 259
 260         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 261         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 262         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 263
 264         if (enable) {
 265                 if (!enable_requested)
 266                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 267                                    HSW_PWR_WELL_ENABLE_REQUEST);
 268
 269                 if (!is_enabled) {
 270                         DRM_DEBUG_KMS("Enabling power well\n");
 271                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 272                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 273                                 DRM_ERROR("Timeout enabling power well\n");
 274                         hsw_power_well_post_enable(dev_priv);
 275                 }
 276
 277         } else {
 278                 if (enable_requested) {
 279                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 280                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 281                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 282                 }
 283         }
 284 }
 285
 286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 287         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 288         BIT(POWER_DOMAIN_PIPE_B) |                      \
 289         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 290         BIT(POWER_DOMAIN_PIPE_C) |                      \
 291         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 292         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 293         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 294         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 295         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 296         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 297         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 298         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 299         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 300         BIT(POWER_DOMAIN_AUX_B) |                       \
 301         BIT(POWER_DOMAIN_AUX_C) |                       \
 302         BIT(POWER_DOMAIN_AUX_D) |                       \
 303         BIT(POWER_DOMAIN_AUDIO) |                       \
 304         BIT(POWER_DOMAIN_VGA) |                         \
 305         BIT(POWER_DOMAIN_INIT))
 306 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 307         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 308         BIT(POWER_DOMAIN_PLLS) |                        \
 309         BIT(POWER_DOMAIN_PIPE_A) |                      \
 310         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 311         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 312         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 313         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 314         BIT(POWER_DOMAIN_AUX_A) |                       \
 315         BIT(POWER_DOMAIN_INIT))
 316 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 317         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 318         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 319         BIT(POWER_DOMAIN_INIT))
 320 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 321         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 322         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 323         BIT(POWER_DOMAIN_INIT))
 324 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 325         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 326         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 327         BIT(POWER_DOMAIN_INIT))
 328 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 329         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 330         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 331         BIT(POWER_DOMAIN_INIT))
 332 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (             \
 333         SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |         \
 334         BIT(POWER_DOMAIN_PLLS) |                        \
 335         BIT(POWER_DOMAIN_INIT))
 336 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 337         (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 338         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 339         SKL_DISPLAY_DDI_A_E_POWER_DOMAINS |             \
 340         SKL_DISPLAY_DDI_B_POWER_DOMAINS |               \
 341         SKL_DISPLAY_DDI_C_POWER_DOMAINS |               \
 342         SKL_DISPLAY_DDI_D_POWER_DOMAINS |               \
 343         SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |           \
 344         BIT(POWER_DOMAIN_INIT))
 345
 346 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 347         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 348         BIT(POWER_DOMAIN_PIPE_B) |                      \
 349         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 350         BIT(POWER_DOMAIN_PIPE_C) |                      \
 351         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 352         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 353         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 354         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 355         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 356         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 357         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 358         BIT(POWER_DOMAIN_AUX_B) |                       \
 359         BIT(POWER_DOMAIN_AUX_C) |                       \
 360         BIT(POWER_DOMAIN_AUDIO) |                       \
 361         BIT(POWER_DOMAIN_VGA) |                         \
 362         BIT(POWER_DOMAIN_INIT))
 363 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 364         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 365         BIT(POWER_DOMAIN_PIPE_A) |                      \
 366         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 367         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 368         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 369         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 370         BIT(POWER_DOMAIN_AUX_A) |                       \
 371         BIT(POWER_DOMAIN_PLLS) |                        \
 372         BIT(POWER_DOMAIN_INIT))
 373 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 374         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 375         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 376         BIT(POWER_DOMAIN_INIT))
 377
 378 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 379 {
 380         struct drm_device *dev = dev_priv->dev;
 381
 382         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 383         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 384                 "DC9 already programmed to be enabled.\n");
 385         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 386                 "DC5 still not disabled to enable DC9.\n");
 387         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 388         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 389
 390          /*
 391           * TODO: check for the following to verify the conditions to enter DC9
 392           * state are satisfied:
 393           * 1] Check relevant display engine registers to verify if mode set
 394           * disable sequence was followed.
 395           * 2] Check if display uninitialize sequence is initialized.
 396           */
 397 }
 398
 399 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 400 {
 401         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 402         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 403                 "DC9 already programmed to be disabled.\n");
 404         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 405                 "DC5 still not disabled.\n");
 406
 407          /*
 408           * TODO: check for the following to verify DC9 state was indeed
 409           * entered before programming to disable it:
 410           * 1] Check relevant display engine registers to verify if mode
 411           *  set disable sequence was followed.
 412           * 2] Check if display uninitialize sequence is initialized.
 413           */
 414 }
 415
 416 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 417 {
 418         uint32_t val;
 419
 420         assert_can_enable_dc9(dev_priv);
 421
 422         DRM_DEBUG_KMS("Enabling DC9\n");
 423
 424         val = I915_READ(DC_STATE_EN);
 425         val |= DC_STATE_EN_DC9;
 426         I915_WRITE(DC_STATE_EN, val);
 427         POSTING_READ(DC_STATE_EN);
 428 }
 429
 430 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 431 {
 432         uint32_t val;
 433
 434         assert_can_disable_dc9(dev_priv);
 435
 436         DRM_DEBUG_KMS("Disabling DC9\n");
 437
 438         val = I915_READ(DC_STATE_EN);
 439         val &= ~DC_STATE_EN_DC9;
 440         I915_WRITE(DC_STATE_EN, val);
 441         POSTING_READ(DC_STATE_EN);
 442 }
 443
 444 static void gen9_set_dc_state_debugmask_memory_up(
 445                         struct drm_i915_private *dev_priv)
 446 {
 447         uint32_t val;
 448
 449         /* The below bit doesn't need to be cleared ever afterwards */
 450         val = I915_READ(DC_STATE_DEBUG);
 451         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 452                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 453                 I915_WRITE(DC_STATE_DEBUG, val);
 454                 POSTING_READ(DC_STATE_DEBUG);
 455         }
 456 }
 457
 458 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 459 {
 460         struct drm_device *dev = dev_priv->dev;
 461         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 462                                         SKL_DISP_PW_2);
 463
 464         WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
 465         WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 466         WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 467
 468         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 469                                 "DC5 already programmed to be enabled.\n");
 470         WARN(dev_priv->pm.suspended,
 471                 "DC5 cannot be enabled, if platform is runtime-suspended.\n");
 472
 473         assert_csr_loaded(dev_priv);
 474 }
 475
 476 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 477 {
 478         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 479                                         SKL_DISP_PW_2);
 480         /*
 481          * During initialization, the firmware may not be loaded yet.
 482          * We still want to make sure that the DC enabling flag is cleared.
 483          */
 484         if (dev_priv->power_domains.initializing)
 485                 return;
 486
 487         WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
 488         WARN(dev_priv->pm.suspended,
 489                 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
 490 }
 491
 492 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 493 {
 494         uint32_t val;
 495
 496         assert_can_enable_dc5(dev_priv);
 497
 498         DRM_DEBUG_KMS("Enabling DC5\n");
 499
 500         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 501
 502         val = I915_READ(DC_STATE_EN);
 503         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 504         val |= DC_STATE_EN_UPTO_DC5;
 505         I915_WRITE(DC_STATE_EN, val);
 506         POSTING_READ(DC_STATE_EN);
 507 }
 508
 509 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 510 {
 511         uint32_t val;
 512
 513         assert_can_disable_dc5(dev_priv);
 514
 515         DRM_DEBUG_KMS("Disabling DC5\n");
 516
 517         val = I915_READ(DC_STATE_EN);
 518         val &= ~DC_STATE_EN_UPTO_DC5;
 519         I915_WRITE(DC_STATE_EN, val);
 520         POSTING_READ(DC_STATE_EN);
 521 }
 522
 523 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 524 {
 525         struct drm_device *dev = dev_priv->dev;
 526
 527         WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
 528         WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 529         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 530                 "Backlight is not disabled.\n");
 531         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 532                 "DC6 already programmed to be enabled.\n");
 533
 534         assert_csr_loaded(dev_priv);
 535 }
 536
 537 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 538 {
 539         /*
 540          * During initialization, the firmware may not be loaded yet.
 541          * We still want to make sure that the DC enabling flag is cleared.
 542          */
 543         if (dev_priv->power_domains.initializing)
 544                 return;
 545
 546         assert_csr_loaded(dev_priv);
 547         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 548                 "DC6 already programmed to be disabled.\n");
 549 }
 550
 551 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 552 {
 553         uint32_t val;
 554
 555         assert_can_enable_dc6(dev_priv);
 556
 557         DRM_DEBUG_KMS("Enabling DC6\n");
 558
 559         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 560
 561         val = I915_READ(DC_STATE_EN);
 562         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 563         val |= DC_STATE_EN_UPTO_DC6;
 564         I915_WRITE(DC_STATE_EN, val);
 565         POSTING_READ(DC_STATE_EN);
 566 }
 567
 568 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 569 {
 570         uint32_t val;
 571
 572         assert_can_disable_dc6(dev_priv);
 573
 574         DRM_DEBUG_KMS("Disabling DC6\n");
 575
 576         val = I915_READ(DC_STATE_EN);
 577         val &= ~DC_STATE_EN_UPTO_DC6;
 578         I915_WRITE(DC_STATE_EN, val);
 579         POSTING_READ(DC_STATE_EN);
 580 }
 581
 582 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 583                         struct i915_power_well *power_well, bool enable)
 584 {
 585         struct drm_device *dev = dev_priv->dev;
 586         uint32_t tmp, fuse_status;
 587         uint32_t req_mask, state_mask;
 588         bool is_enabled, enable_requested, check_fuse_status = false;
 589
 590         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 591         fuse_status = I915_READ(SKL_FUSE_STATUS);
 592
 593         switch (power_well->data) {
 594         case SKL_DISP_PW_1:
 595                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 596                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 597                         DRM_ERROR("PG0 not enabled\n");
 598                         return;
 599                 }
 600                 break;
 601         case SKL_DISP_PW_2:
 602                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 603                         DRM_ERROR("PG1 in disabled state\n");
 604                         return;
 605                 }
 606                 break;
 607         case SKL_DISP_PW_DDI_A_E:
 608         case SKL_DISP_PW_DDI_B:
 609         case SKL_DISP_PW_DDI_C:
 610         case SKL_DISP_PW_DDI_D:
 611         case SKL_DISP_PW_MISC_IO:
 612                 break;
 613         default:
 614                 WARN(1, "Unknown power well %lu\n", power_well->data);
 615                 return;
 616         }
 617
 618         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 619         enable_requested = tmp & req_mask;
 620         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 621         is_enabled = tmp & state_mask;
 622
 623         if (enable) {
 624                 if (!enable_requested) {
 625                         WARN((tmp & state_mask) &&
 626                                 !I915_READ(HSW_PWR_WELL_BIOS),
 627                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 628                                 when request is to disable!\n");
 629                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 630                                 power_well->data == SKL_DISP_PW_2) {
 631                                 if (SKL_ENABLE_DC6(dev)) {
 632                                         skl_disable_dc6(dev_priv);
 633                                         /*
 634                                          * DDI buffer programming unnecessary during driver-load/resume
 635                                          * as it's already done during modeset initialization then.
 636                                          * It's also invalid here as encoder list is still uninitialized.
 637                                          */
 638                                         if (!dev_priv->power_domains.initializing)
 639                                                 intel_prepare_ddi(dev);
 640                                 } else {
 641                                         gen9_disable_dc5(dev_priv);
 642                                 }
 643                         }
 644                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 645                 }
 646
 647                 if (!is_enabled) {
 648                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 649                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 650                                 state_mask), 1))
 651                                 DRM_ERROR("%s enable timeout\n",
 652                                         power_well->name);
 653                         check_fuse_status = true;
 654                 }
 655         } else {
 656                 if (enable_requested) {
 657                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 658                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 659                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 660
 661                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 662                                 power_well->data == SKL_DISP_PW_2) {
 663                                 enum csr_state state;
 664                                 /* TODO: wait for a completion event or
 665                                  * similar here instead of busy
 666                                  * waiting using wait_for function.
 667                                  */
 668                                 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
 669                                                 FW_UNINITIALIZED, 1000);
 670                                 if (state != FW_LOADED)
 671                                         DRM_ERROR("CSR firmware not ready (%d)\n",
 672                                                         state);
 673                                 else
 674                                         if (SKL_ENABLE_DC6(dev))
 675                                                 skl_enable_dc6(dev_priv);
 676                                         else
 677                                                 gen9_enable_dc5(dev_priv);
 678                         }
 679                 }
 680         }
 681
 682         if (check_fuse_status) {
 683                 if (power_well->data == SKL_DISP_PW_1) {
 684                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 685                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 686                                 DRM_ERROR("PG1 distributing status timeout\n");
 687                 } else if (power_well->data == SKL_DISP_PW_2) {
 688                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 689                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 690                                 DRM_ERROR("PG2 distributing status timeout\n");
 691                 }
 692         }
 693
 694         if (enable && !is_enabled)
 695                 skl_power_well_post_enable(dev_priv, power_well);
 696 }
 697
 698 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 699                                    struct i915_power_well *power_well)
 700 {
 701         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 702
 703         /*
 704          * We're taking over the BIOS, so clear any requests made by it since
 705          * the driver is in charge now.
 706          */
 707         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 708                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 709 }
 710
 711 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 712                                   struct i915_power_well *power_well)
 713 {
 714         hsw_set_power_well(dev_priv, power_well, true);
 715 }
 716
 717 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 718                                    struct i915_power_well *power_well)
 719 {
 720         hsw_set_power_well(dev_priv, power_well, false);
 721 }
 722
 723 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 724                                         struct i915_power_well *power_well)
 725 {
 726         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 727                 SKL_POWER_WELL_STATE(power_well->data);
 728
 729         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 730 }
 731
 732 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 733                                 struct i915_power_well *power_well)
 734 {
 735         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 736
 737         /* Clear any request made by BIOS as driver is taking over */
 738         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 739 }
 740
 741 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 742                                 struct i915_power_well *power_well)
 743 {
 744         skl_set_power_well(dev_priv, power_well, true);
 745 }
 746
 747 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 748                                 struct i915_power_well *power_well)
 749 {
 750         skl_set_power_well(dev_priv, power_well, false);
 751 }
 752
 753 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 754                                            struct i915_power_well *power_well)
 755 {
 756 }
 757
 758 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 759                                              struct i915_power_well *power_well)
 760 {
 761         return true;
 762 }
 763
 764 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 765                                struct i915_power_well *power_well, bool enable)
 766 {
 767         enum punit_power_well power_well_id = power_well->data;
 768         u32 mask;
 769         u32 state;
 770         u32 ctrl;
 771
 772         mask = PUNIT_PWRGT_MASK(power_well_id);
 773         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 774                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 775
 776         mutex_lock(&dev_priv->rps.hw_lock);
 777
 778 #define COND \
 779         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 780
 781         if (COND)
 782                 goto out;
 783
 784         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 785         ctrl &= ~mask;
 786         ctrl |= state;
 787         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 788
 789         if (wait_for(COND, 100))
 790                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 791                           state,
 792                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 793
 794 #undef COND
 795
 796 out:
 797         mutex_unlock(&dev_priv->rps.hw_lock);
 798 }
 799
 800 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 801                                    struct i915_power_well *power_well)
 802 {
 803         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 804 }
 805
 806 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 807                                   struct i915_power_well *power_well)
 808 {
 809         vlv_set_power_well(dev_priv, power_well, true);
 810 }
 811
 812 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 813                                    struct i915_power_well *power_well)
 814 {
 815         vlv_set_power_well(dev_priv, power_well, false);
 816 }
 817
 818 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 819                                    struct i915_power_well *power_well)
 820 {
 821         int power_well_id = power_well->data;
 822         bool enabled = false;
 823         u32 mask;
 824         u32 state;
 825         u32 ctrl;
 826
 827         mask = PUNIT_PWRGT_MASK(power_well_id);
 828         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 829
 830         mutex_lock(&dev_priv->rps.hw_lock);
 831
 832         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 833         /*
 834          * We only ever set the power-on and power-gate states, anything
 835          * else is unexpected.
 836          */
 837         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 838                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 839         if (state == ctrl)
 840                 enabled = true;
 841
 842         /*
 843          * A transient state at this point would mean some unexpected party
 844          * is poking at the power controls too.
 845          */
 846         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 847         WARN_ON(ctrl != state);
 848
 849         mutex_unlock(&dev_priv->rps.hw_lock);
 850
 851         return enabled;
 852 }
 853
 854 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 855 {
 856
 857         spin_lock_irq(&dev_priv->irq_lock);
 858         valleyview_enable_display_irqs(dev_priv);
 859         spin_unlock_irq(&dev_priv->irq_lock);
 860
 861         /*
 862          * During driver initialization/resume we can avoid restoring the
 863          * part of the HW/SW state that will be inited anyway explicitly.
 864          */
 865         if (dev_priv->power_domains.initializing)
 866                 return;
 867
 868         intel_hpd_init(dev_priv);
 869
 870         i915_redisable_vga_power_on(dev_priv->dev);
 871 }
 872
 873 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 874 {
 875         spin_lock_irq(&dev_priv->irq_lock);
 876         valleyview_disable_display_irqs(dev_priv);
 877         spin_unlock_irq(&dev_priv->irq_lock);
 878
 879         vlv_power_sequencer_reset(dev_priv);
 880 }
 881
 882 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 883                                           struct i915_power_well *power_well)
 884 {
 885         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 886
 887         vlv_set_power_well(dev_priv, power_well, true);
 888
 889         vlv_display_power_well_init(dev_priv);
 890 }
 891
 892 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 893                                            struct i915_power_well *power_well)
 894 {
 895         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 896
 897         vlv_display_power_well_deinit(dev_priv);
 898
 899         vlv_set_power_well(dev_priv, power_well, false);
 900 }
 901
 902 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 903                                            struct i915_power_well *power_well)
 904 {
 905         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 906
 907         /*
 908          * Enable the CRI clock source so we can get at the
 909          * display and the reference clock for VGA
 910          * hotplug / manual detection.
 911          */
 912         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
 913                    DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
 914         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 915
 916         vlv_set_power_well(dev_priv, power_well, true);
 917
 918         /*
 919          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 920          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 921          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 922          *   b. The other bits such as sfr settings / modesel may all
 923          *      be set to 0.
 924          *
 925          * This should only be done on init and resume from S3 with
 926          * both PLLs disabled, or we risk losing DPIO and PLL
 927          * synchronization.
 928          */
 929         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 930 }
 931
 932 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 933                                             struct i915_power_well *power_well)
 934 {
 935         enum pipe pipe;
 936
 937         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 938
 939         for_each_pipe(dev_priv, pipe)
 940                 assert_pll_disabled(dev_priv, pipe);
 941
 942         /* Assert common reset */
 943         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
 944
 945         vlv_set_power_well(dev_priv, power_well, false);
 946 }
 947
 948 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 949                                            struct i915_power_well *power_well)
 950 {
 951         enum dpio_phy phy;
 952
 953         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
 954                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
 955
 956         /*
 957          * Enable the CRI clock source so we can get at the
 958          * display and the reference clock for VGA
 959          * hotplug / manual detection.
 960          */
 961         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 962                 phy = DPIO_PHY0;
 963                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
 964                            DPLL_REF_CLK_ENABLE_VLV);
 965                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
 966                            DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
 967         } else {
 968                 phy = DPIO_PHY1;
 969                 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
 970                            DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
 971         }
 972         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 973         vlv_set_power_well(dev_priv, power_well, true);
 974
 975         /* Poll for phypwrgood signal */
 976         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
 977                 DRM_ERROR("Display PHY %d is not power up\n", phy);
 978
 979         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
 980         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
 981 }
 982
 983 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 984                                             struct i915_power_well *power_well)
 985 {
 986         enum dpio_phy phy;
 987
 988         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
 989                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
 990
 991         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 992                 phy = DPIO_PHY0;
 993                 assert_pll_disabled(dev_priv, PIPE_A);
 994                 assert_pll_disabled(dev_priv, PIPE_B);
 995         } else {
 996                 phy = DPIO_PHY1;
 997                 assert_pll_disabled(dev_priv, PIPE_C);
 998         }
 999
1000         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1001         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1002
1003         vlv_set_power_well(dev_priv, power_well, false);
1004 }
1005
1006 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1007                                         struct i915_power_well *power_well)
1008 {
1009         enum pipe pipe = power_well->data;
1010         bool enabled;
1011         u32 state, ctrl;
1012
1013         mutex_lock(&dev_priv->rps.hw_lock);
1014
1015         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1016         /*
1017          * We only ever set the power-on and power-gate states, anything
1018          * else is unexpected.
1019          */
1020         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1021         enabled = state == DP_SSS_PWR_ON(pipe);
1022
1023         /*
1024          * A transient state at this point would mean some unexpected party
1025          * is poking at the power controls too.
1026          */
1027         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1028         WARN_ON(ctrl << 16 != state);
1029
1030         mutex_unlock(&dev_priv->rps.hw_lock);
1031
1032         return enabled;
1033 }
1034
1035 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1036                                     struct i915_power_well *power_well,
1037                                     bool enable)
1038 {
1039         enum pipe pipe = power_well->data;
1040         u32 state;
1041         u32 ctrl;
1042
1043         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1044
1045         mutex_lock(&dev_priv->rps.hw_lock);
1046
1047 #define COND \
1048         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1049
1050         if (COND)
1051                 goto out;
1052
1053         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1054         ctrl &= ~DP_SSC_MASK(pipe);
1055         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1056         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1057
1058         if (wait_for(COND, 100))
1059                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1060                           state,
1061                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1062
1063 #undef COND
1064
1065 out:
1066         mutex_unlock(&dev_priv->rps.hw_lock);
1067 }
1068
1069 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1070                                         struct i915_power_well *power_well)
1071 {
1072         WARN_ON_ONCE(power_well->data != PIPE_A);
1073
1074         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1075 }
1076
1077 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1078                                        struct i915_power_well *power_well)
1079 {
1080         WARN_ON_ONCE(power_well->data != PIPE_A);
1081
1082         chv_set_pipe_power_well(dev_priv, power_well, true);
1083
1084         vlv_display_power_well_init(dev_priv);
1085 }
1086
1087 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1088                                         struct i915_power_well *power_well)
1089 {
1090         WARN_ON_ONCE(power_well->data != PIPE_A);
1091
1092         vlv_display_power_well_deinit(dev_priv);
1093
1094         chv_set_pipe_power_well(dev_priv, power_well, false);
1095 }
1096
1097 /**
1098  * intel_display_power_get - grab a power domain reference
1099  * @dev_priv: i915 device instance
1100  * @domain: power domain to reference
1101  *
1102  * This function grabs a power domain reference for @domain and ensures that the
1103  * power domain and all its parents are powered up. Therefore users should only
1104  * grab a reference to the innermost power domain they need.
1105  *
1106  * Any power domain reference obtained by this function must have a symmetric
1107  * call to intel_display_power_put() to release the reference again.
1108  */
1109 void intel_display_power_get(struct drm_i915_private *dev_priv,
1110                              enum intel_display_power_domain domain)
1111 {
1112         struct i915_power_domains *power_domains;
1113         struct i915_power_well *power_well;
1114         int i;
1115
1116         intel_runtime_pm_get(dev_priv);
1117
1118         power_domains = &dev_priv->power_domains;
1119
1120         mutex_lock(&power_domains->lock);
1121
1122         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1123                 if (!power_well->count++)
1124                         intel_power_well_enable(dev_priv, power_well);
1125         }
1126
1127         power_domains->domain_use_count[domain]++;
1128
1129         mutex_unlock(&power_domains->lock);
1130 }
1131
1132 /**
1133  * intel_display_power_put - release a power domain reference
1134  * @dev_priv: i915 device instance
1135  * @domain: power domain to reference
1136  *
1137  * This function drops the power domain reference obtained by
1138  * intel_display_power_get() and might power down the corresponding hardware
1139  * block right away if this is the last reference.
1140  */
1141 void intel_display_power_put(struct drm_i915_private *dev_priv,
1142                              enum intel_display_power_domain domain)
1143 {
1144         struct i915_power_domains *power_domains;
1145         struct i915_power_well *power_well;
1146         int i;
1147
1148         power_domains = &dev_priv->power_domains;
1149
1150         mutex_lock(&power_domains->lock);
1151
1152         WARN_ON(!power_domains->domain_use_count[domain]);
1153         power_domains->domain_use_count[domain]--;
1154
1155         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1156                 WARN_ON(!power_well->count);
1157
1158                 if (!--power_well->count && i915.disable_power_well)
1159                         intel_power_well_disable(dev_priv, power_well);
1160         }
1161
1162         mutex_unlock(&power_domains->lock);
1163
1164         intel_runtime_pm_put(dev_priv);
1165 }
1166
1167 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1168
1169 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1170         BIT(POWER_DOMAIN_PIPE_A) |                      \
1171         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1172         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
1173         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
1174         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
1175         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
1176         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
1177         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
1178         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
1179         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
1180         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1181         BIT(POWER_DOMAIN_PLLS) |                        \
1182         BIT(POWER_DOMAIN_AUX_A) |                       \
1183         BIT(POWER_DOMAIN_AUX_B) |                       \
1184         BIT(POWER_DOMAIN_AUX_C) |                       \
1185         BIT(POWER_DOMAIN_AUX_D) |                       \
1186         BIT(POWER_DOMAIN_INIT))
1187 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1188         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1189         BIT(POWER_DOMAIN_INIT))
1190
1191 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1192         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1193         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1194 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1195         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1196         BIT(POWER_DOMAIN_INIT))
1197
1198 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1199 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1200
1201 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1202         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1203         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1204         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1205         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1206         BIT(POWER_DOMAIN_PORT_CRT) |            \
1207         BIT(POWER_DOMAIN_AUX_B) |               \
1208         BIT(POWER_DOMAIN_AUX_C) |               \
1209         BIT(POWER_DOMAIN_INIT))
1210
1211 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1212         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1213         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1214         BIT(POWER_DOMAIN_AUX_B) |               \
1215         BIT(POWER_DOMAIN_INIT))
1216
1217 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1218         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1219         BIT(POWER_DOMAIN_AUX_B) |               \
1220         BIT(POWER_DOMAIN_INIT))
1221
1222 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1223         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1224         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1225         BIT(POWER_DOMAIN_AUX_C) |               \
1226         BIT(POWER_DOMAIN_INIT))
1227
1228 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1229         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1230         BIT(POWER_DOMAIN_AUX_C) |               \
1231         BIT(POWER_DOMAIN_INIT))
1232
1233 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1234         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1235         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1236         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1237         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1238         BIT(POWER_DOMAIN_AUX_B) |               \
1239         BIT(POWER_DOMAIN_AUX_C) |               \
1240         BIT(POWER_DOMAIN_INIT))
1241
1242 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1243         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
1244         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1245         BIT(POWER_DOMAIN_AUX_D) |               \
1246         BIT(POWER_DOMAIN_INIT))
1247
1248 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1249         .sync_hw = i9xx_always_on_power_well_noop,
1250         .enable = i9xx_always_on_power_well_noop,
1251         .disable = i9xx_always_on_power_well_noop,
1252         .is_enabled = i9xx_always_on_power_well_enabled,
1253 };
1254
1255 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1256         .sync_hw = chv_pipe_power_well_sync_hw,
1257         .enable = chv_pipe_power_well_enable,
1258         .disable = chv_pipe_power_well_disable,
1259         .is_enabled = chv_pipe_power_well_enabled,
1260 };
1261
1262 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1263         .sync_hw = vlv_power_well_sync_hw,
1264         .enable = chv_dpio_cmn_power_well_enable,
1265         .disable = chv_dpio_cmn_power_well_disable,
1266         .is_enabled = vlv_power_well_enabled,
1267 };
1268
1269 static struct i915_power_well i9xx_always_on_power_well[] = {
1270         {
1271                 .name = "always-on",
1272                 .always_on = 1,
1273                 .domains = POWER_DOMAIN_MASK,
1274                 .ops = &i9xx_always_on_power_well_ops,
1275         },
1276 };
1277
1278 static const struct i915_power_well_ops hsw_power_well_ops = {
1279         .sync_hw = hsw_power_well_sync_hw,
1280         .enable = hsw_power_well_enable,
1281         .disable = hsw_power_well_disable,
1282         .is_enabled = hsw_power_well_enabled,
1283 };
1284
1285 static const struct i915_power_well_ops skl_power_well_ops = {
1286         .sync_hw = skl_power_well_sync_hw,
1287         .enable = skl_power_well_enable,
1288         .disable = skl_power_well_disable,
1289         .is_enabled = skl_power_well_enabled,
1290 };
1291
1292 static struct i915_power_well hsw_power_wells[] = {
1293         {
1294                 .name = "always-on",
1295                 .always_on = 1,
1296                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1297                 .ops = &i9xx_always_on_power_well_ops,
1298         },
1299         {
1300                 .name = "display",
1301                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1302                 .ops = &hsw_power_well_ops,
1303         },
1304 };
1305
1306 static struct i915_power_well bdw_power_wells[] = {
1307         {
1308                 .name = "always-on",
1309                 .always_on = 1,
1310                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1311                 .ops = &i9xx_always_on_power_well_ops,
1312         },
1313         {
1314                 .name = "display",
1315                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1316                 .ops = &hsw_power_well_ops,
1317         },
1318 };
1319
1320 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1321         .sync_hw = vlv_power_well_sync_hw,
1322         .enable = vlv_display_power_well_enable,
1323         .disable = vlv_display_power_well_disable,
1324         .is_enabled = vlv_power_well_enabled,
1325 };
1326
1327 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1328         .sync_hw = vlv_power_well_sync_hw,
1329         .enable = vlv_dpio_cmn_power_well_enable,
1330         .disable = vlv_dpio_cmn_power_well_disable,
1331         .is_enabled = vlv_power_well_enabled,
1332 };
1333
1334 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1335         .sync_hw = vlv_power_well_sync_hw,
1336         .enable = vlv_power_well_enable,
1337         .disable = vlv_power_well_disable,
1338         .is_enabled = vlv_power_well_enabled,
1339 };
1340
1341 static struct i915_power_well vlv_power_wells[] = {
1342         {
1343                 .name = "always-on",
1344                 .always_on = 1,
1345                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1346                 .ops = &i9xx_always_on_power_well_ops,
1347         },
1348         {
1349                 .name = "display",
1350                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1351                 .data = PUNIT_POWER_WELL_DISP2D,
1352                 .ops = &vlv_display_power_well_ops,
1353         },
1354         {
1355                 .name = "dpio-tx-b-01",
1356                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1357                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1358                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1359                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1360                 .ops = &vlv_dpio_power_well_ops,
1361                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1362         },
1363         {
1364                 .name = "dpio-tx-b-23",
1365                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1366                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1367                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1368                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1369                 .ops = &vlv_dpio_power_well_ops,
1370                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1371         },
1372         {
1373                 .name = "dpio-tx-c-01",
1374                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1375                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1376                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1377                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1378                 .ops = &vlv_dpio_power_well_ops,
1379                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1380         },
1381         {
1382                 .name = "dpio-tx-c-23",
1383                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1384                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1385                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1386                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1387                 .ops = &vlv_dpio_power_well_ops,
1388                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1389         },
1390         {
1391                 .name = "dpio-common",
1392                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1393                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1394                 .ops = &vlv_dpio_cmn_power_well_ops,
1395         },
1396 };
1397
1398 static struct i915_power_well chv_power_wells[] = {
1399         {
1400                 .name = "always-on",
1401                 .always_on = 1,
1402                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1403                 .ops = &i9xx_always_on_power_well_ops,
1404         },
1405         {
1406                 .name = "display",
1407                 /*
1408                  * Pipe A power well is the new disp2d well. Pipe B and C
1409                  * power wells don't actually exist. Pipe A power well is
1410                  * required for any pipe to work.
1411                  */
1412                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1413                 .data = PIPE_A,
1414                 .ops = &chv_pipe_power_well_ops,
1415         },
1416         {
1417                 .name = "dpio-common-bc",
1418                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1419                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1420                 .ops = &chv_dpio_cmn_power_well_ops,
1421         },
1422         {
1423                 .name = "dpio-common-d",
1424                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1425                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1426                 .ops = &chv_dpio_cmn_power_well_ops,
1427         },
1428 };
1429
1430 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1431                                                  int power_well_id)
1432 {
1433         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1434         struct i915_power_well *power_well;
1435         int i;
1436
1437         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1438                 if (power_well->data == power_well_id)
1439                         return power_well;
1440         }
1441
1442         return NULL;
1443 }
1444
1445 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1446                                     int power_well_id)
1447 {
1448         struct i915_power_well *power_well;
1449         bool ret;
1450
1451         power_well = lookup_power_well(dev_priv, power_well_id);
1452         ret = power_well->ops->is_enabled(dev_priv, power_well);
1453
1454         return ret;
1455 }
1456
1457 static struct i915_power_well skl_power_wells[] = {
1458         {
1459                 .name = "always-on",
1460                 .always_on = 1,
1461                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1462                 .ops = &i9xx_always_on_power_well_ops,
1463         },
1464         {
1465                 .name = "power well 1",
1466                 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1467                 .ops = &skl_power_well_ops,
1468                 .data = SKL_DISP_PW_1,
1469         },
1470         {
1471                 .name = "MISC IO power well",
1472                 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1473                 .ops = &skl_power_well_ops,
1474                 .data = SKL_DISP_PW_MISC_IO,
1475         },
1476         {
1477                 .name = "power well 2",
1478                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1479                 .ops = &skl_power_well_ops,
1480                 .data = SKL_DISP_PW_2,
1481         },
1482         {
1483                 .name = "DDI A/E power well",
1484                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1485                 .ops = &skl_power_well_ops,
1486                 .data = SKL_DISP_PW_DDI_A_E,
1487         },
1488         {
1489                 .name = "DDI B power well",
1490                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1491                 .ops = &skl_power_well_ops,
1492                 .data = SKL_DISP_PW_DDI_B,
1493         },
1494         {
1495                 .name = "DDI C power well",
1496                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1497                 .ops = &skl_power_well_ops,
1498                 .data = SKL_DISP_PW_DDI_C,
1499         },
1500         {
1501                 .name = "DDI D power well",
1502                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1503                 .ops = &skl_power_well_ops,
1504                 .data = SKL_DISP_PW_DDI_D,
1505         },
1506 };
1507
1508 static struct i915_power_well bxt_power_wells[] = {
1509         {
1510                 .name = "always-on",
1511                 .always_on = 1,
1512                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1513                 .ops = &i9xx_always_on_power_well_ops,
1514         },
1515         {
1516                 .name = "power well 1",
1517                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1518                 .ops = &skl_power_well_ops,
1519                 .data = SKL_DISP_PW_1,
1520         },
1521         {
1522                 .name = "power well 2",
1523                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1524                 .ops = &skl_power_well_ops,
1525                 .data = SKL_DISP_PW_2,
1526         }
1527 };
1528
1529 #define set_power_wells(power_domains, __power_wells) ({                \
1530         (power_domains)->power_wells = (__power_wells);                 \
1531         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1532 })
1533
1534 /**
1535  * intel_power_domains_init - initializes the power domain structures
1536  * @dev_priv: i915 device instance
1537  *
1538  * Initializes the power domain structures for @dev_priv depending upon the
1539  * supported platform.
1540  */
1541 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1542 {
1543         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1544
1545         mutex_init(&power_domains->lock);
1546
1547         /*
1548          * The enabling order will be from lower to higher indexed wells,
1549          * the disabling order is reversed.
1550          */
1551         if (IS_HASWELL(dev_priv->dev)) {
1552                 set_power_wells(power_domains, hsw_power_wells);
1553         } else if (IS_BROADWELL(dev_priv->dev)) {
1554                 set_power_wells(power_domains, bdw_power_wells);
1555         } else if (IS_SKYLAKE(dev_priv->dev)) {
1556                 set_power_wells(power_domains, skl_power_wells);
1557         } else if (IS_BROXTON(dev_priv->dev)) {
1558                 set_power_wells(power_domains, bxt_power_wells);
1559         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1560                 set_power_wells(power_domains, chv_power_wells);
1561         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1562                 set_power_wells(power_domains, vlv_power_wells);
1563         } else {
1564                 set_power_wells(power_domains, i9xx_always_on_power_well);
1565         }
1566
1567         return 0;
1568 }
1569
1570 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1571 {
1572         struct drm_device *dev = dev_priv->dev;
1573         struct device *device = &dev->pdev->dev;
1574
1575         if (!HAS_RUNTIME_PM(dev))
1576                 return;
1577
1578         if (!intel_enable_rc6(dev))
1579                 return;
1580
1581         /* Make sure we're not suspended first. */
1582         pm_runtime_get_sync(device);
1583         pm_runtime_disable(device);
1584 }
1585
1586 /**
1587  * intel_power_domains_fini - finalizes the power domain structures
1588  * @dev_priv: i915 device instance
1589  *
1590  * Finalizes the power domain structures for @dev_priv depending upon the
1591  * supported platform. This function also disables runtime pm and ensures that
1592  * the device stays powered up so that the driver can be reloaded.
1593  */
1594 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1595 {
1596         intel_runtime_pm_disable(dev_priv);
1597
1598         /* The i915.ko module is still not prepared to be loaded when
1599          * the power well is not enabled, so just enable it in case
1600          * we're going to unload/reload. */
1601         intel_display_set_init_power(dev_priv, true);
1602 }
1603
1604 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1605 {
1606         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1607         struct i915_power_well *power_well;
1608         int i;
1609
1610         mutex_lock(&power_domains->lock);
1611         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1612                 power_well->ops->sync_hw(dev_priv, power_well);
1613                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1614                                                                      power_well);
1615         }
1616         mutex_unlock(&power_domains->lock);
1617 }
1618
1619 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1620 {
1621         struct i915_power_well *cmn_bc =
1622                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1623         struct i915_power_well *cmn_d =
1624                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1625
1626         /*
1627          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1628          * workaround never ever read DISPLAY_PHY_CONTROL, and
1629          * instead maintain a shadow copy ourselves. Use the actual
1630          * power well state to reconstruct the expected initial
1631          * value.
1632          */
1633         dev_priv->chv_phy_control =
1634                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1635                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1636                 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) |
1637                 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) |
1638                 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0);
1639         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc))
1640                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1641         if (cmn_d->ops->is_enabled(dev_priv, cmn_d))
1642                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1643 }
1644
1645 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1646 {
1647         struct i915_power_well *cmn =
1648                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1649         struct i915_power_well *disp2d =
1650                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1651
1652         /* If the display might be already active skip this */
1653         if (cmn->ops->is_enabled(dev_priv, cmn) &&
1654             disp2d->ops->is_enabled(dev_priv, disp2d) &&
1655             I915_READ(DPIO_CTL) & DPIO_CMNRST)
1656                 return;
1657
1658         DRM_DEBUG_KMS("toggling display PHY side reset\n");
1659
1660         /* cmnlane needs DPLL registers */
1661         disp2d->ops->enable(dev_priv, disp2d);
1662
1663         /*
1664          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1665          * Need to assert and de-assert PHY SB reset by gating the
1666          * common lane power, then un-gating it.
1667          * Simply ungating isn't enough to reset the PHY enough to get
1668          * ports and lanes running.
1669          */
1670         cmn->ops->disable(dev_priv, cmn);
1671 }
1672
1673 /**
1674  * intel_power_domains_init_hw - initialize hardware power domain state
1675  * @dev_priv: i915 device instance
1676  *
1677  * This function initializes the hardware power domain state and enables all
1678  * power domains using intel_display_set_init_power().
1679  */
1680 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1681 {
1682         struct drm_device *dev = dev_priv->dev;
1683         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1684
1685         power_domains->initializing = true;
1686
1687         if (IS_CHERRYVIEW(dev)) {
1688                 chv_phy_control_init(dev_priv);
1689         } else if (IS_VALLEYVIEW(dev)) {
1690                 mutex_lock(&power_domains->lock);
1691                 vlv_cmnlane_wa(dev_priv);
1692                 mutex_unlock(&power_domains->lock);
1693         }
1694
1695         /* For now, we need the power well to be always enabled. */
1696         intel_display_set_init_power(dev_priv, true);
1697         intel_power_domains_resume(dev_priv);
1698         power_domains->initializing = false;
1699 }
1700
1701 /**
1702  * intel_aux_display_runtime_get - grab an auxiliary power domain reference
1703  * @dev_priv: i915 device instance
1704  *
1705  * This function grabs a power domain reference for the auxiliary power domain
1706  * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
1707  * parents are powered up. Therefore users should only grab a reference to the
1708  * innermost power domain they need.
1709  *
1710  * Any power domain reference obtained by this function must have a symmetric
1711  * call to intel_aux_display_runtime_put() to release the reference again.
1712  */
1713 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
1714 {
1715         intel_runtime_pm_get(dev_priv);
1716 }
1717
1718 /**
1719  * intel_aux_display_runtime_put - release an auxiliary power domain reference
1720  * @dev_priv: i915 device instance
1721  *
1722  * This function drops the auxiliary power domain reference obtained by
1723  * intel_aux_display_runtime_get() and might power down the corresponding
1724  * hardware block right away if this is the last reference.
1725  */
1726 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
1727 {
1728         intel_runtime_pm_put(dev_priv);
1729 }
1730
1731 /**
1732  * intel_runtime_pm_get - grab a runtime pm reference
1733  * @dev_priv: i915 device instance
1734  *
1735  * This function grabs a device-level runtime pm reference (mostly used for GEM
1736  * code to ensure the GTT or GT is on) and ensures that it is powered up.
1737  *
1738  * Any runtime pm reference obtained by this function must have a symmetric
1739  * call to intel_runtime_pm_put() to release the reference again.
1740  */
1741 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
1742 {
1743         struct drm_device *dev = dev_priv->dev;
1744         struct device *device = &dev->pdev->dev;
1745
1746         if (!HAS_RUNTIME_PM(dev))
1747                 return;
1748
1749         pm_runtime_get_sync(device);
1750         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
1751 }
1752
1753 /**
1754  * intel_runtime_pm_get_noresume - grab a runtime pm reference
1755  * @dev_priv: i915 device instance
1756  *
1757  * This function grabs a device-level runtime pm reference (mostly used for GEM
1758  * code to ensure the GTT or GT is on).
1759  *
1760  * It will _not_ power up the device but instead only check that it's powered
1761  * on.  Therefore it is only valid to call this functions from contexts where
1762  * the device is known to be powered up and where trying to power it up would
1763  * result in hilarity and deadlocks. That pretty much means only the system
1764  * suspend/resume code where this is used to grab runtime pm references for
1765  * delayed setup down in work items.
1766  *
1767  * Any runtime pm reference obtained by this function must have a symmetric
1768  * call to intel_runtime_pm_put() to release the reference again.
1769  */
1770 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
1771 {
1772         struct drm_device *dev = dev_priv->dev;
1773         struct device *device = &dev->pdev->dev;
1774
1775         if (!HAS_RUNTIME_PM(dev))
1776                 return;
1777
1778         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
1779         pm_runtime_get_noresume(device);
1780 }
1781
1782 /**
1783  * intel_runtime_pm_put - release a runtime pm reference
1784  * @dev_priv: i915 device instance
1785  *
1786  * This function drops the device-level runtime pm reference obtained by
1787  * intel_runtime_pm_get() and might power down the corresponding
1788  * hardware block right away if this is the last reference.
1789  */
1790 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
1791 {
1792         struct drm_device *dev = dev_priv->dev;
1793         struct device *device = &dev->pdev->dev;
1794
1795         if (!HAS_RUNTIME_PM(dev))
1796                 return;
1797
1798         pm_runtime_mark_last_busy(device);
1799         pm_runtime_put_autosuspend(device);
1800 }
1801
1802 /**
1803  * intel_runtime_pm_enable - enable runtime pm
1804  * @dev_priv: i915 device instance
1805  *
1806  * This function enables runtime pm at the end of the driver load sequence.
1807  *
1808  * Note that this function does currently not enable runtime pm for the
1809  * subordinate display power domains. That is only done on the first modeset
1810  * using intel_display_set_init_power().
1811  */
1812 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
1813 {
1814         struct drm_device *dev = dev_priv->dev;
1815         struct device *device = &dev->pdev->dev;
1816
1817         if (!HAS_RUNTIME_PM(dev))
1818                 return;
1819
1820         pm_runtime_set_active(device);
1821
1822         /*
1823          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1824          * requirement.
1825          */
1826         if (!intel_enable_rc6(dev)) {
1827                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1828                 return;
1829         }
1830
1831         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
1832         pm_runtime_mark_last_busy(device);
1833         pm_runtime_use_autosuspend(device);
1834
1835         pm_runtime_put_autosuspend(device);
1836 }
1837