2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/object.h>
26 #include <core/parent.h>
27 #include <core/handle.h>
28 #include <core/class.h>
30 #include <engine/disp.h>
32 #include <subdev/bios.h>
33 #include <subdev/bios/dcb.h>
34 #include <subdev/bios/disp.h>
35 #include <subdev/bios/init.h>
36 #include <subdev/bios/pll.h>
37 #include <subdev/devinit.h>
38 #include <subdev/timer.h>
39 #include <subdev/fb.h>
43 /*******************************************************************************
44 * EVO channel base class
45 ******************************************************************************/
48 nv50_disp_chan_create_(struct nouveau_object *parent,
49 struct nouveau_object *engine,
50 struct nouveau_oclass *oclass, int chid,
51 int length, void **pobject)
53 struct nv50_disp_base *base = (void *)parent;
54 struct nv50_disp_chan *chan;
57 if (base->chan & (1 << chid))
59 base->chan |= (1 << chid);
61 ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
62 (1ULL << NVDEV_ENGINE_DMAOBJ),
73 nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
75 struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
76 base->chan &= ~(1 << chan->chid);
77 nouveau_namedb_destroy(&chan->base);
81 nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
83 struct nv50_disp_priv *priv = (void *)object->engine;
84 struct nv50_disp_chan *chan = (void *)object;
85 return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr);
89 nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
91 struct nv50_disp_priv *priv = (void *)object->engine;
92 struct nv50_disp_chan *chan = (void *)object;
93 nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data);
96 /*******************************************************************************
97 * EVO DMA channel base class
98 ******************************************************************************/
101 nv50_disp_dmac_object_attach(struct nouveau_object *parent,
102 struct nouveau_object *object, u32 name)
104 struct nv50_disp_base *base = (void *)parent->parent;
105 struct nv50_disp_chan *chan = (void *)parent;
106 u32 addr = nv_gpuobj(object)->node->offset;
107 u32 chid = chan->chid;
108 u32 data = (chid << 28) | (addr << 10) | chid;
109 return nouveau_ramht_insert(base->ramht, chid, name, data);
113 nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
115 struct nv50_disp_base *base = (void *)parent->parent;
116 nouveau_ramht_remove(base->ramht, cookie);
120 nv50_disp_dmac_create_(struct nouveau_object *parent,
121 struct nouveau_object *engine,
122 struct nouveau_oclass *oclass, u32 pushbuf, int chid,
123 int length, void **pobject)
125 struct nv50_disp_dmac *dmac;
128 ret = nv50_disp_chan_create_(parent, engine, oclass, chid,
134 dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
138 switch (nv_mclass(dmac->pushdma)) {
141 if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff)
144 switch (dmac->pushdma->target) {
145 case NV_MEM_TARGET_VRAM:
146 dmac->push = 0x00000000 | dmac->pushdma->start >> 8;
148 case NV_MEM_TARGET_PCI_NOSNOOP:
149 dmac->push = 0x00000003 | dmac->pushdma->start >> 8;
163 nv50_disp_dmac_dtor(struct nouveau_object *object)
165 struct nv50_disp_dmac *dmac = (void *)object;
166 nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
167 nv50_disp_chan_destroy(&dmac->base);
171 nv50_disp_dmac_init(struct nouveau_object *object)
173 struct nv50_disp_priv *priv = (void *)object->engine;
174 struct nv50_disp_dmac *dmac = (void *)object;
175 int chid = dmac->base.chid;
178 ret = nv50_disp_chan_init(&dmac->base);
182 /* enable error reporting */
183 nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
185 /* initialise channel for dma command submission */
186 nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
187 nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);
188 nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);
189 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
190 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
191 nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);
193 /* wait for it to go inactive */
194 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {
195 nv_error(dmac, "init timeout, 0x%08x\n",
196 nv_rd32(priv, 0x610200 + (chid * 0x10)));
204 nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
206 struct nv50_disp_priv *priv = (void *)object->engine;
207 struct nv50_disp_dmac *dmac = (void *)object;
208 int chid = dmac->base.chid;
210 /* deactivate channel */
211 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);
212 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);
213 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) {
214 nv_error(dmac, "fini timeout, 0x%08x\n",
215 nv_rd32(priv, 0x610200 + (chid * 0x10)));
220 /* disable error reporting */
221 nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
223 return nv50_disp_chan_fini(&dmac->base, suspend);
226 /*******************************************************************************
227 * EVO master channel object
228 ******************************************************************************/
231 nv50_disp_mast_ctor(struct nouveau_object *parent,
232 struct nouveau_object *engine,
233 struct nouveau_oclass *oclass, void *data, u32 size,
234 struct nouveau_object **pobject)
236 struct nv50_display_mast_class *args = data;
237 struct nv50_disp_dmac *mast;
240 if (size < sizeof(*args))
243 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
244 0, sizeof(*mast), (void **)&mast);
245 *pobject = nv_object(mast);
249 nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach;
250 nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach;
255 nv50_disp_mast_init(struct nouveau_object *object)
257 struct nv50_disp_priv *priv = (void *)object->engine;
258 struct nv50_disp_dmac *mast = (void *)object;
261 ret = nv50_disp_chan_init(&mast->base);
265 /* enable error reporting */
266 nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
268 /* attempt to unstick channel from some unknown state */
269 if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
270 nv_mask(priv, 0x610200, 0x00800000, 0x00800000);
271 if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000)
272 nv_mask(priv, 0x610200, 0x00600000, 0x00600000);
274 /* initialise channel for dma command submission */
275 nv_wr32(priv, 0x610204, mast->push);
276 nv_wr32(priv, 0x610208, 0x00010000);
277 nv_wr32(priv, 0x61020c, 0x00000000);
278 nv_mask(priv, 0x610200, 0x00000010, 0x00000010);
279 nv_wr32(priv, 0x640000, 0x00000000);
280 nv_wr32(priv, 0x610200, 0x01000013);
282 /* wait for it to go inactive */
283 if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) {
284 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200));
292 nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
294 struct nv50_disp_priv *priv = (void *)object->engine;
295 struct nv50_disp_dmac *mast = (void *)object;
297 /* deactivate channel */
298 nv_mask(priv, 0x610200, 0x00000010, 0x00000000);
299 nv_mask(priv, 0x610200, 0x00000003, 0x00000000);
300 if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) {
301 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200));
306 /* disable error reporting */
307 nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
309 return nv50_disp_chan_fini(&mast->base, suspend);
312 struct nouveau_ofuncs
313 nv50_disp_mast_ofuncs = {
314 .ctor = nv50_disp_mast_ctor,
315 .dtor = nv50_disp_dmac_dtor,
316 .init = nv50_disp_mast_init,
317 .fini = nv50_disp_mast_fini,
318 .rd32 = nv50_disp_chan_rd32,
319 .wr32 = nv50_disp_chan_wr32,
322 /*******************************************************************************
323 * EVO sync channel objects
324 ******************************************************************************/
327 nv50_disp_sync_ctor(struct nouveau_object *parent,
328 struct nouveau_object *engine,
329 struct nouveau_oclass *oclass, void *data, u32 size,
330 struct nouveau_object **pobject)
332 struct nv50_display_sync_class *args = data;
333 struct nv50_disp_dmac *dmac;
336 if (size < sizeof(*args) || args->head > 1)
339 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
340 1 + args->head, sizeof(*dmac),
342 *pobject = nv_object(dmac);
346 nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
347 nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
351 struct nouveau_ofuncs
352 nv50_disp_sync_ofuncs = {
353 .ctor = nv50_disp_sync_ctor,
354 .dtor = nv50_disp_dmac_dtor,
355 .init = nv50_disp_dmac_init,
356 .fini = nv50_disp_dmac_fini,
357 .rd32 = nv50_disp_chan_rd32,
358 .wr32 = nv50_disp_chan_wr32,
361 /*******************************************************************************
362 * EVO overlay channel objects
363 ******************************************************************************/
366 nv50_disp_ovly_ctor(struct nouveau_object *parent,
367 struct nouveau_object *engine,
368 struct nouveau_oclass *oclass, void *data, u32 size,
369 struct nouveau_object **pobject)
371 struct nv50_display_ovly_class *args = data;
372 struct nv50_disp_dmac *dmac;
375 if (size < sizeof(*args) || args->head > 1)
378 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
379 3 + args->head, sizeof(*dmac),
381 *pobject = nv_object(dmac);
385 nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
386 nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
390 struct nouveau_ofuncs
391 nv50_disp_ovly_ofuncs = {
392 .ctor = nv50_disp_ovly_ctor,
393 .dtor = nv50_disp_dmac_dtor,
394 .init = nv50_disp_dmac_init,
395 .fini = nv50_disp_dmac_fini,
396 .rd32 = nv50_disp_chan_rd32,
397 .wr32 = nv50_disp_chan_wr32,
400 /*******************************************************************************
401 * EVO PIO channel base class
402 ******************************************************************************/
405 nv50_disp_pioc_create_(struct nouveau_object *parent,
406 struct nouveau_object *engine,
407 struct nouveau_oclass *oclass, int chid,
408 int length, void **pobject)
410 return nv50_disp_chan_create_(parent, engine, oclass, chid,
415 nv50_disp_pioc_dtor(struct nouveau_object *object)
417 struct nv50_disp_pioc *pioc = (void *)object;
418 nv50_disp_chan_destroy(&pioc->base);
422 nv50_disp_pioc_init(struct nouveau_object *object)
424 struct nv50_disp_priv *priv = (void *)object->engine;
425 struct nv50_disp_pioc *pioc = (void *)object;
426 int chid = pioc->base.chid;
429 ret = nv50_disp_chan_init(&pioc->base);
433 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);
434 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {
435 nv_error(pioc, "timeout0: 0x%08x\n",
436 nv_rd32(priv, 0x610200 + (chid * 0x10)));
440 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);
441 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {
442 nv_error(pioc, "timeout1: 0x%08x\n",
443 nv_rd32(priv, 0x610200 + (chid * 0x10)));
451 nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
453 struct nv50_disp_priv *priv = (void *)object->engine;
454 struct nv50_disp_pioc *pioc = (void *)object;
455 int chid = pioc->base.chid;
457 nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
458 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) {
459 nv_error(pioc, "timeout: 0x%08x\n",
460 nv_rd32(priv, 0x610200 + (chid * 0x10)));
465 return nv50_disp_chan_fini(&pioc->base, suspend);
468 /*******************************************************************************
469 * EVO immediate overlay channel objects
470 ******************************************************************************/
473 nv50_disp_oimm_ctor(struct nouveau_object *parent,
474 struct nouveau_object *engine,
475 struct nouveau_oclass *oclass, void *data, u32 size,
476 struct nouveau_object **pobject)
478 struct nv50_display_oimm_class *args = data;
479 struct nv50_disp_pioc *pioc;
482 if (size < sizeof(*args) || args->head > 1)
485 ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head,
486 sizeof(*pioc), (void **)&pioc);
487 *pobject = nv_object(pioc);
494 struct nouveau_ofuncs
495 nv50_disp_oimm_ofuncs = {
496 .ctor = nv50_disp_oimm_ctor,
497 .dtor = nv50_disp_pioc_dtor,
498 .init = nv50_disp_pioc_init,
499 .fini = nv50_disp_pioc_fini,
500 .rd32 = nv50_disp_chan_rd32,
501 .wr32 = nv50_disp_chan_wr32,
504 /*******************************************************************************
505 * EVO cursor channel objects
506 ******************************************************************************/
509 nv50_disp_curs_ctor(struct nouveau_object *parent,
510 struct nouveau_object *engine,
511 struct nouveau_oclass *oclass, void *data, u32 size,
512 struct nouveau_object **pobject)
514 struct nv50_display_curs_class *args = data;
515 struct nv50_disp_pioc *pioc;
518 if (size < sizeof(*args) || args->head > 1)
521 ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head,
522 sizeof(*pioc), (void **)&pioc);
523 *pobject = nv_object(pioc);
530 struct nouveau_ofuncs
531 nv50_disp_curs_ofuncs = {
532 .ctor = nv50_disp_curs_ctor,
533 .dtor = nv50_disp_pioc_dtor,
534 .init = nv50_disp_pioc_init,
535 .fini = nv50_disp_pioc_fini,
536 .rd32 = nv50_disp_chan_rd32,
537 .wr32 = nv50_disp_chan_wr32,
540 /*******************************************************************************
541 * Base display object
542 ******************************************************************************/
545 nv50_disp_base_scanoutpos(struct nouveau_object *object, u32 mthd,
546 void *data, u32 size)
548 struct nv50_disp_priv *priv = (void *)object->engine;
549 struct nv04_display_scanoutpos *args = data;
550 const int head = (mthd & NV50_DISP_MTHD_HEAD);
551 u32 blanke, blanks, total;
553 if (size < sizeof(*args) || head >= priv->head.nr)
555 blanke = nv_rd32(priv, 0x610aec + (head * 0x540));
556 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540));
557 total = nv_rd32(priv, 0x610afc + (head * 0x540));
559 args->vblanke = (blanke & 0xffff0000) >> 16;
560 args->hblanke = (blanke & 0x0000ffff);
561 args->vblanks = (blanks & 0xffff0000) >> 16;
562 args->hblanks = (blanks & 0x0000ffff);
563 args->vtotal = ( total & 0xffff0000) >> 16;
564 args->htotal = ( total & 0x0000ffff);
566 args->time[0] = ktime_to_ns(ktime_get());
567 args->vline = nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff;
568 args->time[1] = ktime_to_ns(ktime_get()); /* vline read locks hline */
569 args->hline = nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff;
574 nv50_disp_base_vblank_enable(struct nouveau_event *event, int head)
576 nv_mask(event->priv, 0x61002c, (4 << head), (4 << head));
580 nv50_disp_base_vblank_disable(struct nouveau_event *event, int head)
582 nv_mask(event->priv, 0x61002c, (4 << head), 0);
586 nv50_disp_base_ctor(struct nouveau_object *parent,
587 struct nouveau_object *engine,
588 struct nouveau_oclass *oclass, void *data, u32 size,
589 struct nouveau_object **pobject)
591 struct nv50_disp_priv *priv = (void *)engine;
592 struct nv50_disp_base *base;
595 ret = nouveau_parent_create(parent, engine, oclass, 0,
596 priv->sclass, 0, &base);
597 *pobject = nv_object(base);
601 priv->base.vblank->priv = priv;
602 priv->base.vblank->enable = nv50_disp_base_vblank_enable;
603 priv->base.vblank->disable = nv50_disp_base_vblank_disable;
604 return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
609 nv50_disp_base_dtor(struct nouveau_object *object)
611 struct nv50_disp_base *base = (void *)object;
612 nouveau_ramht_ref(NULL, &base->ramht);
613 nouveau_parent_destroy(&base->base);
617 nv50_disp_base_init(struct nouveau_object *object)
619 struct nv50_disp_priv *priv = (void *)object->engine;
620 struct nv50_disp_base *base = (void *)object;
624 ret = nouveau_parent_init(&base->base);
628 /* The below segments of code copying values from one register to
629 * another appear to inform EVO of the display capabilities or
630 * something similar. NFI what the 0x614004 caps are for..
632 tmp = nv_rd32(priv, 0x614004);
633 nv_wr32(priv, 0x610184, tmp);
636 for (i = 0; i < priv->head.nr; i++) {
637 tmp = nv_rd32(priv, 0x616100 + (i * 0x800));
638 nv_wr32(priv, 0x610190 + (i * 0x10), tmp);
639 tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
640 nv_wr32(priv, 0x610194 + (i * 0x10), tmp);
641 tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
642 nv_wr32(priv, 0x610198 + (i * 0x10), tmp);
643 tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
644 nv_wr32(priv, 0x61019c + (i * 0x10), tmp);
648 for (i = 0; i < priv->dac.nr; i++) {
649 tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
650 nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp);
654 for (i = 0; i < priv->sor.nr; i++) {
655 tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
656 nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp);
660 for (i = 0; i < priv->pior.nr; i++) {
661 tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
662 nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
665 /* steal display away from vbios, or something like that */
666 if (nv_rd32(priv, 0x610024) & 0x00000100) {
667 nv_wr32(priv, 0x610024, 0x00000100);
668 nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
669 if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
670 nv_error(priv, "timeout acquiring display\n");
675 /* point at display engine memory area (hash table, objects) */
676 nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9);
678 /* enable supervisor interrupts, disable everything else */
679 nv_wr32(priv, 0x61002c, 0x00000370);
680 nv_wr32(priv, 0x610028, 0x00000000);
685 nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
687 struct nv50_disp_priv *priv = (void *)object->engine;
688 struct nv50_disp_base *base = (void *)object;
690 /* disable all interrupts */
691 nv_wr32(priv, 0x610024, 0x00000000);
692 nv_wr32(priv, 0x610020, 0x00000000);
694 return nouveau_parent_fini(&base->base, suspend);
697 struct nouveau_ofuncs
698 nv50_disp_base_ofuncs = {
699 .ctor = nv50_disp_base_ctor,
700 .dtor = nv50_disp_base_dtor,
701 .init = nv50_disp_base_init,
702 .fini = nv50_disp_base_fini,
705 static struct nouveau_omthds
706 nv50_disp_base_omthds[] = {
707 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
708 { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
709 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
710 { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
711 { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
712 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
713 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
714 { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
718 static struct nouveau_oclass
719 nv50_disp_base_oclass[] = {
720 { NV50_DISP_CLASS, &nv50_disp_base_ofuncs, nv50_disp_base_omthds },
724 static struct nouveau_oclass
725 nv50_disp_sclass[] = {
726 { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
727 { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
728 { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
729 { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
730 { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
734 /*******************************************************************************
735 * Display context, tracks instmem allocation and prevents more than one
736 * client using the display hardware at any time.
737 ******************************************************************************/
740 nv50_disp_data_ctor(struct nouveau_object *parent,
741 struct nouveau_object *engine,
742 struct nouveau_oclass *oclass, void *data, u32 size,
743 struct nouveau_object **pobject)
745 struct nv50_disp_priv *priv = (void *)engine;
746 struct nouveau_engctx *ectx;
749 /* no context needed for channel objects... */
750 if (nv_mclass(parent) != NV_DEVICE_CLASS) {
751 atomic_inc(&parent->refcount);
756 /* allocate display hardware to client */
757 mutex_lock(&nv_subdev(priv)->mutex);
758 if (list_empty(&nv_engine(priv)->contexts)) {
759 ret = nouveau_engctx_create(parent, engine, oclass, NULL,
761 NVOBJ_FLAG_HEAP, &ectx);
762 *pobject = nv_object(ectx);
764 mutex_unlock(&nv_subdev(priv)->mutex);
768 struct nouveau_oclass
770 .handle = NV_ENGCTX(DISP, 0x50),
771 .ofuncs = &(struct nouveau_ofuncs) {
772 .ctor = nv50_disp_data_ctor,
773 .dtor = _nouveau_engctx_dtor,
774 .init = _nouveau_engctx_init,
775 .fini = _nouveau_engctx_fini,
776 .rd32 = _nouveau_engctx_rd32,
777 .wr32 = _nouveau_engctx_wr32,
781 /*******************************************************************************
782 * Display engine implementation
783 ******************************************************************************/
786 nv50_disp_intr_error(struct nv50_disp_priv *priv)
788 u32 channels = (nv_rd32(priv, 0x610020) & 0x001f0000) >> 16;
792 for (chid = 0; chid < 5; chid++) {
793 if (!(channels & (1 << chid)))
796 nv_wr32(priv, 0x610020, 0x00010000 << chid);
797 addr = nv_rd32(priv, 0x610080 + (chid * 0x08));
798 data = nv_rd32(priv, 0x610084 + (chid * 0x08));
799 nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);
801 nv_error(priv, "chid %d mthd 0x%04x data 0x%08x 0x%08x\n",
802 chid, addr & 0xffc, data, addr);
807 exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
808 struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
809 struct nvbios_outp *info)
811 struct nouveau_bios *bios = nouveau_bios(priv);
812 u16 mask, type, data;
815 type = DCB_OUTPUT_ANALOG;
819 switch (ctrl & 0x00000f00) {
820 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
821 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
822 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
823 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
824 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
825 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
827 nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
835 switch (ctrl & 0x00000f00) {
836 case 0x00000000: type |= priv->pior.type[outp]; break;
838 nv_error(priv, "unknown PIOR mc 0x%08x\n", ctrl);
843 mask = 0x00c0 & (mask << 6);
844 mask |= 0x0001 << outp;
845 mask |= 0x0100 << head;
847 data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
851 /* off-chip encoders require matching the exact encoder type */
852 if (dcb->location != 0)
853 type |= dcb->extdev << 8;
855 return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info);
859 exec_script(struct nv50_disp_priv *priv, int head, int id)
861 struct nouveau_bios *bios = nouveau_bios(priv);
862 struct nvbios_outp info;
863 struct dcb_output dcb;
864 u8 ver, hdr, cnt, len;
866 u32 ctrl = 0x00000000;
871 for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
872 ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
875 if (!(ctrl & (1 << head))) {
876 if (nv_device(priv)->chipset < 0x90 ||
877 nv_device(priv)->chipset == 0x92 ||
878 nv_device(priv)->chipset == 0xa0) {
883 for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
884 ctrl = nv_rd32(priv, reg + (i * 8));
889 if (!(ctrl & (1 << head))) {
890 for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
891 ctrl = nv_rd32(priv, 0x610b84 + (i * 8));
895 if (!(ctrl & (1 << head)))
899 data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
901 struct nvbios_init init = {
902 .subdev = nv_subdev(priv),
904 .offset = info.script[id],
910 return nvbios_exec(&init) == 0;
917 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
918 struct dcb_output *outp)
920 struct nouveau_bios *bios = nouveau_bios(priv);
921 struct nvbios_outp info1;
922 struct nvbios_ocfg info2;
923 u8 ver, hdr, cnt, len;
924 u32 ctrl = 0x00000000;
930 for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
931 ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
934 if (!(ctrl & (1 << head))) {
935 if (nv_device(priv)->chipset < 0x90 ||
936 nv_device(priv)->chipset == 0x92 ||
937 nv_device(priv)->chipset == 0xa0) {
942 for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
943 ctrl = nv_rd32(priv, reg + (i * 8));
948 if (!(ctrl & (1 << head))) {
949 for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
950 ctrl = nv_rd32(priv, 0x610b80 + (i * 8));
954 if (!(ctrl & (1 << head)))
958 data = exec_lookup(priv, head, i, ctrl, outp, &ver, &hdr, &cnt, &len, &info1);
962 if (outp->location == 0) {
963 switch (outp->type) {
964 case DCB_OUTPUT_TMDS:
965 conf = (ctrl & 0x00000f00) >> 8;
969 case DCB_OUTPUT_LVDS:
970 conf = priv->sor.lvdsconf;
973 conf = (ctrl & 0x00000f00) >> 8;
975 case DCB_OUTPUT_ANALOG:
981 conf = (ctrl & 0x00000f00) >> 8;
985 data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
986 if (data && id < 0xff) {
987 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
989 struct nvbios_init init = {
990 .subdev = nv_subdev(priv),
1006 nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head)
1008 exec_script(priv, head, 1);
1012 nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
1014 exec_script(priv, head, 2);
1018 nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
1020 struct nouveau_devinit *devinit = nouveau_devinit(priv);
1021 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1023 devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
1027 nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv,
1028 struct dcb_output *outp, u32 pclk)
1030 const int link = !(outp->sorconf.link & 1);
1031 const int or = ffs(outp->or) - 1;
1032 const u32 soff = ( or * 0x800);
1033 const u32 loff = (link * 0x080) + soff;
1034 const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
1035 const u32 symbol = 100000;
1036 u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000;
1037 u32 clksor = nv_rd32(priv, 0x614300 + soff);
1038 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
1039 int TU, VTUi, VTUf, VTUa;
1040 u64 link_data_rate, link_ratio, unk;
1041 u32 best_diff = 64 * symbol;
1042 u32 link_nr, link_bw, bits, r;
1044 /* calculate packed data rate for each lane */
1045 if (dpctrl > 0x00030000) link_nr = 4;
1046 else if (dpctrl > 0x00010000) link_nr = 2;
1049 if (clksor & 0x000c0000)
1054 if ((ctrl & 0xf0000) == 0x60000) bits = 30;
1055 else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
1058 link_data_rate = (pclk * bits / 8) / link_nr;
1060 /* calculate ratio of packed data rate to link symbol rate */
1061 link_ratio = link_data_rate * symbol;
1062 r = do_div(link_ratio, link_bw);
1064 for (TU = 64; TU >= 32; TU--) {
1065 /* calculate average number of valid symbols in each TU */
1066 u32 tu_valid = link_ratio * TU;
1069 /* find a hw representation for the fraction.. */
1070 VTUi = tu_valid / symbol;
1071 calc = VTUi * symbol;
1072 diff = tu_valid - calc;
1074 if (diff >= (symbol / 2)) {
1075 VTUf = symbol / (symbol - diff);
1076 if (symbol - (VTUf * diff))
1081 calc += symbol - (symbol / VTUf);
1089 VTUf = min((int)(symbol / diff), 15);
1090 calc += symbol / VTUf;
1093 diff = calc - tu_valid;
1095 /* no remainder, but the hw doesn't like the fractional
1096 * part to be zero. decrement the integer part and
1097 * have the fraction add a whole symbol back
1104 if (diff < best_diff) {
1116 nv_error(priv, "unable to find suitable dp config\n");
1120 /* XXX close to vbios numbers, but not right */
1121 unk = (symbol - link_ratio) * bestTU;
1123 r = do_div(unk, symbol);
1124 r = do_div(unk, symbol);
1127 nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2);
1128 nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
1130 bestVTUi << 8 | unk);
1134 nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1136 struct dcb_output outp;
1137 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1138 u32 hval, hreg = 0x614200 + (head * 0x800);
1141 u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
1143 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
1144 u32 soff = (ffs(outp.or) - 1) * 0x08;
1145 u32 ctrl = nv_rd32(priv, 0x610794 + soff);
1148 switch ((ctrl & 0x000f0000) >> 16) {
1149 case 6: datarate = pclk * 30 / 8; break;
1150 case 5: datarate = pclk * 24 / 8; break;
1153 datarate = pclk * 18 / 8;
1157 nouveau_dp_train(&priv->base, priv->sor.dp,
1158 &outp, head, datarate);
1161 exec_clkcmp(priv, head, 0, pclk, &outp);
1163 if (!outp.location && outp.type == DCB_OUTPUT_ANALOG) {
1164 oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
1169 if (!outp.location) {
1170 if (outp.type == DCB_OUTPUT_DP)
1171 nv50_disp_intr_unk20_2_dp(priv, &outp, pclk);
1172 oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
1173 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
1177 oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
1183 nv_mask(priv, hreg, 0x0000000f, hval);
1184 nv_mask(priv, oreg, mask, oval);
1188 /* If programming a TMDS output on a SOR that can also be configured for
1189 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
1191 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
1192 * the VBIOS scripts on at least one board I have only switch it off on
1193 * link 0, causing a blank display if the output has previously been
1194 * programmed for DisplayPort.
1197 nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
1199 struct nouveau_bios *bios = nouveau_bios(priv);
1200 const int link = !(outp->sorconf.link & 1);
1201 const int or = ffs(outp->or) - 1;
1202 const u32 loff = (or * 0x800) + (link * 0x80);
1203 const u16 mask = (outp->sorconf.link << 6) | outp->or;
1206 if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp))
1207 nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000);
1211 nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head)
1213 struct dcb_output outp;
1214 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1215 if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) {
1216 if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS)
1217 nv50_disp_intr_unk40_0_tmds(priv, &outp);
1219 if (outp.location == 1 && outp.type == DCB_OUTPUT_DP) {
1220 u32 soff = (ffs(outp.or) - 1) * 0x08;
1221 u32 ctrl = nv_rd32(priv, 0x610b84 + soff);
1224 switch ((ctrl & 0x000f0000) >> 16) {
1225 case 6: datarate = pclk * 30 / 8; break;
1226 case 5: datarate = pclk * 24 / 8; break;
1229 datarate = pclk * 18 / 8;
1233 nouveau_dp_train(&priv->base, priv->pior.dp,
1234 &outp, head, datarate);
1240 nv50_disp_intr_supervisor(struct work_struct *work)
1242 struct nv50_disp_priv *priv =
1243 container_of(work, struct nv50_disp_priv, supervisor);
1244 u32 super = nv_rd32(priv, 0x610030);
1247 nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super);
1249 if (priv->super & 0x00000010) {
1250 for (head = 0; head < priv->head.nr; head++) {
1251 if (!(super & (0x00000020 << head)))
1253 if (!(super & (0x00000080 << head)))
1255 nv50_disp_intr_unk10_0(priv, head);
1258 if (priv->super & 0x00000020) {
1259 for (head = 0; head < priv->head.nr; head++) {
1260 if (!(super & (0x00000080 << head)))
1262 nv50_disp_intr_unk20_0(priv, head);
1264 for (head = 0; head < priv->head.nr; head++) {
1265 if (!(super & (0x00000200 << head)))
1267 nv50_disp_intr_unk20_1(priv, head);
1269 for (head = 0; head < priv->head.nr; head++) {
1270 if (!(super & (0x00000080 << head)))
1272 nv50_disp_intr_unk20_2(priv, head);
1275 if (priv->super & 0x00000040) {
1276 for (head = 0; head < priv->head.nr; head++) {
1277 if (!(super & (0x00000080 << head)))
1279 nv50_disp_intr_unk40_0(priv, head);
1283 nv_wr32(priv, 0x610030, 0x80000000);
1287 nv50_disp_intr(struct nouveau_subdev *subdev)
1289 struct nv50_disp_priv *priv = (void *)subdev;
1290 u32 intr0 = nv_rd32(priv, 0x610020);
1291 u32 intr1 = nv_rd32(priv, 0x610024);
1293 if (intr0 & 0x001f0000) {
1294 nv50_disp_intr_error(priv);
1295 intr0 &= ~0x001f0000;
1298 if (intr1 & 0x00000004) {
1299 nouveau_event_trigger(priv->base.vblank, 0);
1300 nv_wr32(priv, 0x610024, 0x00000004);
1301 intr1 &= ~0x00000004;
1304 if (intr1 & 0x00000008) {
1305 nouveau_event_trigger(priv->base.vblank, 1);
1306 nv_wr32(priv, 0x610024, 0x00000008);
1307 intr1 &= ~0x00000008;
1310 if (intr1 & 0x00000070) {
1311 priv->super = (intr1 & 0x00000070);
1312 schedule_work(&priv->supervisor);
1313 nv_wr32(priv, 0x610024, priv->super);
1314 intr1 &= ~0x00000070;
1319 nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1320 struct nouveau_oclass *oclass, void *data, u32 size,
1321 struct nouveau_object **pobject)
1323 struct nv50_disp_priv *priv;
1326 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
1328 *pobject = nv_object(priv);
1332 nv_engine(priv)->sclass = nv50_disp_base_oclass;
1333 nv_engine(priv)->cclass = &nv50_disp_cclass;
1334 nv_subdev(priv)->intr = nv50_disp_intr;
1335 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
1336 priv->sclass = nv50_disp_sclass;
1341 priv->dac.power = nv50_dac_power;
1342 priv->dac.sense = nv50_dac_sense;
1343 priv->sor.power = nv50_sor_power;
1344 priv->pior.power = nv50_pior_power;
1345 priv->pior.dp = &nv50_pior_dp_func;
1349 struct nouveau_oclass
1350 nv50_disp_oclass = {
1351 .handle = NV_ENGINE(DISP, 0x50),
1352 .ofuncs = &(struct nouveau_ofuncs) {
1353 .ctor = nv50_disp_ctor,
1354 .dtor = _nouveau_disp_dtor,
1355 .init = _nouveau_disp_init,
1356 .fini = _nouveau_disp_fini,