drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/class.h>
  31 #include <core/math.h>
  32 #include <core/enum.h>
  33
  34 #include <subdev/timer.h>
  35 #include <subdev/bar.h>
  36 #include <subdev/vm.h>
  37
  38 #include <engine/dmaobj.h>
  39 #include <engine/fifo.h>
  40
  41 #define _(a,b) { (a), ((1 << (a)) | (b)) }
  42 static const struct {
  43         int subdev;
  44         u32 mask;
  45 } fifo_engine[] = {
  46         _(NVDEV_ENGINE_GR      , (1 << NVDEV_ENGINE_SW)),
  47         _(NVDEV_ENGINE_VP      , 0),
  48         _(NVDEV_ENGINE_PPP     , 0),
  49         _(NVDEV_ENGINE_BSP     , 0),
  50         _(NVDEV_ENGINE_COPY0   , 0),
  51         _(NVDEV_ENGINE_COPY1   , 0),
  52         _(NVDEV_ENGINE_VENC    , 0),
  53 };
  54 #undef _
  55 #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
  56
  57 struct nve0_fifo_engn {
  58         struct nouveau_gpuobj *playlist[2];
  59         int cur_playlist;
  60 };
  61
  62 struct nve0_fifo_priv {
  63         struct nouveau_fifo base;
  64         struct nve0_fifo_engn engine[FIFO_ENGINE_NR];
  65         struct {
  66                 struct nouveau_gpuobj *mem;
  67                 struct nouveau_vma bar;
  68         } user;
  69         int spoon_nr;
  70 };
  71
  72 struct nve0_fifo_base {
  73         struct nouveau_fifo_base base;
  74         struct nouveau_gpuobj *pgd;
  75         struct nouveau_vm *vm;
  76 };
  77
  78 struct nve0_fifo_chan {
  79         struct nouveau_fifo_chan base;
  80         u32 engine;
  81 };
  82
  83 /*******************************************************************************
  84  * FIFO channel objects
  85  ******************************************************************************/
  86
  87 static void
  88 nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
  89 {
  90         struct nouveau_bar *bar = nouveau_bar(priv);
  91         struct nve0_fifo_engn *engn = &priv->engine[engine];
  92         struct nouveau_gpuobj *cur;
  93         u32 match = (engine << 16) | 0x00000001;
  94         int i, p;
  95
  96         cur = engn->playlist[engn->cur_playlist];
  97         if (unlikely(cur == NULL)) {
  98                 int ret = nouveau_gpuobj_new(nv_object(priv)->parent, NULL,
  99                                              0x8000, 0x1000, 0, &cur);
 100                 if (ret) {
 101                         nv_error(priv, "playlist alloc failed\n");
 102                         return;
 103                 }
 104
 105                 engn->playlist[engn->cur_playlist] = cur;
 106         }
 107
 108         engn->cur_playlist = !engn->cur_playlist;
 109
 110         for (i = 0, p = 0; i < priv->base.max; i++) {
 111                 u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001;
 112                 if (ctrl != match)
 113                         continue;
 114                 nv_wo32(cur, p + 0, i);
 115                 nv_wo32(cur, p + 4, 0x00000000);
 116                 p += 8;
 117         }
 118         bar->flush(bar);
 119
 120         nv_wr32(priv, 0x002270, cur->addr >> 12);
 121         nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
 122         if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
 123                 nv_error(priv, "playlist %d update timeout\n", engine);
 124 }
 125
 126 static int
 127 nve0_fifo_context_attach(struct nouveau_object *parent,
 128                          struct nouveau_object *object)
 129 {
 130         struct nouveau_bar *bar = nouveau_bar(parent);
 131         struct nve0_fifo_base *base = (void *)parent->parent;
 132         struct nouveau_engctx *ectx = (void *)object;
 133         u32 addr;
 134         int ret;
 135
 136         switch (nv_engidx(object->engine)) {
 137         case NVDEV_ENGINE_SW   : return 0;
 138         case NVDEV_ENGINE_GR   :
 139         case NVDEV_ENGINE_COPY0:
 140         case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
 141         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 142         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 143         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 144         default:
 145                 return -EINVAL;
 146         }
 147
 148         if (!ectx->vma.node) {
 149                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 150                                             NV_MEM_ACCESS_RW, &ectx->vma);
 151                 if (ret)
 152                         return ret;
 153
 154                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 155         }
 156
 157         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 158         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 159         bar->flush(bar);
 160         return 0;
 161 }
 162
 163 static int
 164 nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 165                          struct nouveau_object *object)
 166 {
 167         struct nouveau_bar *bar = nouveau_bar(parent);
 168         struct nve0_fifo_priv *priv = (void *)parent->engine;
 169         struct nve0_fifo_base *base = (void *)parent->parent;
 170         struct nve0_fifo_chan *chan = (void *)parent;
 171         u32 addr;
 172
 173         switch (nv_engidx(object->engine)) {
 174         case NVDEV_ENGINE_SW   : return 0;
 175         case NVDEV_ENGINE_GR   :
 176         case NVDEV_ENGINE_COPY0:
 177         case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
 178         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 179         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 180         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 181         default:
 182                 return -EINVAL;
 183         }
 184
 185         nv_wo32(base, addr + 0x00, 0x00000000);
 186         nv_wo32(base, addr + 0x04, 0x00000000);
 187         bar->flush(bar);
 188
 189         nv_wr32(priv, 0x002634, chan->base.chid);
 190         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 191                 nv_error(priv, "channel %d kick timeout\n", chan->base.chid);
 192                 if (suspend)
 193                         return -EBUSY;
 194         }
 195
 196         return 0;
 197 }
 198
 199 static int
 200 nve0_fifo_chan_ctor(struct nouveau_object *parent,
 201                     struct nouveau_object *engine,
 202                     struct nouveau_oclass *oclass, void *data, u32 size,
 203                     struct nouveau_object **pobject)
 204 {
 205         struct nouveau_bar *bar = nouveau_bar(parent);
 206         struct nve0_fifo_priv *priv = (void *)engine;
 207         struct nve0_fifo_base *base = (void *)parent;
 208         struct nve0_fifo_chan *chan;
 209         struct nve0_channel_ind_class *args = data;
 210         u64 usermem, ioffset, ilength;
 211         int ret, i;
 212
 213         if (size < sizeof(*args))
 214                 return -EINVAL;
 215
 216         for (i = 0; i < FIFO_ENGINE_NR; i++) {
 217                 if (args->engine & (1 << i)) {
 218                         if (nouveau_engine(parent, fifo_engine[i].subdev)) {
 219                                 args->engine = (1 << i);
 220                                 break;
 221                         }
 222                 }
 223         }
 224
 225         if (i == FIFO_ENGINE_NR)
 226                 return -ENODEV;
 227
 228         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 229                                           priv->user.bar.offset, 0x200,
 230                                           args->pushbuf,
 231                                           fifo_engine[i].mask, &chan);
 232         *pobject = nv_object(chan);
 233         if (ret)
 234                 return ret;
 235
 236         nv_parent(chan)->context_attach = nve0_fifo_context_attach;
 237         nv_parent(chan)->context_detach = nve0_fifo_context_detach;
 238         chan->engine = i;
 239
 240         usermem = chan->base.chid * 0x200;
 241         ioffset = args->ioffset;
 242         ilength = log2i(args->ilength / 8);
 243
 244         for (i = 0; i < 0x200; i += 4)
 245                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 246
 247         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 248         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 249         nv_wo32(base, 0x10, 0x0000face);
 250         nv_wo32(base, 0x30, 0xfffff902);
 251         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 252         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 253         nv_wo32(base, 0x84, 0x20400000);
 254         nv_wo32(base, 0x94, 0x30000001);
 255         nv_wo32(base, 0x9c, 0x00000100);
 256         nv_wo32(base, 0xac, 0x0000001f);
 257         nv_wo32(base, 0xe8, chan->base.chid);
 258         nv_wo32(base, 0xb8, 0xf8000000);
 259         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 260         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 261         bar->flush(bar);
 262         return 0;
 263 }
 264
 265 static int
 266 nve0_fifo_chan_init(struct nouveau_object *object)
 267 {
 268         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 269         struct nve0_fifo_priv *priv = (void *)object->engine;
 270         struct nve0_fifo_chan *chan = (void *)object;
 271         u32 chid = chan->base.chid;
 272         int ret;
 273
 274         ret = nouveau_fifo_channel_init(&chan->base);
 275         if (ret)
 276                 return ret;
 277
 278         nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
 279         nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
 280         nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
 281         nve0_fifo_playlist_update(priv, chan->engine);
 282         nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
 283         return 0;
 284 }
 285
 286 static int
 287 nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 288 {
 289         struct nve0_fifo_priv *priv = (void *)object->engine;
 290         struct nve0_fifo_chan *chan = (void *)object;
 291         u32 chid = chan->base.chid;
 292
 293         nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
 294         nve0_fifo_playlist_update(priv, chan->engine);
 295         nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
 296
 297         return nouveau_fifo_channel_fini(&chan->base, suspend);
 298 }
 299
 300 static struct nouveau_ofuncs
 301 nve0_fifo_ofuncs = {
 302         .ctor = nve0_fifo_chan_ctor,
 303         .dtor = _nouveau_fifo_channel_dtor,
 304         .init = nve0_fifo_chan_init,
 305         .fini = nve0_fifo_chan_fini,
 306         .rd32 = _nouveau_fifo_channel_rd32,
 307         .wr32 = _nouveau_fifo_channel_wr32,
 308 };
 309
 310 static struct nouveau_oclass
 311 nve0_fifo_sclass[] = {
 312         { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs },
 313         {}
 314 };
 315
 316 /*******************************************************************************
 317  * FIFO context - instmem heap and vm setup
 318  ******************************************************************************/
 319
 320 static int
 321 nve0_fifo_context_ctor(struct nouveau_object *parent,
 322                     struct nouveau_object *engine,
 323                     struct nouveau_oclass *oclass, void *data, u32 size,
 324                     struct nouveau_object **pobject)
 325 {
 326         struct nve0_fifo_base *base;
 327         int ret;
 328
 329         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 330                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
 331         *pobject = nv_object(base);
 332         if (ret)
 333                 return ret;
 334
 335         ret = nouveau_gpuobj_new(parent, NULL, 0x10000, 0x1000, 0, &base->pgd);
 336         if (ret)
 337                 return ret;
 338
 339         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 340         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 341         nv_wo32(base, 0x0208, 0xffffffff);
 342         nv_wo32(base, 0x020c, 0x000000ff);
 343
 344         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 345         if (ret)
 346                 return ret;
 347
 348         return 0;
 349 }
 350
 351 static void
 352 nve0_fifo_context_dtor(struct nouveau_object *object)
 353 {
 354         struct nve0_fifo_base *base = (void *)object;
 355         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 356         nouveau_gpuobj_ref(NULL, &base->pgd);
 357         nouveau_fifo_context_destroy(&base->base);
 358 }
 359
 360 static struct nouveau_oclass
 361 nve0_fifo_cclass = {
 362         .handle = NV_ENGCTX(FIFO, 0xe0),
 363         .ofuncs = &(struct nouveau_ofuncs) {
 364                 .ctor = nve0_fifo_context_ctor,
 365                 .dtor = nve0_fifo_context_dtor,
 366                 .init = _nouveau_fifo_context_init,
 367                 .fini = _nouveau_fifo_context_fini,
 368                 .rd32 = _nouveau_fifo_context_rd32,
 369                 .wr32 = _nouveau_fifo_context_wr32,
 370         },
 371 };
 372
 373 /*******************************************************************************
 374  * PFIFO engine
 375  ******************************************************************************/
 376
 377 static const struct nouveau_enum nve0_fifo_fault_unit[] = {
 378         {}
 379 };
 380
 381 static const struct nouveau_enum nve0_fifo_fault_reason[] = {
 382         { 0x00, "PT_NOT_PRESENT" },
 383         { 0x01, "PT_TOO_SHORT" },
 384         { 0x02, "PAGE_NOT_PRESENT" },
 385         { 0x03, "VM_LIMIT_EXCEEDED" },
 386         { 0x04, "NO_CHANNEL" },
 387         { 0x05, "PAGE_SYSTEM_ONLY" },
 388         { 0x06, "PAGE_READ_ONLY" },
 389         { 0x0a, "COMPRESSED_SYSRAM" },
 390         { 0x0c, "INVALID_STORAGE_TYPE" },
 391         {}
 392 };
 393
 394 static const struct nouveau_enum nve0_fifo_fault_hubclient[] = {
 395         {}
 396 };
 397
 398 static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
 399         {}
 400 };
 401
 402 static const struct nouveau_bitfield nve0_fifo_subfifo_intr[] = {
 403         { 0x00200000, "ILLEGAL_MTHD" },
 404         { 0x00800000, "EMPTY_SUBC" },
 405         {}
 406 };
 407
 408 static void
 409 nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
 410 {
 411         u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10));
 412         u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10));
 413         u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
 414         u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
 415         u32 client = (stat & 0x00001f00) >> 8;
 416
 417         nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
 418                        "write" : "read", (u64)vahi << 32 | valo);
 419         nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
 420         printk("] from ");
 421         nouveau_enum_print(nve0_fifo_fault_unit, unit);
 422         if (stat & 0x00000040) {
 423                 printk("/");
 424                 nouveau_enum_print(nve0_fifo_fault_hubclient, client);
 425         } else {
 426                 printk("/GPC%d/", (stat & 0x1f000000) >> 24);
 427                 nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
 428         }
 429         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 430 }
 431
 432 static int
 433 nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 434 {
 435         struct nve0_fifo_chan *chan = NULL;
 436         struct nouveau_handle *bind;
 437         unsigned long flags;
 438         int ret = -EINVAL;
 439
 440         spin_lock_irqsave(&priv->base.lock, flags);
 441         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 442                 chan = (void *)priv->base.channel[chid];
 443         if (unlikely(!chan))
 444                 goto out;
 445
 446         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 447         if (likely(bind)) {
 448                 if (!mthd || !nv_call(bind->object, mthd, data))
 449                         ret = 0;
 450                 nouveau_namedb_put(bind);
 451         }
 452
 453 out:
 454         spin_unlock_irqrestore(&priv->base.lock, flags);
 455         return ret;
 456 }
 457
 458 static void
 459 nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
 460 {
 461         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 462         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 463         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 464         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
 465         u32 subc = (addr & 0x00070000) >> 16;
 466         u32 mthd = (addr & 0x00003ffc);
 467         u32 show = stat;
 468
 469         if (stat & 0x00200000) {
 470                 if (mthd == 0x0054) {
 471                         if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
 472                                 show &= ~0x00200000;
 473                 }
 474         }
 475
 476         if (stat & 0x00800000) {
 477                 if (!nve0_fifo_swmthd(priv, chid, mthd, data))
 478                         show &= ~0x00800000;
 479         }
 480
 481         if (show) {
 482                 nv_error(priv, "SUBFIFO%d:", unit);
 483                 nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
 484                 printk("\n");
 485                 nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x "
 486                                "data 0x%08x\n",
 487                          unit, chid, subc, mthd, data);
 488         }
 489
 490         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 491         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 492 }
 493
 494 static void
 495 nve0_fifo_intr(struct nouveau_subdev *subdev)
 496 {
 497         struct nve0_fifo_priv *priv = (void *)subdev;
 498         u32 mask = nv_rd32(priv, 0x002140);
 499         u32 stat = nv_rd32(priv, 0x002100) & mask;
 500
 501         if (stat & 0x00000100) {
 502                 nv_warn(priv, "unknown status 0x00000100\n");
 503                 nv_wr32(priv, 0x002100, 0x00000100);
 504                 stat &= ~0x00000100;
 505         }
 506
 507         if (stat & 0x10000000) {
 508                 u32 units = nv_rd32(priv, 0x00259c);
 509                 u32 u = units;
 510
 511                 while (u) {
 512                         int i = ffs(u) - 1;
 513                         nve0_fifo_isr_vm_fault(priv, i);
 514                         u &= ~(1 << i);
 515                 }
 516
 517                 nv_wr32(priv, 0x00259c, units);
 518                 stat &= ~0x10000000;
 519         }
 520
 521         if (stat & 0x20000000) {
 522                 u32 units = nv_rd32(priv, 0x0025a0);
 523                 u32 u = units;
 524
 525                 while (u) {
 526                         int i = ffs(u) - 1;
 527                         nve0_fifo_isr_subfifo_intr(priv, i);
 528                         u &= ~(1 << i);
 529                 }
 530
 531                 nv_wr32(priv, 0x0025a0, units);
 532                 stat &= ~0x20000000;
 533         }
 534
 535         if (stat & 0x40000000) {
 536                 nv_warn(priv, "unknown status 0x40000000\n");
 537                 nv_mask(priv, 0x002a00, 0x00000000, 0x00000000);
 538                 stat &= ~0x40000000;
 539         }
 540
 541         if (stat) {
 542                 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
 543                 nv_wr32(priv, 0x002100, stat);
 544                 nv_wr32(priv, 0x002140, 0);
 545         }
 546 }
 547
 548 static int
 549 nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 550                struct nouveau_oclass *oclass, void *data, u32 size,
 551                struct nouveau_object **pobject)
 552 {
 553         struct nve0_fifo_priv *priv;
 554         int ret;
 555
 556         ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv);
 557         *pobject = nv_object(priv);
 558         if (ret)
 559                 return ret;
 560
 561         ret = nouveau_gpuobj_new(parent, NULL, 4096 * 0x200, 0x1000,
 562                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
 563         if (ret)
 564                 return ret;
 565
 566         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 567                                 &priv->user.bar);
 568         if (ret)
 569                 return ret;
 570
 571         nv_subdev(priv)->unit = 0x00000100;
 572         nv_subdev(priv)->intr = nve0_fifo_intr;
 573         nv_engine(priv)->cclass = &nve0_fifo_cclass;
 574         nv_engine(priv)->sclass = nve0_fifo_sclass;
 575         return 0;
 576 }
 577
 578 static void
 579 nve0_fifo_dtor(struct nouveau_object *object)
 580 {
 581         struct nve0_fifo_priv *priv = (void *)object;
 582         int i;
 583
 584         nouveau_gpuobj_unmap(&priv->user.bar);
 585         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 586
 587         for (i = 0; i < ARRAY_SIZE(priv->engine); i++) {
 588                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
 589                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
 590         }
 591
 592         nouveau_fifo_destroy(&priv->base);
 593 }
 594
 595 static int
 596 nve0_fifo_init(struct nouveau_object *object)
 597 {
 598         struct nve0_fifo_priv *priv = (void *)object;
 599         int ret, i;
 600
 601         ret = nouveau_fifo_init(&priv->base);
 602         if (ret)
 603                 return ret;
 604
 605         /* enable all available PSUBFIFOs */
 606         nv_wr32(priv, 0x000204, 0xffffffff);
 607         priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
 608         nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
 609
 610         /* PSUBFIFO[n] */
 611         for (i = 0; i < priv->spoon_nr; i++) {
 612                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 613                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 614                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 615         }
 616
 617         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 618
 619         nv_wr32(priv, 0x002a00, 0xffffffff);
 620         nv_wr32(priv, 0x002100, 0xffffffff);
 621         nv_wr32(priv, 0x002140, 0xbfffffff);
 622         return 0;
 623 }
 624
 625 struct nouveau_oclass
 626 nve0_fifo_oclass = {
 627         .handle = NV_ENGINE(FIFO, 0xe0),
 628         .ofuncs = &(struct nouveau_ofuncs) {
 629                 .ctor = nve0_fifo_ctor,
 630                 .dtor = nve0_fifo_dtor,
 631                 .init = nve0_fifo_init,
 632                 .fini = _nouveau_fifo_fini,
 633         },
 634 };