drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/class.h>
  31 #include <core/math.h>
  32 #include <core/enum.h>
  33
  34 #include <subdev/timer.h>
  35 #include <subdev/bar.h>
  36 #include <subdev/vm.h>
  37
  38 #include <engine/dmaobj.h>
  39 #include <engine/fifo.h>
  40
  41 #define _(a,b) { (a), ((1 << (a)) | (b)) }
  42 static const struct {
  43         int subdev;
  44         u32 mask;
  45 } fifo_engine[] = {
  46         _(NVDEV_ENGINE_GR      , (1 << NVDEV_ENGINE_SW)),
  47         _(NVDEV_ENGINE_VP      , 0),
  48         _(NVDEV_ENGINE_PPP     , 0),
  49         _(NVDEV_ENGINE_BSP     , 0),
  50         _(NVDEV_ENGINE_COPY0   , 0),
  51         _(NVDEV_ENGINE_COPY1   , 0),
  52         _(NVDEV_ENGINE_VENC    , 0),
  53 };
  54 #undef _
  55 #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
  56
  57 struct nve0_fifo_engn {
  58         struct nouveau_gpuobj *playlist[2];
  59         int cur_playlist;
  60 };
  61
  62 struct nve0_fifo_priv {
  63         struct nouveau_fifo base;
  64         struct nve0_fifo_engn engine[FIFO_ENGINE_NR];
  65         struct {
  66                 struct nouveau_gpuobj *mem;
  67                 struct nouveau_vma bar;
  68         } user;
  69         int spoon_nr;
  70 };
  71
  72 struct nve0_fifo_base {
  73         struct nouveau_fifo_base base;
  74         struct nouveau_gpuobj *pgd;
  75         struct nouveau_vm *vm;
  76 };
  77
  78 struct nve0_fifo_chan {
  79         struct nouveau_fifo_chan base;
  80         u32 engine;
  81 };
  82
  83 /*******************************************************************************
  84  * FIFO channel objects
  85  ******************************************************************************/
  86
  87 static void
  88 nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
  89 {
  90         struct nouveau_bar *bar = nouveau_bar(priv);
  91         struct nve0_fifo_engn *engn = &priv->engine[engine];
  92         struct nouveau_gpuobj *cur;
  93         u32 match = (engine << 16) | 0x00000001;
  94         int i, p;
  95
  96         cur = engn->playlist[engn->cur_playlist];
  97         if (unlikely(cur == NULL)) {
  98                 int ret = nouveau_gpuobj_new(nv_object(priv)->parent, NULL,
  99                                              0x8000, 0x1000, 0, &cur);
 100                 if (ret) {
 101                         nv_error(priv, "playlist alloc failed\n");
 102                         return;
 103                 }
 104
 105                 engn->playlist[engn->cur_playlist] = cur;
 106         }
 107
 108         engn->cur_playlist = !engn->cur_playlist;
 109
 110         for (i = 0, p = 0; i < priv->base.max; i++) {
 111                 u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001;
 112                 if (ctrl != match)
 113                         continue;
 114                 nv_wo32(cur, p + 0, i);
 115                 nv_wo32(cur, p + 4, 0x00000000);
 116                 p += 8;
 117         }
 118         bar->flush(bar);
 119
 120         nv_wr32(priv, 0x002270, cur->addr >> 12);
 121         nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
 122         if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
 123                 nv_error(priv, "playlist %d update timeout\n", engine);
 124 }
 125
 126 static int
 127 nve0_fifo_context_attach(struct nouveau_object *parent,
 128                          struct nouveau_object *object)
 129 {
 130         struct nouveau_bar *bar = nouveau_bar(parent);
 131         struct nve0_fifo_base *base = (void *)parent->parent;
 132         struct nouveau_engctx *ectx = (void *)object;
 133         u32 addr;
 134         int ret;
 135
 136         switch (nv_engidx(object->engine)) {
 137         case NVDEV_ENGINE_SW   : return 0;
 138         case NVDEV_ENGINE_GR   :
 139         case NVDEV_ENGINE_COPY0:
 140         case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
 141         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 142         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 143         default:
 144                 return -EINVAL;
 145         }
 146
 147         if (!ectx->vma.node) {
 148                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 149                                             NV_MEM_ACCESS_RW, &ectx->vma);
 150                 if (ret)
 151                         return ret;
 152
 153                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 154         }
 155
 156         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 157         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 158         bar->flush(bar);
 159         return 0;
 160 }
 161
 162 static int
 163 nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 164                          struct nouveau_object *object)
 165 {
 166         struct nouveau_bar *bar = nouveau_bar(parent);
 167         struct nve0_fifo_priv *priv = (void *)parent->engine;
 168         struct nve0_fifo_base *base = (void *)parent->parent;
 169         struct nve0_fifo_chan *chan = (void *)parent;
 170         u32 addr;
 171
 172         switch (nv_engidx(object->engine)) {
 173         case NVDEV_ENGINE_SW   : return 0;
 174         case NVDEV_ENGINE_GR   :
 175         case NVDEV_ENGINE_COPY0:
 176         case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
 177         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 178         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 179         default:
 180                 return -EINVAL;
 181         }
 182
 183         nv_wo32(base, addr + 0x00, 0x00000000);
 184         nv_wo32(base, addr + 0x04, 0x00000000);
 185         bar->flush(bar);
 186
 187         nv_wr32(priv, 0x002634, chan->base.chid);
 188         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 189                 nv_error(priv, "channel %d kick timeout\n", chan->base.chid);
 190                 if (suspend)
 191                         return -EBUSY;
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int
 198 nve0_fifo_chan_ctor(struct nouveau_object *parent,
 199                     struct nouveau_object *engine,
 200                     struct nouveau_oclass *oclass, void *data, u32 size,
 201                     struct nouveau_object **pobject)
 202 {
 203         struct nouveau_bar *bar = nouveau_bar(parent);
 204         struct nve0_fifo_priv *priv = (void *)engine;
 205         struct nve0_fifo_base *base = (void *)parent;
 206         struct nve0_fifo_chan *chan;
 207         struct nve0_channel_ind_class *args = data;
 208         u64 usermem, ioffset, ilength;
 209         int ret, i;
 210
 211         if (size < sizeof(*args))
 212                 return -EINVAL;
 213
 214         for (i = 0; i < FIFO_ENGINE_NR; i++) {
 215                 if (args->engine & (1 << i)) {
 216                         if (nouveau_engine(parent, fifo_engine[i].subdev)) {
 217                                 args->engine = (1 << i);
 218                                 break;
 219                         }
 220                 }
 221         }
 222
 223         if (i == FIFO_ENGINE_NR)
 224                 return -ENODEV;
 225
 226         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 227                                           priv->user.bar.offset, 0x200,
 228                                           args->pushbuf,
 229                                           fifo_engine[i].mask, &chan);
 230         *pobject = nv_object(chan);
 231         if (ret)
 232                 return ret;
 233
 234         nv_parent(chan)->context_attach = nve0_fifo_context_attach;
 235         nv_parent(chan)->context_detach = nve0_fifo_context_detach;
 236         chan->engine = i;
 237
 238         usermem = chan->base.chid * 0x200;
 239         ioffset = args->ioffset;
 240         ilength = log2i(args->ilength / 8);
 241
 242         for (i = 0; i < 0x200; i += 4)
 243                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 244
 245         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 246         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 247         nv_wo32(base, 0x10, 0x0000face);
 248         nv_wo32(base, 0x30, 0xfffff902);
 249         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 250         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 251         nv_wo32(base, 0x84, 0x20400000);
 252         nv_wo32(base, 0x94, 0x30000001);
 253         nv_wo32(base, 0x9c, 0x00000100);
 254         nv_wo32(base, 0xac, 0x0000001f);
 255         nv_wo32(base, 0xe8, chan->base.chid);
 256         nv_wo32(base, 0xb8, 0xf8000000);
 257         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 258         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 259         bar->flush(bar);
 260         return 0;
 261 }
 262
 263 static int
 264 nve0_fifo_chan_init(struct nouveau_object *object)
 265 {
 266         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 267         struct nve0_fifo_priv *priv = (void *)object->engine;
 268         struct nve0_fifo_chan *chan = (void *)object;
 269         u32 chid = chan->base.chid;
 270         int ret;
 271
 272         ret = nouveau_fifo_channel_init(&chan->base);
 273         if (ret)
 274                 return ret;
 275
 276         nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
 277         nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
 278         nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
 279         nve0_fifo_playlist_update(priv, chan->engine);
 280         nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
 281         return 0;
 282 }
 283
 284 static int
 285 nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 286 {
 287         struct nve0_fifo_priv *priv = (void *)object->engine;
 288         struct nve0_fifo_chan *chan = (void *)object;
 289         u32 chid = chan->base.chid;
 290
 291         nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
 292         nve0_fifo_playlist_update(priv, chan->engine);
 293         nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
 294
 295         return nouveau_fifo_channel_fini(&chan->base, suspend);
 296 }
 297
 298 static struct nouveau_ofuncs
 299 nve0_fifo_ofuncs = {
 300         .ctor = nve0_fifo_chan_ctor,
 301         .dtor = _nouveau_fifo_channel_dtor,
 302         .init = nve0_fifo_chan_init,
 303         .fini = nve0_fifo_chan_fini,
 304         .rd32 = _nouveau_fifo_channel_rd32,
 305         .wr32 = _nouveau_fifo_channel_wr32,
 306 };
 307
 308 static struct nouveau_oclass
 309 nve0_fifo_sclass[] = {
 310         { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs },
 311         {}
 312 };
 313
 314 /*******************************************************************************
 315  * FIFO context - instmem heap and vm setup
 316  ******************************************************************************/
 317
 318 static int
 319 nve0_fifo_context_ctor(struct nouveau_object *parent,
 320                     struct nouveau_object *engine,
 321                     struct nouveau_oclass *oclass, void *data, u32 size,
 322                     struct nouveau_object **pobject)
 323 {
 324         struct nve0_fifo_base *base;
 325         int ret;
 326
 327         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 328                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
 329         *pobject = nv_object(base);
 330         if (ret)
 331                 return ret;
 332
 333         ret = nouveau_gpuobj_new(parent, NULL, 0x10000, 0x1000, 0, &base->pgd);
 334         if (ret)
 335                 return ret;
 336
 337         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 338         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 339         nv_wo32(base, 0x0208, 0xffffffff);
 340         nv_wo32(base, 0x020c, 0x000000ff);
 341
 342         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 343         if (ret)
 344                 return ret;
 345
 346         return 0;
 347 }
 348
 349 static void
 350 nve0_fifo_context_dtor(struct nouveau_object *object)
 351 {
 352         struct nve0_fifo_base *base = (void *)object;
 353         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 354         nouveau_gpuobj_ref(NULL, &base->pgd);
 355         nouveau_fifo_context_destroy(&base->base);
 356 }
 357
 358 static struct nouveau_oclass
 359 nve0_fifo_cclass = {
 360         .handle = NV_ENGCTX(FIFO, 0xe0),
 361         .ofuncs = &(struct nouveau_ofuncs) {
 362                 .ctor = nve0_fifo_context_ctor,
 363                 .dtor = nve0_fifo_context_dtor,
 364                 .init = _nouveau_fifo_context_init,
 365                 .fini = _nouveau_fifo_context_fini,
 366                 .rd32 = _nouveau_fifo_context_rd32,
 367                 .wr32 = _nouveau_fifo_context_wr32,
 368         },
 369 };
 370
 371 /*******************************************************************************
 372  * PFIFO engine
 373  ******************************************************************************/
 374
 375 static const struct nouveau_enum nve0_fifo_fault_unit[] = {
 376         {}
 377 };
 378
 379 static const struct nouveau_enum nve0_fifo_fault_reason[] = {
 380         { 0x00, "PT_NOT_PRESENT" },
 381         { 0x01, "PT_TOO_SHORT" },
 382         { 0x02, "PAGE_NOT_PRESENT" },
 383         { 0x03, "VM_LIMIT_EXCEEDED" },
 384         { 0x04, "NO_CHANNEL" },
 385         { 0x05, "PAGE_SYSTEM_ONLY" },
 386         { 0x06, "PAGE_READ_ONLY" },
 387         { 0x0a, "COMPRESSED_SYSRAM" },
 388         { 0x0c, "INVALID_STORAGE_TYPE" },
 389         {}
 390 };
 391
 392 static const struct nouveau_enum nve0_fifo_fault_hubclient[] = {
 393         {}
 394 };
 395
 396 static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
 397         {}
 398 };
 399
 400 static const struct nouveau_bitfield nve0_fifo_subfifo_intr[] = {
 401         { 0x00200000, "ILLEGAL_MTHD" },
 402         { 0x00800000, "EMPTY_SUBC" },
 403         {}
 404 };
 405
 406 static void
 407 nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
 408 {
 409         u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10));
 410         u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10));
 411         u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
 412         u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
 413         u32 client = (stat & 0x00001f00) >> 8;
 414
 415         nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
 416                        "write" : "read", (u64)vahi << 32 | valo);
 417         nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
 418         printk("] from ");
 419         nouveau_enum_print(nve0_fifo_fault_unit, unit);
 420         if (stat & 0x00000040) {
 421                 printk("/");
 422                 nouveau_enum_print(nve0_fifo_fault_hubclient, client);
 423         } else {
 424                 printk("/GPC%d/", (stat & 0x1f000000) >> 24);
 425                 nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
 426         }
 427         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 428 }
 429
 430 static int
 431 nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 432 {
 433         struct nve0_fifo_chan *chan = NULL;
 434         struct nouveau_handle *bind;
 435         unsigned long flags;
 436         int ret = -EINVAL;
 437
 438         spin_lock_irqsave(&priv->base.lock, flags);
 439         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 440                 chan = (void *)priv->base.channel[chid];
 441         if (unlikely(!chan))
 442                 goto out;
 443
 444         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 445         if (likely(bind)) {
 446                 if (!mthd || !nv_call(bind->object, mthd, data))
 447                         ret = 0;
 448                 nouveau_namedb_put(bind);
 449         }
 450
 451 out:
 452         spin_unlock_irqrestore(&priv->base.lock, flags);
 453         return ret;
 454 }
 455
 456 static void
 457 nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
 458 {
 459         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 460         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 461         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 462         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
 463         u32 subc = (addr & 0x00070000) >> 16;
 464         u32 mthd = (addr & 0x00003ffc);
 465         u32 show = stat;
 466
 467         if (stat & 0x00200000) {
 468                 if (mthd == 0x0054) {
 469                         if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
 470                                 show &= ~0x00200000;
 471                 }
 472         }
 473
 474         if (stat & 0x00800000) {
 475                 if (!nve0_fifo_swmthd(priv, chid, mthd, data))
 476                         show &= ~0x00800000;
 477         }
 478
 479         if (show) {
 480                 nv_error(priv, "SUBFIFO%d:", unit);
 481                 nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
 482                 printk("\n");
 483                 nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x "
 484                                "data 0x%08x\n",
 485                          unit, chid, subc, mthd, data);
 486         }
 487
 488         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 489         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 490 }
 491
 492 static void
 493 nve0_fifo_intr(struct nouveau_subdev *subdev)
 494 {
 495         struct nve0_fifo_priv *priv = (void *)subdev;
 496         u32 mask = nv_rd32(priv, 0x002140);
 497         u32 stat = nv_rd32(priv, 0x002100) & mask;
 498
 499         if (stat & 0x00000100) {
 500                 nv_warn(priv, "unknown status 0x00000100\n");
 501                 nv_wr32(priv, 0x002100, 0x00000100);
 502                 stat &= ~0x00000100;
 503         }
 504
 505         if (stat & 0x10000000) {
 506                 u32 units = nv_rd32(priv, 0x00259c);
 507                 u32 u = units;
 508
 509                 while (u) {
 510                         int i = ffs(u) - 1;
 511                         nve0_fifo_isr_vm_fault(priv, i);
 512                         u &= ~(1 << i);
 513                 }
 514
 515                 nv_wr32(priv, 0x00259c, units);
 516                 stat &= ~0x10000000;
 517         }
 518
 519         if (stat & 0x20000000) {
 520                 u32 units = nv_rd32(priv, 0x0025a0);
 521                 u32 u = units;
 522
 523                 while (u) {
 524                         int i = ffs(u) - 1;
 525                         nve0_fifo_isr_subfifo_intr(priv, i);
 526                         u &= ~(1 << i);
 527                 }
 528
 529                 nv_wr32(priv, 0x0025a0, units);
 530                 stat &= ~0x20000000;
 531         }
 532
 533         if (stat & 0x40000000) {
 534                 nv_warn(priv, "unknown status 0x40000000\n");
 535                 nv_mask(priv, 0x002a00, 0x00000000, 0x00000000);
 536                 stat &= ~0x40000000;
 537         }
 538
 539         if (stat) {
 540                 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
 541                 nv_wr32(priv, 0x002100, stat);
 542                 nv_wr32(priv, 0x002140, 0);
 543         }
 544 }
 545
 546 static int
 547 nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 548                struct nouveau_oclass *oclass, void *data, u32 size,
 549                struct nouveau_object **pobject)
 550 {
 551         struct nve0_fifo_priv *priv;
 552         int ret;
 553
 554         ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv);
 555         *pobject = nv_object(priv);
 556         if (ret)
 557                 return ret;
 558
 559         ret = nouveau_gpuobj_new(parent, NULL, 4096 * 0x200, 0x1000,
 560                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
 561         if (ret)
 562                 return ret;
 563
 564         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 565                                 &priv->user.bar);
 566         if (ret)
 567                 return ret;
 568
 569         nv_subdev(priv)->unit = 0x00000100;
 570         nv_subdev(priv)->intr = nve0_fifo_intr;
 571         nv_engine(priv)->cclass = &nve0_fifo_cclass;
 572         nv_engine(priv)->sclass = nve0_fifo_sclass;
 573         return 0;
 574 }
 575
 576 static void
 577 nve0_fifo_dtor(struct nouveau_object *object)
 578 {
 579         struct nve0_fifo_priv *priv = (void *)object;
 580         int i;
 581
 582         nouveau_gpuobj_unmap(&priv->user.bar);
 583         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 584
 585         for (i = 0; i < ARRAY_SIZE(priv->engine); i++) {
 586                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
 587                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
 588         }
 589
 590         nouveau_fifo_destroy(&priv->base);
 591 }
 592
 593 static int
 594 nve0_fifo_init(struct nouveau_object *object)
 595 {
 596         struct nve0_fifo_priv *priv = (void *)object;
 597         int ret, i;
 598
 599         ret = nouveau_fifo_init(&priv->base);
 600         if (ret)
 601                 return ret;
 602
 603         /* enable all available PSUBFIFOs */
 604         nv_wr32(priv, 0x000204, 0xffffffff);
 605         priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
 606         nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
 607
 608         /* PSUBFIFO[n] */
 609         for (i = 0; i < priv->spoon_nr; i++) {
 610                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 611                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 612                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 613         }
 614
 615         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 616
 617         nv_wr32(priv, 0x002a00, 0xffffffff);
 618         nv_wr32(priv, 0x002100, 0xffffffff);
 619         nv_wr32(priv, 0x002140, 0xbfffffff);
 620         return 0;
 621 }
 622
 623 struct nouveau_oclass
 624 nve0_fifo_oclass = {
 625         .handle = NV_ENGINE(FIFO, 0xe0),
 626         .ofuncs = &(struct nouveau_ofuncs) {
 627                 .ctor = nve0_fifo_ctor,
 628                 .dtor = nve0_fifo_dtor,
 629                 .init = nve0_fifo_init,
 630                 .fini = _nouveau_fifo_fini,
 631         },
 632 };