1 /* fuc microcode for nvc0 PGRAPH/GPC
3 * Copyright 2011 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
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9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
27 * m4 gpcnvc0.fuc | envyas -a -w -m fuc -V fuc3 -o gpcnvc0.fuc.h
31 * - bracket certain functions with scratch writes, useful for debugging
32 * - watchdog timer around ctx operations
35 .section #nvc0_grgpc_data
38 gpc_mmio_list_head: .b32 0
39 gpc_mmio_list_tail: .b32 0
43 tpc_mmio_list_head: .b32 0
44 tpc_mmio_list_tail: .b32 0
48 // chipset descriptions
51 .b16 #nvc0_gpc_mmio_head
52 .b16 #nvc0_gpc_mmio_tail
53 .b16 #nvc0_tpc_mmio_head
54 .b16 #nvc0_tpc_mmio_tail
56 .b16 #nvc0_gpc_mmio_head
57 .b16 #nvc1_gpc_mmio_tail
58 .b16 #nvc0_tpc_mmio_head
59 .b16 #nvc1_tpc_mmio_tail
61 .b16 #nvc0_gpc_mmio_head
62 .b16 #nvc0_gpc_mmio_tail
63 .b16 #nvc0_tpc_mmio_head
64 .b16 #nvc3_tpc_mmio_tail
66 .b16 #nvc0_gpc_mmio_head
67 .b16 #nvc0_gpc_mmio_tail
68 .b16 #nvc0_tpc_mmio_head
69 .b16 #nvc3_tpc_mmio_tail
71 .b16 #nvc0_gpc_mmio_head
72 .b16 #nvc0_gpc_mmio_tail
73 .b16 #nvc0_tpc_mmio_head
74 .b16 #nvc0_tpc_mmio_tail
76 .b16 #nvc0_gpc_mmio_head
77 .b16 #nvc0_gpc_mmio_tail
78 .b16 #nvc0_tpc_mmio_head
79 .b16 #nvc3_tpc_mmio_tail
81 .b16 #nvc0_gpc_mmio_head
82 .b16 #nvc0_gpc_mmio_tail
83 .b16 #nvc0_tpc_mmio_head
84 .b16 #nvcf_tpc_mmio_tail
86 .b16 #nvd9_gpc_mmio_head
87 .b16 #nvd9_gpc_mmio_tail
88 .b16 #nvd9_tpc_mmio_head
89 .b16 #nvd9_tpc_mmio_tail
91 .b16 #nvd9_gpc_mmio_head
92 .b16 #nvd9_gpc_mmio_tail
93 .b16 #nvd9_tpc_mmio_head
94 .b16 #nvd9_tpc_mmio_tail
99 mmctx_data(0x000380, 1)
100 mmctx_data(0x000400, 6)
101 mmctx_data(0x000450, 9)
102 mmctx_data(0x000600, 1)
103 mmctx_data(0x000684, 1)
104 mmctx_data(0x000700, 5)
105 mmctx_data(0x000800, 1)
106 mmctx_data(0x000808, 3)
107 mmctx_data(0x000828, 1)
108 mmctx_data(0x000830, 1)
109 mmctx_data(0x0008d8, 1)
110 mmctx_data(0x0008e0, 1)
111 mmctx_data(0x0008e8, 6)
112 mmctx_data(0x00091c, 1)
113 mmctx_data(0x000924, 3)
114 mmctx_data(0x000b00, 1)
115 mmctx_data(0x000b08, 6)
116 mmctx_data(0x000bb8, 1)
117 mmctx_data(0x000c08, 1)
118 mmctx_data(0x000c10, 8)
119 mmctx_data(0x000c80, 1)
120 mmctx_data(0x000c8c, 1)
121 mmctx_data(0x001000, 3)
122 mmctx_data(0x001014, 1)
124 mmctx_data(0x000c6c, 1);
128 mmctx_data(0x000380, 1)
129 mmctx_data(0x000400, 2)
130 mmctx_data(0x00040c, 3)
131 mmctx_data(0x000450, 9)
132 mmctx_data(0x000600, 1)
133 mmctx_data(0x000684, 1)
134 mmctx_data(0x000700, 5)
135 mmctx_data(0x000800, 1)
136 mmctx_data(0x000808, 3)
137 mmctx_data(0x000828, 1)
138 mmctx_data(0x000830, 1)
139 mmctx_data(0x0008d8, 1)
140 mmctx_data(0x0008e0, 1)
141 mmctx_data(0x0008e8, 6)
142 mmctx_data(0x00091c, 1)
143 mmctx_data(0x000924, 3)
144 mmctx_data(0x000b00, 1)
145 mmctx_data(0x000b08, 6)
146 mmctx_data(0x000bb8, 1)
147 mmctx_data(0x000c08, 1)
148 mmctx_data(0x000c10, 8)
149 mmctx_data(0x000c6c, 1)
150 mmctx_data(0x000c80, 1)
151 mmctx_data(0x000c8c, 1)
152 mmctx_data(0x001000, 3)
153 mmctx_data(0x001014, 1)
158 mmctx_data(0x000018, 1)
159 mmctx_data(0x00003c, 1)
160 mmctx_data(0x000048, 1)
161 mmctx_data(0x000064, 1)
162 mmctx_data(0x000088, 1)
163 mmctx_data(0x000200, 6)
164 mmctx_data(0x00021c, 2)
165 mmctx_data(0x000300, 6)
166 mmctx_data(0x0003d0, 1)
167 mmctx_data(0x0003e0, 2)
168 mmctx_data(0x000400, 3)
169 mmctx_data(0x000420, 1)
170 mmctx_data(0x0004b0, 1)
171 mmctx_data(0x0004e8, 1)
172 mmctx_data(0x0004f4, 1)
173 mmctx_data(0x000520, 2)
174 mmctx_data(0x000604, 4)
175 mmctx_data(0x000644, 20)
176 mmctx_data(0x000698, 1)
177 mmctx_data(0x000750, 2)
179 mmctx_data(0x000758, 1)
180 mmctx_data(0x0002c4, 1)
181 mmctx_data(0x0006e0, 1)
183 mmctx_data(0x0004bc, 1)
185 mmctx_data(0x000544, 1)
189 mmctx_data(0x000018, 1)
190 mmctx_data(0x00003c, 1)
191 mmctx_data(0x000048, 1)
192 mmctx_data(0x000064, 1)
193 mmctx_data(0x000088, 1)
194 mmctx_data(0x000200, 6)
195 mmctx_data(0x00021c, 2)
196 mmctx_data(0x0002c4, 1)
197 mmctx_data(0x000300, 6)
198 mmctx_data(0x0003d0, 1)
199 mmctx_data(0x0003e0, 2)
200 mmctx_data(0x000400, 3)
201 mmctx_data(0x000420, 3)
202 mmctx_data(0x0004b0, 1)
203 mmctx_data(0x0004e8, 1)
204 mmctx_data(0x0004f4, 1)
205 mmctx_data(0x000520, 2)
206 mmctx_data(0x000544, 1)
207 mmctx_data(0x000604, 4)
208 mmctx_data(0x000644, 20)
209 mmctx_data(0x000698, 1)
210 mmctx_data(0x0006e0, 1)
211 mmctx_data(0x000730, 11)
214 .section #nvc0_grgpc_code
216 define(`include_code')
219 // reports an exception to the host
221 // In: $r15 error code (see nvc0.fuc)
225 mov $r14 -0x67ec // 0x9814
227 call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
230 call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET
234 // GPC fuc initialisation, executed by triggering ucode start, will
235 // fall through to main loop after completion.
238 // CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
239 // CC_SCRATCH[1]: context base
243 // 31:31: set to signal completion
245 // 31:0: GPC context size
251 // enable fifo access
254 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
256 // setup i0 handler, and route all interrupts to it
260 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
262 // enable fifo interrupt
264 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
269 // figure out which GPC we are, and how many TPCs we have
272 iord $r2 I[$r1 + 0x000] // UNITS
277 st b32 D[$r0 + #tpc_count] $r2
278 st b32 D[$r0 + #tpc_mask] $r3
280 iord $r2 I[$r1 + 0x000] // MYINDEX
281 st b32 D[$r0 + #gpc_id] $r2
283 // find context data for this chipset
286 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
287 mov $r1 #chipsets - 12
290 ld b32 $r3 D[$r1 + 0x00]
294 bra ne #init_find_chipset
298 // initialise context base, and size tracking
302 iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
303 clear b32 $r3 // track GPC context size here
305 // set mmctx base addresses now so we don't have to do it later,
306 // they don't currently ever change
310 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
311 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
313 // calculate GPC mmio context size, store the chipset-specific
314 // mmio list pointers somewhere we can get at them later without
315 // re-parsing the chipset list
318 ld b16 $r14 D[$r1 + 4]
319 ld b16 $r15 D[$r1 + 6]
320 st b16 D[$r0 + #gpc_mmio_list_head] $r14
321 st b16 D[$r0 + #gpc_mmio_list_tail] $r15
326 // calculate per-TPC mmio context size, store the list pointers
327 ld b16 $r14 D[$r1 + 8]
328 ld b16 $r15 D[$r1 + 10]
329 st b16 D[$r0 + #tpc_mmio_list_head] $r14
330 st b16 D[$r0 + #tpc_mmio_list_tail] $r15
332 ld b32 $r14 D[$r0 + #tpc_count]
337 // round up base/size to 256 byte boundary (for strand SWBASE)
340 iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
348 // calculate size of strand context data
350 call #strand_ctx_init
353 // save context size, and tell HUB we're done
356 iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
360 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
362 // Main program loop, very simple, sleeps until woken up by the interrupt
363 // handler, pulls a command from the queue and executes its handler
372 // 0x0000-0x0003 are all context transfers
374 bra nc #main_not_ctx_xfer
375 // fetch $flags and mask off $p1/$p2
380 // set $p1/$p2 according to transfer type
384 // transfer context data
390 or $r15 E_BAD_COMMAND
406 // incoming fifo command?
407 iord $r10 I[$r0 + 0x200] // INTR
408 and $r11 $r10 0x00000004
410 // queue incoming fifo command for later processing
413 iord $r14 I[$r11 + 0x100] // FIFO_CMD
414 iord $r15 I[$r11 + 0x000] // FIFO_DATA
418 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
420 // ack, and wake up main()
422 iowr I[$r0 + 0x100] $r10 // INTR_ACK
436 // Set this GPC's bit in HUB_BAR, used to signal completion of various
437 // activities to the HUB fuc
441 ld b32 $r14 D[$r0 + #gpc_id]
443 mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
448 // Disables various things, waits a bit, and re-enables them..
450 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
451 // good description for the bits we turn off? Anyways, without this,
452 // funny things happen.
458 iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
462 bra ne #ctx_redswitch_delay
464 iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
467 // Transfer GPC context data between GPU and storage area
469 // In: $r15 context base address
470 // $p1 clear on save, set on load
471 // $p2 set if opposite direction done/will be done, so:
472 // on save it means: "a load will follow this save"
473 // on load it means: "a save preceeded this load"
476 // set context base address
479 iowr I[$r1 + 0x000] $r15// MEM_BASE
480 bra not $p1 #ctx_xfer_not_load
488 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
492 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
495 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
498 xbit $r10 $flags $p1 // direction
502 ld b32 $r12 D[$r0 + #gpc_id]
504 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
505 ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
506 ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
507 mov $r14 0 // not multi
510 // per-TPC mmio context
511 xbit $r10 $flags $p1 // direction
514 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
515 ld b32 $r12 D[$r0 + #gpc_id]
517 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
518 ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
519 ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
520 ld b32 $r15 D[$r0 + #tpc_mask]
521 mov $r14 0x800 // stride = 0x800
524 // wait for strands to finish
527 // if load, or a save without a load following, do some
528 // unknown stuff that's done after finishing a block of
530 bra $p1 #ctx_xfer_post
531 bra not $p2 #ctx_xfer_done
536 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
539 // mark completion in HUB's barrier
541 call #hub_barrier_done