1 /* fuc microcode for nvc0 PGRAPH/HUB
3 * Copyright 2011 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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27 * m4 hubnvc0.fuc | envyas -a -w -m fuc -V fuc3 -o hubnvc0.fuc.h
30 .section #nvc0_grhub_data
35 hub_mmio_list_head: .b32 0
36 hub_mmio_list_tail: .b32 0
42 .b16 #nvc0_hub_mmio_head
43 .b16 #nvc0_hub_mmio_tail
45 .b16 #nvc0_hub_mmio_head
46 .b16 #nvc1_hub_mmio_tail
48 .b16 #nvc0_hub_mmio_head
49 .b16 #nvc0_hub_mmio_tail
51 .b16 #nvc0_hub_mmio_head
52 .b16 #nvc0_hub_mmio_tail
54 .b16 #nvc0_hub_mmio_head
55 .b16 #nvc0_hub_mmio_tail
57 .b16 #nvc0_hub_mmio_head
58 .b16 #nvc0_hub_mmio_tail
60 .b16 #nvc0_hub_mmio_head
61 .b16 #nvc0_hub_mmio_tail
63 .b16 #nvd9_hub_mmio_head
64 .b16 #nvd9_hub_mmio_tail
66 .b16 #nvd9_hub_mmio_head
67 .b16 #nvd9_hub_mmio_tail
71 mmctx_data(0x17e91c, 2)
72 mmctx_data(0x400204, 2)
73 mmctx_data(0x404004, 11)
74 mmctx_data(0x404044, 1)
75 mmctx_data(0x404094, 14)
76 mmctx_data(0x4040d0, 7)
77 mmctx_data(0x4040f8, 1)
78 mmctx_data(0x404130, 3)
79 mmctx_data(0x404150, 3)
80 mmctx_data(0x404164, 2)
81 mmctx_data(0x404174, 3)
82 mmctx_data(0x404200, 8)
83 mmctx_data(0x404404, 14)
84 mmctx_data(0x404460, 4)
85 mmctx_data(0x404480, 1)
86 mmctx_data(0x404498, 1)
87 mmctx_data(0x404604, 4)
88 mmctx_data(0x404618, 32)
89 mmctx_data(0x404698, 21)
90 mmctx_data(0x4046f0, 2)
91 mmctx_data(0x404700, 22)
92 mmctx_data(0x405800, 1)
93 mmctx_data(0x405830, 3)
94 mmctx_data(0x405854, 1)
95 mmctx_data(0x405870, 4)
96 mmctx_data(0x405a00, 2)
97 mmctx_data(0x405a18, 1)
98 mmctx_data(0x406020, 1)
99 mmctx_data(0x406028, 4)
100 mmctx_data(0x4064a8, 2)
101 mmctx_data(0x4064b4, 2)
102 mmctx_data(0x407804, 1)
103 mmctx_data(0x40780c, 6)
104 mmctx_data(0x4078bc, 1)
105 mmctx_data(0x408000, 7)
106 mmctx_data(0x408064, 1)
107 mmctx_data(0x408800, 3)
108 mmctx_data(0x408900, 4)
109 mmctx_data(0x408980, 1)
111 mmctx_data(0x4064c0, 2)
115 mmctx_data(0x17e91c, 2)
116 mmctx_data(0x400204, 2)
117 mmctx_data(0x404004, 10)
118 mmctx_data(0x404044, 1)
119 mmctx_data(0x404094, 14)
120 mmctx_data(0x4040d0, 7)
121 mmctx_data(0x4040f8, 1)
122 mmctx_data(0x404130, 3)
123 mmctx_data(0x404150, 3)
124 mmctx_data(0x404164, 2)
125 mmctx_data(0x404178, 2)
126 mmctx_data(0x404200, 8)
127 mmctx_data(0x404404, 14)
128 mmctx_data(0x404460, 4)
129 mmctx_data(0x404480, 1)
130 mmctx_data(0x404498, 1)
131 mmctx_data(0x404604, 4)
132 mmctx_data(0x404618, 32)
133 mmctx_data(0x404698, 21)
134 mmctx_data(0x4046f0, 2)
135 mmctx_data(0x404700, 22)
136 mmctx_data(0x405800, 1)
137 mmctx_data(0x405830, 3)
138 mmctx_data(0x405854, 1)
139 mmctx_data(0x405870, 4)
140 mmctx_data(0x405a00, 2)
141 mmctx_data(0x405a18, 1)
142 mmctx_data(0x406020, 1)
143 mmctx_data(0x406028, 4)
144 mmctx_data(0x4064a8, 2)
145 mmctx_data(0x4064b4, 5)
146 mmctx_data(0x407804, 1)
147 mmctx_data(0x40780c, 6)
148 mmctx_data(0x4078bc, 1)
149 mmctx_data(0x408000, 7)
150 mmctx_data(0x408064, 1)
151 mmctx_data(0x408800, 3)
152 mmctx_data(0x408900, 3)
153 mmctx_data(0x408980, 1)
158 chan_mmio_count: .b32 0
159 chan_mmio_address: .b32 0
164 .section #nvc0_grhub_code
166 define(`include_code')
169 // reports an exception to the host
171 // In: $r15 error code (see nvc0.fuc)
177 iowr I[$r14 + 0x000] $r15 // CC_SCRATCH[5] = error code
181 iowr I[$r14 + 0x000] $r15 // INTR_UP_SET
185 // HUB fuc initialisation, executed by triggering ucode start, will
186 // fall through to main loop after completion.
189 // CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
193 // 31:31: set to signal completion
195 // 31:0: total PGRAPH context size
202 // enable fifo access
205 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
207 // setup i0 handler, and route all interrupts to it
211 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
213 // route HUB_CHANNEL_SWITCH to fuc interrupt 8
216 mov $r2 0x2003 // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8
217 iowr I[$r3 + 0x000] $r2
219 // not sure what these are, route them because NVIDIA does, and
220 // the IRQ handler will signal the host if we ever get one.. we
221 // may find out if/why we need to handle these if so..
224 iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9
226 iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10
228 iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15
230 // enable all INTR_UP interrupts
236 // enable fifo, ctxsw, 9, 10, 15 interrupts
237 mov $r2 -0x78fc // 0x8704
239 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
241 // fifo level triggered, rest edge
249 // fetch enabled GPC/ROP counts
250 mov $r14 -0x69fc // 0x409604
254 st b32 D[$r0 + #rop_count] $r1
256 st b32 D[$r0 + #gpc_count] $r15
258 // set BAR_REQMASK to GPC mask
264 iowr I[$r2 + 0x000] $r1
265 iowr I[$r2 + 0x100] $r1
267 // find context data for this chipset
270 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
271 mov $r15 #chipsets - 8
274 ld b32 $r3 D[$r15 + 0x00]
278 bra ne #init_find_chipset
282 // context size calculation, reserve first 256 bytes for use by fuc
286 // calculate size of mmio context data
287 ld b16 $r14 D[$r15 + 4]
288 ld b16 $r15 D[$r15 + 6]
290 st b32 D[$r0 + #hub_mmio_list_head] $r14
291 st b32 D[$r0 + #hub_mmio_list_tail] $r15
294 // set mmctx base addresses now so we don't have to do it later,
295 // they don't (currently) ever change
299 iowr I[$r3 + 0x000] $r4 // MMCTX_SAVE_SWBASE
300 iowr I[$r3 + 0x100] $r4 // MMCTX_LOAD_SWBASE
304 iowr I[$r3 + 0x000] $r15 // MMCTX_LOAD_COUNT, wtf for?!?
306 // strands, base offset needs to be aligned to 256 bytes
311 call #strand_ctx_init
314 // initialise each GPC in sequence by passing in the offset of its
315 // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
316 // has previously been uploaded by the host) running.
318 // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
319 // when it has completed, and return the size of its context data
320 // in GPCn_CC_SCRATCH[1]
322 ld b32 $r3 D[$r0 + #gpc_count]
326 // setup, and start GPC ucode running
327 add b32 $r14 $r4 0x804
329 call #nv_wr32 // CC_SCRATCH[1] = ctx offset
330 add b32 $r14 $r4 0x800
332 call #nv_wr32 // CC_SCRATCH[0] = chipset
333 add b32 $r14 $r4 0x10c
336 add b32 $r14 $r4 0x104
337 call #nv_wr32 // ENTRY
338 add b32 $r14 $r4 0x100
339 mov $r15 2 // CTRL_START_TRIGGER
340 call #nv_wr32 // CTRL
342 // wait for it to complete, and adjust context size
343 add b32 $r14 $r4 0x800
348 add b32 $r14 $r4 0x804
357 // save context size, and tell host we're ready
360 iowr I[$r2 + 0x100] $r1 // CC_SCRATCH[1] = context size
364 iowr I[$r2 + 0x000] $r1 // CC_SCRATCH[0] |= 0x80000000
366 // Main program loop, very simple, sleeps until woken up by the interrupt
367 // handler, pulls a command from the queue and executes its handler
370 // sleep until we have something to do
377 // context switch, requested by GPU?
379 bra ne #main_not_ctx_switch
383 iord $r2 I[$r1 + 0x100] // CHAN_NEXT
384 iord $r1 I[$r1 + 0x000] // CHAN_CUR
389 bra e #chsw_prev_no_next
421 // ack the context switch request
426 iowr I[$r1 + 0x000] $r2 // 0x409b0c
430 // request to set current channel? (*not* a context switch)
433 bra ne #main_not_ctx_chan
438 // request to store current channel context?
441 bra ne #main_not_ctx_save
451 or $r15 E_BAD_COMMAND
460 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
475 // incoming fifo command?
476 iord $r10 I[$r0 + 0x200] // INTR
477 and $r11 $r10 0x00000004
479 // queue incoming fifo command for later processing
482 iord $r14 I[$r11 + 0x100] // FIFO_CMD
483 iord $r15 I[$r11 + 0x000] // FIFO_DATA
487 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
489 // context switch request?
491 and $r11 $r10 0x00000100
493 // enqueue a context switch for later processing
498 // anything we didn't handle, bring it to the host's attention
506 iowr I[$r10] $r11 // INTR_UP_SET
508 // ack, and wake up main()
510 iowr I[$r0 + 0x100] $r10 // INTR_ACK
524 // Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
533 bra e #ctx_4160s_wait
536 // Without clearing again at end of xfer, some things cause PGRAPH
537 // to hang with STATUS=0x00000007 until it's cleared.. fbcon can
538 // still function with it set however...
546 // Again, not real sure
548 // In: $r15 value to set 0x404170 to
557 // Waits for a ctx_4170s() call to complete
567 // Disables various things, waits a bit, and re-enables them..
569 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
570 // good description for the bits we turn off? Anyways, without this,
571 // funny things happen.
577 iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL
581 bra ne #ctx_redswitch_delay
583 iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL
586 // Not a clue what this is for, except that unless the value is 0x10, the
587 // strand context is saved (and presumably restored) incorrectly..
589 // In: $r15 value to set to (0x00/0x10 are used)
594 iowr I[$r14] $r15 // HUB(0x86c) = val
597 call #nv_wr32 // ROP(0xa14) = val
600 call #nv_wr32 // GPC(0x86c) = val
603 // ctx_load - load's a channel's ctxctl data, and selects its vm
605 // In: $r2 channel address
610 // switch to channel, somewhat magic in parts..
611 mov $r10 12 // DONE_UNK12
615 iowr I[$r1 + 0x000] $r0 // 0x409a24
618 iowr I[$r3 + 0x100] $r2 // CHAN_NEXT
622 iowr I[$r1 + 0x000] $r2 // MEM_CHAN
623 iowr I[$r1 + 0x100] $r4 // MEM_CMD
625 iord $r4 I[$r1 + 0x100]
627 bra ne #ctx_chan_wait_0
628 iowr I[$r3 + 0x000] $r2 // CHAN_CUR
630 // load channel header, fetch PGRAPH context pointer
639 iowr I[$r1 + 0x000] $r2 // MEM_BASE
644 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram
645 mov $r1 0x10 // chan + 0x0210
647 sethi $r2 0x00020000 // 16 bytes
652 // update current context
653 ld b32 $r1 D[$r0 + #xfer_data + 4]
655 ld b32 $r2 D[$r0 + #xfer_data + 0]
658 st b32 D[$r0 + #ctx_current] $r1
660 // set transfer base to start of context, and fetch context header
664 iowr I[$r2 + 0x000] $r1 // MEM_BASE
668 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm
670 sethi $r1 0x00060000 // 256 bytes
678 // ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
679 // the active channel for ctxctl, but not actually transfer
680 // any context data. intended for use only during initial
681 // context construction.
683 // In: $r2 channel address
688 mov $r10 12 // DONE_UNK12
693 iowr I[$r1 + 0x000] $r2 // MEM_CMD = 5 (???)
695 iord $r2 I[$r1 + 0x000]
697 bra ne #ctx_chan_wait
701 // Execute per-context state overrides list
703 // Only executed on the first load of a channel. Might want to look into
704 // removing this and having the host directly modify the channel's context
705 // to change this state... The nouveau DRM already builds this list as
706 // it's definitely needed for NVIDIA's, so we may as well use it for now
708 // Input: $r1 mmio list length
711 // set transfer base to be the mmio list
712 ld b32 $r3 D[$r0 + #chan_mmio_address]
715 iowr I[$r2 + 0x000] $r3 // MEM_BASE
719 // fetch next 256 bytes of mmio list if necessary
721 bra ne #ctx_mmio_pull
723 sethi $r5 0x00060000 // 256 bytes
727 // execute a single list entry
729 ld b32 $r14 D[$r4 + #xfer_data + 0x00]
730 ld b32 $r15 D[$r4 + #xfer_data + 0x04]
736 bra ne #ctx_mmio_loop
738 // set transfer base back to the current context
740 ld b32 $r3 D[$r0 + #ctx_current]
741 iowr I[$r2 + 0x000] $r3 // MEM_BASE
743 // disable the mmio list now, we don't need/want to execute it again
744 st b32 D[$r0 + #chan_mmio_count] $r0
746 sethi $r1 0x00060000 // 256 bytes
751 // Transfer HUB context data between GPU and storage area
753 // In: $r2 channel address
754 // $p1 clear on save, set on load
755 // $p2 set if opposite direction done/will be done, so:
756 // on save it means: "a load will follow this save"
757 // on load it means: "a save preceeded this load"
760 // according to mwk, some kind of wait for idle
764 iowr I[$r15 + 0x200] $r14
766 iord $r14 I[$r15 + 0x000]
768 bra ne #ctx_xfer_idle
770 bra not $p1 #ctx_xfer_pre
771 bra $p2 #ctx_xfer_pre_load
776 bra not $p1 #ctx_xfer_exec
787 // fetch context pointer, and initiate xfer on all GPCs
789 ld b32 $r1 D[$r0 + #ctx_current]
792 iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
796 call #nv_wr32 // GPC_BCAST_WRCMD_DATA = ctx pointer
802 call #nv_wr32 // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
808 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
812 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
815 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
818 xbit $r10 $flags $p1 // direction
819 or $r10 6 // first, last
820 mov $r11 0 // base = 0
821 ld b32 $r12 D[$r0 + #hub_mmio_list_head]
822 ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
823 mov $r14 0 // not multi
826 // wait for GPCs to all complete
827 mov $r10 8 // DONE_BAR
830 // wait for strand xfer to complete
834 bra $p1 #ctx_xfer_post
835 mov $r10 12 // DONE_UNK12
840 iowr I[$r1] $r2 // MEM_CMD
841 ctx_xfer_post_save_wait:
844 bra ne #ctx_xfer_post_save_wait
846 bra $p2 #ctx_xfer_done
857 bra not $p1 #ctx_xfer_no_post_mmio
858 ld b32 $r1 D[$r0 + #chan_mmio_count]
860 bra e #ctx_xfer_no_post_mmio
863 ctx_xfer_no_post_mmio: