drivers/gpu/drm/nouveau/core/engine/graph/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/os.h>
  27 #include <core/class.h>
  28 #include <core/handle.h>
  29 #include <core/engctx.h>
  30
  31 #include <subdev/fb.h>
  32 #include <subdev/timer.h>
  33
  34 #include <engine/graph.h>
  35 #include <engine/fifo.h>
  36
  37 #include "nv40.h"
  38 #include "regs.h"
  39
  40 struct nv40_graph_priv {
  41         struct nouveau_graph base;
  42         u32 size;
  43 };
  44
  45 struct nv40_graph_chan {
  46         struct nouveau_graph_chan base;
  47 };
  48
  49 /*******************************************************************************
  50  * Graphics object classes
  51  ******************************************************************************/
  52
  53 static int
  54 nv40_graph_object_ctor(struct nouveau_object *parent,
  55                        struct nouveau_object *engine,
  56                        struct nouveau_oclass *oclass, void *data, u32 size,
  57                        struct nouveau_object **pobject)
  58 {
  59         struct nouveau_gpuobj *obj;
  60         int ret;
  61
  62         ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
  63                                     20, 16, 0, &obj);
  64         *pobject = nv_object(obj);
  65         if (ret)
  66                 return ret;
  67
  68         nv_wo32(obj, 0x00, nv_mclass(obj));
  69         nv_wo32(obj, 0x04, 0x00000000);
  70         nv_wo32(obj, 0x08, 0x00000000);
  71 #ifdef __BIG_ENDIAN
  72         nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
  73 #endif
  74         nv_wo32(obj, 0x0c, 0x00000000);
  75         nv_wo32(obj, 0x10, 0x00000000);
  76         return 0;
  77 }
  78
  79 static struct nouveau_ofuncs
  80 nv40_graph_ofuncs = {
  81         .ctor = nv40_graph_object_ctor,
  82         .dtor = _nouveau_gpuobj_dtor,
  83         .init = _nouveau_gpuobj_init,
  84         .fini = _nouveau_gpuobj_fini,
  85         .rd32 = _nouveau_gpuobj_rd32,
  86         .wr32 = _nouveau_gpuobj_wr32,
  87 };
  88
  89 static struct nouveau_oclass
  90 nv40_graph_sclass[] = {
  91         { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
  92         { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
  93         { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
  94         { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
  95         { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
  96         { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
  97         { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
  98         { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
  99         { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
 100         { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
 101         { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
 102         { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
 103         { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
 104         { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
 105         { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
 106         { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
 107         {},
 108 };
 109
 110 static struct nouveau_oclass
 111 nv44_graph_sclass[] = {
 112         { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
 113         { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
 114         { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
 115         { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
 116         { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
 117         { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
 118         { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
 119         { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
 120         { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
 121         { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
 122         { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
 123         { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
 124         { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
 125         { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
 126         { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
 127         { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
 128         {},
 129 };
 130
 131 /*******************************************************************************
 132  * PGRAPH context
 133  ******************************************************************************/
 134
 135 static int
 136 nv40_graph_context_ctor(struct nouveau_object *parent,
 137                         struct nouveau_object *engine,
 138                         struct nouveau_oclass *oclass, void *data, u32 size,
 139                         struct nouveau_object **pobject)
 140 {
 141         struct nv40_graph_priv *priv = (void *)engine;
 142         struct nv40_graph_chan *chan;
 143         int ret;
 144
 145         ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
 146                                            priv->size, 16,
 147                                            NVOBJ_FLAG_ZERO_ALLOC, &chan);
 148         *pobject = nv_object(chan);
 149         if (ret)
 150                 return ret;
 151
 152         nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
 153         nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
 154         return 0;
 155 }
 156
 157 static int
 158 nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
 159 {
 160         struct nv40_graph_priv *priv = (void *)object->engine;
 161         struct nv40_graph_chan *chan = (void *)object;
 162         u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
 163         int ret = 0;
 164
 165         nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
 166
 167         if (nv_rd32(priv, 0x40032c) == inst) {
 168                 if (suspend) {
 169                         nv_wr32(priv, 0x400720, 0x00000000);
 170                         nv_wr32(priv, 0x400784, inst);
 171                         nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
 172                         nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
 173                         if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
 174                                 u32 insn = nv_rd32(priv, 0x400308);
 175                                 nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
 176                                 ret = -EBUSY;
 177                         }
 178                 }
 179
 180                 nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
 181         }
 182
 183         if (nv_rd32(priv, 0x400330) == inst)
 184                 nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
 185
 186         nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
 187         return ret;
 188 }
 189
 190 static struct nouveau_oclass
 191 nv40_graph_cclass = {
 192         .handle = NV_ENGCTX(GR, 0x40),
 193         .ofuncs = &(struct nouveau_ofuncs) {
 194                 .ctor = nv40_graph_context_ctor,
 195                 .dtor = _nouveau_graph_context_dtor,
 196                 .init = _nouveau_graph_context_init,
 197                 .fini = nv40_graph_context_fini,
 198                 .rd32 = _nouveau_graph_context_rd32,
 199                 .wr32 = _nouveau_graph_context_wr32,
 200         },
 201 };
 202
 203 /*******************************************************************************
 204  * PGRAPH engine/subdev functions
 205  ******************************************************************************/
 206
 207 static void
 208 nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
 209 {
 210         struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
 211         struct nouveau_fifo *pfifo = nouveau_fifo(engine);
 212         struct nv40_graph_priv *priv = (void *)engine;
 213         unsigned long flags;
 214
 215         pfifo->pause(pfifo, &flags);
 216         nv04_graph_idle(priv);
 217
 218         switch (nv_device(priv)->chipset) {
 219         case 0x40:
 220         case 0x41:
 221         case 0x42:
 222         case 0x43:
 223         case 0x45:
 224         case 0x4e:
 225                 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
 226                 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
 227                 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
 228                 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 229                 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 230                 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
 231                 switch (nv_device(priv)->chipset) {
 232                 case 0x40:
 233                 case 0x45:
 234                         nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
 235                         nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
 236                         break;
 237                 case 0x41:
 238                 case 0x42:
 239                 case 0x43:
 240                         nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
 241                         nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
 242                         break;
 243                 default:
 244                         break;
 245                 }
 246                 break;
 247         case 0x44:
 248         case 0x4a:
 249                 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
 250                 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
 251                 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
 252                 break;
 253         case 0x46:
 254         case 0x4c:
 255         case 0x47:
 256         case 0x49:
 257         case 0x4b:
 258         case 0x63:
 259         case 0x67:
 260         case 0x68:
 261                 nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
 262                 nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
 263                 nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
 264                 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 265                 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 266                 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
 267                 switch (nv_device(priv)->chipset) {
 268                 case 0x47:
 269                 case 0x49:
 270                 case 0x4b:
 271                         nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
 272                         nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
 273                         break;
 274                 default:
 275                         break;
 276                 }
 277                 break;
 278         default:
 279                 break;
 280         }
 281
 282         pfifo->start(pfifo, &flags);
 283 }
 284
 285 static void
 286 nv40_graph_intr(struct nouveau_subdev *subdev)
 287 {
 288         struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 289         struct nouveau_engine *engine = nv_engine(subdev);
 290         struct nouveau_object *engctx;
 291         struct nouveau_handle *handle = NULL;
 292         struct nv40_graph_priv *priv = (void *)subdev;
 293         u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
 294         u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
 295         u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
 296         u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
 297         u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
 298         u32 subc = (addr & 0x00070000) >> 16;
 299         u32 mthd = (addr & 0x00001ffc);
 300         u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
 301         u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
 302         u32 show = stat;
 303         int chid;
 304
 305         engctx = nouveau_engctx_get(engine, inst);
 306         chid   = pfifo->chid(pfifo, engctx);
 307
 308         if (stat & NV_PGRAPH_INTR_ERROR) {
 309                 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 310                         handle = nouveau_handle_get_class(engctx, class);
 311                         if (handle && !nv_call(handle->object, mthd, data))
 312                                 show &= ~NV_PGRAPH_INTR_ERROR;
 313                         nouveau_handle_put(handle);
 314                 }
 315
 316                 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
 317                         nv_mask(priv, 0x402000, 0, 0);
 318                 }
 319         }
 320
 321         nv_wr32(priv, NV03_PGRAPH_INTR, stat);
 322         nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
 323
 324         if (show) {
 325                 nv_error(priv, "%s", "");
 326                 nouveau_bitfield_print(nv10_graph_intr_name, show);
 327                 pr_cont(" nsource:");
 328                 nouveau_bitfield_print(nv04_graph_nsource, nsource);
 329                 pr_cont(" nstatus:");
 330                 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
 331                 pr_cont("\n");
 332                 nv_error(priv,
 333                          "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 334                          chid, inst << 4, nouveau_client_name(engctx), subc,
 335                          class, mthd, data);
 336         }
 337
 338         nouveau_engctx_put(engctx);
 339 }
 340
 341 static int
 342 nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 343                struct nouveau_oclass *oclass, void *data, u32 size,
 344                struct nouveau_object **pobject)
 345 {
 346         struct nv40_graph_priv *priv;
 347         int ret;
 348
 349         ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
 350         *pobject = nv_object(priv);
 351         if (ret)
 352                 return ret;
 353
 354         nv_subdev(priv)->unit = 0x00001000;
 355         nv_subdev(priv)->intr = nv40_graph_intr;
 356         nv_engine(priv)->cclass = &nv40_graph_cclass;
 357         if (nv44_graph_class(priv))
 358                 nv_engine(priv)->sclass = nv44_graph_sclass;
 359         else
 360                 nv_engine(priv)->sclass = nv40_graph_sclass;
 361         nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
 362         return 0;
 363 }
 364
 365 static int
 366 nv40_graph_init(struct nouveau_object *object)
 367 {
 368         struct nouveau_engine *engine = nv_engine(object);
 369         struct nouveau_fb *pfb = nouveau_fb(object);
 370         struct nv40_graph_priv *priv = (void *)engine;
 371         int ret, i, j;
 372         u32 vramsz;
 373
 374         ret = nouveau_graph_init(&priv->base);
 375         if (ret)
 376                 return ret;
 377
 378         /* generate and upload context program */
 379         ret = nv40_grctx_init(nv_device(priv), &priv->size);
 380         if (ret)
 381                 return ret;
 382
 383         /* No context present currently */
 384         nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 385
 386         nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 387         nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 388
 389         nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 390         nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
 391         nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 392         nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
 393         nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
 394         nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 395
 396         nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 397         nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 398
 399         j = nv_rd32(priv, 0x1540) & 0xff;
 400         if (j) {
 401                 for (i = 0; !(j & 1); j >>= 1, i++)
 402                         ;
 403                 nv_wr32(priv, 0x405000, i);
 404         }
 405
 406         if (nv_device(priv)->chipset == 0x40) {
 407                 nv_wr32(priv, 0x4009b0, 0x83280fff);
 408                 nv_wr32(priv, 0x4009b4, 0x000000a0);
 409         } else {
 410                 nv_wr32(priv, 0x400820, 0x83280eff);
 411                 nv_wr32(priv, 0x400824, 0x000000a0);
 412         }
 413
 414         switch (nv_device(priv)->chipset) {
 415         case 0x40:
 416         case 0x45:
 417                 nv_wr32(priv, 0x4009b8, 0x0078e366);
 418                 nv_wr32(priv, 0x4009bc, 0x0000014c);
 419                 break;
 420         case 0x41:
 421         case 0x42: /* pciid also 0x00Cx */
 422         /* case 0x0120: XXX (pciid) */
 423                 nv_wr32(priv, 0x400828, 0x007596ff);
 424                 nv_wr32(priv, 0x40082c, 0x00000108);
 425                 break;
 426         case 0x43:
 427                 nv_wr32(priv, 0x400828, 0x0072cb77);
 428                 nv_wr32(priv, 0x40082c, 0x00000108);
 429                 break;
 430         case 0x44:
 431         case 0x46: /* G72 */
 432         case 0x4a:
 433         case 0x4c: /* G7x-based C51 */
 434         case 0x4e:
 435                 nv_wr32(priv, 0x400860, 0);
 436                 nv_wr32(priv, 0x400864, 0);
 437                 break;
 438         case 0x47: /* G70 */
 439         case 0x49: /* G71 */
 440         case 0x4b: /* G73 */
 441                 nv_wr32(priv, 0x400828, 0x07830610);
 442                 nv_wr32(priv, 0x40082c, 0x0000016A);
 443                 break;
 444         default:
 445                 break;
 446         }
 447
 448         nv_wr32(priv, 0x400b38, 0x2ffff800);
 449         nv_wr32(priv, 0x400b3c, 0x00006000);
 450
 451         /* Tiling related stuff. */
 452         switch (nv_device(priv)->chipset) {
 453         case 0x44:
 454         case 0x4a:
 455                 nv_wr32(priv, 0x400bc4, 0x1003d888);
 456                 nv_wr32(priv, 0x400bbc, 0xb7a7b500);
 457                 break;
 458         case 0x46:
 459                 nv_wr32(priv, 0x400bc4, 0x0000e024);
 460                 nv_wr32(priv, 0x400bbc, 0xb7a7b520);
 461                 break;
 462         case 0x4c:
 463         case 0x4e:
 464         case 0x67:
 465                 nv_wr32(priv, 0x400bc4, 0x1003d888);
 466                 nv_wr32(priv, 0x400bbc, 0xb7a7b540);
 467                 break;
 468         default:
 469                 break;
 470         }
 471
 472         /* Turn all the tiling regions off. */
 473         for (i = 0; i < pfb->tile.regions; i++)
 474                 engine->tile_prog(engine, i);
 475
 476         /* begin RAM config */
 477         vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
 478         switch (nv_device(priv)->chipset) {
 479         case 0x40:
 480                 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
 481                 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
 482                 nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
 483                 nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
 484                 nv_wr32(priv, 0x400820, 0);
 485                 nv_wr32(priv, 0x400824, 0);
 486                 nv_wr32(priv, 0x400864, vramsz);
 487                 nv_wr32(priv, 0x400868, vramsz);
 488                 break;
 489         default:
 490                 switch (nv_device(priv)->chipset) {
 491                 case 0x41:
 492                 case 0x42:
 493                 case 0x43:
 494                 case 0x45:
 495                 case 0x4e:
 496                 case 0x44:
 497                 case 0x4a:
 498                         nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
 499                         nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
 500                         break;
 501                 default:
 502                         nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
 503                         nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
 504                         break;
 505                 }
 506                 nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
 507                 nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
 508                 nv_wr32(priv, 0x400840, 0);
 509                 nv_wr32(priv, 0x400844, 0);
 510                 nv_wr32(priv, 0x4008A0, vramsz);
 511                 nv_wr32(priv, 0x4008A4, vramsz);
 512                 break;
 513         }
 514
 515         return 0;
 516 }
 517
 518 struct nouveau_oclass
 519 nv40_graph_oclass = {
 520         .handle = NV_ENGINE(GR, 0x40),
 521         .ofuncs = &(struct nouveau_ofuncs) {
 522                 .ctor = nv40_graph_ctor,
 523                 .dtor = _nouveau_graph_dtor,
 524                 .init = nv40_graph_init,
 525                 .fini = _nouveau_graph_fini,
 526         },
 527 };