drivers/gpu/drm/nouveau/core/include/core/class.h

   1 #ifndef __NOUVEAU_CLASS_H__
   2 #define __NOUVEAU_CLASS_H__
   3
   4 /* Device class
   5  *
   6  * 0080: NV_DEVICE
   7  */
   8 #define NV_DEVICE_CLASS                                              0x00000080
   9
  10 #define NV_DEVICE_DISABLE_IDENTIFY                        0x0000000000000001ULL
  11 #define NV_DEVICE_DISABLE_MMIO                            0x0000000000000002ULL
  12 #define NV_DEVICE_DISABLE_VBIOS                           0x0000000000000004ULL
  13 #define NV_DEVICE_DISABLE_CORE                            0x0000000000000008ULL
  14 #define NV_DEVICE_DISABLE_DISP                            0x0000000000010000ULL
  15 #define NV_DEVICE_DISABLE_FIFO                            0x0000000000020000ULL
  16 #define NV_DEVICE_DISABLE_GRAPH                           0x0000000100000000ULL
  17 #define NV_DEVICE_DISABLE_MPEG                            0x0000000200000000ULL
  18 #define NV_DEVICE_DISABLE_ME                              0x0000000400000000ULL
  19 #define NV_DEVICE_DISABLE_VP                              0x0000000800000000ULL
  20 #define NV_DEVICE_DISABLE_CRYPT                           0x0000001000000000ULL
  21 #define NV_DEVICE_DISABLE_BSP                             0x0000002000000000ULL
  22 #define NV_DEVICE_DISABLE_PPP                             0x0000004000000000ULL
  23 #define NV_DEVICE_DISABLE_COPY0                           0x0000008000000000ULL
  24 #define NV_DEVICE_DISABLE_COPY1                           0x0000010000000000ULL
  25 #define NV_DEVICE_DISABLE_VIC                             0x0000020000000000ULL
  26 #define NV_DEVICE_DISABLE_VENC                            0x0000040000000000ULL
  27
  28 struct nv_device_class {
  29         u64 device;     /* device identifier, ~0 for client default */
  30         u64 disable;    /* disable particular subsystems */
  31         u64 debug0;     /* as above, but *internal* ids, and *NOT* ABI */
  32 };
  33
  34 /* DMA object classes
  35  *
  36  * 0002: NV_DMA_FROM_MEMORY
  37  * 0003: NV_DMA_TO_MEMORY
  38  * 003d: NV_DMA_IN_MEMORY
  39  */
  40 #define NV_DMA_FROM_MEMORY_CLASS                                     0x00000002
  41 #define NV_DMA_TO_MEMORY_CLASS                                       0x00000003
  42 #define NV_DMA_IN_MEMORY_CLASS                                       0x0000003d
  43
  44 #define NV_DMA_TARGET_MASK                                           0x000000ff
  45 #define NV_DMA_TARGET_VM                                             0x00000000
  46 #define NV_DMA_TARGET_VRAM                                           0x00000001
  47 #define NV_DMA_TARGET_PCI                                            0x00000002
  48 #define NV_DMA_TARGET_PCI_US                                         0x00000003
  49 #define NV_DMA_TARGET_AGP                                            0x00000004
  50 #define NV_DMA_ACCESS_MASK                                           0x00000f00
  51 #define NV_DMA_ACCESS_VM                                             0x00000000
  52 #define NV_DMA_ACCESS_RD                                             0x00000100
  53 #define NV_DMA_ACCESS_WR                                             0x00000200
  54 #define NV_DMA_ACCESS_RDWR                                           0x00000300
  55
  56 /* NV50:NVC0 */
  57 #define NV50_DMA_CONF0_ENABLE                                        0x80000000
  58 #define NV50_DMA_CONF0_PRIV                                          0x00300000
  59 #define NV50_DMA_CONF0_PRIV_VM                                       0x00000000
  60 #define NV50_DMA_CONF0_PRIV_US                                       0x00100000
  61 #define NV50_DMA_CONF0_PRIV__S                                       0x00200000
  62 #define NV50_DMA_CONF0_PART                                          0x00030000
  63 #define NV50_DMA_CONF0_PART_VM                                       0x00000000
  64 #define NV50_DMA_CONF0_PART_256                                      0x00010000
  65 #define NV50_DMA_CONF0_PART_1KB                                      0x00020000
  66 #define NV50_DMA_CONF0_COMP                                          0x00000180
  67 #define NV50_DMA_CONF0_COMP_NONE                                     0x00000000
  68 #define NV50_DMA_CONF0_COMP_VM                                       0x00000180
  69 #define NV50_DMA_CONF0_TYPE                                          0x0000007f
  70 #define NV50_DMA_CONF0_TYPE_LINEAR                                   0x00000000
  71 #define NV50_DMA_CONF0_TYPE_VM                                       0x0000007f
  72
  73 /* NVC0:NVD9 */
  74 #define NVC0_DMA_CONF0_ENABLE                                        0x80000000
  75 #define NVC0_DMA_CONF0_PRIV                                          0x00300000
  76 #define NVC0_DMA_CONF0_PRIV_VM                                       0x00000000
  77 #define NVC0_DMA_CONF0_PRIV_US                                       0x00100000
  78 #define NVC0_DMA_CONF0_PRIV__S                                       0x00200000
  79 #define NVC0_DMA_CONF0_UNKN /* PART? */                              0x00030000
  80 #define NVC0_DMA_CONF0_TYPE                                          0x000000ff
  81 #define NVC0_DMA_CONF0_TYPE_LINEAR                                   0x00000000
  82 #define NVC0_DMA_CONF0_TYPE_VM                                       0x000000ff
  83
  84 /* NVD9- */
  85 #define NVD0_DMA_CONF0_ENABLE                                        0x80000000
  86 #define NVD0_DMA_CONF0_PAGE                                          0x00000400
  87 #define NVD0_DMA_CONF0_PAGE_LP                                       0x00000000
  88 #define NVD0_DMA_CONF0_PAGE_SP                                       0x00000400
  89 #define NVD0_DMA_CONF0_TYPE                                          0x000000ff
  90 #define NVD0_DMA_CONF0_TYPE_LINEAR                                   0x00000000
  91 #define NVD0_DMA_CONF0_TYPE_VM                                       0x000000ff
  92
  93 struct nv_dma_class {
  94         u32 flags;
  95         u32 pad0;
  96         u64 start;
  97         u64 limit;
  98         u32 conf0;
  99 };
 100
 101 /* Perfmon counter class
 102  *
 103  * XXXX: NV_PERFCTR
 104  */
 105 #define NV_PERFCTR_CLASS                                             0x0000ffff
 106 #define NV_PERFCTR_QUERY                                             0x00000000
 107 #define NV_PERFCTR_SAMPLE                                            0x00000001
 108 #define NV_PERFCTR_READ                                              0x00000002
 109
 110 struct nv_perfctr_class {
 111         u16 logic_op;
 112         struct {
 113                 char __user *name; /*XXX: use cfu when exposed to userspace */
 114                 u32 size;
 115         } signal[4];
 116 };
 117
 118 struct nv_perfctr_query {
 119         u32 iter;
 120         u32 size;
 121         char __user *name; /*XXX: use ctu when exposed to userspace */
 122 };
 123
 124 struct nv_perfctr_sample {
 125 };
 126
 127 struct nv_perfctr_read {
 128         u32 ctr;
 129         u32 clk;
 130 };
 131
 132 /* Device control class
 133  *
 134  * XXXX: NV_CONTROL
 135  */
 136 #define NV_CONTROL_CLASS                                             0x0000fffe
 137
 138 #define NV_CONTROL_PSTATE_INFO                                       0x00000000
 139 #define NV_CONTROL_PSTATE_INFO_USTATE_DISABLE                              (-1)
 140 #define NV_CONTROL_PSTATE_INFO_USTATE_PERFMON                              (-2)
 141 #define NV_CONTROL_PSTATE_INFO_PSTATE_UNKNOWN                              (-1)
 142 #define NV_CONTROL_PSTATE_INFO_PSTATE_PERFMON                              (-2)
 143 #define NV_CONTROL_PSTATE_ATTR                                       0x00000001
 144 #define NV_CONTROL_PSTATE_ATTR_STATE_CURRENT                               (-1)
 145 #define NV_CONTROL_PSTATE_USER                                       0x00000002
 146 #define NV_CONTROL_PSTATE_USER_STATE_UNKNOWN                               (-1)
 147 #define NV_CONTROL_PSTATE_USER_STATE_PERFMON                               (-2)
 148
 149 struct nv_control_pstate_info {
 150         u32 count; /* out: number of power states */
 151         s32 ustate; /* out: current target pstate index */
 152         u32 pstate; /* out: current pstate index */
 153 };
 154
 155 struct nv_control_pstate_attr {
 156         s32 state; /*  in: index of pstate to query
 157                     * out: pstate identifier
 158                     */
 159         u32 index; /*  in: index of attribute to query
 160                     * out: index of next attribute, or 0 if no more
 161                     */
 162         char name[32];
 163         char unit[16];
 164         u32 min;
 165         u32 max;
 166 };
 167
 168 struct nv_control_pstate_user {
 169         s32 state; /*  in: pstate identifier */
 170 };
 171
 172 /* DMA FIFO channel classes
 173  *
 174  * 006b: NV03_CHANNEL_DMA
 175  * 006e: NV10_CHANNEL_DMA
 176  * 176e: NV17_CHANNEL_DMA
 177  * 406e: NV40_CHANNEL_DMA
 178  * 506e: NV50_CHANNEL_DMA
 179  * 826e: NV84_CHANNEL_DMA
 180  */
 181 #define NV03_CHANNEL_DMA_CLASS                                       0x0000006b
 182 #define NV10_CHANNEL_DMA_CLASS                                       0x0000006e
 183 #define NV17_CHANNEL_DMA_CLASS                                       0x0000176e
 184 #define NV40_CHANNEL_DMA_CLASS                                       0x0000406e
 185 #define NV50_CHANNEL_DMA_CLASS                                       0x0000506e
 186 #define NV84_CHANNEL_DMA_CLASS                                       0x0000826e
 187
 188 struct nv03_channel_dma_class {
 189         u32 pushbuf;
 190         u32 pad0;
 191         u64 offset;
 192 };
 193
 194 /* Indirect FIFO channel classes
 195  *
 196  * 506f: NV50_CHANNEL_IND
 197  * 826f: NV84_CHANNEL_IND
 198  * 906f: NVC0_CHANNEL_IND
 199  * a06f: NVE0_CHANNEL_IND
 200  */
 201
 202 #define NV50_CHANNEL_IND_CLASS                                       0x0000506f
 203 #define NV84_CHANNEL_IND_CLASS                                       0x0000826f
 204 #define NVC0_CHANNEL_IND_CLASS                                       0x0000906f
 205 #define NVE0_CHANNEL_IND_CLASS                                       0x0000a06f
 206
 207 struct nv50_channel_ind_class {
 208         u32 pushbuf;
 209         u32 ilength;
 210         u64 ioffset;
 211 };
 212
 213 #define NVE0_CHANNEL_IND_ENGINE_GR                                   0x00000001
 214 #define NVE0_CHANNEL_IND_ENGINE_VP                                   0x00000002
 215 #define NVE0_CHANNEL_IND_ENGINE_PPP                                  0x00000004
 216 #define NVE0_CHANNEL_IND_ENGINE_BSP                                  0x00000008
 217 #define NVE0_CHANNEL_IND_ENGINE_CE0                                  0x00000010
 218 #define NVE0_CHANNEL_IND_ENGINE_CE1                                  0x00000020
 219 #define NVE0_CHANNEL_IND_ENGINE_ENC                                  0x00000040
 220
 221 struct nve0_channel_ind_class {
 222         u32 pushbuf;
 223         u32 ilength;
 224         u64 ioffset;
 225         u32 engine;
 226 };
 227
 228 /* 0046: NV04_DISP
 229  */
 230
 231 #define NV04_DISP_CLASS                                              0x00000046
 232
 233 #define NV04_DISP_MTHD                                               0x00000000
 234 #define NV04_DISP_MTHD_HEAD                                          0x00000001
 235
 236 #define NV04_DISP_SCANOUTPOS                                         0x00000000
 237
 238 struct nv04_display_class {
 239 };
 240
 241 struct nv04_display_scanoutpos {
 242         s64 time[2];
 243         u32 vblanks;
 244         u32 vblanke;
 245         u32 vtotal;
 246         u32 vline;
 247         u32 hblanks;
 248         u32 hblanke;
 249         u32 htotal;
 250         u32 hline;
 251 };
 252
 253 /* 5070: NV50_DISP
 254  * 8270: NV84_DISP
 255  * 8370: NVA0_DISP
 256  * 8870: NV94_DISP
 257  * 8570: NVA3_DISP
 258  * 9070: NVD0_DISP
 259  * 9170: NVE0_DISP
 260  * 9270: NVF0_DISP
 261  */
 262
 263 #define NV50_DISP_CLASS                                              0x00005070
 264 #define NV84_DISP_CLASS                                              0x00008270
 265 #define NVA0_DISP_CLASS                                              0x00008370
 266 #define NV94_DISP_CLASS                                              0x00008870
 267 #define NVA3_DISP_CLASS                                              0x00008570
 268 #define NVD0_DISP_CLASS                                              0x00009070
 269 #define NVE0_DISP_CLASS                                              0x00009170
 270 #define NVF0_DISP_CLASS                                              0x00009270
 271
 272 #define NV50_DISP_MTHD                                               0x00000000
 273 #define NV50_DISP_MTHD_HEAD                                          0x00000003
 274
 275 #define NV50_DISP_SCANOUTPOS                                         0x00000000
 276
 277 #define NV50_DISP_SOR_MTHD                                           0x00010000
 278 #define NV50_DISP_SOR_MTHD_TYPE                                      0x0000f000
 279 #define NV50_DISP_SOR_MTHD_HEAD                                      0x00000018
 280 #define NV50_DISP_SOR_MTHD_LINK                                      0x00000004
 281 #define NV50_DISP_SOR_MTHD_OR                                        0x00000003
 282
 283 #define NV50_DISP_SOR_PWR                                            0x00010000
 284 #define NV50_DISP_SOR_PWR_STATE                                      0x00000001
 285 #define NV50_DISP_SOR_PWR_STATE_ON                                   0x00000001
 286 #define NV50_DISP_SOR_PWR_STATE_OFF                                  0x00000000
 287 #define NVA3_DISP_SOR_HDA_ELD                                        0x00010100
 288 #define NV84_DISP_SOR_HDMI_PWR                                       0x00012000
 289 #define NV84_DISP_SOR_HDMI_PWR_STATE                                 0x40000000
 290 #define NV84_DISP_SOR_HDMI_PWR_STATE_OFF                             0x00000000
 291 #define NV84_DISP_SOR_HDMI_PWR_STATE_ON                              0x40000000
 292 #define NV84_DISP_SOR_HDMI_PWR_MAX_AC_PACKET                         0x001f0000
 293 #define NV84_DISP_SOR_HDMI_PWR_REKEY                                 0x0000007f
 294 #define NV50_DISP_SOR_LVDS_SCRIPT                                    0x00013000
 295 #define NV50_DISP_SOR_LVDS_SCRIPT_ID                                 0x0000ffff
 296
 297 #define NV50_DISP_DAC_MTHD                                           0x00020000
 298 #define NV50_DISP_DAC_MTHD_TYPE                                      0x0000f000
 299 #define NV50_DISP_DAC_MTHD_OR                                        0x00000003
 300
 301 #define NV50_DISP_DAC_PWR                                            0x00020000
 302 #define NV50_DISP_DAC_PWR_HSYNC                                      0x00000001
 303 #define NV50_DISP_DAC_PWR_HSYNC_ON                                   0x00000000
 304 #define NV50_DISP_DAC_PWR_HSYNC_LO                                   0x00000001
 305 #define NV50_DISP_DAC_PWR_VSYNC                                      0x00000004
 306 #define NV50_DISP_DAC_PWR_VSYNC_ON                                   0x00000000
 307 #define NV50_DISP_DAC_PWR_VSYNC_LO                                   0x00000004
 308 #define NV50_DISP_DAC_PWR_DATA                                       0x00000010
 309 #define NV50_DISP_DAC_PWR_DATA_ON                                    0x00000000
 310 #define NV50_DISP_DAC_PWR_DATA_LO                                    0x00000010
 311 #define NV50_DISP_DAC_PWR_STATE                                      0x00000040
 312 #define NV50_DISP_DAC_PWR_STATE_ON                                   0x00000000
 313 #define NV50_DISP_DAC_PWR_STATE_OFF                                  0x00000040
 314 #define NV50_DISP_DAC_LOAD                                           0x00020100
 315 #define NV50_DISP_DAC_LOAD_VALUE                                     0x00000007
 316
 317 #define NV50_DISP_PIOR_MTHD                                          0x00030000
 318 #define NV50_DISP_PIOR_MTHD_TYPE                                     0x0000f000
 319 #define NV50_DISP_PIOR_MTHD_OR                                       0x00000003
 320
 321 #define NV50_DISP_PIOR_PWR                                           0x00030000
 322 #define NV50_DISP_PIOR_PWR_STATE                                     0x00000001
 323 #define NV50_DISP_PIOR_PWR_STATE_ON                                  0x00000001
 324 #define NV50_DISP_PIOR_PWR_STATE_OFF                                 0x00000000
 325 #define NV50_DISP_PIOR_TMDS_PWR                                      0x00032000
 326 #define NV50_DISP_PIOR_TMDS_PWR_STATE                                0x00000001
 327 #define NV50_DISP_PIOR_TMDS_PWR_STATE_ON                             0x00000001
 328 #define NV50_DISP_PIOR_TMDS_PWR_STATE_OFF                            0x00000000
 329 #define NV50_DISP_PIOR_DP_PWR                                        0x00036000
 330 #define NV50_DISP_PIOR_DP_PWR_STATE                                  0x00000001
 331 #define NV50_DISP_PIOR_DP_PWR_STATE_ON                               0x00000001
 332 #define NV50_DISP_PIOR_DP_PWR_STATE_OFF                              0x00000000
 333
 334 struct nv50_display_class {
 335 };
 336
 337 /* 507a: NV50_DISP_CURS
 338  * 827a: NV84_DISP_CURS
 339  * 837a: NVA0_DISP_CURS
 340  * 887a: NV94_DISP_CURS
 341  * 857a: NVA3_DISP_CURS
 342  * 907a: NVD0_DISP_CURS
 343  * 917a: NVE0_DISP_CURS
 344  * 927a: NVF0_DISP_CURS
 345  */
 346
 347 #define NV50_DISP_CURS_CLASS                                         0x0000507a
 348 #define NV84_DISP_CURS_CLASS                                         0x0000827a
 349 #define NVA0_DISP_CURS_CLASS                                         0x0000837a
 350 #define NV94_DISP_CURS_CLASS                                         0x0000887a
 351 #define NVA3_DISP_CURS_CLASS                                         0x0000857a
 352 #define NVD0_DISP_CURS_CLASS                                         0x0000907a
 353 #define NVE0_DISP_CURS_CLASS                                         0x0000917a
 354 #define NVF0_DISP_CURS_CLASS                                         0x0000927a
 355
 356 struct nv50_display_curs_class {
 357         u32 head;
 358 };
 359
 360 /* 507b: NV50_DISP_OIMM
 361  * 827b: NV84_DISP_OIMM
 362  * 837b: NVA0_DISP_OIMM
 363  * 887b: NV94_DISP_OIMM
 364  * 857b: NVA3_DISP_OIMM
 365  * 907b: NVD0_DISP_OIMM
 366  * 917b: NVE0_DISP_OIMM
 367  * 927b: NVE0_DISP_OIMM
 368  */
 369
 370 #define NV50_DISP_OIMM_CLASS                                         0x0000507b
 371 #define NV84_DISP_OIMM_CLASS                                         0x0000827b
 372 #define NVA0_DISP_OIMM_CLASS                                         0x0000837b
 373 #define NV94_DISP_OIMM_CLASS                                         0x0000887b
 374 #define NVA3_DISP_OIMM_CLASS                                         0x0000857b
 375 #define NVD0_DISP_OIMM_CLASS                                         0x0000907b
 376 #define NVE0_DISP_OIMM_CLASS                                         0x0000917b
 377 #define NVF0_DISP_OIMM_CLASS                                         0x0000927b
 378
 379 struct nv50_display_oimm_class {
 380         u32 head;
 381 };
 382
 383 /* 507c: NV50_DISP_SYNC
 384  * 827c: NV84_DISP_SYNC
 385  * 837c: NVA0_DISP_SYNC
 386  * 887c: NV94_DISP_SYNC
 387  * 857c: NVA3_DISP_SYNC
 388  * 907c: NVD0_DISP_SYNC
 389  * 917c: NVE0_DISP_SYNC
 390  * 927c: NVF0_DISP_SYNC
 391  */
 392
 393 #define NV50_DISP_SYNC_CLASS                                         0x0000507c
 394 #define NV84_DISP_SYNC_CLASS                                         0x0000827c
 395 #define NVA0_DISP_SYNC_CLASS                                         0x0000837c
 396 #define NV94_DISP_SYNC_CLASS                                         0x0000887c
 397 #define NVA3_DISP_SYNC_CLASS                                         0x0000857c
 398 #define NVD0_DISP_SYNC_CLASS                                         0x0000907c
 399 #define NVE0_DISP_SYNC_CLASS                                         0x0000917c
 400 #define NVF0_DISP_SYNC_CLASS                                         0x0000927c
 401
 402 struct nv50_display_sync_class {
 403         u32 pushbuf;
 404         u32 head;
 405 };
 406
 407 /* 507d: NV50_DISP_MAST
 408  * 827d: NV84_DISP_MAST
 409  * 837d: NVA0_DISP_MAST
 410  * 887d: NV94_DISP_MAST
 411  * 857d: NVA3_DISP_MAST
 412  * 907d: NVD0_DISP_MAST
 413  * 917d: NVE0_DISP_MAST
 414  * 927d: NVF0_DISP_MAST
 415  */
 416
 417 #define NV50_DISP_MAST_CLASS                                         0x0000507d
 418 #define NV84_DISP_MAST_CLASS                                         0x0000827d
 419 #define NVA0_DISP_MAST_CLASS                                         0x0000837d
 420 #define NV94_DISP_MAST_CLASS                                         0x0000887d
 421 #define NVA3_DISP_MAST_CLASS                                         0x0000857d
 422 #define NVD0_DISP_MAST_CLASS                                         0x0000907d
 423 #define NVE0_DISP_MAST_CLASS                                         0x0000917d
 424 #define NVF0_DISP_MAST_CLASS                                         0x0000927d
 425
 426 struct nv50_display_mast_class {
 427         u32 pushbuf;
 428 };
 429
 430 /* 507e: NV50_DISP_OVLY
 431  * 827e: NV84_DISP_OVLY
 432  * 837e: NVA0_DISP_OVLY
 433  * 887e: NV94_DISP_OVLY
 434  * 857e: NVA3_DISP_OVLY
 435  * 907e: NVD0_DISP_OVLY
 436  * 917e: NVE0_DISP_OVLY
 437  * 927e: NVF0_DISP_OVLY
 438  */
 439
 440 #define NV50_DISP_OVLY_CLASS                                         0x0000507e
 441 #define NV84_DISP_OVLY_CLASS                                         0x0000827e
 442 #define NVA0_DISP_OVLY_CLASS                                         0x0000837e
 443 #define NV94_DISP_OVLY_CLASS                                         0x0000887e
 444 #define NVA3_DISP_OVLY_CLASS                                         0x0000857e
 445 #define NVD0_DISP_OVLY_CLASS                                         0x0000907e
 446 #define NVE0_DISP_OVLY_CLASS                                         0x0000917e
 447 #define NVF0_DISP_OVLY_CLASS                                         0x0000927e
 448
 449 struct nv50_display_ovly_class {
 450         u32 pushbuf;
 451         u32 head;
 452 };
 453
 454 #endif