drivers/gpu/drm/nouveau/include/nvif/class.h

   1 #ifndef __NVIF_CLASS_H__
   2 #define __NVIF_CLASS_H__
   3
   4 /* these class numbers are made up by us, and not nvidia-assigned */
   5 #define NVIF_CLASS_CONTROL                                    /* if0001.h */ -1
   6 #define NVIF_CLASS_PERFMON                                    /* if0002.h */ -2
   7 #define NVIF_CLASS_PERFDOM                                    /* if0003.h */ -3
   8 #define NVIF_CLASS_SW_NV04                                    /* if0004.h */ -4
   9 #define NVIF_CLASS_SW_NV10                                    /* if0005.h */ -5
  10 #define NVIF_CLASS_SW_NV50                                    /* if0005.h */ -6
  11 #define NVIF_CLASS_SW_GF100                                   /* if0005.h */ -7
  12
  13 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
  14 #define NV_NULL_CLASS                                                0x00000030
  15
  16 #define NV_DEVICE                                     /* cl0080.h */ 0x00000080
  17
  18 #define NV_DMA_FROM_MEMORY                            /* cl0002.h */ 0x00000002
  19 #define NV_DMA_TO_MEMORY                              /* cl0002.h */ 0x00000003
  20 #define NV_DMA_IN_MEMORY                              /* cl0002.h */ 0x0000003d
  21
  22 #define NV50_TWOD                                                    0x0000502d
  23 #define FERMI_TWOD_A                                                 0x0000902d
  24
  25 #define NV50_MEMORY_TO_MEMORY_FORMAT                                 0x00005039
  26 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
  27
  28 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
  29 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
  30
  31 #define NV04_DISP                                     /* cl0046.h */ 0x00000046
  32
  33 #define NV03_CHANNEL_DMA                              /* cl506b.h */ 0x0000006b
  34 #define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e
  35 #define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e
  36 #define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e
  37 #define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e
  38 #define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e
  39
  40 #define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f
  41 #define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f
  42 #define FERMI_CHANNEL_GPFIFO                          /* cl906f.h */ 0x0000906f
  43 #define KEPLER_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000a06f
  44 #define KEPLER_CHANNEL_GPFIFO_B                       /* cla06f.h */ 0x0000a16f
  45 #define MAXWELL_CHANNEL_GPFIFO_A                      /* cla06f.h */ 0x0000b06f
  46 #define PASCAL_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000c06f
  47
  48 #define NV50_DISP                                     /* cl5070.h */ 0x00005070
  49 #define G82_DISP                                      /* cl5070.h */ 0x00008270
  50 #define GT200_DISP                                    /* cl5070.h */ 0x00008370
  51 #define GT214_DISP                                    /* cl5070.h */ 0x00008570
  52 #define GT206_DISP                                    /* cl5070.h */ 0x00008870
  53 #define GF110_DISP                                    /* cl5070.h */ 0x00009070
  54 #define GK104_DISP                                    /* cl5070.h */ 0x00009170
  55 #define GK110_DISP                                    /* cl5070.h */ 0x00009270
  56 #define GM107_DISP                                    /* cl5070.h */ 0x00009470
  57 #define GM200_DISP                                    /* cl5070.h */ 0x00009570
  58 #define GP100_DISP                                    /* cl5070.h */ 0x00009770
  59 #define GP102_DISP                                    /* cl5070.h */ 0x00009870
  60
  61 #define NV31_MPEG                                                    0x00003174
  62 #define G82_MPEG                                                     0x00008274
  63
  64 #define NV74_VP2                                                     0x00007476
  65
  66 #define NV50_DISP_CURSOR                              /* cl507a.h */ 0x0000507a
  67 #define G82_DISP_CURSOR                               /* cl507a.h */ 0x0000827a
  68 #define GT214_DISP_CURSOR                             /* cl507a.h */ 0x0000857a
  69 #define GF110_DISP_CURSOR                             /* cl507a.h */ 0x0000907a
  70 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
  71
  72 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
  73 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
  74 #define GT214_DISP_OVERLAY                            /* cl507b.h */ 0x0000857b
  75 #define GF110_DISP_OVERLAY                            /* cl507b.h */ 0x0000907b
  76 #define GK104_DISP_OVERLAY                            /* cl507b.h */ 0x0000917b
  77
  78 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
  79 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
  80 #define GT200_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000837c
  81 #define GT214_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000857c
  82 #define GF110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000907c
  83 #define GK104_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000917c
  84 #define GK110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000927c
  85
  86 #define NV50_DISP_CORE_CHANNEL_DMA                    /* cl507d.h */ 0x0000507d
  87 #define G82_DISP_CORE_CHANNEL_DMA                     /* cl507d.h */ 0x0000827d
  88 #define GT200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000837d
  89 #define GT214_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000857d
  90 #define GT206_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000887d
  91 #define GF110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000907d
  92 #define GK104_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000917d
  93 #define GK110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000927d
  94 #define GM107_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000947d
  95 #define GM200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000957d
  96 #define GP100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000977d
  97 #define GP102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000987d
  98
  99 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
 100 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
 101 #define GT200_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000837e
 102 #define GT214_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000857e
 103 #define GF110_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000907e
 104 #define GK104_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000917e
 105
 106 #define NV50_TESLA                                                   0x00005097
 107 #define G82_TESLA                                                    0x00008297
 108 #define GT200_TESLA                                                  0x00008397
 109 #define GT214_TESLA                                                  0x00008597
 110 #define GT21A_TESLA                                                  0x00008697
 111
 112 #define FERMI_A                                       /* cl9097.h */ 0x00009097
 113 #define FERMI_B                                       /* cl9097.h */ 0x00009197
 114 #define FERMI_C                                       /* cl9097.h */ 0x00009297
 115
 116 #define KEPLER_A                                      /* cl9097.h */ 0x0000a097
 117 #define KEPLER_B                                      /* cl9097.h */ 0x0000a197
 118 #define KEPLER_C                                      /* cl9097.h */ 0x0000a297
 119
 120 #define MAXWELL_A                                     /* cl9097.h */ 0x0000b097
 121 #define MAXWELL_B                                     /* cl9097.h */ 0x0000b197
 122
 123 #define PASCAL_A                                      /* cl9097.h */ 0x0000c097
 124
 125 #define NV74_BSP                                                     0x000074b0
 126
 127 #define GT212_MSVLD                                                  0x000085b1
 128 #define IGT21A_MSVLD                                                 0x000086b1
 129 #define G98_MSVLD                                                    0x000088b1
 130 #define GF100_MSVLD                                                  0x000090b1
 131 #define GK104_MSVLD                                                  0x000095b1
 132
 133 #define GT212_MSPDEC                                                 0x000085b2
 134 #define G98_MSPDEC                                                   0x000088b2
 135 #define GF100_MSPDEC                                                 0x000090b2
 136 #define GK104_MSPDEC                                                 0x000095b2
 137
 138 #define GT212_MSPPP                                                  0x000085b3
 139 #define G98_MSPPP                                                    0x000088b3
 140 #define GF100_MSPPP                                                  0x000090b3
 141
 142 #define G98_SEC                                                      0x000088b4
 143
 144 #define GT212_DMA                                                    0x000085b5
 145 #define FERMI_DMA                                                    0x000090b5
 146 #define KEPLER_DMA_COPY_A                                            0x0000a0b5
 147 #define MAXWELL_DMA_COPY_A                                           0x0000b0b5
 148 #define PASCAL_DMA_COPY_A                                            0x0000c0b5
 149 #define PASCAL_DMA_COPY_B                                            0x0000c1b5
 150
 151 #define FERMI_DECOMPRESS                                             0x000090b8
 152
 153 #define NV50_COMPUTE                                                 0x000050c0
 154 #define GT214_COMPUTE                                                0x000085c0
 155 #define FERMI_COMPUTE_A                                              0x000090c0
 156 #define FERMI_COMPUTE_B                                              0x000091c0
 157 #define KEPLER_COMPUTE_A                                             0x0000a0c0
 158 #define KEPLER_COMPUTE_B                                             0x0000a1c0
 159 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
 160 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
 161 #define PASCAL_COMPUTE_A                                             0x0000c0c0
 162
 163 #define NV74_CIPHER                                                  0x000074c1
 164 #endif