2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <nvif/class.h>
27 #include <nvif/cl0002.h>
28 #include <nvif/cl006b.h>
29 #include <nvif/cl506f.h>
30 #include <nvif/cl906f.h>
31 #include <nvif/cla06f.h>
32 #include <nvif/ioctl.h>
35 #include <core/client.h>
37 #include "nouveau_drv.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_bo.h"
40 #include "nouveau_chan.h"
41 #include "nouveau_fence.h"
42 #include "nouveau_abi16.h"
44 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
45 int nouveau_vram_pushbuf;
46 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
49 nouveau_channel_idle(struct nouveau_channel *chan)
51 if (likely(chan && chan->fence)) {
52 struct nouveau_cli *cli = (void *)chan->user.client;
53 struct nouveau_fence *fence = NULL;
56 ret = nouveau_fence_new(chan, false, &fence);
58 ret = nouveau_fence_wait(fence, false, false);
59 nouveau_fence_unref(&fence);
63 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
64 chan->chid, nvxx_client(&cli->base)->name);
72 nouveau_channel_del(struct nouveau_channel **pchan)
74 struct nouveau_channel *chan = *pchan;
77 nouveau_fence(chan->drm)->context_del(chan);
78 nvif_object_fini(&chan->nvsw);
79 nvif_object_fini(&chan->gart);
80 nvif_object_fini(&chan->vram);
81 nvif_object_fini(&chan->user);
82 nvif_object_fini(&chan->push.ctxdma);
83 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
84 nouveau_bo_unmap(chan->push.buffer);
85 if (chan->push.buffer && chan->push.buffer->pin_refcnt)
86 nouveau_bo_unpin(chan->push.buffer);
87 nouveau_bo_ref(NULL, &chan->push.buffer);
94 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
95 u32 size, struct nouveau_channel **pchan)
97 struct nouveau_cli *cli = (void *)device->object.client;
98 struct nvkm_mmu *mmu = nvxx_mmu(device);
99 struct nv_dma_v0 args = {};
100 struct nouveau_channel *chan;
104 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
108 chan->device = device;
111 /* allocate memory for dma push buffer */
112 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
113 if (nouveau_vram_pushbuf)
114 target = TTM_PL_FLAG_VRAM;
116 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL,
119 ret = nouveau_bo_pin(chan->push.buffer, target, false);
121 ret = nouveau_bo_map(chan->push.buffer);
125 nouveau_channel_del(pchan);
129 /* create dma object covering the *entire* memory space that the
130 * pushbuf lives in, this is because the GEM code requires that
131 * we be able to call out to other (indirect) push buffers
133 chan->push.vma.offset = chan->push.buffer->bo.offset;
135 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
136 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
139 nouveau_channel_del(pchan);
143 args.target = NV_DMA_V0_TARGET_VM;
144 args.access = NV_DMA_V0_ACCESS_VM;
146 args.limit = cli->vm->mmu->limit - 1;
148 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
149 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
150 /* nv04 vram pushbuf hack, retarget to its location in
151 * the framebuffer bar rather than direct vram access..
152 * nfi why this exists, it came from the -nv ddx.
154 args.target = NV_DMA_V0_TARGET_PCI;
155 args.access = NV_DMA_V0_ACCESS_RDWR;
156 args.start = nvxx_device(device)->func->
157 resource_addr(nvxx_device(device), 1);
158 args.limit = args.start + device->info.ram_user - 1;
160 args.target = NV_DMA_V0_TARGET_VRAM;
161 args.access = NV_DMA_V0_ACCESS_RDWR;
163 args.limit = device->info.ram_user - 1;
166 if (chan->drm->agp.bridge) {
167 args.target = NV_DMA_V0_TARGET_AGP;
168 args.access = NV_DMA_V0_ACCESS_RDWR;
169 args.start = chan->drm->agp.base;
170 args.limit = chan->drm->agp.base +
171 chan->drm->agp.size - 1;
173 args.target = NV_DMA_V0_TARGET_VM;
174 args.access = NV_DMA_V0_ACCESS_RDWR;
176 args.limit = mmu->limit - 1;
180 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
181 &args, sizeof(args), &chan->push.ctxdma);
183 nouveau_channel_del(pchan);
191 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
192 u32 engine, struct nouveau_channel **pchan)
194 static const u16 oclasses[] = { PASCAL_CHANNEL_GPFIFO_A,
195 MAXWELL_CHANNEL_GPFIFO_A,
196 KEPLER_CHANNEL_GPFIFO_B,
197 KEPLER_CHANNEL_GPFIFO_A,
198 FERMI_CHANNEL_GPFIFO,
202 const u16 *oclass = oclasses;
204 struct nv50_channel_gpfifo_v0 nv50;
205 struct fermi_channel_gpfifo_v0 fermi;
206 struct kepler_channel_gpfifo_a_v0 kepler;
208 struct nouveau_channel *chan;
212 /* allocate dma push buffer */
213 ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
218 /* create channel object */
220 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
221 args.kepler.version = 0;
222 args.kepler.engines = engine;
223 args.kepler.ilength = 0x02000;
224 args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
226 size = sizeof(args.kepler);
228 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
229 args.fermi.version = 0;
230 args.fermi.ilength = 0x02000;
231 args.fermi.ioffset = 0x10000 + chan->push.vma.offset;
233 size = sizeof(args.fermi);
235 args.nv50.version = 0;
236 args.nv50.ilength = 0x02000;
237 args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
238 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
240 size = sizeof(args.nv50);
243 ret = nvif_object_init(&device->object, 0, *oclass++,
244 &args, size, &chan->user);
246 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
247 chan->chid = args.kepler.chid;
249 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
250 chan->chid = args.fermi.chid;
252 chan->chid = args.nv50.chid;
257 nouveau_channel_del(pchan);
262 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
263 struct nouveau_channel **pchan)
265 static const u16 oclasses[] = { NV40_CHANNEL_DMA,
270 const u16 *oclass = oclasses;
271 struct nv03_channel_dma_v0 args;
272 struct nouveau_channel *chan;
275 /* allocate dma push buffer */
276 ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
281 /* create channel object */
283 args.pushbuf = nvif_handle(&chan->push.ctxdma);
284 args.offset = chan->push.vma.offset;
287 ret = nvif_object_init(&device->object, 0, *oclass++,
288 &args, sizeof(args), &chan->user);
290 chan->chid = args.chid;
293 } while (ret && *oclass);
295 nouveau_channel_del(pchan);
300 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
302 struct nvif_device *device = chan->device;
303 struct nouveau_cli *cli = (void *)chan->user.client;
304 struct nvkm_mmu *mmu = nvxx_mmu(device);
305 struct nv_dma_v0 args = {};
308 nvif_object_map(&chan->user);
310 /* allocate dma objects to cover all allowed vram, and gart */
311 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
312 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
313 args.target = NV_DMA_V0_TARGET_VM;
314 args.access = NV_DMA_V0_ACCESS_VM;
316 args.limit = cli->vm->mmu->limit - 1;
318 args.target = NV_DMA_V0_TARGET_VRAM;
319 args.access = NV_DMA_V0_ACCESS_RDWR;
321 args.limit = device->info.ram_user - 1;
324 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
325 &args, sizeof(args), &chan->vram);
329 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
330 args.target = NV_DMA_V0_TARGET_VM;
331 args.access = NV_DMA_V0_ACCESS_VM;
333 args.limit = cli->vm->mmu->limit - 1;
335 if (chan->drm->agp.bridge) {
336 args.target = NV_DMA_V0_TARGET_AGP;
337 args.access = NV_DMA_V0_ACCESS_RDWR;
338 args.start = chan->drm->agp.base;
339 args.limit = chan->drm->agp.base +
340 chan->drm->agp.size - 1;
342 args.target = NV_DMA_V0_TARGET_VM;
343 args.access = NV_DMA_V0_ACCESS_RDWR;
345 args.limit = mmu->limit - 1;
348 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
349 &args, sizeof(args), &chan->gart);
354 /* initialise dma tracking parameters */
355 switch (chan->user.oclass & 0x00ff) {
358 chan->user_put = 0x40;
359 chan->user_get = 0x44;
360 chan->dma.max = (0x10000 / 4) - 2;
363 chan->user_put = 0x40;
364 chan->user_get = 0x44;
365 chan->user_get_hi = 0x60;
366 chan->dma.ib_base = 0x10000 / 4;
367 chan->dma.ib_max = (0x02000 / 8) - 1;
368 chan->dma.ib_put = 0;
369 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
370 chan->dma.max = chan->dma.ib_base;
375 chan->dma.cur = chan->dma.put;
376 chan->dma.free = chan->dma.max - chan->dma.cur;
378 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
382 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
383 OUT_RING(chan, 0x00000000);
385 /* allocate software object class (used for fences on <= nv05) */
386 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
387 ret = nvif_object_init(&chan->user, 0x006e,
389 NULL, 0, &chan->nvsw);
393 ret = RING_SPACE(chan, 2);
397 BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
398 OUT_RING (chan, chan->nvsw.handle);
402 /* initialise synchronisation */
403 return nouveau_fence(chan->drm)->context_new(chan);
407 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
408 u32 arg0, u32 arg1, struct nouveau_channel **pchan)
410 struct nouveau_cli *cli = (void *)device->object.client;
414 /* hack until fencenv50 is fixed, and agp access relaxed */
415 super = cli->base.super;
416 cli->base.super = true;
418 ret = nouveau_channel_ind(drm, device, arg0, pchan);
420 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
421 ret = nouveau_channel_dma(drm, device, pchan);
423 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
428 ret = nouveau_channel_init(*pchan, arg0, arg1);
430 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
431 nouveau_channel_del(pchan);
435 cli->base.super = super;