drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42
  43 static void nouveau_stub_takedown(struct drm_device *dev) {}
  44 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  45
  46 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  47 {
  48         struct drm_nouveau_private *dev_priv = dev->dev_private;
  49         struct nouveau_engine *engine = &dev_priv->engine;
  50
  51         switch (dev_priv->chipset & 0xf0) {
  52         case 0x00:
  53                 engine->instmem.init            = nv04_instmem_init;
  54                 engine->instmem.takedown        = nv04_instmem_takedown;
  55                 engine->instmem.suspend         = nv04_instmem_suspend;
  56                 engine->instmem.resume          = nv04_instmem_resume;
  57                 engine->instmem.get             = nv04_instmem_get;
  58                 engine->instmem.put             = nv04_instmem_put;
  59                 engine->instmem.map             = nv04_instmem_map;
  60                 engine->instmem.unmap           = nv04_instmem_unmap;
  61                 engine->instmem.flush           = nv04_instmem_flush;
  62                 engine->mc.init                 = nv04_mc_init;
  63                 engine->mc.takedown             = nv04_mc_takedown;
  64                 engine->timer.init              = nv04_timer_init;
  65                 engine->timer.read              = nv04_timer_read;
  66                 engine->timer.takedown          = nv04_timer_takedown;
  67                 engine->fb.init                 = nv04_fb_init;
  68                 engine->fb.takedown             = nv04_fb_takedown;
  69                 engine->fifo.channels           = 16;
  70                 engine->fifo.init               = nv04_fifo_init;
  71                 engine->fifo.takedown           = nv04_fifo_fini;
  72                 engine->fifo.disable            = nv04_fifo_disable;
  73                 engine->fifo.enable             = nv04_fifo_enable;
  74                 engine->fifo.reassign           = nv04_fifo_reassign;
  75                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  76                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  77                 engine->fifo.create_context     = nv04_fifo_create_context;
  78                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  79                 engine->fifo.load_context       = nv04_fifo_load_context;
  80                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  81                 engine->display.early_init      = nv04_display_early_init;
  82                 engine->display.late_takedown   = nv04_display_late_takedown;
  83                 engine->display.create          = nv04_display_create;
  84                 engine->display.destroy         = nv04_display_destroy;
  85                 engine->display.init            = nv04_display_init;
  86                 engine->display.fini            = nv04_display_fini;
  87                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  88                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  89                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  90                 engine->vram.init               = nv04_fb_vram_init;
  91                 engine->vram.takedown           = nouveau_stub_takedown;
  92                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  93                 break;
  94         case 0x10:
  95                 engine->instmem.init            = nv04_instmem_init;
  96                 engine->instmem.takedown        = nv04_instmem_takedown;
  97                 engine->instmem.suspend         = nv04_instmem_suspend;
  98                 engine->instmem.resume          = nv04_instmem_resume;
  99                 engine->instmem.get             = nv04_instmem_get;
 100                 engine->instmem.put             = nv04_instmem_put;
 101                 engine->instmem.map             = nv04_instmem_map;
 102                 engine->instmem.unmap           = nv04_instmem_unmap;
 103                 engine->instmem.flush           = nv04_instmem_flush;
 104                 engine->mc.init                 = nv04_mc_init;
 105                 engine->mc.takedown             = nv04_mc_takedown;
 106                 engine->timer.init              = nv04_timer_init;
 107                 engine->timer.read              = nv04_timer_read;
 108                 engine->timer.takedown          = nv04_timer_takedown;
 109                 engine->fb.init                 = nv10_fb_init;
 110                 engine->fb.takedown             = nv10_fb_takedown;
 111                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 112                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 113                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 114                 engine->fifo.channels           = 32;
 115                 engine->fifo.init               = nv10_fifo_init;
 116                 engine->fifo.takedown           = nv04_fifo_fini;
 117                 engine->fifo.disable            = nv04_fifo_disable;
 118                 engine->fifo.enable             = nv04_fifo_enable;
 119                 engine->fifo.reassign           = nv04_fifo_reassign;
 120                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 121                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 122                 engine->fifo.create_context     = nv10_fifo_create_context;
 123                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 124                 engine->fifo.load_context       = nv10_fifo_load_context;
 125                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 126                 engine->display.early_init      = nv04_display_early_init;
 127                 engine->display.late_takedown   = nv04_display_late_takedown;
 128                 engine->display.create          = nv04_display_create;
 129                 engine->display.destroy         = nv04_display_destroy;
 130                 engine->display.init            = nv04_display_init;
 131                 engine->display.fini            = nv04_display_fini;
 132                 engine->gpio.drive              = nv10_gpio_drive;
 133                 engine->gpio.sense              = nv10_gpio_sense;
 134                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 135                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 136                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 137                 if (dev_priv->chipset == 0x1a ||
 138                     dev_priv->chipset == 0x1f)
 139                         engine->vram.init       = nv1a_fb_vram_init;
 140                 else
 141                         engine->vram.init       = nv10_fb_vram_init;
 142                 engine->vram.takedown           = nouveau_stub_takedown;
 143                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 144                 break;
 145         case 0x20:
 146                 engine->instmem.init            = nv04_instmem_init;
 147                 engine->instmem.takedown        = nv04_instmem_takedown;
 148                 engine->instmem.suspend         = nv04_instmem_suspend;
 149                 engine->instmem.resume          = nv04_instmem_resume;
 150                 engine->instmem.get             = nv04_instmem_get;
 151                 engine->instmem.put             = nv04_instmem_put;
 152                 engine->instmem.map             = nv04_instmem_map;
 153                 engine->instmem.unmap           = nv04_instmem_unmap;
 154                 engine->instmem.flush           = nv04_instmem_flush;
 155                 engine->mc.init                 = nv04_mc_init;
 156                 engine->mc.takedown             = nv04_mc_takedown;
 157                 engine->timer.init              = nv04_timer_init;
 158                 engine->timer.read              = nv04_timer_read;
 159                 engine->timer.takedown          = nv04_timer_takedown;
 160                 engine->fb.init                 = nv20_fb_init;
 161                 engine->fb.takedown             = nv20_fb_takedown;
 162                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 163                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 164                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 165                 engine->fifo.channels           = 32;
 166                 engine->fifo.init               = nv10_fifo_init;
 167                 engine->fifo.takedown           = nv04_fifo_fini;
 168                 engine->fifo.disable            = nv04_fifo_disable;
 169                 engine->fifo.enable             = nv04_fifo_enable;
 170                 engine->fifo.reassign           = nv04_fifo_reassign;
 171                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 172                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 173                 engine->fifo.create_context     = nv10_fifo_create_context;
 174                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 175                 engine->fifo.load_context       = nv10_fifo_load_context;
 176                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 177                 engine->display.early_init      = nv04_display_early_init;
 178                 engine->display.late_takedown   = nv04_display_late_takedown;
 179                 engine->display.create          = nv04_display_create;
 180                 engine->display.destroy         = nv04_display_destroy;
 181                 engine->display.init            = nv04_display_init;
 182                 engine->display.fini            = nv04_display_fini;
 183                 engine->gpio.drive              = nv10_gpio_drive;
 184                 engine->gpio.sense              = nv10_gpio_sense;
 185                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 186                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 187                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 188                 engine->vram.init               = nv20_fb_vram_init;
 189                 engine->vram.takedown           = nouveau_stub_takedown;
 190                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 191                 break;
 192         case 0x30:
 193                 engine->instmem.init            = nv04_instmem_init;
 194                 engine->instmem.takedown        = nv04_instmem_takedown;
 195                 engine->instmem.suspend         = nv04_instmem_suspend;
 196                 engine->instmem.resume          = nv04_instmem_resume;
 197                 engine->instmem.get             = nv04_instmem_get;
 198                 engine->instmem.put             = nv04_instmem_put;
 199                 engine->instmem.map             = nv04_instmem_map;
 200                 engine->instmem.unmap           = nv04_instmem_unmap;
 201                 engine->instmem.flush           = nv04_instmem_flush;
 202                 engine->mc.init                 = nv04_mc_init;
 203                 engine->mc.takedown             = nv04_mc_takedown;
 204                 engine->timer.init              = nv04_timer_init;
 205                 engine->timer.read              = nv04_timer_read;
 206                 engine->timer.takedown          = nv04_timer_takedown;
 207                 engine->fb.init                 = nv30_fb_init;
 208                 engine->fb.takedown             = nv30_fb_takedown;
 209                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 210                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 211                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 212                 engine->fifo.channels           = 32;
 213                 engine->fifo.init               = nv10_fifo_init;
 214                 engine->fifo.takedown           = nv04_fifo_fini;
 215                 engine->fifo.disable            = nv04_fifo_disable;
 216                 engine->fifo.enable             = nv04_fifo_enable;
 217                 engine->fifo.reassign           = nv04_fifo_reassign;
 218                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 219                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 220                 engine->fifo.create_context     = nv10_fifo_create_context;
 221                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 222                 engine->fifo.load_context       = nv10_fifo_load_context;
 223                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 224                 engine->display.early_init      = nv04_display_early_init;
 225                 engine->display.late_takedown   = nv04_display_late_takedown;
 226                 engine->display.create          = nv04_display_create;
 227                 engine->display.destroy         = nv04_display_destroy;
 228                 engine->display.init            = nv04_display_init;
 229                 engine->display.fini            = nv04_display_fini;
 230                 engine->gpio.drive              = nv10_gpio_drive;
 231                 engine->gpio.sense              = nv10_gpio_sense;
 232                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 233                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 234                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 235                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 236                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 237                 engine->vram.init               = nv20_fb_vram_init;
 238                 engine->vram.takedown           = nouveau_stub_takedown;
 239                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 240                 break;
 241         case 0x40:
 242         case 0x60:
 243                 engine->instmem.init            = nv04_instmem_init;
 244                 engine->instmem.takedown        = nv04_instmem_takedown;
 245                 engine->instmem.suspend         = nv04_instmem_suspend;
 246                 engine->instmem.resume          = nv04_instmem_resume;
 247                 engine->instmem.get             = nv04_instmem_get;
 248                 engine->instmem.put             = nv04_instmem_put;
 249                 engine->instmem.map             = nv04_instmem_map;
 250                 engine->instmem.unmap           = nv04_instmem_unmap;
 251                 engine->instmem.flush           = nv04_instmem_flush;
 252                 engine->mc.init                 = nv40_mc_init;
 253                 engine->mc.takedown             = nv40_mc_takedown;
 254                 engine->timer.init              = nv04_timer_init;
 255                 engine->timer.read              = nv04_timer_read;
 256                 engine->timer.takedown          = nv04_timer_takedown;
 257                 engine->fb.init                 = nv40_fb_init;
 258                 engine->fb.takedown             = nv40_fb_takedown;
 259                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 260                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 261                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 262                 engine->fifo.channels           = 32;
 263                 engine->fifo.init               = nv40_fifo_init;
 264                 engine->fifo.takedown           = nv04_fifo_fini;
 265                 engine->fifo.disable            = nv04_fifo_disable;
 266                 engine->fifo.enable             = nv04_fifo_enable;
 267                 engine->fifo.reassign           = nv04_fifo_reassign;
 268                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 269                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 270                 engine->fifo.create_context     = nv40_fifo_create_context;
 271                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 272                 engine->fifo.load_context       = nv40_fifo_load_context;
 273                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 274                 engine->display.early_init      = nv04_display_early_init;
 275                 engine->display.late_takedown   = nv04_display_late_takedown;
 276                 engine->display.create          = nv04_display_create;
 277                 engine->display.destroy         = nv04_display_destroy;
 278                 engine->display.init            = nv04_display_init;
 279                 engine->display.fini            = nv04_display_fini;
 280                 engine->gpio.init               = nv10_gpio_init;
 281                 engine->gpio.fini               = nv10_gpio_fini;
 282                 engine->gpio.drive              = nv10_gpio_drive;
 283                 engine->gpio.sense              = nv10_gpio_sense;
 284                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 285                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 286                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 287                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 288                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 289                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 290                 engine->pm.temp_get             = nv40_temp_get;
 291                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 292                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 293                 engine->vram.init               = nv40_fb_vram_init;
 294                 engine->vram.takedown           = nouveau_stub_takedown;
 295                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 296                 break;
 297         case 0x50:
 298         case 0x80: /* gotta love NVIDIA's consistency.. */
 299         case 0x90:
 300         case 0xa0:
 301                 engine->instmem.init            = nv50_instmem_init;
 302                 engine->instmem.takedown        = nv50_instmem_takedown;
 303                 engine->instmem.suspend         = nv50_instmem_suspend;
 304                 engine->instmem.resume          = nv50_instmem_resume;
 305                 engine->instmem.get             = nv50_instmem_get;
 306                 engine->instmem.put             = nv50_instmem_put;
 307                 engine->instmem.map             = nv50_instmem_map;
 308                 engine->instmem.unmap           = nv50_instmem_unmap;
 309                 if (dev_priv->chipset == 0x50)
 310                         engine->instmem.flush   = nv50_instmem_flush;
 311                 else
 312                         engine->instmem.flush   = nv84_instmem_flush;
 313                 engine->mc.init                 = nv50_mc_init;
 314                 engine->mc.takedown             = nv50_mc_takedown;
 315                 engine->timer.init              = nv04_timer_init;
 316                 engine->timer.read              = nv04_timer_read;
 317                 engine->timer.takedown          = nv04_timer_takedown;
 318                 engine->fb.init                 = nv50_fb_init;
 319                 engine->fb.takedown             = nv50_fb_takedown;
 320                 engine->fifo.channels           = 128;
 321                 engine->fifo.init               = nv50_fifo_init;
 322                 engine->fifo.takedown           = nv50_fifo_takedown;
 323                 engine->fifo.disable            = nv04_fifo_disable;
 324                 engine->fifo.enable             = nv04_fifo_enable;
 325                 engine->fifo.reassign           = nv04_fifo_reassign;
 326                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 327                 engine->fifo.create_context     = nv50_fifo_create_context;
 328                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 329                 engine->fifo.load_context       = nv50_fifo_load_context;
 330                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 331                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 332                 engine->display.early_init      = nv50_display_early_init;
 333                 engine->display.late_takedown   = nv50_display_late_takedown;
 334                 engine->display.create          = nv50_display_create;
 335                 engine->display.destroy         = nv50_display_destroy;
 336                 engine->display.init            = nv50_display_init;
 337                 engine->display.fini            = nv50_display_fini;
 338                 engine->gpio.init               = nv50_gpio_init;
 339                 engine->gpio.fini               = nv50_gpio_fini;
 340                 engine->gpio.drive              = nv50_gpio_drive;
 341                 engine->gpio.sense              = nv50_gpio_sense;
 342                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 343                 switch (dev_priv->chipset) {
 344                 case 0x84:
 345                 case 0x86:
 346                 case 0x92:
 347                 case 0x94:
 348                 case 0x96:
 349                 case 0x98:
 350                 case 0xa0:
 351                 case 0xaa:
 352                 case 0xac:
 353                 case 0x50:
 354                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 355                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 356                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 357                         break;
 358                 default:
 359                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 360                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 361                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 362                         break;
 363                 }
 364                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 365                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 366                 if (dev_priv->chipset >= 0x84)
 367                         engine->pm.temp_get     = nv84_temp_get;
 368                 else
 369                         engine->pm.temp_get     = nv40_temp_get;
 370                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 371                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 372                 engine->vram.init               = nv50_vram_init;
 373                 engine->vram.takedown           = nv50_vram_fini;
 374                 engine->vram.get                = nv50_vram_new;
 375                 engine->vram.put                = nv50_vram_del;
 376                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 377                 break;
 378         case 0xc0:
 379                 engine->instmem.init            = nvc0_instmem_init;
 380                 engine->instmem.takedown        = nvc0_instmem_takedown;
 381                 engine->instmem.suspend         = nvc0_instmem_suspend;
 382                 engine->instmem.resume          = nvc0_instmem_resume;
 383                 engine->instmem.get             = nv50_instmem_get;
 384                 engine->instmem.put             = nv50_instmem_put;
 385                 engine->instmem.map             = nv50_instmem_map;
 386                 engine->instmem.unmap           = nv50_instmem_unmap;
 387                 engine->instmem.flush           = nv84_instmem_flush;
 388                 engine->mc.init                 = nv50_mc_init;
 389                 engine->mc.takedown             = nv50_mc_takedown;
 390                 engine->timer.init              = nv04_timer_init;
 391                 engine->timer.read              = nv04_timer_read;
 392                 engine->timer.takedown          = nv04_timer_takedown;
 393                 engine->fb.init                 = nvc0_fb_init;
 394                 engine->fb.takedown             = nvc0_fb_takedown;
 395                 engine->fifo.channels           = 128;
 396                 engine->fifo.init               = nvc0_fifo_init;
 397                 engine->fifo.takedown           = nvc0_fifo_takedown;
 398                 engine->fifo.disable            = nvc0_fifo_disable;
 399                 engine->fifo.enable             = nvc0_fifo_enable;
 400                 engine->fifo.reassign           = nvc0_fifo_reassign;
 401                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 402                 engine->fifo.create_context     = nvc0_fifo_create_context;
 403                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 404                 engine->fifo.load_context       = nvc0_fifo_load_context;
 405                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 406                 engine->display.early_init      = nv50_display_early_init;
 407                 engine->display.late_takedown   = nv50_display_late_takedown;
 408                 engine->display.create          = nv50_display_create;
 409                 engine->display.destroy         = nv50_display_destroy;
 410                 engine->display.init            = nv50_display_init;
 411                 engine->display.fini            = nv50_display_fini;
 412                 engine->gpio.init               = nv50_gpio_init;
 413                 engine->gpio.fini               = nv50_gpio_fini;
 414                 engine->gpio.drive              = nv50_gpio_drive;
 415                 engine->gpio.sense              = nv50_gpio_sense;
 416                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 417                 engine->vram.init               = nvc0_vram_init;
 418                 engine->vram.takedown           = nv50_vram_fini;
 419                 engine->vram.get                = nvc0_vram_new;
 420                 engine->vram.put                = nv50_vram_del;
 421                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 422                 engine->pm.temp_get             = nv84_temp_get;
 423                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 424                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 425                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 426                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 427                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 428                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 429                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 430                 break;
 431         case 0xd0:
 432                 engine->instmem.init            = nvc0_instmem_init;
 433                 engine->instmem.takedown        = nvc0_instmem_takedown;
 434                 engine->instmem.suspend         = nvc0_instmem_suspend;
 435                 engine->instmem.resume          = nvc0_instmem_resume;
 436                 engine->instmem.get             = nv50_instmem_get;
 437                 engine->instmem.put             = nv50_instmem_put;
 438                 engine->instmem.map             = nv50_instmem_map;
 439                 engine->instmem.unmap           = nv50_instmem_unmap;
 440                 engine->instmem.flush           = nv84_instmem_flush;
 441                 engine->mc.init                 = nv50_mc_init;
 442                 engine->mc.takedown             = nv50_mc_takedown;
 443                 engine->timer.init              = nv04_timer_init;
 444                 engine->timer.read              = nv04_timer_read;
 445                 engine->timer.takedown          = nv04_timer_takedown;
 446                 engine->fb.init                 = nvc0_fb_init;
 447                 engine->fb.takedown             = nvc0_fb_takedown;
 448                 engine->fifo.channels           = 128;
 449                 engine->fifo.init               = nvc0_fifo_init;
 450                 engine->fifo.takedown           = nvc0_fifo_takedown;
 451                 engine->fifo.disable            = nvc0_fifo_disable;
 452                 engine->fifo.enable             = nvc0_fifo_enable;
 453                 engine->fifo.reassign           = nvc0_fifo_reassign;
 454                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 455                 engine->fifo.create_context     = nvc0_fifo_create_context;
 456                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 457                 engine->fifo.load_context       = nvc0_fifo_load_context;
 458                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 459                 engine->display.early_init      = nouveau_stub_init;
 460                 engine->display.late_takedown   = nouveau_stub_takedown;
 461                 engine->display.create          = nvd0_display_create;
 462                 engine->display.destroy         = nvd0_display_destroy;
 463                 engine->display.init            = nvd0_display_init;
 464                 engine->display.fini            = nvd0_display_fini;
 465                 engine->gpio.init               = nv50_gpio_init;
 466                 engine->gpio.fini               = nv50_gpio_fini;
 467                 engine->gpio.drive              = nvd0_gpio_drive;
 468                 engine->gpio.sense              = nvd0_gpio_sense;
 469                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 470                 engine->vram.init               = nvc0_vram_init;
 471                 engine->vram.takedown           = nv50_vram_fini;
 472                 engine->vram.get                = nvc0_vram_new;
 473                 engine->vram.put                = nv50_vram_del;
 474                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 475                 engine->pm.temp_get             = nv84_temp_get;
 476                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 477                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 478                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 479                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 480                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 481                 break;
 482         default:
 483                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 484                 return 1;
 485         }
 486
 487         /* headless mode */
 488         if (nouveau_modeset == 2) {
 489                 engine->display.early_init = nouveau_stub_init;
 490                 engine->display.late_takedown = nouveau_stub_takedown;
 491                 engine->display.create = nouveau_stub_init;
 492                 engine->display.init = nouveau_stub_init;
 493                 engine->display.destroy = nouveau_stub_takedown;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static unsigned int
 500 nouveau_vga_set_decode(void *priv, bool state)
 501 {
 502         struct drm_device *dev = priv;
 503         struct drm_nouveau_private *dev_priv = dev->dev_private;
 504
 505         if (dev_priv->chipset >= 0x40)
 506                 nv_wr32(dev, 0x88054, state);
 507         else
 508                 nv_wr32(dev, 0x1854, state);
 509
 510         if (state)
 511                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 512                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 513         else
 514                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 515 }
 516
 517 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 518                                          enum vga_switcheroo_state state)
 519 {
 520         struct drm_device *dev = pci_get_drvdata(pdev);
 521         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 522         if (state == VGA_SWITCHEROO_ON) {
 523                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 524                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 525                 nouveau_pci_resume(pdev);
 526                 drm_kms_helper_poll_enable(dev);
 527                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 528         } else {
 529                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 530                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 531                 drm_kms_helper_poll_disable(dev);
 532                 nouveau_switcheroo_optimus_dsm();
 533                 nouveau_pci_suspend(pdev, pmm);
 534                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 535         }
 536 }
 537
 538 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 539 {
 540         struct drm_device *dev = pci_get_drvdata(pdev);
 541         nouveau_fbcon_output_poll_changed(dev);
 542 }
 543
 544 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 545 {
 546         struct drm_device *dev = pci_get_drvdata(pdev);
 547         bool can_switch;
 548
 549         spin_lock(&dev->count_lock);
 550         can_switch = (dev->open_count == 0);
 551         spin_unlock(&dev->count_lock);
 552         return can_switch;
 553 }
 554
 555 int
 556 nouveau_card_init(struct drm_device *dev)
 557 {
 558         struct drm_nouveau_private *dev_priv = dev->dev_private;
 559         struct nouveau_engine *engine;
 560         int ret, e = 0;
 561
 562         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 563         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 564                                        nouveau_switcheroo_reprobe,
 565                                        nouveau_switcheroo_can_switch);
 566
 567         /* Initialise internal driver API hooks */
 568         ret = nouveau_init_engine_ptrs(dev);
 569         if (ret)
 570                 goto out;
 571         engine = &dev_priv->engine;
 572         spin_lock_init(&dev_priv->channels.lock);
 573         spin_lock_init(&dev_priv->tile.lock);
 574         spin_lock_init(&dev_priv->context_switch_lock);
 575         spin_lock_init(&dev_priv->vm_lock);
 576
 577         /* Make the CRTCs and I2C buses accessible */
 578         ret = engine->display.early_init(dev);
 579         if (ret)
 580                 goto out;
 581
 582         /* Parse BIOS tables / Run init tables if card not POSTed */
 583         ret = nouveau_bios_init(dev);
 584         if (ret)
 585                 goto out_display_early;
 586
 587         /* workaround an odd issue on nvc1 by disabling the device's
 588          * nosnoop capability.  hopefully won't cause issues until a
 589          * better fix is found - assuming there is one...
 590          */
 591         if (dev_priv->chipset == 0xc1) {
 592                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 593         }
 594
 595         /* PMC */
 596         ret = engine->mc.init(dev);
 597         if (ret)
 598                 goto out_bios;
 599
 600         /* PTIMER */
 601         ret = engine->timer.init(dev);
 602         if (ret)
 603                 goto out_mc;
 604
 605         /* PFB */
 606         ret = engine->fb.init(dev);
 607         if (ret)
 608                 goto out_timer;
 609
 610         ret = engine->vram.init(dev);
 611         if (ret)
 612                 goto out_fb;
 613
 614         /* PGPIO */
 615         ret = nouveau_gpio_create(dev);
 616         if (ret)
 617                 goto out_vram;
 618
 619         ret = nouveau_gpuobj_init(dev);
 620         if (ret)
 621                 goto out_gpio;
 622
 623         ret = engine->instmem.init(dev);
 624         if (ret)
 625                 goto out_gpuobj;
 626
 627         ret = nouveau_mem_vram_init(dev);
 628         if (ret)
 629                 goto out_instmem;
 630
 631         ret = nouveau_mem_gart_init(dev);
 632         if (ret)
 633                 goto out_ttmvram;
 634
 635         if (!dev_priv->noaccel) {
 636                 switch (dev_priv->card_type) {
 637                 case NV_04:
 638                         nv04_graph_create(dev);
 639                         break;
 640                 case NV_10:
 641                         nv10_graph_create(dev);
 642                         break;
 643                 case NV_20:
 644                 case NV_30:
 645                         nv20_graph_create(dev);
 646                         break;
 647                 case NV_40:
 648                         nv40_graph_create(dev);
 649                         break;
 650                 case NV_50:
 651                         nv50_graph_create(dev);
 652                         break;
 653                 case NV_C0:
 654                 case NV_D0:
 655                         nvc0_graph_create(dev);
 656                         break;
 657                 default:
 658                         break;
 659                 }
 660
 661                 switch (dev_priv->chipset) {
 662                 case 0x84:
 663                 case 0x86:
 664                 case 0x92:
 665                 case 0x94:
 666                 case 0x96:
 667                 case 0xa0:
 668                         nv84_crypt_create(dev);
 669                         break;
 670                 case 0x98:
 671                 case 0xaa:
 672                 case 0xac:
 673                         nv98_crypt_create(dev);
 674                         break;
 675                 }
 676
 677                 switch (dev_priv->card_type) {
 678                 case NV_50:
 679                         switch (dev_priv->chipset) {
 680                         case 0xa3:
 681                         case 0xa5:
 682                         case 0xa8:
 683                         case 0xaf:
 684                                 nva3_copy_create(dev);
 685                                 break;
 686                         }
 687                         break;
 688                 case NV_C0:
 689                         nvc0_copy_create(dev, 0);
 690                         nvc0_copy_create(dev, 1);
 691                         break;
 692                 default:
 693                         break;
 694                 }
 695
 696                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 697                         nv84_bsp_create(dev);
 698                         nv84_vp_create(dev);
 699                         nv98_ppp_create(dev);
 700                 } else
 701                 if (dev_priv->chipset >= 0x84) {
 702                         nv50_mpeg_create(dev);
 703                         nv84_bsp_create(dev);
 704                         nv84_vp_create(dev);
 705                 } else
 706                 if (dev_priv->chipset >= 0x50) {
 707                         nv50_mpeg_create(dev);
 708                 } else
 709                 if (dev_priv->card_type == NV_40 ||
 710                     dev_priv->chipset == 0x31 ||
 711                     dev_priv->chipset == 0x34 ||
 712                     dev_priv->chipset == 0x36) {
 713                         nv31_mpeg_create(dev);
 714                 }
 715
 716                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 717                         if (dev_priv->eng[e]) {
 718                                 ret = dev_priv->eng[e]->init(dev, e);
 719                                 if (ret)
 720                                         goto out_engine;
 721                         }
 722                 }
 723
 724                 /* PFIFO */
 725                 ret = engine->fifo.init(dev);
 726                 if (ret)
 727                         goto out_engine;
 728         }
 729
 730         ret = nouveau_irq_init(dev);
 731         if (ret)
 732                 goto out_fifo;
 733
 734         ret = nouveau_display_create(dev);
 735         if (ret)
 736                 goto out_irq;
 737
 738         nouveau_backlight_init(dev);
 739         nouveau_pm_init(dev);
 740
 741         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 742                 ret = nouveau_fence_init(dev);
 743                 if (ret)
 744                         goto out_pm;
 745
 746                 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
 747                                             NvDmaFB, NvDmaTT);
 748                 if (ret)
 749                         goto out_fence;
 750
 751                 mutex_unlock(&dev_priv->channel->mutex);
 752         }
 753
 754         if (dev->mode_config.num_crtc) {
 755                 ret = nouveau_display_init(dev);
 756                 if (ret)
 757                         goto out_chan;
 758
 759                 nouveau_fbcon_init(dev);
 760         }
 761
 762         return 0;
 763
 764 out_chan:
 765         nouveau_channel_put_unlocked(&dev_priv->channel);
 766 out_fence:
 767         nouveau_fence_fini(dev);
 768 out_pm:
 769         nouveau_pm_fini(dev);
 770         nouveau_backlight_exit(dev);
 771         nouveau_display_destroy(dev);
 772 out_irq:
 773         nouveau_irq_fini(dev);
 774 out_fifo:
 775         if (!dev_priv->noaccel)
 776                 engine->fifo.takedown(dev);
 777 out_engine:
 778         if (!dev_priv->noaccel) {
 779                 for (e = e - 1; e >= 0; e--) {
 780                         if (!dev_priv->eng[e])
 781                                 continue;
 782                         dev_priv->eng[e]->fini(dev, e, false);
 783                         dev_priv->eng[e]->destroy(dev,e );
 784                 }
 785         }
 786         nouveau_mem_gart_fini(dev);
 787 out_ttmvram:
 788         nouveau_mem_vram_fini(dev);
 789 out_instmem:
 790         engine->instmem.takedown(dev);
 791 out_gpuobj:
 792         nouveau_gpuobj_takedown(dev);
 793 out_gpio:
 794         nouveau_gpio_destroy(dev);
 795 out_vram:
 796         engine->vram.takedown(dev);
 797 out_fb:
 798         engine->fb.takedown(dev);
 799 out_timer:
 800         engine->timer.takedown(dev);
 801 out_mc:
 802         engine->mc.takedown(dev);
 803 out_bios:
 804         nouveau_bios_takedown(dev);
 805 out_display_early:
 806         engine->display.late_takedown(dev);
 807 out:
 808         vga_client_register(dev->pdev, NULL, NULL, NULL);
 809         return ret;
 810 }
 811
 812 static void nouveau_card_takedown(struct drm_device *dev)
 813 {
 814         struct drm_nouveau_private *dev_priv = dev->dev_private;
 815         struct nouveau_engine *engine = &dev_priv->engine;
 816         int e;
 817
 818         if (dev->mode_config.num_crtc) {
 819                 nouveau_fbcon_fini(dev);
 820                 nouveau_display_fini(dev);
 821         }
 822
 823         if (dev_priv->channel) {
 824                 nouveau_channel_put_unlocked(&dev_priv->channel);
 825                 nouveau_fence_fini(dev);
 826         }
 827
 828         nouveau_pm_fini(dev);
 829         nouveau_backlight_exit(dev);
 830         nouveau_display_destroy(dev);
 831
 832         if (!dev_priv->noaccel) {
 833                 engine->fifo.takedown(dev);
 834                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 835                         if (dev_priv->eng[e]) {
 836                                 dev_priv->eng[e]->fini(dev, e, false);
 837                                 dev_priv->eng[e]->destroy(dev,e );
 838                         }
 839                 }
 840         }
 841
 842         if (dev_priv->vga_ram) {
 843                 nouveau_bo_unpin(dev_priv->vga_ram);
 844                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 845         }
 846
 847         mutex_lock(&dev->struct_mutex);
 848         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 849         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 850         mutex_unlock(&dev->struct_mutex);
 851         nouveau_mem_gart_fini(dev);
 852         nouveau_mem_vram_fini(dev);
 853
 854         engine->instmem.takedown(dev);
 855         nouveau_gpuobj_takedown(dev);
 856
 857         nouveau_gpio_destroy(dev);
 858         engine->vram.takedown(dev);
 859         engine->fb.takedown(dev);
 860         engine->timer.takedown(dev);
 861         engine->mc.takedown(dev);
 862
 863         nouveau_bios_takedown(dev);
 864         engine->display.late_takedown(dev);
 865
 866         nouveau_irq_fini(dev);
 867
 868         vga_client_register(dev->pdev, NULL, NULL, NULL);
 869 }
 870
 871 int
 872 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 873 {
 874         struct drm_nouveau_private *dev_priv = dev->dev_private;
 875         struct nouveau_fpriv *fpriv;
 876         int ret;
 877
 878         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 879         if (unlikely(!fpriv))
 880                 return -ENOMEM;
 881
 882         spin_lock_init(&fpriv->lock);
 883         INIT_LIST_HEAD(&fpriv->channels);
 884
 885         if (dev_priv->card_type == NV_50) {
 886                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 887                                      &fpriv->vm);
 888                 if (ret) {
 889                         kfree(fpriv);
 890                         return ret;
 891                 }
 892         } else
 893         if (dev_priv->card_type >= NV_C0) {
 894                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 895                                      &fpriv->vm);
 896                 if (ret) {
 897                         kfree(fpriv);
 898                         return ret;
 899                 }
 900         }
 901
 902         file_priv->driver_priv = fpriv;
 903         return 0;
 904 }
 905
 906 /* here a client dies, release the stuff that was allocated for its
 907  * file_priv */
 908 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 909 {
 910         nouveau_channel_cleanup(dev, file_priv);
 911 }
 912
 913 void
 914 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
 915 {
 916         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 917         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
 918         kfree(fpriv);
 919 }
 920
 921 /* first module load, setup the mmio/fb mapping */
 922 /* KMS: we need mmio at load time, not when the first drm client opens. */
 923 int nouveau_firstopen(struct drm_device *dev)
 924 {
 925         return 0;
 926 }
 927
 928 /* if we have an OF card, copy vbios to RAMIN */
 929 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 930 {
 931 #if defined(__powerpc__)
 932         int size, i;
 933         const uint32_t *bios;
 934         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 935         if (!dn) {
 936                 NV_INFO(dev, "Unable to get the OF node\n");
 937                 return;
 938         }
 939
 940         bios = of_get_property(dn, "NVDA,BMP", &size);
 941         if (bios) {
 942                 for (i = 0; i < size; i += 4)
 943                         nv_wi32(dev, i, bios[i/4]);
 944                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 945         } else {
 946                 NV_INFO(dev, "Unable to get the OF bios\n");
 947         }
 948 #endif
 949 }
 950
 951 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 952 {
 953         struct pci_dev *pdev = dev->pdev;
 954         struct apertures_struct *aper = alloc_apertures(3);
 955         if (!aper)
 956                 return NULL;
 957
 958         aper->ranges[0].base = pci_resource_start(pdev, 1);
 959         aper->ranges[0].size = pci_resource_len(pdev, 1);
 960         aper->count = 1;
 961
 962         if (pci_resource_len(pdev, 2)) {
 963                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 964                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 965                 aper->count++;
 966         }
 967
 968         if (pci_resource_len(pdev, 3)) {
 969                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 970                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 971                 aper->count++;
 972         }
 973
 974         return aper;
 975 }
 976
 977 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 978 {
 979         struct drm_nouveau_private *dev_priv = dev->dev_private;
 980         bool primary = false;
 981         dev_priv->apertures = nouveau_get_apertures(dev);
 982         if (!dev_priv->apertures)
 983                 return -ENOMEM;
 984
 985 #ifdef CONFIG_X86
 986         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 987 #endif
 988
 989         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 990         return 0;
 991 }
 992
 993 int nouveau_load(struct drm_device *dev, unsigned long flags)
 994 {
 995         struct drm_nouveau_private *dev_priv;
 996         uint32_t reg0 = ~0, strap;
 997         resource_size_t mmio_start_offs;
 998         int ret;
 999
1000         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1001         if (!dev_priv) {
1002                 ret = -ENOMEM;
1003                 goto err_out;
1004         }
1005         dev->dev_private = dev_priv;
1006         dev_priv->dev = dev;
1007
1008         pci_set_master(dev->pdev);
1009
1010         dev_priv->flags = flags & NOUVEAU_FLAGS;
1011
1012         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1013                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1014
1015         /* first up, map the start of mmio and determine the chipset */
1016         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1017         if (dev_priv->mmio) {
1018 #ifdef __BIG_ENDIAN
1019                 /* put the card into big-endian mode if it's not */
1020                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1021                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1022                 DRM_MEMORYBARRIER();
1023 #endif
1024
1025                 /* determine chipset and derive architecture from it */
1026                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1027                 if ((reg0 & 0x0f000000) > 0) {
1028                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1029                         switch (dev_priv->chipset & 0xf0) {
1030                         case 0x10:
1031                         case 0x20:
1032                         case 0x30:
1033                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1034                                 break;
1035                         case 0x40:
1036                         case 0x60:
1037                                 dev_priv->card_type = NV_40;
1038                                 break;
1039                         case 0x50:
1040                         case 0x80:
1041                         case 0x90:
1042                         case 0xa0:
1043                                 dev_priv->card_type = NV_50;
1044                                 break;
1045                         case 0xc0:
1046                                 dev_priv->card_type = NV_C0;
1047                                 break;
1048                         case 0xd0:
1049                                 dev_priv->card_type = NV_D0;
1050                                 break;
1051                         default:
1052                                 break;
1053                         }
1054                 } else
1055                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1056                         if (reg0 & 0x00f00000)
1057                                 dev_priv->chipset = 0x05;
1058                         else
1059                                 dev_priv->chipset = 0x04;
1060                         dev_priv->card_type = NV_04;
1061                 }
1062
1063                 iounmap(dev_priv->mmio);
1064         }
1065
1066         if (!dev_priv->card_type) {
1067                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1068                 ret = -EINVAL;
1069                 goto err_priv;
1070         }
1071
1072         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1073                      dev_priv->card_type, reg0);
1074
1075         /* map the mmio regs */
1076         mmio_start_offs = pci_resource_start(dev->pdev, 0);
1077         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
1078         if (!dev_priv->mmio) {
1079                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1080                          "Please report your setup to " DRIVER_EMAIL "\n");
1081                 ret = -EINVAL;
1082                 goto err_priv;
1083         }
1084         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
1085                                         (unsigned long long)mmio_start_offs);
1086
1087         /* determine frequency of timing crystal */
1088         strap = nv_rd32(dev, 0x101000);
1089         if ( dev_priv->chipset < 0x17 ||
1090             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1091                 strap &= 0x00000040;
1092         else
1093                 strap &= 0x00400040;
1094
1095         switch (strap) {
1096         case 0x00000000: dev_priv->crystal = 13500; break;
1097         case 0x00000040: dev_priv->crystal = 14318; break;
1098         case 0x00400000: dev_priv->crystal = 27000; break;
1099         case 0x00400040: dev_priv->crystal = 25000; break;
1100         }
1101
1102         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1103
1104         /* Determine whether we'll attempt acceleration or not, some
1105          * cards are disabled by default here due to them being known
1106          * non-functional, or never been tested due to lack of hw.
1107          */
1108         dev_priv->noaccel = !!nouveau_noaccel;
1109         if (nouveau_noaccel == -1) {
1110                 switch (dev_priv->chipset) {
1111                 case 0xd9: /* known broken */
1112                         NV_INFO(dev, "acceleration disabled by default, pass "
1113                                      "noaccel=0 to force enable\n");
1114                         dev_priv->noaccel = true;
1115                         break;
1116                 default:
1117                         dev_priv->noaccel = false;
1118                         break;
1119                 }
1120         }
1121
1122         ret = nouveau_remove_conflicting_drivers(dev);
1123         if (ret)
1124                 goto err_mmio;
1125
1126         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1127         if (dev_priv->card_type >= NV_40) {
1128                 int ramin_bar = 2;
1129                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1130                         ramin_bar = 3;
1131
1132                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1133                 dev_priv->ramin =
1134                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1135                                 dev_priv->ramin_size);
1136                 if (!dev_priv->ramin) {
1137                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1138                         ret = -ENOMEM;
1139                         goto err_mmio;
1140                 }
1141         } else {
1142                 dev_priv->ramin_size = 1 * 1024 * 1024;
1143                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1144                                           dev_priv->ramin_size);
1145                 if (!dev_priv->ramin) {
1146                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1147                         ret = -ENOMEM;
1148                         goto err_mmio;
1149                 }
1150         }
1151
1152         nouveau_OF_copy_vbios_to_ramin(dev);
1153
1154         /* Special flags */
1155         if (dev->pci_device == 0x01a0)
1156                 dev_priv->flags |= NV_NFORCE;
1157         else if (dev->pci_device == 0x01f0)
1158                 dev_priv->flags |= NV_NFORCE2;
1159
1160         /* For kernel modesetting, init card now and bring up fbcon */
1161         ret = nouveau_card_init(dev);
1162         if (ret)
1163                 goto err_ramin;
1164
1165         return 0;
1166
1167 err_ramin:
1168         iounmap(dev_priv->ramin);
1169 err_mmio:
1170         iounmap(dev_priv->mmio);
1171 err_priv:
1172         kfree(dev_priv);
1173         dev->dev_private = NULL;
1174 err_out:
1175         return ret;
1176 }
1177
1178 void nouveau_lastclose(struct drm_device *dev)
1179 {
1180         vga_switcheroo_process_delayed_switch();
1181 }
1182
1183 int nouveau_unload(struct drm_device *dev)
1184 {
1185         struct drm_nouveau_private *dev_priv = dev->dev_private;
1186
1187         nouveau_card_takedown(dev);
1188
1189         iounmap(dev_priv->mmio);
1190         iounmap(dev_priv->ramin);
1191
1192         kfree(dev_priv);
1193         dev->dev_private = NULL;
1194         return 0;
1195 }
1196
1197 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1198                                                 struct drm_file *file_priv)
1199 {
1200         struct drm_nouveau_private *dev_priv = dev->dev_private;
1201         struct drm_nouveau_getparam *getparam = data;
1202
1203         switch (getparam->param) {
1204         case NOUVEAU_GETPARAM_CHIPSET_ID:
1205                 getparam->value = dev_priv->chipset;
1206                 break;
1207         case NOUVEAU_GETPARAM_PCI_VENDOR:
1208                 getparam->value = dev->pci_vendor;
1209                 break;
1210         case NOUVEAU_GETPARAM_PCI_DEVICE:
1211                 getparam->value = dev->pci_device;
1212                 break;
1213         case NOUVEAU_GETPARAM_BUS_TYPE:
1214                 if (drm_pci_device_is_agp(dev))
1215                         getparam->value = NV_AGP;
1216                 else if (pci_is_pcie(dev->pdev))
1217                         getparam->value = NV_PCIE;
1218                 else
1219                         getparam->value = NV_PCI;
1220                 break;
1221         case NOUVEAU_GETPARAM_FB_SIZE:
1222                 getparam->value = dev_priv->fb_available_size;
1223                 break;
1224         case NOUVEAU_GETPARAM_AGP_SIZE:
1225                 getparam->value = dev_priv->gart_info.aper_size;
1226                 break;
1227         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1228                 getparam->value = 0; /* deprecated */
1229                 break;
1230         case NOUVEAU_GETPARAM_PTIMER_TIME:
1231                 getparam->value = dev_priv->engine.timer.read(dev);
1232                 break;
1233         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1234                 getparam->value = 1;
1235                 break;
1236         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1237                 getparam->value = 1;
1238                 break;
1239         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1240                 /* NV40 and NV50 versions are quite different, but register
1241                  * address is the same. User is supposed to know the card
1242                  * family anyway... */
1243                 if (dev_priv->chipset >= 0x40) {
1244                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1245                         break;
1246                 }
1247                 /* FALLTHRU */
1248         default:
1249                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1250                 return -EINVAL;
1251         }
1252
1253         return 0;
1254 }
1255
1256 int
1257 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1258                        struct drm_file *file_priv)
1259 {
1260         struct drm_nouveau_setparam *setparam = data;
1261
1262         switch (setparam->param) {
1263         default:
1264                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1265                 return -EINVAL;
1266         }
1267
1268         return 0;
1269 }
1270
1271 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1272 bool
1273 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1274                 uint32_t reg, uint32_t mask, uint32_t val)
1275 {
1276         struct drm_nouveau_private *dev_priv = dev->dev_private;
1277         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1278         uint64_t start = ptimer->read(dev);
1279
1280         do {
1281                 if ((nv_rd32(dev, reg) & mask) == val)
1282                         return true;
1283         } while (ptimer->read(dev) - start < timeout);
1284
1285         return false;
1286 }
1287
1288 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1289 bool
1290 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1291                 uint32_t reg, uint32_t mask, uint32_t val)
1292 {
1293         struct drm_nouveau_private *dev_priv = dev->dev_private;
1294         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1295         uint64_t start = ptimer->read(dev);
1296
1297         do {
1298                 if ((nv_rd32(dev, reg) & mask) != val)
1299                         return true;
1300         } while (ptimer->read(dev) - start < timeout);
1301
1302         return false;
1303 }
1304
1305 /* Wait until cond(data) == true, up until timeout has hit */
1306 bool
1307 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1308                 bool (*cond)(void *), void *data)
1309 {
1310         struct drm_nouveau_private *dev_priv = dev->dev_private;
1311         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1312         u64 start = ptimer->read(dev);
1313
1314         do {
1315                 if (cond(data) == true)
1316                         return true;
1317         } while (ptimer->read(dev) - start < timeout);
1318
1319         return false;
1320 }
1321
1322 /* Waits for PGRAPH to go completely idle */
1323 bool nouveau_wait_for_idle(struct drm_device *dev)
1324 {
1325         struct drm_nouveau_private *dev_priv = dev->dev_private;
1326         uint32_t mask = ~0;
1327
1328         if (dev_priv->card_type == NV_40)
1329                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1330
1331         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1332                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1333                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1334                 return false;
1335         }
1336
1337         return true;
1338 }
1339