2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
22 #include <core/tegra.h>
23 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
27 nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
31 ret = regulator_enable(tdev->vdd);
35 ret = clk_prepare_enable(tdev->clk);
39 ret = clk_prepare_enable(tdev->clk_ref);
43 ret = clk_prepare_enable(tdev->clk_pwr);
46 clk_set_rate(tdev->clk_pwr, 204000000);
49 reset_control_assert(tdev->rst);
52 ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
57 reset_control_deassert(tdev->rst);
63 clk_disable_unprepare(tdev->clk_pwr);
66 clk_disable_unprepare(tdev->clk_ref);
68 clk_disable_unprepare(tdev->clk);
70 regulator_disable(tdev->vdd);
76 nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
78 reset_control_assert(tdev->rst);
81 clk_disable_unprepare(tdev->clk_pwr);
83 clk_disable_unprepare(tdev->clk_ref);
84 clk_disable_unprepare(tdev->clk);
87 return regulator_disable(tdev->vdd);
91 nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev)
93 #if IS_ENABLED(CONFIG_IOMMU_API)
94 struct device *dev = &tdev->pdev->dev;
95 unsigned long pgsize_bitmap;
98 if (!tdev->func->iommu_bit)
101 mutex_init(&tdev->iommu.mutex);
103 if (iommu_present(&platform_bus_type)) {
104 tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type);
105 if (IS_ERR(tdev->iommu.domain))
109 * A IOMMU is only usable if it supports page sizes smaller
110 * or equal to the system's PAGE_SIZE, with a preference if
113 pgsize_bitmap = tdev->iommu.domain->ops->pgsize_bitmap;
114 if (pgsize_bitmap & PAGE_SIZE) {
115 tdev->iommu.pgshift = PAGE_SHIFT;
117 tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
118 if (tdev->iommu.pgshift == 0) {
119 dev_warn(dev, "unsupported IOMMU page size\n");
122 tdev->iommu.pgshift -= 1;
125 ret = iommu_attach_device(tdev->iommu.domain, dev);
129 ret = nvkm_mm_init(&tdev->iommu.mm, 0,
130 (1ULL << tdev->func->iommu_bit) >>
131 tdev->iommu.pgshift, 1);
139 iommu_detach_device(tdev->iommu.domain, dev);
142 iommu_domain_free(tdev->iommu.domain);
145 tdev->iommu.domain = NULL;
146 tdev->iommu.pgshift = 0;
147 dev_err(dev, "cannot initialize IOMMU MM\n");
152 nvkm_device_tegra_remove_iommu(struct nvkm_device_tegra *tdev)
154 #if IS_ENABLED(CONFIG_IOMMU_API)
155 if (tdev->iommu.domain) {
156 nvkm_mm_fini(&tdev->iommu.mm);
157 iommu_detach_device(tdev->iommu.domain, tdev->device.dev);
158 iommu_domain_free(tdev->iommu.domain);
163 static struct nvkm_device_tegra *
164 nvkm_device_tegra(struct nvkm_device *device)
166 return container_of(device, struct nvkm_device_tegra, device);
169 static struct resource *
170 nvkm_device_tegra_resource(struct nvkm_device *device, unsigned bar)
172 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device);
173 return platform_get_resource(tdev->pdev, IORESOURCE_MEM, bar);
176 static resource_size_t
177 nvkm_device_tegra_resource_addr(struct nvkm_device *device, unsigned bar)
179 struct resource *res = nvkm_device_tegra_resource(device, bar);
180 return res ? res->start : 0;
183 static resource_size_t
184 nvkm_device_tegra_resource_size(struct nvkm_device *device, unsigned bar)
186 struct resource *res = nvkm_device_tegra_resource(device, bar);
187 return res ? resource_size(res) : 0;
191 nvkm_device_tegra_intr(int irq, void *arg)
193 struct nvkm_device_tegra *tdev = arg;
194 struct nvkm_mc *mc = tdev->device.mc;
195 bool handled = false;
197 nvkm_mc_intr_unarm(mc);
198 nvkm_mc_intr(mc, &handled);
199 nvkm_mc_intr_rearm(mc);
201 return handled ? IRQ_HANDLED : IRQ_NONE;
205 nvkm_device_tegra_fini(struct nvkm_device *device, bool suspend)
207 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device);
209 free_irq(tdev->irq, tdev);
215 nvkm_device_tegra_init(struct nvkm_device *device)
217 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device);
220 irq = platform_get_irq_byname(tdev->pdev, "stall");
224 ret = request_irq(irq, nvkm_device_tegra_intr,
225 IRQF_SHARED, "nvkm", tdev);
234 nvkm_device_tegra_dtor(struct nvkm_device *device)
236 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device);
237 nvkm_device_tegra_power_down(tdev);
238 nvkm_device_tegra_remove_iommu(tdev);
242 static const struct nvkm_device_func
243 nvkm_device_tegra_func = {
244 .tegra = nvkm_device_tegra,
245 .dtor = nvkm_device_tegra_dtor,
246 .init = nvkm_device_tegra_init,
247 .fini = nvkm_device_tegra_fini,
248 .resource_addr = nvkm_device_tegra_resource_addr,
249 .resource_size = nvkm_device_tegra_resource_size,
250 .cpu_coherent = false,
254 nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
255 struct platform_device *pdev,
256 const char *cfg, const char *dbg,
257 bool detect, bool mmio, u64 subdev_mask,
258 struct nvkm_device **pdevice)
260 struct nvkm_device_tegra *tdev;
263 if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL)))
269 tdev->vdd = devm_regulator_get(&pdev->dev, "vdd");
270 if (IS_ERR(tdev->vdd)) {
271 ret = PTR_ERR(tdev->vdd);
275 tdev->rst = devm_reset_control_get(&pdev->dev, "gpu");
276 if (IS_ERR(tdev->rst)) {
277 ret = PTR_ERR(tdev->rst);
281 tdev->clk = devm_clk_get(&pdev->dev, "gpu");
282 if (IS_ERR(tdev->clk)) {
283 ret = PTR_ERR(tdev->clk);
287 if (func->require_ref_clk)
288 tdev->clk_ref = devm_clk_get(&pdev->dev, "ref");
289 if (IS_ERR(tdev->clk_ref)) {
290 ret = PTR_ERR(tdev->clk_ref);
294 tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
295 if (IS_ERR(tdev->clk_pwr)) {
296 ret = PTR_ERR(tdev->clk_pwr);
301 * The IOMMU bit defines the upper limit of the GPU-addressable space.
302 * This will be refined in nouveau_ttm_init but we need to do it early
303 * for instmem to behave properly
305 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(tdev->func->iommu_bit));
309 nvkm_device_tegra_probe_iommu(tdev);
311 ret = nvkm_device_tegra_power_up(tdev);
315 tdev->gpu_speedo = tegra_sku_info.gpu_speedo_value;
316 ret = nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev,
317 NVKM_DEVICE_TEGRA, pdev->id, NULL,
318 cfg, dbg, detect, mmio, subdev_mask,
323 *pdevice = &tdev->device;
328 nvkm_device_tegra_power_down(tdev);
330 nvkm_device_tegra_remove_iommu(tdev);
337 nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
338 struct platform_device *pdev,
339 const char *cfg, const char *dbg,
340 bool detect, bool mmio, u64 subdev_mask,
341 struct nvkm_device **pdevice)