2 * Copyright 2014 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include <subdev/bios.h>
29 #include <subdev/bios/init.h>
30 #include <subdev/i2c.h>
32 #include <nvif/event.h>
46 nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay)
48 struct nvkm_dp *dp = lt->dp;
51 if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
52 mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
56 ret = nvkm_rdaux(dp->aux, DPCD_LS02, lt->stat, 6);
61 ret = nvkm_rdaux(dp->aux, DPCD_LS0C, <->pc2stat, 1);
64 OUTP_TRACE(&dp->outp, "status %6ph pc2 %02x",
65 lt->stat, lt->pc2stat);
67 OUTP_TRACE(&dp->outp, "status %6ph", lt->stat);
74 nvkm_dp_train_drive(struct lt_state *lt, bool pc)
76 struct nvkm_dp *dp = lt->dp;
79 for (i = 0; i < lt->link_nr; i++) {
80 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
81 u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3;
82 u8 lpre = (lane & 0x0c) >> 2;
83 u8 lvsw = (lane & 0x03) >> 0;
89 lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
91 lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
92 lvsw = hivs = 3 - (lpre & 3);
95 lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
98 lt->conf[i] = (lpre << 3) | lvsw;
99 lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
101 OUTP_TRACE(&dp->outp, "config lane %d %02x %02x",
102 i, lt->conf[i], lpc2);
103 dp->func->drv_ctl(dp, i, lvsw & 3, lpre & 3, lpc2 & 3);
106 ret = nvkm_wraux(dp->aux, DPCD_LC03(0), lt->conf, 4);
111 ret = nvkm_wraux(dp->aux, DPCD_LC0F, lt->pc2conf, 2);
120 nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)
122 struct nvkm_dp *dp = lt->dp;
125 OUTP_TRACE(&dp->outp, "training pattern %d", pattern);
126 dp->func->pattern(dp, pattern);
128 nvkm_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1);
129 sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
131 nvkm_wraux(dp->aux, DPCD_LC02, &sink_tp, 1);
135 nvkm_dp_train_eq(struct lt_state *lt)
137 bool eq_done = false, cr_done = true;
140 if (lt->dp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED)
141 nvkm_dp_train_pattern(lt, 3);
143 nvkm_dp_train_pattern(lt, 2);
147 nvkm_dp_train_drive(lt, lt->pc2)) ||
148 nvkm_dp_train_sense(lt, lt->pc2, 400))
151 eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
152 for (i = 0; i < lt->link_nr && eq_done; i++) {
153 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
154 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
156 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
157 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
160 } while (!eq_done && cr_done && ++tries <= 5);
162 return eq_done ? 0 : -1;
166 nvkm_dp_train_cr(struct lt_state *lt)
168 bool cr_done = false, abort = false;
169 int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
172 nvkm_dp_train_pattern(lt, 1);
175 if (nvkm_dp_train_drive(lt, false) ||
176 nvkm_dp_train_sense(lt, false, 100))
180 for (i = 0; i < lt->link_nr; i++) {
181 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
182 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
184 if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
190 if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
191 voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
194 } while (!cr_done && !abort && ++tries < 5);
196 return cr_done ? 0 : -1;
200 nvkm_dp_train_links(struct lt_state *lt)
202 struct nvkm_dp *dp = lt->dp;
203 struct nvkm_disp *disp = dp->outp.disp;
204 struct nvkm_subdev *subdev = &disp->engine.subdev;
205 struct nvkm_bios *bios = subdev->device->bios;
206 struct nvbios_init init = {
210 .outp = &dp->outp.info,
218 OUTP_DBG(&dp->outp, "%d lanes at %d KB/s", lt->link_nr, lt->link_bw);
220 /* Intersect misc. capabilities of the OR and sink. */
221 if (disp->engine.subdev.device->chipset < 0xd0)
222 dp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
223 lt->pc2 = dp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED;
225 /* Set desired link configuration on the source. */
226 if ((lnkcmp = lt->dp->info.lnkcmp)) {
227 if (dp->version < 0x30) {
228 while ((lt->link_bw / 10) < nvbios_rd16(bios, lnkcmp))
230 init.offset = nvbios_rd16(bios, lnkcmp + 2);
232 while ((lt->link_bw / 27000) < nvbios_rd08(bios, lnkcmp))
234 init.offset = nvbios_rd16(bios, lnkcmp + 1);
240 ret = dp->func->lnk_ctl(dp, lt->link_nr, lt->link_bw / 27000,
241 dp->dpcd[DPCD_RC02] &
242 DPCD_RC02_ENHANCED_FRAME_CAP);
245 OUTP_ERR(&dp->outp, "lnk_ctl failed with %d", ret);
249 dp->func->lnk_pwr(dp, lt->link_nr);
251 /* Set desired link configuration on the sink. */
252 sink[0] = lt->link_bw / 27000;
253 sink[1] = lt->link_nr;
254 if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
255 sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
257 return nvkm_wraux(dp->aux, DPCD_LC00_LINK_BW_SET, sink, 2);
261 nvkm_dp_train_fini(struct lt_state *lt)
263 struct nvkm_dp *dp = lt->dp;
264 struct nvkm_subdev *subdev = &dp->outp.disp->engine.subdev;
265 struct nvbios_init init = {
267 .bios = subdev->device->bios,
268 .outp = &dp->outp.info,
273 /* Execute AfterLinkTraining script from DP Info table. */
274 init.offset = dp->info.script[1],
279 nvkm_dp_train_init(struct lt_state *lt, bool spread)
281 struct nvkm_dp *dp = lt->dp;
282 struct nvkm_subdev *subdev = &dp->outp.disp->engine.subdev;
283 struct nvbios_init init = {
285 .bios = subdev->device->bios,
286 .outp = &dp->outp.info,
291 /* Execute EnableSpread/DisableSpread script from DP Info table. */
293 init.offset = dp->info.script[2];
295 init.offset = dp->info.script[3];
298 /* Execute BeforeLinkTraining script from DP Info table. */
299 init.offset = dp->info.script[0];
303 static const struct dp_rates {
307 } nvkm_dp_rates[] = {
308 { 2160000, 0x14, 4 },
309 { 1080000, 0x0a, 4 },
310 { 1080000, 0x14, 2 },
321 nvkm_dp_train(struct nvkm_dp *dp)
323 struct nv50_disp *disp = nv50_disp(dp->outp.disp);
324 const struct dp_rates *cfg = nvkm_dp_rates - 1;
325 struct lt_state lt = {
331 if (!dp->outp.info.location && disp->func->sor.magic)
332 disp->func->sor.magic(&dp->outp);
334 if ((dp->dpcd[2] & 0x1f) > dp->outp.info.dpconf.link_nr) {
335 dp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
336 dp->dpcd[2] |= dp->outp.info.dpconf.link_nr;
338 if (dp->dpcd[1] > dp->outp.info.dpconf.link_bw)
339 dp->dpcd[1] = dp->outp.info.dpconf.link_bw;
341 /* Ensure sink is not in a low-power state. */
342 if (!nvkm_rdaux(dp->aux, DPCD_SC00, &pwr, 1)) {
343 if ((pwr & DPCD_SC00_SET_POWER) != DPCD_SC00_SET_POWER_D0) {
344 pwr &= ~DPCD_SC00_SET_POWER;
345 pwr |= DPCD_SC00_SET_POWER_D0;
346 nvkm_wraux(dp->aux, DPCD_SC00, &pwr, 1);
351 nvkm_dp_train_init(<, dp->dpcd[3] & 0x01);
352 while (ret = -EIO, (++cfg)->rate) {
353 /* Skip configurations not supported by both OR and sink. */
354 while (cfg->nr > (dp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) ||
355 cfg->bw > (dp->dpcd[DPCD_RC01_MAX_LINK_RATE]))
357 lt.link_bw = cfg->bw * 27000;
358 lt.link_nr = cfg->nr;
360 /* Program selected link configuration. */
361 ret = nvkm_dp_train_links(<);
363 /* Attempt to train the link in this configuration. */
364 memset(lt.stat, 0x00, sizeof(lt.stat));
365 if (!nvkm_dp_train_cr(<) &&
366 !nvkm_dp_train_eq(<))
370 /* nvkm_dp_train_links() handled training, or
371 * we failed to communicate with the sink.
376 nvkm_dp_train_pattern(<, 0);
377 nvkm_dp_train_fini(<);
379 OUTP_ERR(&dp->outp, "training failed");
381 OUTP_DBG(&dp->outp, "training done");
382 atomic_set(&dp->lt.done, 1);
386 nvkm_output_dp_train(struct nvkm_outp *outp, u32 datarate)
388 struct nvkm_dp *dp = nvkm_dp(outp);
394 mutex_lock(&dp->mutex);
396 /* check that the link is trained at a high enough rate */
397 ret = nvkm_rdaux(dp->aux, DPCD_LC00_LINK_BW_SET, link, 2);
400 "failed to read link config, assuming no sink");
404 linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
405 linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */
406 datarate = (datarate + 9) / 10; /* -> decakilobits */
407 if (linkrate < datarate) {
408 OUTP_DBG(&dp->outp, "link not trained at sufficient rate");
412 /* check that link is still trained */
413 ret = nvkm_rdaux(dp->aux, DPCD_LS02, stat, 3);
416 "failed to read link status, assuming no sink");
420 if (stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE) {
421 for (i = 0; i < (link[1] & DPCD_LC01_LANE_COUNT_SET); i++) {
422 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f;
423 if (!(lane & DPCD_LS02_LANE0_CR_DONE) ||
424 !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
425 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) {
427 "lane %d not equalised", lane);
433 OUTP_DBG(&dp->outp, "no inter-lane alignment");
437 if (retrain || !atomic_read(&dp->lt.done)) {
438 /* no sink, but still need to configure source */
439 if (dp->dpcd[DPCD_RC00_DPCD_REV] == 0x00) {
440 dp->dpcd[DPCD_RC01_MAX_LINK_RATE] =
441 dp->outp.info.dpconf.link_bw;
442 dp->dpcd[DPCD_RC02] =
443 dp->outp.info.dpconf.link_nr;
448 mutex_unlock(&dp->mutex);
453 nvkm_dp_enable(struct nvkm_dp *dp, bool enable)
455 struct nvkm_i2c_aux *aux = dp->aux;
459 OUTP_DBG(&dp->outp, "aux power -> always");
460 nvkm_i2c_aux_monitor(aux, true);
464 if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd,
466 nvkm_output_dp_train(&dp->outp, 0);
472 OUTP_DBG(&dp->outp, "aux power -> demand");
473 nvkm_i2c_aux_monitor(aux, false);
477 atomic_set(&dp->lt.done, 0);
481 nvkm_dp_hpd(struct nvkm_notify *notify)
483 const struct nvkm_i2c_ntfy_rep *line = notify->data;
484 struct nvkm_dp *dp = container_of(notify, typeof(*dp), hpd);
485 struct nvkm_conn *conn = dp->outp.conn;
486 struct nvkm_disp *disp = dp->outp.disp;
487 struct nvif_notify_conn_rep_v0 rep = {};
489 OUTP_DBG(&dp->outp, "HPD: %d", line->mask);
490 nvkm_dp_enable(dp, true);
492 if (line->mask & NVKM_I2C_UNPLUG)
493 rep.mask |= NVIF_NOTIFY_CONN_V0_UNPLUG;
494 if (line->mask & NVKM_I2C_PLUG)
495 rep.mask |= NVIF_NOTIFY_CONN_V0_PLUG;
497 nvkm_event_send(&disp->hpd, rep.mask, conn->index, &rep, sizeof(rep));
498 return NVKM_NOTIFY_KEEP;
502 nvkm_dp_irq(struct nvkm_notify *notify)
504 const struct nvkm_i2c_ntfy_rep *line = notify->data;
505 struct nvkm_dp *dp = container_of(notify, typeof(*dp), irq);
506 struct nvkm_conn *conn = dp->outp.conn;
507 struct nvkm_disp *disp = dp->outp.disp;
508 struct nvif_notify_conn_rep_v0 rep = {
509 .mask = NVIF_NOTIFY_CONN_V0_IRQ,
512 OUTP_DBG(&dp->outp, "IRQ: %d", line->mask);
513 nvkm_output_dp_train(&dp->outp, 0);
515 nvkm_event_send(&disp->hpd, rep.mask, conn->index, &rep, sizeof(rep));
516 return NVKM_NOTIFY_KEEP;
520 nvkm_dp_fini(struct nvkm_outp *outp)
522 struct nvkm_dp *dp = nvkm_dp(outp);
523 nvkm_notify_put(&dp->hpd);
524 nvkm_notify_put(&dp->irq);
525 nvkm_dp_enable(dp, false);
529 nvkm_dp_init(struct nvkm_outp *outp)
531 struct nvkm_dp *dp = nvkm_dp(outp);
532 nvkm_notify_put(&dp->outp.conn->hpd);
533 nvkm_dp_enable(dp, true);
534 nvkm_notify_get(&dp->irq);
535 nvkm_notify_get(&dp->hpd);
539 nvkm_dp_dtor(struct nvkm_outp *outp)
541 struct nvkm_dp *dp = nvkm_dp(outp);
542 nvkm_notify_fini(&dp->hpd);
543 nvkm_notify_fini(&dp->irq);
547 static const struct nvkm_outp_func
549 .dtor = nvkm_dp_dtor,
550 .init = nvkm_dp_init,
551 .fini = nvkm_dp_fini,
555 nvkm_dp_ctor(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
556 struct nvkm_i2c_aux *aux, struct nvkm_dp *dp)
558 struct nvkm_device *device = disp->engine.subdev.device;
559 struct nvkm_bios *bios = device->bios;
560 struct nvkm_i2c *i2c = device->i2c;
565 ret = nvkm_outp_ctor(&nvkm_dp_func, disp, index, dcbE, &dp->outp);
571 OUTP_ERR(&dp->outp, "no aux");
575 /* bios data is not optional */
576 data = nvbios_dpout_match(bios, dp->outp.info.hasht,
577 dp->outp.info.hashm, &dp->version,
578 &hdr, &cnt, &len, &dp->info);
580 OUTP_ERR(&dp->outp, "no bios dp data");
584 OUTP_DBG(&dp->outp, "bios dp %02x %02x %02x %02x",
585 dp->version, hdr, cnt, len);
587 /* link maintenance */
588 ret = nvkm_notify_init(NULL, &i2c->event, nvkm_dp_irq, true,
589 &(struct nvkm_i2c_ntfy_req) {
590 .mask = NVKM_I2C_IRQ,
593 sizeof(struct nvkm_i2c_ntfy_req),
594 sizeof(struct nvkm_i2c_ntfy_rep),
597 OUTP_ERR(&dp->outp, "error monitoring aux irq: %d", ret);
601 mutex_init(&dp->mutex);
602 atomic_set(&dp->lt.done, 0);
604 /* hotplug detect, replaces gpio-based mechanism with aux events */
605 ret = nvkm_notify_init(NULL, &i2c->event, nvkm_dp_hpd, true,
606 &(struct nvkm_i2c_ntfy_req) {
607 .mask = NVKM_I2C_PLUG | NVKM_I2C_UNPLUG,
610 sizeof(struct nvkm_i2c_ntfy_req),
611 sizeof(struct nvkm_i2c_ntfy_rep),
614 OUTP_ERR(&dp->outp, "error monitoring aux hpd: %d", ret);
622 nvkm_output_dp_new_(const struct nvkm_output_dp_func *func,
623 struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
624 struct nvkm_outp **poutp)
626 struct nvkm_i2c *i2c = disp->engine.subdev.device->i2c;
627 struct nvkm_i2c_aux *aux;
630 if (dcbE->location == 0)
631 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_CCB(dcbE->i2c_index));
633 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbE->extdev));
635 if (!(dp = kzalloc(sizeof(*dp), GFP_KERNEL)))
640 return nvkm_dp_ctor(disp, index, dcbE, aux, dp);