drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "head.h"
  26 #include "rootnv50.h"
  27
  28 #include <subdev/bios.h>
  29 #include <subdev/bios/disp.h>
  30 #include <subdev/bios/init.h>
  31 #include <subdev/bios/pll.h>
  32 #include <subdev/devinit.h>
  33
  34 void
  35 gf119_disp_vblank_init(struct nv50_disp *disp, int head)
  36 {
  37         struct nvkm_device *device = disp->base.engine.subdev.device;
  38         nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
  39 }
  40
  41 void
  42 gf119_disp_vblank_fini(struct nv50_disp *disp, int head)
  43 {
  44         struct nvkm_device *device = disp->base.engine.subdev.device;
  45         nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
  46 }
  47
  48 static struct nvkm_output *
  49 exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
  50             u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
  51             struct nvbios_outp *info)
  52 {
  53         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
  54         struct nvkm_bios *bios = subdev->device->bios;
  55         struct nvkm_output *outp;
  56         u16 mask, type;
  57
  58         if (or < 4) {
  59                 type = DCB_OUTPUT_ANALOG;
  60                 mask = 0;
  61         } else {
  62                 or -= 4;
  63                 switch (ctrl & 0x00000f00) {
  64                 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
  65                 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
  66                 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
  67                 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
  68                 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
  69                 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
  70                 default:
  71                         nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl);
  72                         return NULL;
  73                 }
  74         }
  75
  76         mask  = 0x00c0 & (mask << 6);
  77         mask |= 0x0001 << or;
  78         mask |= 0x0100 << head;
  79
  80         list_for_each_entry(outp, &disp->base.outp, head) {
  81                 if ((outp->info.hasht & 0xff) == type &&
  82                     (outp->info.hashm & mask) == mask) {
  83                         *data = nvbios_outp_match(bios, outp->info.hasht, mask,
  84                                                   ver, hdr, cnt, len, info);
  85                         if (!*data)
  86                                 return NULL;
  87                         return outp;
  88                 }
  89         }
  90
  91         return NULL;
  92 }
  93
  94 static struct nvkm_output *
  95 exec_script(struct nv50_disp *disp, int head, int id)
  96 {
  97         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
  98         struct nvkm_device *device = subdev->device;
  99         struct nvkm_bios *bios = device->bios;
 100         struct nvkm_output *outp;
 101         struct nvbios_outp info;
 102         u8  ver, hdr, cnt, len;
 103         u32 data, ctrl = 0;
 104         int or;
 105
 106         for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
 107                 ctrl = nvkm_rd32(device, 0x640180 + (or * 0x20));
 108                 if (ctrl & (1 << head))
 109                         break;
 110         }
 111
 112         if (or == 8)
 113                 return NULL;
 114
 115         outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
 116         if (outp) {
 117                 struct nvbios_init init = {
 118                         .subdev = subdev,
 119                         .bios = bios,
 120                         .offset = info.script[id],
 121                         .outp = &outp->info,
 122                         .crtc = head,
 123                         .execute = 1,
 124                 };
 125
 126                 nvbios_exec(&init);
 127         }
 128
 129         return outp;
 130 }
 131
 132 static struct nvkm_output *
 133 exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
 134 {
 135         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 136         struct nvkm_device *device = subdev->device;
 137         struct nvkm_bios *bios = device->bios;
 138         struct nvkm_output *outp;
 139         struct nvbios_outp info1;
 140         struct nvbios_ocfg info2;
 141         u8  ver, hdr, cnt, len;
 142         u32 data, ctrl = 0;
 143         int or;
 144
 145         for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
 146                 ctrl = nvkm_rd32(device, 0x660180 + (or * 0x20));
 147                 if (ctrl & (1 << head))
 148                         break;
 149         }
 150
 151         if (or == 8)
 152                 return NULL;
 153
 154         outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
 155         if (!outp)
 156                 return NULL;
 157
 158         *conf = (ctrl & 0x00000f00) >> 8;
 159         switch (outp->info.type) {
 160         case DCB_OUTPUT_TMDS:
 161                 if (*conf == 5)
 162                         *conf |= 0x0100;
 163                 break;
 164         case DCB_OUTPUT_LVDS:
 165                 *conf |= disp->sor.lvdsconf;
 166                 break;
 167         default:
 168                 break;
 169         }
 170
 171         data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8,
 172                                  &ver, &hdr, &cnt, &len, &info2);
 173         if (data && id < 0xff) {
 174                 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
 175                 if (data) {
 176                         struct nvbios_init init = {
 177                                 .subdev = subdev,
 178                                 .bios = bios,
 179                                 .offset = data,
 180                                 .outp = &outp->info,
 181                                 .crtc = head,
 182                                 .execute = 1,
 183                         };
 184
 185                         nvbios_exec(&init);
 186                 }
 187         }
 188
 189         return outp;
 190 }
 191
 192 static void
 193 gf119_disp_intr_unk1_0(struct nv50_disp *disp, int head)
 194 {
 195         exec_script(disp, head, 1);
 196 }
 197
 198 static void
 199 gf119_disp_intr_unk2_0(struct nv50_disp *disp, int head)
 200 {
 201         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 202         struct nvkm_output *outp = exec_script(disp, head, 2);
 203
 204         /* see note in nv50_disp_intr_unk20_0() */
 205         if (outp && outp->info.type == DCB_OUTPUT_DP) {
 206                 struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
 207                 if (!outpdp->lt.mst) {
 208                         struct nvbios_init init = {
 209                                 .subdev = subdev,
 210                                 .bios = subdev->device->bios,
 211                                 .outp = &outp->info,
 212                                 .crtc = head,
 213                                 .offset = outpdp->info.script[4],
 214                                 .execute = 1,
 215                         };
 216
 217                         nvkm_notify_put(&outpdp->irq);
 218                         nvbios_exec(&init);
 219                         atomic_set(&outpdp->lt.done, 0);
 220                 }
 221         }
 222 }
 223
 224 static void
 225 gf119_disp_intr_unk2_1(struct nv50_disp *disp, int head)
 226 {
 227         struct nvkm_device *device = disp->base.engine.subdev.device;
 228         struct nvkm_devinit *devinit = device->devinit;
 229         u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
 230         if (pclk)
 231                 nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk);
 232         nvkm_wr32(device, 0x612200 + (head * 0x800), 0x00000000);
 233 }
 234
 235 static void
 236 gf119_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head,
 237                           struct dcb_output *outp)
 238 {
 239         struct nvkm_device *device = disp->base.engine.subdev.device;
 240         const int or = ffs(outp->or) - 1;
 241         const u32 ctrl = nvkm_rd32(device, 0x660200 + (or   * 0x020));
 242         const u32 conf = nvkm_rd32(device, 0x660404 + (head * 0x300));
 243         const s32 vactive = nvkm_rd32(device, 0x660414 + (head * 0x300)) & 0xffff;
 244         const s32 vblanke = nvkm_rd32(device, 0x66041c + (head * 0x300)) & 0xffff;
 245         const s32 vblanks = nvkm_rd32(device, 0x660420 + (head * 0x300)) & 0xffff;
 246         const u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
 247         const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
 248         const u32 hoff = (head * 0x800);
 249         const u32 soff = (  or * 0x800);
 250         const u32 loff = (link * 0x080) + soff;
 251         const u32 symbol = 100000;
 252         const u32 TU = 64;
 253         u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff);
 254         u32 clksor = nvkm_rd32(device, 0x612300 + soff);
 255         u32 datarate, link_nr, link_bw, bits;
 256         u64 ratio, value;
 257
 258         link_nr  = hweight32(dpctrl & 0x000f0000);
 259         link_bw  = (clksor & 0x007c0000) >> 18;
 260         link_bw *= 27000;
 261
 262         /* symbols/hblank - algorithm taken from comments in tegra driver */
 263         value = vblanke + vactive - vblanks - 7;
 264         value = value * link_bw;
 265         do_div(value, pclk);
 266         value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
 267         nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, value);
 268
 269         /* symbols/vblank - algorithm taken from comments in tegra driver */
 270         value = vblanks - vblanke - 25;
 271         value = value * link_bw;
 272         do_div(value, pclk);
 273         value = value - ((36 / link_nr) + 3) - 1;
 274         nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, value);
 275
 276         /* watermark */
 277         if      ((conf & 0x3c0) == 0x180) bits = 30;
 278         else if ((conf & 0x3c0) == 0x140) bits = 24;
 279         else                              bits = 18;
 280         datarate = (pclk * bits) / 8;
 281
 282         ratio  = datarate;
 283         ratio *= symbol;
 284         do_div(ratio, link_nr * link_bw);
 285
 286         value  = (symbol - ratio) * TU;
 287         value *= ratio;
 288         do_div(value, symbol);
 289         do_div(value, symbol);
 290
 291         value += 5;
 292         value |= 0x08000000;
 293
 294         nvkm_wr32(device, 0x616610 + hoff, value);
 295 }
 296
 297 static void
 298 gf119_disp_intr_unk2_2(struct nv50_disp *disp, int head)
 299 {
 300         struct nvkm_device *device = disp->base.engine.subdev.device;
 301         struct nvkm_output *outp;
 302         u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
 303         u32 conf, addr, data;
 304
 305         outp = exec_clkcmp(disp, head, 0xff, pclk, &conf);
 306         if (!outp)
 307                 return;
 308
 309         /* see note in nv50_disp_intr_unk20_2() */
 310         if (outp->info.type == DCB_OUTPUT_DP) {
 311                 u32 sync = nvkm_rd32(device, 0x660404 + (head * 0x300));
 312                 switch ((sync & 0x000003c0) >> 6) {
 313                 case 6: pclk = pclk * 30; break;
 314                 case 5: pclk = pclk * 24; break;
 315                 case 2:
 316                 default:
 317                         pclk = pclk * 18;
 318                         break;
 319                 }
 320
 321                 if (nvkm_output_dp_train(outp, pclk))
 322                         OUTP_ERR(outp, "link not trained before attach");
 323         } else {
 324                 if (disp->func->sor.magic)
 325                         disp->func->sor.magic(outp);
 326         }
 327
 328         exec_clkcmp(disp, head, 0, pclk, &conf);
 329
 330         if (outp->info.type == DCB_OUTPUT_ANALOG) {
 331                 addr = 0x612280 + (ffs(outp->info.or) - 1) * 0x800;
 332                 data = 0x00000000;
 333         } else {
 334                 addr = 0x612300 + (ffs(outp->info.or) - 1) * 0x800;
 335                 data = (conf & 0x0100) ? 0x00000101 : 0x00000000;
 336                 switch (outp->info.type) {
 337                 case DCB_OUTPUT_TMDS:
 338                         nvkm_mask(device, addr, 0x007c0000, 0x00280000);
 339                         break;
 340                 case DCB_OUTPUT_DP:
 341                         gf119_disp_intr_unk2_2_tu(disp, head, &outp->info);
 342                         break;
 343                 default:
 344                         break;
 345                 }
 346         }
 347
 348         nvkm_mask(device, addr, 0x00000707, data);
 349 }
 350
 351 static void
 352 gf119_disp_intr_unk4_0(struct nv50_disp *disp, int head)
 353 {
 354         struct nvkm_device *device = disp->base.engine.subdev.device;
 355         u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
 356         u32 conf;
 357
 358         exec_clkcmp(disp, head, 1, pclk, &conf);
 359 }
 360
 361 void
 362 gf119_disp_super(struct work_struct *work)
 363 {
 364         struct nv50_disp *disp =
 365                 container_of(work, struct nv50_disp, supervisor);
 366         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 367         struct nvkm_device *device = subdev->device;
 368         struct nvkm_head *head;
 369         u32 mask[4];
 370
 371         nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super));
 372         list_for_each_entry(head, &disp->base.head, head) {
 373                 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800));
 374                 HEAD_DBG(head, "%08x", mask[head->id]);
 375         }
 376
 377         if (disp->super & 0x00000001) {
 378                 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
 379                 list_for_each_entry(head, &disp->base.head, head) {
 380                         if (!(mask[head->id] & 0x00001000))
 381                                 continue;
 382                         nvkm_debug(subdev, "supervisor 1.0 - head %d\n", head->id);
 383                         gf119_disp_intr_unk1_0(disp, head->id);
 384                 }
 385         } else
 386         if (disp->super & 0x00000002) {
 387                 list_for_each_entry(head, &disp->base.head, head) {
 388                         if (!(mask[head->id] & 0x00001000))
 389                                 continue;
 390                         nvkm_debug(subdev, "supervisor 2.0 - head %d\n", head->id);
 391                         gf119_disp_intr_unk2_0(disp, head->id);
 392                 }
 393                 list_for_each_entry(head, &disp->base.head, head) {
 394                         if (!(mask[head->id] & 0x00010000))
 395                                 continue;
 396                         nvkm_debug(subdev, "supervisor 2.1 - head %d\n", head->id);
 397                         gf119_disp_intr_unk2_1(disp, head->id);
 398                 }
 399                 list_for_each_entry(head, &disp->base.head, head) {
 400                         if (!(mask[head->id] & 0x00001000))
 401                                 continue;
 402                         nvkm_debug(subdev, "supervisor 2.2 - head %d\n", head->id);
 403                         gf119_disp_intr_unk2_2(disp, head->id);
 404                 }
 405         } else
 406         if (disp->super & 0x00000004) {
 407                 list_for_each_entry(head, &disp->base.head, head) {
 408                         if (!(mask[head->id] & 0x00001000))
 409                                 continue;
 410                         nvkm_debug(subdev, "supervisor 3.0 - head %d\n", head->id);
 411                         gf119_disp_intr_unk4_0(disp, head->id);
 412                 }
 413         }
 414
 415         list_for_each_entry(head, &disp->base.head, head)
 416                 nvkm_wr32(device, 0x6101d4 + (head->id * 0x800), 0x00000000);
 417         nvkm_wr32(device, 0x6101d0, 0x80000000);
 418 }
 419
 420 void
 421 gf119_disp_intr_error(struct nv50_disp *disp, int chid)
 422 {
 423         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 424         struct nvkm_device *device = subdev->device;
 425         u32 mthd = nvkm_rd32(device, 0x6101f0 + (chid * 12));
 426         u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12));
 427         u32 unkn = nvkm_rd32(device, 0x6101f8 + (chid * 12));
 428
 429         nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
 430                    chid, (mthd & 0x0000ffc), data, mthd, unkn);
 431
 432         if (chid < ARRAY_SIZE(disp->chan)) {
 433                 switch (mthd & 0xffc) {
 434                 case 0x0080:
 435                         nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
 436                         break;
 437                 default:
 438                         break;
 439                 }
 440         }
 441
 442         nvkm_wr32(device, 0x61009c, (1 << chid));
 443         nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000);
 444 }
 445
 446 void
 447 gf119_disp_intr(struct nv50_disp *disp)
 448 {
 449         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 450         struct nvkm_device *device = subdev->device;
 451         struct nvkm_head *head;
 452         u32 intr = nvkm_rd32(device, 0x610088);
 453
 454         if (intr & 0x00000001) {
 455                 u32 stat = nvkm_rd32(device, 0x61008c);
 456                 while (stat) {
 457                         int chid = __ffs(stat); stat &= ~(1 << chid);
 458                         nv50_disp_chan_uevent_send(disp, chid);
 459                         nvkm_wr32(device, 0x61008c, 1 << chid);
 460                 }
 461                 intr &= ~0x00000001;
 462         }
 463
 464         if (intr & 0x00000002) {
 465                 u32 stat = nvkm_rd32(device, 0x61009c);
 466                 int chid = ffs(stat) - 1;
 467                 if (chid >= 0)
 468                         disp->func->intr_error(disp, chid);
 469                 intr &= ~0x00000002;
 470         }
 471
 472         if (intr & 0x00100000) {
 473                 u32 stat = nvkm_rd32(device, 0x6100ac);
 474                 if (stat & 0x00000007) {
 475                         disp->super = (stat & 0x00000007);
 476                         schedule_work(&disp->supervisor);
 477                         nvkm_wr32(device, 0x6100ac, disp->super);
 478                         stat &= ~0x00000007;
 479                 }
 480
 481                 if (stat) {
 482                         nvkm_warn(subdev, "intr24 %08x\n", stat);
 483                         nvkm_wr32(device, 0x6100ac, stat);
 484                 }
 485
 486                 intr &= ~0x00100000;
 487         }
 488
 489         list_for_each_entry(head, &disp->base.head, head) {
 490                 const u32 hoff = head->id * 0x800;
 491                 u32 mask = 0x01000000 << head->id;
 492                 if (mask & intr) {
 493                         u32 stat = nvkm_rd32(device, 0x6100bc + hoff);
 494                         if (stat & 0x00000001)
 495                                 nvkm_disp_vblank(&disp->base, head->id);
 496                         nvkm_mask(device, 0x6100bc + hoff, 0, 0);
 497                         nvkm_rd32(device, 0x6100c0 + hoff);
 498                 }
 499         }
 500 }
 501
 502 int
 503 gf119_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
 504                 int index, struct nvkm_disp **pdisp)
 505 {
 506         u32 heads = nvkm_rd32(device, 0x022448);
 507         return nv50_disp_new_(func, device, index, heads, pdisp);
 508 }
 509
 510 static const struct nv50_disp_func
 511 gf119_disp = {
 512         .intr = gf119_disp_intr,
 513         .intr_error = gf119_disp_intr_error,
 514         .uevent = &gf119_disp_chan_uevent,
 515         .super = gf119_disp_super,
 516         .root = &gf119_disp_root_oclass,
 517         .head.new = gf119_head_new,
 518         .head.vblank_init = gf119_disp_vblank_init,
 519         .head.vblank_fini = gf119_disp_vblank_fini,
 520         .head.scanoutpos = gf119_disp_root_scanoutpos,
 521         .outp.internal.crt = nv50_dac_output_new,
 522         .outp.internal.tmds = nv50_sor_output_new,
 523         .outp.internal.lvds = nv50_sor_output_new,
 524         .outp.internal.dp = gf119_sor_dp_new,
 525         .dac.nr = 3,
 526         .dac.power = nv50_dac_power,
 527         .dac.sense = nv50_dac_sense,
 528         .sor.nr = 4,
 529         .sor.power = nv50_sor_power,
 530         .sor.hda_eld = gf119_hda_eld,
 531         .sor.hdmi = gf119_hdmi_ctrl,
 532 };
 533
 534 int
 535 gf119_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
 536 {
 537         return gf119_disp_new_(&gf119_disp, device, index, pdisp);
 538 }