2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #include <core/client.h>
30 #include <core/enum.h>
31 #include <core/gpuobj.h>
32 #include <subdev/bios.h>
33 #include <subdev/bios/disp.h>
34 #include <subdev/bios/init.h>
35 #include <subdev/bios/pll.h>
36 #include <subdev/devinit.h>
37 #include <subdev/timer.h>
39 static const struct nvkm_disp_oclass *
40 nv50_disp_root_(struct nvkm_disp *base)
42 return nv50_disp(base)->func->root;
46 nv50_disp_outp_internal_crt_(struct nvkm_disp *base, int index,
47 struct dcb_output *dcb, struct nvkm_output **poutp)
49 struct nv50_disp *disp = nv50_disp(base);
50 return disp->func->outp.internal.crt(base, index, dcb, poutp);
54 nv50_disp_outp_internal_tmds_(struct nvkm_disp *base, int index,
55 struct dcb_output *dcb,
56 struct nvkm_output **poutp)
58 struct nv50_disp *disp = nv50_disp(base);
59 return disp->func->outp.internal.tmds(base, index, dcb, poutp);
63 nv50_disp_outp_internal_lvds_(struct nvkm_disp *base, int index,
64 struct dcb_output *dcb,
65 struct nvkm_output **poutp)
67 struct nv50_disp *disp = nv50_disp(base);
68 return disp->func->outp.internal.lvds(base, index, dcb, poutp);
72 nv50_disp_outp_internal_dp_(struct nvkm_disp *base, int index,
73 struct dcb_output *dcb, struct nvkm_output **poutp)
75 struct nv50_disp *disp = nv50_disp(base);
76 if (disp->func->outp.internal.dp)
77 return disp->func->outp.internal.dp(base, index, dcb, poutp);
82 nv50_disp_outp_external_tmds_(struct nvkm_disp *base, int index,
83 struct dcb_output *dcb,
84 struct nvkm_output **poutp)
86 struct nv50_disp *disp = nv50_disp(base);
87 if (disp->func->outp.external.tmds)
88 return disp->func->outp.external.tmds(base, index, dcb, poutp);
93 nv50_disp_outp_external_dp_(struct nvkm_disp *base, int index,
94 struct dcb_output *dcb, struct nvkm_output **poutp)
96 struct nv50_disp *disp = nv50_disp(base);
97 if (disp->func->outp.external.dp)
98 return disp->func->outp.external.dp(base, index, dcb, poutp);
103 nv50_disp_intr_(struct nvkm_disp *base)
105 struct nv50_disp *disp = nv50_disp(base);
106 disp->func->intr(disp);
110 nv50_disp_dtor_(struct nvkm_disp *base)
112 struct nv50_disp *disp = nv50_disp(base);
113 nvkm_event_fini(&disp->uevent);
117 static const struct nvkm_disp_func
119 .dtor = nv50_disp_dtor_,
120 .intr = nv50_disp_intr_,
121 .root = nv50_disp_root_,
122 .outp.internal.crt = nv50_disp_outp_internal_crt_,
123 .outp.internal.tmds = nv50_disp_outp_internal_tmds_,
124 .outp.internal.lvds = nv50_disp_outp_internal_lvds_,
125 .outp.internal.dp = nv50_disp_outp_internal_dp_,
126 .outp.external.tmds = nv50_disp_outp_external_tmds_,
127 .outp.external.dp = nv50_disp_outp_external_dp_,
131 nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
132 int index, int heads, struct nvkm_disp **pdisp)
134 struct nv50_disp *disp;
137 if (!(disp = kzalloc(sizeof(*disp), GFP_KERNEL)))
139 INIT_WORK(&disp->supervisor, func->super);
141 *pdisp = &disp->base;
143 ret = nvkm_disp_ctor(&nv50_disp_, device, index, &disp->base);
147 for (i = 0; func->head.new && i < heads; i++) {
148 ret = func->head.new(&disp->base, i);
153 for (i = 0; func->dac.new && i < func->dac.nr; i++) {
154 ret = func->dac.new(&disp->base, i);
159 for (i = 0; func->pior.new && i < func->pior.nr; i++) {
160 ret = func->pior.new(&disp->base, i);
165 for (i = 0; func->sor.new && i < func->sor.nr; i++) {
166 ret = func->sor.new(&disp->base, i);
171 return nvkm_event_init(func->uevent, 1, 1 + (heads * 4), &disp->uevent);
174 static struct nvkm_output *
175 exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
176 u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
177 struct nvbios_outp *info)
179 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
180 struct nvkm_bios *bios = subdev->device->bios;
181 struct nvkm_output *outp;
185 type = DCB_OUTPUT_ANALOG;
189 switch (ctrl & 0x00000f00) {
190 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
191 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
192 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
193 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
194 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
195 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
197 nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl);
205 switch (ctrl & 0x00000f00) {
206 case 0x00000000: type |= disp->pior.type[or]; break;
208 nvkm_error(subdev, "unknown PIOR mc %08x\n", ctrl);
213 mask = 0x00c0 & (mask << 6);
214 mask |= 0x0001 << or;
215 mask |= 0x0100 << head;
217 list_for_each_entry(outp, &disp->base.outp, head) {
218 if ((outp->info.hasht & 0xff) == type &&
219 (outp->info.hashm & mask) == mask) {
220 *data = nvbios_outp_match(bios, outp->info.hasht, mask,
221 ver, hdr, cnt, len, info);
231 static struct nvkm_output *
232 exec_script(struct nv50_disp *disp, int head, int id)
234 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
235 struct nvkm_device *device = subdev->device;
236 struct nvkm_bios *bios = device->bios;
237 struct nvkm_output *outp;
238 struct nvbios_outp info;
239 u8 ver, hdr, cnt, len;
245 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
246 ctrl = nvkm_rd32(device, 0x610b5c + (i * 8));
249 if (!(ctrl & (1 << head))) {
250 if (device->chipset < 0x90 ||
251 device->chipset == 0x92 ||
252 device->chipset == 0xa0) {
257 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
258 ctrl = nvkm_rd32(device, reg + (i * 8));
263 if (!(ctrl & (1 << head))) {
264 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
265 ctrl = nvkm_rd32(device, 0x610b84 + (i * 8));
269 if (!(ctrl & (1 << head)))
273 outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
275 struct nvbios_init init = {
278 .offset = info.script[id],
290 static struct nvkm_output *
291 exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
293 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
294 struct nvkm_device *device = subdev->device;
295 struct nvkm_bios *bios = device->bios;
296 struct nvkm_output *outp;
297 struct nvbios_outp info1;
298 struct nvbios_ocfg info2;
299 u8 ver, hdr, cnt, len;
305 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
306 ctrl = nvkm_rd32(device, 0x610b58 + (i * 8));
309 if (!(ctrl & (1 << head))) {
310 if (device->chipset < 0x90 ||
311 device->chipset == 0x92 ||
312 device->chipset == 0xa0) {
317 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
318 ctrl = nvkm_rd32(device, reg + (i * 8));
323 if (!(ctrl & (1 << head))) {
324 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
325 ctrl = nvkm_rd32(device, 0x610b80 + (i * 8));
329 if (!(ctrl & (1 << head)))
333 outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
337 *conf = (ctrl & 0x00000f00) >> 8;
338 if (outp->info.location == 0) {
339 switch (outp->info.type) {
340 case DCB_OUTPUT_TMDS:
344 case DCB_OUTPUT_LVDS:
345 *conf |= disp->sor.lvdsconf;
351 *conf = (ctrl & 0x00000f00) >> 8;
355 data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8,
356 &ver, &hdr, &cnt, &len, &info2);
357 if (data && id < 0xff) {
358 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
360 struct nvbios_init init = {
376 /* If programming a TMDS output on a SOR that can also be configured for
377 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
379 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
380 * the VBIOS scripts on at least one board I have only switch it off on
381 * link 0, causing a blank display if the output has previously been
382 * programmed for DisplayPort.
385 nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp,
386 struct dcb_output *outp)
388 struct nvkm_device *device = disp->base.engine.subdev.device;
389 struct nvkm_bios *bios = device->bios;
390 const int link = !(outp->sorconf.link & 1);
391 const int or = ffs(outp->or) - 1;
392 const u32 loff = (or * 0x800) + (link * 0x80);
393 const u16 mask = (outp->sorconf.link << 6) | outp->or;
394 struct dcb_output match;
397 if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match))
398 nvkm_mask(device, 0x61c10c + loff, 0x00000001, 0x00000000);
402 nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head)
404 struct nvkm_device *device = disp->base.engine.subdev.device;
405 struct nvkm_output *outp;
406 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
409 outp = exec_clkcmp(disp, head, 1, pclk, &conf);
413 if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS)
414 nv50_disp_intr_unk40_0_tmds(disp, &outp->info);
415 nv50_disp_dptmds_war_3(disp, &outp->info);
419 nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head,
420 struct dcb_output *outp, u32 pclk)
422 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
423 struct nvkm_device *device = subdev->device;
424 const int link = !(outp->sorconf.link & 1);
425 const int or = ffs(outp->or) - 1;
426 const u32 soff = ( or * 0x800);
427 const u32 loff = (link * 0x080) + soff;
428 const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8));
429 const u32 symbol = 100000;
430 const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff;
431 const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff;
432 const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff;
433 u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff);
434 u32 clksor = nvkm_rd32(device, 0x614300 + soff);
435 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
436 int TU, VTUi, VTUf, VTUa;
437 u64 link_data_rate, link_ratio, unk;
438 u32 best_diff = 64 * symbol;
439 u32 link_nr, link_bw, bits;
442 link_bw = (clksor & 0x000c0000) ? 270000 : 162000;
443 link_nr = hweight32(dpctrl & 0x000f0000);
445 /* symbols/hblank - algorithm taken from comments in tegra driver */
446 value = vblanke + vactive - vblanks - 7;
447 value = value * link_bw;
449 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
450 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value);
452 /* symbols/vblank - algorithm taken from comments in tegra driver */
453 value = vblanks - vblanke - 25;
454 value = value * link_bw;
456 value = value - ((36 / link_nr) + 3) - 1;
457 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value);
459 /* watermark / activesym */
460 if ((ctrl & 0xf0000) == 0x60000) bits = 30;
461 else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
464 link_data_rate = (pclk * bits / 8) / link_nr;
466 /* calculate ratio of packed data rate to link symbol rate */
467 link_ratio = link_data_rate * symbol;
468 do_div(link_ratio, link_bw);
470 for (TU = 64; TU >= 32; TU--) {
471 /* calculate average number of valid symbols in each TU */
472 u32 tu_valid = link_ratio * TU;
475 /* find a hw representation for the fraction.. */
476 VTUi = tu_valid / symbol;
477 calc = VTUi * symbol;
478 diff = tu_valid - calc;
480 if (diff >= (symbol / 2)) {
481 VTUf = symbol / (symbol - diff);
482 if (symbol - (VTUf * diff))
487 calc += symbol - (symbol / VTUf);
495 VTUf = min((int)(symbol / diff), 15);
496 calc += symbol / VTUf;
499 diff = calc - tu_valid;
501 /* no remainder, but the hw doesn't like the fractional
502 * part to be zero. decrement the integer part and
503 * have the fraction add a whole symbol back
510 if (diff < best_diff) {
522 nvkm_error(subdev, "unable to find suitable dp config\n");
526 /* XXX close to vbios numbers, but not right */
527 unk = (symbol - link_ratio) * bestTU;
533 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2);
534 nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
536 bestVTUi << 8 | unk);
540 nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head)
542 struct nvkm_device *device = disp->base.engine.subdev.device;
543 struct nvkm_output *outp;
544 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
545 u32 hval, hreg = 0x614200 + (head * 0x800);
549 outp = exec_clkcmp(disp, head, 0xff, pclk, &conf);
553 /* we allow both encoder attach and detach operations to occur
554 * within a single supervisor (ie. modeset) sequence. the
555 * encoder detach scripts quite often switch off power to the
556 * lanes, which requires the link to be re-trained.
558 * this is not generally an issue as the sink "must" (heh)
559 * signal an irq when it's lost sync so the driver can
562 * however, on some boards, if one does not configure at least
563 * the gpu side of the link *before* attaching, then various
564 * things can go horribly wrong (PDISP disappearing from mmio,
565 * third supervisor never happens, etc).
567 * the solution is simply to retrain here, if necessary. last
568 * i checked, the binary driver userspace does not appear to
569 * trigger this situation (it forces an UPDATE between steps).
571 if (outp->info.type == DCB_OUTPUT_DP) {
572 u32 soff = (ffs(outp->info.or) - 1) * 0x08;
575 if (outp->info.location == 0) {
576 ctrl = nvkm_rd32(device, 0x610794 + soff);
579 ctrl = nvkm_rd32(device, 0x610b80 + soff);
583 switch ((ctrl & 0x000f0000) >> 16) {
584 case 6: datarate = pclk * 30; break;
585 case 5: datarate = pclk * 24; break;
588 datarate = pclk * 18;
592 if (nvkm_output_dp_train(outp, datarate / soff))
593 OUTP_ERR(outp, "link not trained before attach");
596 exec_clkcmp(disp, head, 0, pclk, &conf);
598 if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) {
599 oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800;
604 if (!outp->info.location) {
605 if (outp->info.type == DCB_OUTPUT_DP)
606 nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk);
607 oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800;
608 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
612 oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800;
618 nvkm_mask(device, hreg, 0x0000000f, hval);
619 nvkm_mask(device, oreg, mask, oval);
621 nv50_disp_dptmds_war_2(disp, &outp->info);
625 nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head)
627 struct nvkm_device *device = disp->base.engine.subdev.device;
628 struct nvkm_devinit *devinit = device->devinit;
629 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
631 nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk);
635 nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head)
637 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
638 struct nvkm_output *outp = exec_script(disp, head, 2);
640 /* the binary driver does this outside of the supervisor handling
641 * (after the third supervisor from a detach). we (currently?)
642 * allow both detach/attach to happen in the same set of
643 * supervisor interrupts, so it would make sense to execute this
644 * (full power down?) script after all the detach phases of the
645 * supervisor handling. like with training if needed from the
646 * second supervisor, nvidia doesn't do this, so who knows if it's
647 * entirely safe, but it does appear to work..
649 * without this script being run, on some configurations i've
650 * seen, switching from DP to TMDS on a DP connector may result
651 * in a blank screen (SOR_PWR off/on can restore it)
653 if (outp && outp->info.type == DCB_OUTPUT_DP) {
654 struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
655 struct nvbios_init init = {
657 .bios = subdev->device->bios,
660 .offset = outpdp->info.script[4],
664 atomic_set(&outpdp->lt.done, 0);
670 nv50_disp_intr_unk10_0(struct nv50_disp *disp, int head)
672 exec_script(disp, head, 1);
676 nv50_disp_super(struct work_struct *work)
678 struct nv50_disp *disp =
679 container_of(work, struct nv50_disp, supervisor);
680 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
681 struct nvkm_device *device = subdev->device;
682 struct nvkm_head *head;
683 u32 super = nvkm_rd32(device, 0x610030);
685 nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super);
687 if (disp->super & 0x00000010) {
688 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
689 list_for_each_entry(head, &disp->base.head, head) {
690 if (!(super & (0x00000020 << head->id)))
692 if (!(super & (0x00000080 << head->id)))
694 nv50_disp_intr_unk10_0(disp, head->id);
697 if (disp->super & 0x00000020) {
698 list_for_each_entry(head, &disp->base.head, head) {
699 if (!(super & (0x00000080 << head->id)))
701 nv50_disp_intr_unk20_0(disp, head->id);
703 list_for_each_entry(head, &disp->base.head, head) {
704 if (!(super & (0x00000200 << head->id)))
706 nv50_disp_intr_unk20_1(disp, head->id);
708 list_for_each_entry(head, &disp->base.head, head) {
709 if (!(super & (0x00000080 << head->id)))
711 nv50_disp_intr_unk20_2(disp, head->id);
714 if (disp->super & 0x00000040) {
715 list_for_each_entry(head, &disp->base.head, head) {
716 if (!(super & (0x00000080 << head->id)))
718 nv50_disp_intr_unk40_0(disp, head->id);
720 nv50_disp_update_sppll1(disp);
723 nvkm_wr32(device, 0x610030, 0x80000000);
726 static const struct nvkm_enum
727 nv50_disp_intr_error_type[] = {
728 { 3, "ILLEGAL_MTHD" },
729 { 4, "INVALID_VALUE" },
730 { 5, "INVALID_STATE" },
731 { 7, "INVALID_HANDLE" },
735 static const struct nvkm_enum
736 nv50_disp_intr_error_code[] = {
742 nv50_disp_intr_error(struct nv50_disp *disp, int chid)
744 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
745 struct nvkm_device *device = subdev->device;
746 u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08));
747 u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08));
748 u32 code = (addr & 0x00ff0000) >> 16;
749 u32 type = (addr & 0x00007000) >> 12;
750 u32 mthd = (addr & 0x00000ffc);
751 const struct nvkm_enum *ec, *et;
753 et = nvkm_enum_find(nv50_disp_intr_error_type, type);
754 ec = nvkm_enum_find(nv50_disp_intr_error_code, code);
757 "ERROR %d [%s] %02x [%s] chid %d mthd %04x data %08x\n",
758 type, et ? et->name : "", code, ec ? ec->name : "",
761 if (chid < ARRAY_SIZE(disp->chan)) {
764 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
771 nvkm_wr32(device, 0x610020, 0x00010000 << chid);
772 nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000);
776 nv50_disp_intr(struct nv50_disp *disp)
778 struct nvkm_device *device = disp->base.engine.subdev.device;
779 u32 intr0 = nvkm_rd32(device, 0x610020);
780 u32 intr1 = nvkm_rd32(device, 0x610024);
782 while (intr0 & 0x001f0000) {
783 u32 chid = __ffs(intr0 & 0x001f0000) - 16;
784 nv50_disp_intr_error(disp, chid);
785 intr0 &= ~(0x00010000 << chid);
788 while (intr0 & 0x0000001f) {
789 u32 chid = __ffs(intr0 & 0x0000001f);
790 nv50_disp_chan_uevent_send(disp, chid);
791 intr0 &= ~(0x00000001 << chid);
794 if (intr1 & 0x00000004) {
795 nvkm_disp_vblank(&disp->base, 0);
796 nvkm_wr32(device, 0x610024, 0x00000004);
799 if (intr1 & 0x00000008) {
800 nvkm_disp_vblank(&disp->base, 1);
801 nvkm_wr32(device, 0x610024, 0x00000008);
804 if (intr1 & 0x00000070) {
805 disp->super = (intr1 & 0x00000070);
806 schedule_work(&disp->supervisor);
807 nvkm_wr32(device, 0x610024, disp->super);
811 static const struct nv50_disp_func
813 .intr = nv50_disp_intr,
814 .uevent = &nv50_disp_chan_uevent,
815 .super = nv50_disp_super,
816 .root = &nv50_disp_root_oclass,
817 .head.new = nv50_head_new,
818 .outp.internal.crt = nv50_dac_output_new,
819 .outp.internal.tmds = nv50_sor_output_new,
820 .outp.internal.lvds = nv50_sor_output_new,
821 .outp.external.tmds = nv50_pior_output_new,
822 .outp.external.dp = nv50_pior_dp_new,
824 .dac.new = nv50_dac_new,
825 .dac.power = nv50_dac_power,
826 .dac.sense = nv50_dac_sense,
828 .sor.new = nv50_sor_new,
829 .sor.power = nv50_sor_power,
831 .pior.new = nv50_pior_new,
832 .pior.power = nv50_pior_power,
836 nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
838 return nv50_disp_new_(&nv50_disp, device, index, 2, pdisp);