2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/bmp.h>
27 #include <subdev/bios/conn.h>
28 #include <subdev/bios/dcb.h>
29 #include <subdev/bios/dp.h>
30 #include <subdev/bios/gpio.h>
31 #include <subdev/bios/init.h>
32 #include <subdev/bios/ramcfg.h>
34 #include <subdev/devinit.h>
35 #include <subdev/gpio.h>
36 #include <subdev/i2c.h>
37 #include <subdev/vga.h>
39 #define bioslog(lvl, fmt, args...) do { \
40 nvkm_printk(init->subdev, lvl, info, "0x%04x[%c]: "fmt, \
41 init->offset, init_exec(init) ? \
42 '0' + (init->nested - 1) : ' ', ##args); \
44 #define cont(fmt, args...) do { \
45 if (init->subdev->debug >= NV_DBG_TRACE) \
46 printk(fmt, ##args); \
48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
52 /******************************************************************************
53 * init parser control flow helpers
54 *****************************************************************************/
57 init_exec(struct nvbios_init *init)
59 return (init->execute == 1) || ((init->execute & 5) == 5);
63 init_exec_set(struct nvbios_init *init, bool exec)
65 if (exec) init->execute &= 0xfd;
66 else init->execute |= 0x02;
70 init_exec_inv(struct nvbios_init *init)
72 init->execute ^= 0x02;
76 init_exec_force(struct nvbios_init *init, bool exec)
78 if (exec) init->execute |= 0x04;
79 else init->execute &= 0xfb;
82 /******************************************************************************
83 * init parser wrappers for normal register/i2c/whatever accessors
84 *****************************************************************************/
87 init_or(struct nvbios_init *init)
89 if (init_exec(init)) {
91 return ffs(init->outp->or) - 1;
92 error("script needs OR!!\n");
98 init_link(struct nvbios_init *init)
100 if (init_exec(init)) {
102 return !(init->outp->sorconf.link & 1);
103 error("script needs OR link\n");
109 init_crtc(struct nvbios_init *init)
111 if (init_exec(init)) {
114 error("script needs crtc\n");
120 init_conn(struct nvbios_init *init)
122 struct nvkm_bios *bios = init->bios;
123 struct nvbios_connE connE;
127 if (init_exec(init)) {
129 conn = init->outp->connector;
130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
135 error("script needs connector type\n");
142 init_nvreg(struct nvbios_init *init, u32 reg)
144 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
146 /* C51 (at least) sometimes has the lower bits set which the VBIOS
147 * interprets to mean that access needs to go through certain IO
148 * ports instead. The NVIDIA binary driver has been seen to access
149 * these through the NV register address, so lets assume we can
154 /* GF8+ display scripts need register addresses mangled a bit to
155 * select a specific CRTC/OR
157 if (init->bios->subdev.device->card_type >= NV_50) {
158 if (reg & 0x80000000) {
159 reg += init_crtc(init) * 0x800;
163 if (reg & 0x40000000) {
164 reg += init_or(init) * 0x800;
166 if (reg & 0x20000000) {
167 reg += init_link(init) * 0x80;
173 if (reg & ~0x00fffffc)
174 warn("unknown bits in register 0x%08x\n", reg);
176 return nvkm_devinit_mmio(devinit, reg);
180 init_rd32(struct nvbios_init *init, u32 reg)
182 struct nvkm_device *device = init->bios->subdev.device;
183 reg = init_nvreg(init, reg);
184 if (reg != ~0 && init_exec(init))
185 return nvkm_rd32(device, reg);
190 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
192 struct nvkm_device *device = init->bios->subdev.device;
193 reg = init_nvreg(init, reg);
194 if (reg != ~0 && init_exec(init))
195 nvkm_wr32(device, reg, val);
199 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
201 struct nvkm_device *device = init->bios->subdev.device;
202 reg = init_nvreg(init, reg);
203 if (reg != ~0 && init_exec(init)) {
204 u32 tmp = nvkm_rd32(device, reg);
205 nvkm_wr32(device, reg, (tmp & ~mask) | val);
212 init_rdport(struct nvbios_init *init, u16 port)
215 return nvkm_rdport(init->subdev->device, init->crtc, port);
220 init_wrport(struct nvbios_init *init, u16 port, u8 value)
223 nvkm_wrport(init->subdev->device, init->crtc, port, value);
227 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
229 struct nvkm_subdev *subdev = init->subdev;
230 if (init_exec(init)) {
231 int head = init->crtc < 0 ? 0 : init->crtc;
232 return nvkm_rdvgai(subdev->device, head, port, index);
238 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
240 struct nvkm_device *device = init->subdev->device;
242 /* force head 0 for updates to cr44, it only exists on first head */
243 if (device->card_type < NV_50) {
244 if (port == 0x03d4 && index == 0x44)
248 if (init_exec(init)) {
249 int head = init->crtc < 0 ? 0 : init->crtc;
250 nvkm_wrvgai(device, head, port, index, value);
253 /* select head 1 if cr44 write selected it */
254 if (device->card_type < NV_50) {
255 if (port == 0x03d4 && index == 0x44 && value == 3)
260 static struct i2c_adapter *
261 init_i2c(struct nvbios_init *init, int index)
263 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c;
264 struct nvkm_i2c_bus *bus;
267 index = NVKM_I2C_BUS_PRI;
268 if (init->outp && init->outp->i2c_upper_default)
269 index = NVKM_I2C_BUS_SEC;
272 bus = nvkm_i2c_bus_find(i2c, index);
273 return bus ? &bus->i2c : NULL;
277 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
279 struct i2c_adapter *adap = init_i2c(init, index);
280 if (adap && init_exec(init))
281 return nvkm_rdi2cr(adap, addr, reg);
286 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
288 struct i2c_adapter *adap = init_i2c(init, index);
289 if (adap && init_exec(init))
290 return nvkm_wri2cr(adap, addr, reg, val);
294 static struct nvkm_i2c_aux *
295 init_aux(struct nvbios_init *init)
297 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c;
300 error("script needs output for aux\n");
303 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index);
307 init_rdauxr(struct nvbios_init *init, u32 addr)
309 struct nvkm_i2c_aux *aux = init_aux(init);
312 if (aux && init_exec(init)) {
313 int ret = nvkm_rdaux(aux, addr, &data, 1);
316 trace("auxch read failed with %d\n", ret);
323 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
325 struct nvkm_i2c_aux *aux = init_aux(init);
326 if (aux && init_exec(init)) {
327 int ret = nvkm_wraux(aux, addr, &data, 1);
329 trace("auxch write failed with %d\n", ret);
336 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
338 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
339 if (init_exec(init)) {
340 int ret = nvkm_devinit_pll_set(devinit, id, freq);
342 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
346 /******************************************************************************
347 * parsing of bios structures that are required to execute init tables
348 *****************************************************************************/
351 init_table(struct nvkm_bios *bios, u16 *len)
353 struct bit_entry bit_I;
355 if (!bit_entry(bios, 'I', &bit_I)) {
360 if (bmp_version(bios) >= 0x0510) {
362 return bios->bmp_offset + 75;
369 init_table_(struct nvbios_init *init, u16 offset, const char *name)
371 struct nvkm_bios *bios = init->bios;
372 u16 len, data = init_table(bios, &len);
374 if (len >= offset + 2) {
375 data = nvbios_rd16(bios, data + offset);
379 warn("%s pointer invalid\n", name);
383 warn("init data too short for %s pointer", name);
387 warn("init data not found\n");
391 #define init_script_table(b) init_table_((b), 0x00, "script table")
392 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
393 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
394 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
395 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
396 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
397 #define init_function_table(b) init_table_((b), 0x0c, "function table")
398 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
401 init_script(struct nvkm_bios *bios, int index)
403 struct nvbios_init init = { .bios = bios };
404 u16 bmp_ver = bmp_version(bios), data;
406 if (bmp_ver && bmp_ver < 0x0510) {
407 if (index > 1 || bmp_ver < 0x0100)
410 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
411 return nvbios_rd16(bios, data + (index * 2));
414 data = init_script_table(&init);
416 return nvbios_rd16(bios, data + (index * 2));
422 init_unknown_script(struct nvkm_bios *bios)
424 u16 len, data = init_table(bios, &len);
425 if (data && len >= 16)
426 return nvbios_rd16(bios, data + 14);
431 init_ram_restrict_group_count(struct nvbios_init *init)
433 return nvbios_ramcfg_count(init->bios);
437 init_ram_restrict(struct nvbios_init *init)
439 /* This appears to be the behaviour of the VBIOS parser, and *is*
440 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
441 * avoid fucking up the memory controller (somehow) by reading it
442 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
444 * Preserving the non-caching behaviour on earlier chipsets just
445 * in case *not* re-reading the strap causes similar breakage.
447 if (!init->ramcfg || init->bios->version.major < 0x70)
448 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
449 return (init->ramcfg & 0x7fffffff);
453 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
455 struct nvkm_bios *bios = init->bios;
456 u16 table = init_xlat_table(init);
458 u16 data = nvbios_rd16(bios, table + (index * 2));
460 return nvbios_rd08(bios, data + offset);
461 warn("xlat table pointer %d invalid\n", index);
466 /******************************************************************************
467 * utility functions used by various init opcode handlers
468 *****************************************************************************/
471 init_condition_met(struct nvbios_init *init, u8 cond)
473 struct nvkm_bios *bios = init->bios;
474 u16 table = init_condition_table(init);
476 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0);
477 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4);
478 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8);
479 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
480 cond, reg, msk, val);
481 return (init_rd32(init, reg) & msk) == val;
487 init_io_condition_met(struct nvbios_init *init, u8 cond)
489 struct nvkm_bios *bios = init->bios;
490 u16 table = init_io_condition_table(init);
492 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0);
493 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2);
494 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3);
495 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4);
496 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
497 cond, port, index, mask, value);
498 return (init_rdvgai(init, port, index) & mask) == value;
504 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
506 struct nvkm_bios *bios = init->bios;
507 u16 table = init_io_flag_condition_table(init);
509 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0);
510 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2);
511 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3);
512 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4);
513 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5);
514 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7);
515 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8);
516 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
517 return (nvbios_rd08(bios, data + ioval) & dmask) == value;
523 init_shift(u32 data, u8 shift)
526 return data >> shift;
527 return data << (0x100 - shift);
531 init_tmds_reg(struct nvbios_init *init, u8 tmds)
533 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
534 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
535 * CR58 for CR57 = 0 to index a table of offsets to the basic
537 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
538 * CR58 for CR57 = 0 to index a table of offsets to the basic
539 * 0x6808b0 address, and then flip the offset by 8.
541 const int pramdac_offset[13] = {
542 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
543 const u32 pramdac_table[4] = {
544 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
548 u32 dacoffset = pramdac_offset[init->outp->or];
551 return 0x6808b0 + dacoffset;
555 error("tmds opcodes need dcb\n");
557 if (tmds < ARRAY_SIZE(pramdac_table))
558 return pramdac_table[tmds];
560 error("tmds selector 0x%02x unknown\n", tmds);
566 /******************************************************************************
567 * init opcode handlers
568 *****************************************************************************/
571 * init_reserved - stub for various unknown/unused single-byte opcodes
575 init_reserved(struct nvbios_init *init)
577 u8 opcode = nvbios_rd08(init->bios, init->offset);
589 trace("RESERVED 0x%02x\t", opcode);
590 for (i = 1; i < length; i++)
591 cont(" 0x%02x", nvbios_rd08(init->bios, init->offset + i));
593 init->offset += length;
597 * INIT_DONE - opcode 0x71
601 init_done(struct nvbios_init *init)
604 init->offset = 0x0000;
608 * INIT_IO_RESTRICT_PROG - opcode 0x32
612 init_io_restrict_prog(struct nvbios_init *init)
614 struct nvkm_bios *bios = init->bios;
615 u16 port = nvbios_rd16(bios, init->offset + 1);
616 u8 index = nvbios_rd08(bios, init->offset + 3);
617 u8 mask = nvbios_rd08(bios, init->offset + 4);
618 u8 shift = nvbios_rd08(bios, init->offset + 5);
619 u8 count = nvbios_rd08(bios, init->offset + 6);
620 u32 reg = nvbios_rd32(bios, init->offset + 7);
623 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
624 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
625 reg, port, index, mask, shift);
628 conf = (init_rdvgai(init, port, index) & mask) >> shift;
629 for (i = 0; i < count; i++) {
630 u32 data = nvbios_rd32(bios, init->offset);
633 trace("\t0x%08x *\n", data);
634 init_wr32(init, reg, data);
636 trace("\t0x%08x\n", data);
645 * INIT_REPEAT - opcode 0x33
649 init_repeat(struct nvbios_init *init)
651 struct nvkm_bios *bios = init->bios;
652 u8 count = nvbios_rd08(bios, init->offset + 1);
653 u16 repeat = init->repeat;
655 trace("REPEAT\t0x%02x\n", count);
658 init->repeat = init->offset;
659 init->repend = init->offset;
661 init->offset = init->repeat;
664 trace("REPEAT\t0x%02x\n", count);
666 init->offset = init->repend;
667 init->repeat = repeat;
671 * INIT_IO_RESTRICT_PLL - opcode 0x34
675 init_io_restrict_pll(struct nvbios_init *init)
677 struct nvkm_bios *bios = init->bios;
678 u16 port = nvbios_rd16(bios, init->offset + 1);
679 u8 index = nvbios_rd08(bios, init->offset + 3);
680 u8 mask = nvbios_rd08(bios, init->offset + 4);
681 u8 shift = nvbios_rd08(bios, init->offset + 5);
682 s8 iofc = nvbios_rd08(bios, init->offset + 6);
683 u8 count = nvbios_rd08(bios, init->offset + 7);
684 u32 reg = nvbios_rd32(bios, init->offset + 8);
687 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
688 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
689 reg, port, index, mask, shift, iofc);
692 conf = (init_rdvgai(init, port, index) & mask) >> shift;
693 for (i = 0; i < count; i++) {
694 u32 freq = nvbios_rd16(bios, init->offset) * 10;
697 trace("\t%dkHz *\n", freq);
698 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
700 init_prog_pll(init, reg, freq);
702 trace("\t%dkHz\n", freq);
711 * INIT_END_REPEAT - opcode 0x36
715 init_end_repeat(struct nvbios_init *init)
717 trace("END_REPEAT\n");
721 init->repend = init->offset;
727 * INIT_COPY - opcode 0x37
731 init_copy(struct nvbios_init *init)
733 struct nvkm_bios *bios = init->bios;
734 u32 reg = nvbios_rd32(bios, init->offset + 1);
735 u8 shift = nvbios_rd08(bios, init->offset + 5);
736 u8 smask = nvbios_rd08(bios, init->offset + 6);
737 u16 port = nvbios_rd16(bios, init->offset + 7);
738 u8 index = nvbios_rd08(bios, init->offset + 9);
739 u8 mask = nvbios_rd08(bios, init->offset + 10);
742 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
743 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
744 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
745 (shift & 0x80) ? (0x100 - shift) : shift, smask);
748 data = init_rdvgai(init, port, index) & mask;
749 data |= init_shift(init_rd32(init, reg), shift) & smask;
750 init_wrvgai(init, port, index, data);
754 * INIT_NOT - opcode 0x38
758 init_not(struct nvbios_init *init)
766 * INIT_IO_FLAG_CONDITION - opcode 0x39
770 init_io_flag_condition(struct nvbios_init *init)
772 struct nvkm_bios *bios = init->bios;
773 u8 cond = nvbios_rd08(bios, init->offset + 1);
775 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
778 if (!init_io_flag_condition_met(init, cond))
779 init_exec_set(init, false);
783 * INIT_DP_CONDITION - opcode 0x3a
787 init_dp_condition(struct nvbios_init *init)
789 struct nvkm_bios *bios = init->bios;
790 struct nvbios_dpout info;
791 u8 cond = nvbios_rd08(bios, init->offset + 1);
792 u8 unkn = nvbios_rd08(bios, init->offset + 2);
793 u8 ver, hdr, cnt, len;
796 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
801 if (init_conn(init) != DCB_CONNECTOR_eDP)
802 init_exec_set(init, false);
807 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
808 (init->outp->or << 0) |
809 (init->outp->sorconf.link << 6),
810 &ver, &hdr, &cnt, &len, &info)))
812 if (!(info.flags & cond))
813 init_exec_set(init, false);
818 warn("script needs dp output table data\n");
821 if (!(init_rdauxr(init, 0x0d) & 1))
822 init_exec_set(init, false);
825 warn("unknown dp condition 0x%02x\n", cond);
831 * INIT_IO_MASK_OR - opcode 0x3b
835 init_io_mask_or(struct nvbios_init *init)
837 struct nvkm_bios *bios = init->bios;
838 u8 index = nvbios_rd08(bios, init->offset + 1);
839 u8 or = init_or(init);
842 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
845 data = init_rdvgai(init, 0x03d4, index);
846 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
850 * INIT_IO_OR - opcode 0x3c
854 init_io_or(struct nvbios_init *init)
856 struct nvkm_bios *bios = init->bios;
857 u8 index = nvbios_rd08(bios, init->offset + 1);
858 u8 or = init_or(init);
861 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
864 data = init_rdvgai(init, 0x03d4, index);
865 init_wrvgai(init, 0x03d4, index, data | (1 << or));
869 * INIT_ANDN_REG - opcode 0x47
873 init_andn_reg(struct nvbios_init *init)
875 struct nvkm_bios *bios = init->bios;
876 u32 reg = nvbios_rd32(bios, init->offset + 1);
877 u32 mask = nvbios_rd32(bios, init->offset + 5);
879 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
882 init_mask(init, reg, mask, 0);
886 * INIT_OR_REG - opcode 0x48
890 init_or_reg(struct nvbios_init *init)
892 struct nvkm_bios *bios = init->bios;
893 u32 reg = nvbios_rd32(bios, init->offset + 1);
894 u32 mask = nvbios_rd32(bios, init->offset + 5);
896 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
899 init_mask(init, reg, 0, mask);
903 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
907 init_idx_addr_latched(struct nvbios_init *init)
909 struct nvkm_bios *bios = init->bios;
910 u32 creg = nvbios_rd32(bios, init->offset + 1);
911 u32 dreg = nvbios_rd32(bios, init->offset + 5);
912 u32 mask = nvbios_rd32(bios, init->offset + 9);
913 u32 data = nvbios_rd32(bios, init->offset + 13);
914 u8 count = nvbios_rd08(bios, init->offset + 17);
916 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
917 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
921 u8 iaddr = nvbios_rd08(bios, init->offset + 0);
922 u8 idata = nvbios_rd08(bios, init->offset + 1);
924 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
927 init_wr32(init, dreg, idata);
928 init_mask(init, creg, ~mask, data | iaddr);
933 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
937 init_io_restrict_pll2(struct nvbios_init *init)
939 struct nvkm_bios *bios = init->bios;
940 u16 port = nvbios_rd16(bios, init->offset + 1);
941 u8 index = nvbios_rd08(bios, init->offset + 3);
942 u8 mask = nvbios_rd08(bios, init->offset + 4);
943 u8 shift = nvbios_rd08(bios, init->offset + 5);
944 u8 count = nvbios_rd08(bios, init->offset + 6);
945 u32 reg = nvbios_rd32(bios, init->offset + 7);
948 trace("IO_RESTRICT_PLL2\t"
949 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
950 reg, port, index, mask, shift);
953 conf = (init_rdvgai(init, port, index) & mask) >> shift;
954 for (i = 0; i < count; i++) {
955 u32 freq = nvbios_rd32(bios, init->offset);
957 trace("\t%dkHz *\n", freq);
958 init_prog_pll(init, reg, freq);
960 trace("\t%dkHz\n", freq);
968 * INIT_PLL2 - opcode 0x4b
972 init_pll2(struct nvbios_init *init)
974 struct nvkm_bios *bios = init->bios;
975 u32 reg = nvbios_rd32(bios, init->offset + 1);
976 u32 freq = nvbios_rd32(bios, init->offset + 5);
978 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
981 init_prog_pll(init, reg, freq);
985 * INIT_I2C_BYTE - opcode 0x4c
989 init_i2c_byte(struct nvbios_init *init)
991 struct nvkm_bios *bios = init->bios;
992 u8 index = nvbios_rd08(bios, init->offset + 1);
993 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
994 u8 count = nvbios_rd08(bios, init->offset + 3);
996 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1000 u8 reg = nvbios_rd08(bios, init->offset + 0);
1001 u8 mask = nvbios_rd08(bios, init->offset + 1);
1002 u8 data = nvbios_rd08(bios, init->offset + 2);
1005 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1008 val = init_rdi2cr(init, index, addr, reg);
1011 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1016 * INIT_ZM_I2C_BYTE - opcode 0x4d
1020 init_zm_i2c_byte(struct nvbios_init *init)
1022 struct nvkm_bios *bios = init->bios;
1023 u8 index = nvbios_rd08(bios, init->offset + 1);
1024 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1025 u8 count = nvbios_rd08(bios, init->offset + 3);
1027 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1031 u8 reg = nvbios_rd08(bios, init->offset + 0);
1032 u8 data = nvbios_rd08(bios, init->offset + 1);
1034 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1037 init_wri2cr(init, index, addr, reg, data);
1042 * INIT_ZM_I2C - opcode 0x4e
1046 init_zm_i2c(struct nvbios_init *init)
1048 struct nvkm_bios *bios = init->bios;
1049 u8 index = nvbios_rd08(bios, init->offset + 1);
1050 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1051 u8 count = nvbios_rd08(bios, init->offset + 3);
1054 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1057 for (i = 0; i < count; i++) {
1058 data[i] = nvbios_rd08(bios, init->offset);
1059 trace("\t0x%02x\n", data[i]);
1063 if (init_exec(init)) {
1064 struct i2c_adapter *adap = init_i2c(init, index);
1065 struct i2c_msg msg = {
1066 .addr = addr, .flags = 0, .len = count, .buf = data,
1070 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1)
1071 warn("i2c wr failed, %d\n", ret);
1076 * INIT_TMDS - opcode 0x4f
1080 init_tmds(struct nvbios_init *init)
1082 struct nvkm_bios *bios = init->bios;
1083 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1084 u8 addr = nvbios_rd08(bios, init->offset + 2);
1085 u8 mask = nvbios_rd08(bios, init->offset + 3);
1086 u8 data = nvbios_rd08(bios, init->offset + 4);
1087 u32 reg = init_tmds_reg(init, tmds);
1089 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1090 tmds, addr, mask, data);
1096 init_wr32(init, reg + 0, addr | 0x00010000);
1097 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1098 init_wr32(init, reg + 0, addr);
1102 * INIT_ZM_TMDS_GROUP - opcode 0x50
1106 init_zm_tmds_group(struct nvbios_init *init)
1108 struct nvkm_bios *bios = init->bios;
1109 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1110 u8 count = nvbios_rd08(bios, init->offset + 2);
1111 u32 reg = init_tmds_reg(init, tmds);
1113 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1117 u8 addr = nvbios_rd08(bios, init->offset + 0);
1118 u8 data = nvbios_rd08(bios, init->offset + 1);
1120 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1123 init_wr32(init, reg + 4, data);
1124 init_wr32(init, reg + 0, addr);
1129 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1133 init_cr_idx_adr_latch(struct nvbios_init *init)
1135 struct nvkm_bios *bios = init->bios;
1136 u8 addr0 = nvbios_rd08(bios, init->offset + 1);
1137 u8 addr1 = nvbios_rd08(bios, init->offset + 2);
1138 u8 base = nvbios_rd08(bios, init->offset + 3);
1139 u8 count = nvbios_rd08(bios, init->offset + 4);
1142 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1145 save0 = init_rdvgai(init, 0x03d4, addr0);
1147 u8 data = nvbios_rd08(bios, init->offset);
1149 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1152 init_wrvgai(init, 0x03d4, addr0, base++);
1153 init_wrvgai(init, 0x03d4, addr1, data);
1155 init_wrvgai(init, 0x03d4, addr0, save0);
1159 * INIT_CR - opcode 0x52
1163 init_cr(struct nvbios_init *init)
1165 struct nvkm_bios *bios = init->bios;
1166 u8 addr = nvbios_rd08(bios, init->offset + 1);
1167 u8 mask = nvbios_rd08(bios, init->offset + 2);
1168 u8 data = nvbios_rd08(bios, init->offset + 3);
1171 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1174 val = init_rdvgai(init, 0x03d4, addr) & mask;
1175 init_wrvgai(init, 0x03d4, addr, val | data);
1179 * INIT_ZM_CR - opcode 0x53
1183 init_zm_cr(struct nvbios_init *init)
1185 struct nvkm_bios *bios = init->bios;
1186 u8 addr = nvbios_rd08(bios, init->offset + 1);
1187 u8 data = nvbios_rd08(bios, init->offset + 2);
1189 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1192 init_wrvgai(init, 0x03d4, addr, data);
1196 * INIT_ZM_CR_GROUP - opcode 0x54
1200 init_zm_cr_group(struct nvbios_init *init)
1202 struct nvkm_bios *bios = init->bios;
1203 u8 count = nvbios_rd08(bios, init->offset + 1);
1205 trace("ZM_CR_GROUP\n");
1209 u8 addr = nvbios_rd08(bios, init->offset + 0);
1210 u8 data = nvbios_rd08(bios, init->offset + 1);
1212 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1215 init_wrvgai(init, 0x03d4, addr, data);
1220 * INIT_CONDITION_TIME - opcode 0x56
1224 init_condition_time(struct nvbios_init *init)
1226 struct nvkm_bios *bios = init->bios;
1227 u8 cond = nvbios_rd08(bios, init->offset + 1);
1228 u8 retry = nvbios_rd08(bios, init->offset + 2);
1229 u8 wait = min((u16)retry * 50, 100);
1231 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1234 if (!init_exec(init))
1238 if (init_condition_met(init, cond))
1243 init_exec_set(init, false);
1247 * INIT_LTIME - opcode 0x57
1251 init_ltime(struct nvbios_init *init)
1253 struct nvkm_bios *bios = init->bios;
1254 u16 msec = nvbios_rd16(bios, init->offset + 1);
1256 trace("LTIME\t0x%04x\n", msec);
1259 if (init_exec(init))
1264 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1268 init_zm_reg_sequence(struct nvbios_init *init)
1270 struct nvkm_bios *bios = init->bios;
1271 u32 base = nvbios_rd32(bios, init->offset + 1);
1272 u8 count = nvbios_rd08(bios, init->offset + 5);
1274 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1278 u32 data = nvbios_rd32(bios, init->offset);
1280 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1283 init_wr32(init, base, data);
1289 * INIT_PLL_INDIRECT - opcode 0x59
1293 init_pll_indirect(struct nvbios_init *init)
1295 struct nvkm_bios *bios = init->bios;
1296 u32 reg = nvbios_rd32(bios, init->offset + 1);
1297 u16 addr = nvbios_rd16(bios, init->offset + 5);
1298 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000;
1300 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
1304 init_prog_pll(init, reg, freq);
1308 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1312 init_zm_reg_indirect(struct nvbios_init *init)
1314 struct nvkm_bios *bios = init->bios;
1315 u32 reg = nvbios_rd32(bios, init->offset + 1);
1316 u16 addr = nvbios_rd16(bios, init->offset + 5);
1317 u32 data = nvbios_rd32(bios, addr);
1319 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
1323 init_wr32(init, addr, data);
1327 * INIT_SUB_DIRECT - opcode 0x5b
1331 init_sub_direct(struct nvbios_init *init)
1333 struct nvkm_bios *bios = init->bios;
1334 u16 addr = nvbios_rd16(bios, init->offset + 1);
1337 trace("SUB_DIRECT\t0x%04x\n", addr);
1339 if (init_exec(init)) {
1340 save = init->offset;
1341 init->offset = addr;
1342 if (nvbios_exec(init)) {
1343 error("error parsing sub-table\n");
1346 init->offset = save;
1353 * INIT_JUMP - opcode 0x5c
1357 init_jump(struct nvbios_init *init)
1359 struct nvkm_bios *bios = init->bios;
1360 u16 offset = nvbios_rd16(bios, init->offset + 1);
1362 trace("JUMP\t0x%04x\n", offset);
1364 if (init_exec(init))
1365 init->offset = offset;
1371 * INIT_I2C_IF - opcode 0x5e
1375 init_i2c_if(struct nvbios_init *init)
1377 struct nvkm_bios *bios = init->bios;
1378 u8 index = nvbios_rd08(bios, init->offset + 1);
1379 u8 addr = nvbios_rd08(bios, init->offset + 2);
1380 u8 reg = nvbios_rd08(bios, init->offset + 3);
1381 u8 mask = nvbios_rd08(bios, init->offset + 4);
1382 u8 data = nvbios_rd08(bios, init->offset + 5);
1385 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1386 index, addr, reg, mask, data);
1388 init_exec_force(init, true);
1390 value = init_rdi2cr(init, index, addr, reg);
1391 if ((value & mask) != data)
1392 init_exec_set(init, false);
1394 init_exec_force(init, false);
1398 * INIT_COPY_NV_REG - opcode 0x5f
1402 init_copy_nv_reg(struct nvbios_init *init)
1404 struct nvkm_bios *bios = init->bios;
1405 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1406 u8 shift = nvbios_rd08(bios, init->offset + 5);
1407 u32 smask = nvbios_rd32(bios, init->offset + 6);
1408 u32 sxor = nvbios_rd32(bios, init->offset + 10);
1409 u32 dreg = nvbios_rd32(bios, init->offset + 14);
1410 u32 dmask = nvbios_rd32(bios, init->offset + 18);
1413 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1414 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1415 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1416 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1419 data = init_shift(init_rd32(init, sreg), shift);
1420 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1424 * INIT_ZM_INDEX_IO - opcode 0x62
1428 init_zm_index_io(struct nvbios_init *init)
1430 struct nvkm_bios *bios = init->bios;
1431 u16 port = nvbios_rd16(bios, init->offset + 1);
1432 u8 index = nvbios_rd08(bios, init->offset + 3);
1433 u8 data = nvbios_rd08(bios, init->offset + 4);
1435 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1438 init_wrvgai(init, port, index, data);
1442 * INIT_COMPUTE_MEM - opcode 0x63
1446 init_compute_mem(struct nvbios_init *init)
1448 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
1450 trace("COMPUTE_MEM\n");
1453 init_exec_force(init, true);
1454 if (init_exec(init))
1455 nvkm_devinit_meminit(devinit);
1456 init_exec_force(init, false);
1460 * INIT_RESET - opcode 0x65
1464 init_reset(struct nvbios_init *init)
1466 struct nvkm_bios *bios = init->bios;
1467 u32 reg = nvbios_rd32(bios, init->offset + 1);
1468 u32 data1 = nvbios_rd32(bios, init->offset + 5);
1469 u32 data2 = nvbios_rd32(bios, init->offset + 9);
1472 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1474 init_exec_force(init, true);
1476 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1477 init_wr32(init, reg, data1);
1479 init_wr32(init, reg, data2);
1480 init_wr32(init, 0x00184c, savepci19);
1481 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1483 init_exec_force(init, false);
1487 * INIT_CONFIGURE_MEM - opcode 0x66
1491 init_configure_mem_clk(struct nvbios_init *init)
1493 u16 mdata = bmp_mem_init_table(init->bios);
1495 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1500 init_configure_mem(struct nvbios_init *init)
1502 struct nvkm_bios *bios = init->bios;
1506 trace("CONFIGURE_MEM\n");
1509 if (bios->version.major > 2) {
1513 init_exec_force(init, true);
1515 mdata = init_configure_mem_clk(init);
1516 sdata = bmp_sdr_seq_table(bios);
1517 if (nvbios_rd08(bios, mdata) & 0x01)
1518 sdata = bmp_ddr_seq_table(bios);
1519 mdata += 6; /* skip to data */
1521 data = init_rdvgai(init, 0x03c4, 0x01);
1522 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1524 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) {
1526 case 0x10021c: /* CKE_NORMAL */
1527 case 0x1002d0: /* CMD_REFRESH */
1528 case 0x1002d4: /* CMD_PRECHARGE */
1532 data = nvbios_rd32(bios, mdata);
1534 if (data == 0xffffffff)
1539 init_wr32(init, addr, data);
1542 init_exec_force(init, false);
1546 * INIT_CONFIGURE_CLK - opcode 0x67
1550 init_configure_clk(struct nvbios_init *init)
1552 struct nvkm_bios *bios = init->bios;
1555 trace("CONFIGURE_CLK\n");
1558 if (bios->version.major > 2) {
1562 init_exec_force(init, true);
1564 mdata = init_configure_mem_clk(init);
1567 clock = nvbios_rd16(bios, mdata + 4) * 10;
1568 init_prog_pll(init, 0x680500, clock);
1571 clock = nvbios_rd16(bios, mdata + 2) * 10;
1572 if (nvbios_rd08(bios, mdata) & 0x01)
1574 init_prog_pll(init, 0x680504, clock);
1576 init_exec_force(init, false);
1580 * INIT_CONFIGURE_PREINIT - opcode 0x68
1584 init_configure_preinit(struct nvbios_init *init)
1586 struct nvkm_bios *bios = init->bios;
1589 trace("CONFIGURE_PREINIT\n");
1592 if (bios->version.major > 2) {
1596 init_exec_force(init, true);
1598 strap = init_rd32(init, 0x101000);
1599 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1600 init_wrvgai(init, 0x03d4, 0x3c, strap);
1602 init_exec_force(init, false);
1606 * INIT_IO - opcode 0x69
1610 init_io(struct nvbios_init *init)
1612 struct nvkm_bios *bios = init->bios;
1613 u16 port = nvbios_rd16(bios, init->offset + 1);
1614 u8 mask = nvbios_rd16(bios, init->offset + 3);
1615 u8 data = nvbios_rd16(bios, init->offset + 4);
1618 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1621 /* ummm.. yes.. should really figure out wtf this is and why it's
1622 * needed some day.. it's almost certainly wrong, but, it also
1623 * somehow makes things work...
1625 if (bios->subdev.device->card_type >= NV_50 &&
1626 port == 0x03c3 && data == 0x01) {
1627 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1628 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1629 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1630 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1632 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1633 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1634 init_wr32(init, 0x614100, 0x00800018);
1635 init_wr32(init, 0x614900, 0x00800018);
1637 init_wr32(init, 0x614100, 0x10000018);
1638 init_wr32(init, 0x614900, 0x10000018);
1641 value = init_rdport(init, port) & mask;
1642 init_wrport(init, port, data | value);
1646 * INIT_SUB - opcode 0x6b
1650 init_sub(struct nvbios_init *init)
1652 struct nvkm_bios *bios = init->bios;
1653 u8 index = nvbios_rd08(bios, init->offset + 1);
1656 trace("SUB\t0x%02x\n", index);
1658 addr = init_script(bios, index);
1659 if (addr && init_exec(init)) {
1660 save = init->offset;
1661 init->offset = addr;
1662 if (nvbios_exec(init)) {
1663 error("error parsing sub-table\n");
1666 init->offset = save;
1673 * INIT_RAM_CONDITION - opcode 0x6d
1677 init_ram_condition(struct nvbios_init *init)
1679 struct nvkm_bios *bios = init->bios;
1680 u8 mask = nvbios_rd08(bios, init->offset + 1);
1681 u8 value = nvbios_rd08(bios, init->offset + 2);
1683 trace("RAM_CONDITION\t"
1684 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1687 if ((init_rd32(init, 0x100000) & mask) != value)
1688 init_exec_set(init, false);
1692 * INIT_NV_REG - opcode 0x6e
1696 init_nv_reg(struct nvbios_init *init)
1698 struct nvkm_bios *bios = init->bios;
1699 u32 reg = nvbios_rd32(bios, init->offset + 1);
1700 u32 mask = nvbios_rd32(bios, init->offset + 5);
1701 u32 data = nvbios_rd32(bios, init->offset + 9);
1703 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1706 init_mask(init, reg, ~mask, data);
1710 * INIT_MACRO - opcode 0x6f
1714 init_macro(struct nvbios_init *init)
1716 struct nvkm_bios *bios = init->bios;
1717 u8 macro = nvbios_rd08(bios, init->offset + 1);
1720 trace("MACRO\t0x%02x\n", macro);
1722 table = init_macro_table(init);
1724 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0);
1725 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4);
1726 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1727 init_wr32(init, addr, data);
1734 * INIT_RESUME - opcode 0x72
1738 init_resume(struct nvbios_init *init)
1742 init_exec_set(init, true);
1746 * INIT_STRAP_CONDITION - opcode 0x73
1750 init_strap_condition(struct nvbios_init *init)
1752 struct nvkm_bios *bios = init->bios;
1753 u32 mask = nvbios_rd32(bios, init->offset + 1);
1754 u32 value = nvbios_rd32(bios, init->offset + 5);
1756 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value);
1759 if ((init_rd32(init, 0x101000) & mask) != value)
1760 init_exec_set(init, false);
1764 * INIT_TIME - opcode 0x74
1768 init_time(struct nvbios_init *init)
1770 struct nvkm_bios *bios = init->bios;
1771 u16 usec = nvbios_rd16(bios, init->offset + 1);
1773 trace("TIME\t0x%04x\n", usec);
1776 if (init_exec(init)) {
1780 mdelay((usec + 900) / 1000);
1785 * INIT_CONDITION - opcode 0x75
1789 init_condition(struct nvbios_init *init)
1791 struct nvkm_bios *bios = init->bios;
1792 u8 cond = nvbios_rd08(bios, init->offset + 1);
1794 trace("CONDITION\t0x%02x\n", cond);
1797 if (!init_condition_met(init, cond))
1798 init_exec_set(init, false);
1802 * INIT_IO_CONDITION - opcode 0x76
1806 init_io_condition(struct nvbios_init *init)
1808 struct nvkm_bios *bios = init->bios;
1809 u8 cond = nvbios_rd08(bios, init->offset + 1);
1811 trace("IO_CONDITION\t0x%02x\n", cond);
1814 if (!init_io_condition_met(init, cond))
1815 init_exec_set(init, false);
1819 * INIT_ZM_REG16 - opcode 0x77
1823 init_zm_reg16(struct nvbios_init *init)
1825 struct nvkm_bios *bios = init->bios;
1826 u32 addr = nvbios_rd32(bios, init->offset + 1);
1827 u16 data = nvbios_rd16(bios, init->offset + 5);
1829 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data);
1832 init_wr32(init, addr, data);
1836 * INIT_INDEX_IO - opcode 0x78
1840 init_index_io(struct nvbios_init *init)
1842 struct nvkm_bios *bios = init->bios;
1843 u16 port = nvbios_rd16(bios, init->offset + 1);
1844 u8 index = nvbios_rd16(bios, init->offset + 3);
1845 u8 mask = nvbios_rd08(bios, init->offset + 4);
1846 u8 data = nvbios_rd08(bios, init->offset + 5);
1849 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1850 port, index, mask, data);
1853 value = init_rdvgai(init, port, index) & mask;
1854 init_wrvgai(init, port, index, data | value);
1858 * INIT_PLL - opcode 0x79
1862 init_pll(struct nvbios_init *init)
1864 struct nvkm_bios *bios = init->bios;
1865 u32 reg = nvbios_rd32(bios, init->offset + 1);
1866 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10;
1868 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1871 init_prog_pll(init, reg, freq);
1875 * INIT_ZM_REG - opcode 0x7a
1879 init_zm_reg(struct nvbios_init *init)
1881 struct nvkm_bios *bios = init->bios;
1882 u32 addr = nvbios_rd32(bios, init->offset + 1);
1883 u32 data = nvbios_rd32(bios, init->offset + 5);
1885 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1888 if (addr == 0x000200)
1891 init_wr32(init, addr, data);
1895 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1899 init_ram_restrict_pll(struct nvbios_init *init)
1901 struct nvkm_bios *bios = init->bios;
1902 u8 type = nvbios_rd08(bios, init->offset + 1);
1903 u8 count = init_ram_restrict_group_count(init);
1904 u8 strap = init_ram_restrict(init);
1907 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1910 for (cconf = 0; cconf < count; cconf++) {
1911 u32 freq = nvbios_rd32(bios, init->offset);
1913 if (cconf == strap) {
1914 trace("%dkHz *\n", freq);
1915 init_prog_pll(init, type, freq);
1917 trace("%dkHz\n", freq);
1925 * INIT_GPIO - opcode 0x8e
1929 init_gpio(struct nvbios_init *init)
1931 struct nvkm_gpio *gpio = init->bios->subdev.device->gpio;
1936 if (init_exec(init))
1937 nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED);
1941 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1945 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1947 struct nvkm_bios *bios = init->bios;
1948 u32 addr = nvbios_rd32(bios, init->offset + 1);
1949 u8 incr = nvbios_rd08(bios, init->offset + 5);
1950 u8 num = nvbios_rd08(bios, init->offset + 6);
1951 u8 count = init_ram_restrict_group_count(init);
1952 u8 index = init_ram_restrict(init);
1955 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1956 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1959 for (i = 0; i < num; i++) {
1960 trace("\tR[0x%06x] = {\n", addr);
1961 for (j = 0; j < count; j++) {
1962 u32 data = nvbios_rd32(bios, init->offset);
1965 trace("\t\t0x%08x *\n", data);
1966 init_wr32(init, addr, data);
1968 trace("\t\t0x%08x\n", data);
1979 * INIT_COPY_ZM_REG - opcode 0x90
1983 init_copy_zm_reg(struct nvbios_init *init)
1985 struct nvkm_bios *bios = init->bios;
1986 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1987 u32 dreg = nvbios_rd32(bios, init->offset + 5);
1989 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1992 init_wr32(init, dreg, init_rd32(init, sreg));
1996 * INIT_ZM_REG_GROUP - opcode 0x91
2000 init_zm_reg_group(struct nvbios_init *init)
2002 struct nvkm_bios *bios = init->bios;
2003 u32 addr = nvbios_rd32(bios, init->offset + 1);
2004 u8 count = nvbios_rd08(bios, init->offset + 5);
2006 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
2010 u32 data = nvbios_rd32(bios, init->offset);
2011 trace("\t0x%08x\n", data);
2012 init_wr32(init, addr, data);
2018 * INIT_XLAT - opcode 0x96
2022 init_xlat(struct nvbios_init *init)
2024 struct nvkm_bios *bios = init->bios;
2025 u32 saddr = nvbios_rd32(bios, init->offset + 1);
2026 u8 sshift = nvbios_rd08(bios, init->offset + 5);
2027 u8 smask = nvbios_rd08(bios, init->offset + 6);
2028 u8 index = nvbios_rd08(bios, init->offset + 7);
2029 u32 daddr = nvbios_rd32(bios, init->offset + 8);
2030 u32 dmask = nvbios_rd32(bios, init->offset + 12);
2031 u8 shift = nvbios_rd08(bios, init->offset + 16);
2034 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
2035 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
2036 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
2037 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
2040 data = init_shift(init_rd32(init, saddr), sshift) & smask;
2041 data = init_xlat_(init, index, data) << shift;
2042 init_mask(init, daddr, ~dmask, data);
2046 * INIT_ZM_MASK_ADD - opcode 0x97
2050 init_zm_mask_add(struct nvbios_init *init)
2052 struct nvkm_bios *bios = init->bios;
2053 u32 addr = nvbios_rd32(bios, init->offset + 1);
2054 u32 mask = nvbios_rd32(bios, init->offset + 5);
2055 u32 add = nvbios_rd32(bios, init->offset + 9);
2058 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
2061 data = init_rd32(init, addr);
2062 data = (data & mask) | ((data + add) & ~mask);
2063 init_wr32(init, addr, data);
2067 * INIT_AUXCH - opcode 0x98
2071 init_auxch(struct nvbios_init *init)
2073 struct nvkm_bios *bios = init->bios;
2074 u32 addr = nvbios_rd32(bios, init->offset + 1);
2075 u8 count = nvbios_rd08(bios, init->offset + 5);
2077 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2081 u8 mask = nvbios_rd08(bios, init->offset + 0);
2082 u8 data = nvbios_rd08(bios, init->offset + 1);
2083 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2084 mask = init_rdauxr(init, addr) & mask;
2085 init_wrauxr(init, addr, mask | data);
2091 * INIT_AUXCH - opcode 0x99
2095 init_zm_auxch(struct nvbios_init *init)
2097 struct nvkm_bios *bios = init->bios;
2098 u32 addr = nvbios_rd32(bios, init->offset + 1);
2099 u8 count = nvbios_rd08(bios, init->offset + 5);
2101 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2105 u8 data = nvbios_rd08(bios, init->offset + 0);
2106 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2107 init_wrauxr(init, addr, data);
2113 * INIT_I2C_LONG_IF - opcode 0x9a
2117 init_i2c_long_if(struct nvbios_init *init)
2119 struct nvkm_bios *bios = init->bios;
2120 u8 index = nvbios_rd08(bios, init->offset + 1);
2121 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
2122 u8 reglo = nvbios_rd08(bios, init->offset + 3);
2123 u8 reghi = nvbios_rd08(bios, init->offset + 4);
2124 u8 mask = nvbios_rd08(bios, init->offset + 5);
2125 u8 data = nvbios_rd08(bios, init->offset + 6);
2126 struct i2c_adapter *adap;
2128 trace("I2C_LONG_IF\t"
2129 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2130 index, addr, reglo, reghi, mask, data);
2133 adap = init_i2c(init, index);
2135 u8 i[2] = { reghi, reglo };
2137 struct i2c_msg msg[] = {
2138 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2139 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2143 ret = i2c_transfer(adap, msg, 2);
2144 if (ret == 2 && ((o[0] & mask) == data))
2148 init_exec_set(init, false);
2152 * INIT_GPIO_NE - opcode 0xa9
2156 init_gpio_ne(struct nvbios_init *init)
2158 struct nvkm_bios *bios = init->bios;
2159 struct nvkm_gpio *gpio = bios->subdev.device->gpio;
2160 struct dcb_gpio_func func;
2161 u8 count = nvbios_rd08(bios, init->offset + 1);
2162 u8 idx = 0, ver, len;
2168 for (i = init->offset; i < init->offset + count; i++)
2169 cont("0x%02x ", nvbios_rd08(bios, i));
2172 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2173 if (func.func != DCB_GPIO_UNUSED) {
2174 for (i = init->offset; i < init->offset + count; i++) {
2175 if (func.func == nvbios_rd08(bios, i))
2179 trace("\tFUNC[0x%02x]", func.func);
2180 if (i == (init->offset + count)) {
2182 if (init_exec(init))
2183 nvkm_gpio_reset(gpio, func.func);
2189 init->offset += count;
2192 static struct nvbios_init_opcode {
2193 void (*exec)(struct nvbios_init *);
2195 [0x32] = { init_io_restrict_prog },
2196 [0x33] = { init_repeat },
2197 [0x34] = { init_io_restrict_pll },
2198 [0x36] = { init_end_repeat },
2199 [0x37] = { init_copy },
2200 [0x38] = { init_not },
2201 [0x39] = { init_io_flag_condition },
2202 [0x3a] = { init_dp_condition },
2203 [0x3b] = { init_io_mask_or },
2204 [0x3c] = { init_io_or },
2205 [0x47] = { init_andn_reg },
2206 [0x48] = { init_or_reg },
2207 [0x49] = { init_idx_addr_latched },
2208 [0x4a] = { init_io_restrict_pll2 },
2209 [0x4b] = { init_pll2 },
2210 [0x4c] = { init_i2c_byte },
2211 [0x4d] = { init_zm_i2c_byte },
2212 [0x4e] = { init_zm_i2c },
2213 [0x4f] = { init_tmds },
2214 [0x50] = { init_zm_tmds_group },
2215 [0x51] = { init_cr_idx_adr_latch },
2216 [0x52] = { init_cr },
2217 [0x53] = { init_zm_cr },
2218 [0x54] = { init_zm_cr_group },
2219 [0x56] = { init_condition_time },
2220 [0x57] = { init_ltime },
2221 [0x58] = { init_zm_reg_sequence },
2222 [0x59] = { init_pll_indirect },
2223 [0x5a] = { init_zm_reg_indirect },
2224 [0x5b] = { init_sub_direct },
2225 [0x5c] = { init_jump },
2226 [0x5e] = { init_i2c_if },
2227 [0x5f] = { init_copy_nv_reg },
2228 [0x62] = { init_zm_index_io },
2229 [0x63] = { init_compute_mem },
2230 [0x65] = { init_reset },
2231 [0x66] = { init_configure_mem },
2232 [0x67] = { init_configure_clk },
2233 [0x68] = { init_configure_preinit },
2234 [0x69] = { init_io },
2235 [0x6b] = { init_sub },
2236 [0x6d] = { init_ram_condition },
2237 [0x6e] = { init_nv_reg },
2238 [0x6f] = { init_macro },
2239 [0x71] = { init_done },
2240 [0x72] = { init_resume },
2241 [0x73] = { init_strap_condition },
2242 [0x74] = { init_time },
2243 [0x75] = { init_condition },
2244 [0x76] = { init_io_condition },
2245 [0x77] = { init_zm_reg16 },
2246 [0x78] = { init_index_io },
2247 [0x79] = { init_pll },
2248 [0x7a] = { init_zm_reg },
2249 [0x87] = { init_ram_restrict_pll },
2250 [0x8c] = { init_reserved },
2251 [0x8d] = { init_reserved },
2252 [0x8e] = { init_gpio },
2253 [0x8f] = { init_ram_restrict_zm_reg_group },
2254 [0x90] = { init_copy_zm_reg },
2255 [0x91] = { init_zm_reg_group },
2256 [0x92] = { init_reserved },
2257 [0x96] = { init_xlat },
2258 [0x97] = { init_zm_mask_add },
2259 [0x98] = { init_auxch },
2260 [0x99] = { init_zm_auxch },
2261 [0x9a] = { init_i2c_long_if },
2262 [0xa9] = { init_gpio_ne },
2263 [0xaa] = { init_reserved },
2266 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2269 nvbios_exec(struct nvbios_init *init)
2272 while (init->offset) {
2273 u8 opcode = nvbios_rd08(init->bios, init->offset);
2274 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2275 error("unknown opcode 0x%02x\n", opcode);
2279 init_opcode[opcode].exec(init);
2286 nvbios_init(struct nvkm_subdev *subdev, bool execute)
2288 struct nvkm_bios *bios = subdev->device->bios;
2294 nvkm_debug(subdev, "running init tables\n");
2295 while (!ret && (data = (init_script(bios, ++i)))) {
2296 struct nvbios_init init = {
2302 .execute = execute ? 1 : 0,
2305 ret = nvbios_exec(&init);
2308 /* the vbios parser will run this right after the normal init
2309 * tables, whereas the binary driver appears to run it later.
2311 if (!ret && (data = init_unknown_script(bios))) {
2312 struct nvbios_init init = {
2318 .execute = execute ? 1 : 0,
2321 ret = nvbios_exec(&init);