drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

   1 /*
   2  * DMM IOMMU driver support functions for TI OMAP processors.
   3  *
   4  * Author: Rob Clark <rob@ti.com>
   5  *         Andy Gross <andy.gross@ti.com>
   6  *
   7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/list.h>
  26 #include <linux/mm.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h> /* platform_device() */
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/time.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/wait.h>
  34
  35 #include "omap_dmm_tiler.h"
  36 #include "omap_dmm_priv.h"
  37
  38 #define DMM_DRIVER_NAME "dmm"
  39
  40 /* mappings for associating views to luts */
  41 static struct tcm *containers[TILFMT_NFORMATS];
  42 static struct dmm *omap_dmm;
  43
  44 #if defined(CONFIG_OF)
  45 static const struct of_device_id dmm_of_match[];
  46 #endif
  47
  48 /* global spinlock for protecting lists */
  49 static DEFINE_SPINLOCK(list_lock);
  50
  51 /* Geometry table */
  52 #define GEOM(xshift, yshift, bytes_per_pixel) { \
  53                 .x_shft = (xshift), \
  54                 .y_shft = (yshift), \
  55                 .cpp    = (bytes_per_pixel), \
  56                 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
  57                 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
  58         }
  59
  60 static const struct {
  61         uint32_t x_shft;        /* unused X-bits (as part of bpp) */
  62         uint32_t y_shft;        /* unused Y-bits (as part of bpp) */
  63         uint32_t cpp;           /* bytes/chars per pixel */
  64         uint32_t slot_w;        /* width of each slot (in pixels) */
  65         uint32_t slot_h;        /* height of each slot (in pixels) */
  66 } geom[TILFMT_NFORMATS] = {
  67         [TILFMT_8BIT]  = GEOM(0, 0, 1),
  68         [TILFMT_16BIT] = GEOM(0, 1, 2),
  69         [TILFMT_32BIT] = GEOM(1, 1, 4),
  70         [TILFMT_PAGE]  = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
  71 };
  72
  73
  74 /* lookup table for registers w/ per-engine instances */
  75 static const uint32_t reg[][4] = {
  76         [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
  77                         DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
  78         [PAT_DESCR]  = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
  79                         DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
  80 };
  81
  82 /* simple allocator to grab next 16 byte aligned memory from txn */
  83 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
  84 {
  85         void *ptr;
  86         struct refill_engine *engine = txn->engine_handle;
  87
  88         /* dmm programming requires 16 byte aligned addresses */
  89         txn->current_pa = round_up(txn->current_pa, 16);
  90         txn->current_va = (void *)round_up((long)txn->current_va, 16);
  91
  92         ptr = txn->current_va;
  93         *pa = txn->current_pa;
  94
  95         txn->current_pa += sz;
  96         txn->current_va += sz;
  97
  98         BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
  99
 100         return ptr;
 101 }
 102
 103 /* check status and spin until wait_mask comes true */
 104 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
 105 {
 106         struct dmm *dmm = engine->dmm;
 107         uint32_t r = 0, err, i;
 108
 109         i = DMM_FIXED_RETRY_COUNT;
 110         while (true) {
 111                 r = readl(dmm->base + reg[PAT_STATUS][engine->id]);
 112                 err = r & DMM_PATSTATUS_ERR;
 113                 if (err)
 114                         return -EFAULT;
 115
 116                 if ((r & wait_mask) == wait_mask)
 117                         break;
 118
 119                 if (--i == 0)
 120                         return -ETIMEDOUT;
 121
 122                 udelay(1);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static void release_engine(struct refill_engine *engine)
 129 {
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&list_lock, flags);
 133         list_add(&engine->idle_node, &omap_dmm->idle_head);
 134         spin_unlock_irqrestore(&list_lock, flags);
 135
 136         atomic_inc(&omap_dmm->engine_counter);
 137         wake_up_interruptible(&omap_dmm->engine_queue);
 138 }
 139
 140 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
 141 {
 142         struct dmm *dmm = arg;
 143         uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS);
 144         int i;
 145
 146         /* ack IRQ */
 147         writel(status, dmm->base + DMM_PAT_IRQSTATUS);
 148
 149         for (i = 0; i < dmm->num_engines; i++) {
 150                 if (status & DMM_IRQSTAT_LST) {
 151                         if (dmm->engines[i].async)
 152                                 release_engine(&dmm->engines[i]);
 153
 154                         complete(&dmm->engines[i].compl);
 155                 }
 156
 157                 status >>= 8;
 158         }
 159
 160         return IRQ_HANDLED;
 161 }
 162
 163 /**
 164  * Get a handle for a DMM transaction
 165  */
 166 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
 167 {
 168         struct dmm_txn *txn = NULL;
 169         struct refill_engine *engine = NULL;
 170         int ret;
 171         unsigned long flags;
 172
 173
 174         /* wait until an engine is available */
 175         ret = wait_event_interruptible(omap_dmm->engine_queue,
 176                 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
 177         if (ret)
 178                 return ERR_PTR(ret);
 179
 180         /* grab an idle engine */
 181         spin_lock_irqsave(&list_lock, flags);
 182         if (!list_empty(&dmm->idle_head)) {
 183                 engine = list_entry(dmm->idle_head.next, struct refill_engine,
 184                                         idle_node);
 185                 list_del(&engine->idle_node);
 186         }
 187         spin_unlock_irqrestore(&list_lock, flags);
 188
 189         BUG_ON(!engine);
 190
 191         txn = &engine->txn;
 192         engine->tcm = tcm;
 193         txn->engine_handle = engine;
 194         txn->last_pat = NULL;
 195         txn->current_va = engine->refill_va;
 196         txn->current_pa = engine->refill_pa;
 197
 198         return txn;
 199 }
 200
 201 /**
 202  * Add region to DMM transaction.  If pages or pages[i] is NULL, then the
 203  * corresponding slot is cleared (ie. dummy_pa is programmed)
 204  */
 205 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
 206                 struct page **pages, uint32_t npages, uint32_t roll)
 207 {
 208         dma_addr_t pat_pa = 0, data_pa = 0;
 209         uint32_t *data;
 210         struct pat *pat;
 211         struct refill_engine *engine = txn->engine_handle;
 212         int columns = (1 + area->x1 - area->x0);
 213         int rows = (1 + area->y1 - area->y0);
 214         int i = columns*rows;
 215
 216         pat = alloc_dma(txn, sizeof(struct pat), &pat_pa);
 217
 218         if (txn->last_pat)
 219                 txn->last_pat->next_pa = (uint32_t)pat_pa;
 220
 221         pat->area = *area;
 222
 223         /* adjust Y coordinates based off of container parameters */
 224         pat->area.y0 += engine->tcm->y_offset;
 225         pat->area.y1 += engine->tcm->y_offset;
 226
 227         pat->ctrl = (struct pat_ctrl){
 228                         .start = 1,
 229                         .lut_id = engine->tcm->lut_id,
 230                 };
 231
 232         data = alloc_dma(txn, 4*i, &data_pa);
 233         /* FIXME: what if data_pa is more than 32-bit ? */
 234         pat->data_pa = data_pa;
 235
 236         while (i--) {
 237                 int n = i + roll;
 238                 if (n >= npages)
 239                         n -= npages;
 240                 data[i] = (pages && pages[n]) ?
 241                         page_to_phys(pages[n]) : engine->dmm->dummy_pa;
 242         }
 243
 244         txn->last_pat = pat;
 245
 246         return;
 247 }
 248
 249 /**
 250  * Commit the DMM transaction.
 251  */
 252 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
 253 {
 254         int ret = 0;
 255         struct refill_engine *engine = txn->engine_handle;
 256         struct dmm *dmm = engine->dmm;
 257
 258         if (!txn->last_pat) {
 259                 dev_err(engine->dmm->dev, "need at least one txn\n");
 260                 ret = -EINVAL;
 261                 goto cleanup;
 262         }
 263
 264         txn->last_pat->next_pa = 0;
 265
 266         /* write to PAT_DESCR to clear out any pending transaction */
 267         writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]);
 268
 269         /* wait for engine ready: */
 270         ret = wait_status(engine, DMM_PATSTATUS_READY);
 271         if (ret) {
 272                 ret = -EFAULT;
 273                 goto cleanup;
 274         }
 275
 276         /* mark whether it is async to denote list management in IRQ handler */
 277         engine->async = wait ? false : true;
 278         reinit_completion(&engine->compl);
 279         /* verify that the irq handler sees the 'async' and completion value */
 280         smp_mb();
 281
 282         /* kick reload */
 283         writel(engine->refill_pa,
 284                 dmm->base + reg[PAT_DESCR][engine->id]);
 285
 286         if (wait) {
 287                 if (!wait_for_completion_timeout(&engine->compl,
 288                                 msecs_to_jiffies(1))) {
 289                         dev_err(dmm->dev, "timed out waiting for done\n");
 290                         ret = -ETIMEDOUT;
 291                 }
 292         }
 293
 294 cleanup:
 295         /* only place engine back on list if we are done with it */
 296         if (ret || wait)
 297                 release_engine(engine);
 298
 299         return ret;
 300 }
 301
 302 /*
 303  * DMM programming
 304  */
 305 static int fill(struct tcm_area *area, struct page **pages,
 306                 uint32_t npages, uint32_t roll, bool wait)
 307 {
 308         int ret = 0;
 309         struct tcm_area slice, area_s;
 310         struct dmm_txn *txn;
 311
 312         txn = dmm_txn_init(omap_dmm, area->tcm);
 313         if (IS_ERR_OR_NULL(txn))
 314                 return -ENOMEM;
 315
 316         tcm_for_each_slice(slice, *area, area_s) {
 317                 struct pat_area p_area = {
 318                                 .x0 = slice.p0.x,  .y0 = slice.p0.y,
 319                                 .x1 = slice.p1.x,  .y1 = slice.p1.y,
 320                 };
 321
 322                 dmm_txn_append(txn, &p_area, pages, npages, roll);
 323
 324                 roll += tcm_sizeof(slice);
 325         }
 326
 327         ret = dmm_txn_commit(txn, wait);
 328
 329         return ret;
 330 }
 331
 332 /*
 333  * Pin/unpin
 334  */
 335
 336 /* note: slots for which pages[i] == NULL are filled w/ dummy page
 337  */
 338 int tiler_pin(struct tiler_block *block, struct page **pages,
 339                 uint32_t npages, uint32_t roll, bool wait)
 340 {
 341         int ret;
 342
 343         ret = fill(&block->area, pages, npages, roll, wait);
 344
 345         if (ret)
 346                 tiler_unpin(block);
 347
 348         return ret;
 349 }
 350
 351 int tiler_unpin(struct tiler_block *block)
 352 {
 353         return fill(&block->area, NULL, 0, 0, false);
 354 }
 355
 356 /*
 357  * Reserve/release
 358  */
 359 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
 360                 uint16_t h, uint16_t align)
 361 {
 362         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 363         u32 min_align = 128;
 364         int ret;
 365         unsigned long flags;
 366
 367         BUG_ON(!validfmt(fmt));
 368
 369         /* convert width/height to slots */
 370         w = DIV_ROUND_UP(w, geom[fmt].slot_w);
 371         h = DIV_ROUND_UP(h, geom[fmt].slot_h);
 372
 373         /* convert alignment to slots */
 374         min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp));
 375         align = ALIGN(align, min_align);
 376         align /= geom[fmt].slot_w * geom[fmt].cpp;
 377
 378         block->fmt = fmt;
 379
 380         ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area);
 381         if (ret) {
 382                 kfree(block);
 383                 return ERR_PTR(-ENOMEM);
 384         }
 385
 386         /* add to allocation list */
 387         spin_lock_irqsave(&list_lock, flags);
 388         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 389         spin_unlock_irqrestore(&list_lock, flags);
 390
 391         return block;
 392 }
 393
 394 struct tiler_block *tiler_reserve_1d(size_t size)
 395 {
 396         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 397         int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 398         unsigned long flags;
 399
 400         if (!block)
 401                 return ERR_PTR(-ENOMEM);
 402
 403         block->fmt = TILFMT_PAGE;
 404
 405         if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
 406                                 &block->area)) {
 407                 kfree(block);
 408                 return ERR_PTR(-ENOMEM);
 409         }
 410
 411         spin_lock_irqsave(&list_lock, flags);
 412         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 413         spin_unlock_irqrestore(&list_lock, flags);
 414
 415         return block;
 416 }
 417
 418 /* note: if you have pin'd pages, you should have already unpin'd first! */
 419 int tiler_release(struct tiler_block *block)
 420 {
 421         int ret = tcm_free(&block->area);
 422         unsigned long flags;
 423
 424         if (block->area.tcm)
 425                 dev_err(omap_dmm->dev, "failed to release block\n");
 426
 427         spin_lock_irqsave(&list_lock, flags);
 428         list_del(&block->alloc_node);
 429         spin_unlock_irqrestore(&list_lock, flags);
 430
 431         kfree(block);
 432         return ret;
 433 }
 434
 435 /*
 436  * Utils
 437  */
 438
 439 /* calculate the tiler space address of a pixel in a view orientation...
 440  * below description copied from the display subsystem section of TRM:
 441  *
 442  * When the TILER is addressed, the bits:
 443  *   [28:27] = 0x0 for 8-bit tiled
 444  *             0x1 for 16-bit tiled
 445  *             0x2 for 32-bit tiled
 446  *             0x3 for page mode
 447  *   [31:29] = 0x0 for 0-degree view
 448  *             0x1 for 180-degree view + mirroring
 449  *             0x2 for 0-degree view + mirroring
 450  *             0x3 for 180-degree view
 451  *             0x4 for 270-degree view + mirroring
 452  *             0x5 for 270-degree view
 453  *             0x6 for 90-degree view
 454  *             0x7 for 90-degree view + mirroring
 455  * Otherwise the bits indicated the corresponding bit address to access
 456  * the SDRAM.
 457  */
 458 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
 459 {
 460         u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
 461
 462         x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
 463         y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
 464         alignment = geom[fmt].x_shft + geom[fmt].y_shft;
 465
 466         /* validate coordinate */
 467         x_mask = MASK(x_bits);
 468         y_mask = MASK(y_bits);
 469
 470         if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
 471                 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
 472                                 x, x, x_mask, y, y, y_mask);
 473                 return 0;
 474         }
 475
 476         /* account for mirroring */
 477         if (orient & MASK_X_INVERT)
 478                 x ^= x_mask;
 479         if (orient & MASK_Y_INVERT)
 480                 y ^= y_mask;
 481
 482         /* get coordinate address */
 483         if (orient & MASK_XY_FLIP)
 484                 tmp = ((x << y_bits) + y);
 485         else
 486                 tmp = ((y << x_bits) + x);
 487
 488         return TIL_ADDR((tmp << alignment), orient, fmt);
 489 }
 490
 491 dma_addr_t tiler_ssptr(struct tiler_block *block)
 492 {
 493         BUG_ON(!validfmt(block->fmt));
 494
 495         return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
 496                         block->area.p0.x * geom[block->fmt].slot_w,
 497                         block->area.p0.y * geom[block->fmt].slot_h);
 498 }
 499
 500 dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,
 501                 uint32_t x, uint32_t y)
 502 {
 503         struct tcm_pt *p = &block->area.p0;
 504         BUG_ON(!validfmt(block->fmt));
 505
 506         return tiler_get_address(block->fmt, orient,
 507                         (p->x * geom[block->fmt].slot_w) + x,
 508                         (p->y * geom[block->fmt].slot_h) + y);
 509 }
 510
 511 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
 512 {
 513         BUG_ON(!validfmt(fmt));
 514         *w = round_up(*w, geom[fmt].slot_w);
 515         *h = round_up(*h, geom[fmt].slot_h);
 516 }
 517
 518 uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)
 519 {
 520         BUG_ON(!validfmt(fmt));
 521
 522         if (orient & MASK_XY_FLIP)
 523                 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
 524         else
 525                 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
 526 }
 527
 528 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 529 {
 530         tiler_align(fmt, &w, &h);
 531         return geom[fmt].cpp * w * h;
 532 }
 533
 534 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 535 {
 536         BUG_ON(!validfmt(fmt));
 537         return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
 538 }
 539
 540 uint32_t tiler_get_cpu_cache_flags(void)
 541 {
 542         return omap_dmm->plat_data->cpu_cache_flags;
 543 }
 544
 545 bool dmm_is_available(void)
 546 {
 547         return omap_dmm ? true : false;
 548 }
 549
 550 static int omap_dmm_remove(struct platform_device *dev)
 551 {
 552         struct tiler_block *block, *_block;
 553         int i;
 554         unsigned long flags;
 555
 556         if (omap_dmm) {
 557                 /* free all area regions */
 558                 spin_lock_irqsave(&list_lock, flags);
 559                 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
 560                                         alloc_node) {
 561                         list_del(&block->alloc_node);
 562                         kfree(block);
 563                 }
 564                 spin_unlock_irqrestore(&list_lock, flags);
 565
 566                 for (i = 0; i < omap_dmm->num_lut; i++)
 567                         if (omap_dmm->tcm && omap_dmm->tcm[i])
 568                                 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
 569                 kfree(omap_dmm->tcm);
 570
 571                 kfree(omap_dmm->engines);
 572                 if (omap_dmm->refill_va)
 573                         dma_free_writecombine(omap_dmm->dev,
 574                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 575                                 omap_dmm->refill_va,
 576                                 omap_dmm->refill_pa);
 577                 if (omap_dmm->dummy_page)
 578                         __free_page(omap_dmm->dummy_page);
 579
 580                 if (omap_dmm->irq > 0)
 581                         free_irq(omap_dmm->irq, omap_dmm);
 582
 583                 iounmap(omap_dmm->base);
 584                 kfree(omap_dmm);
 585                 omap_dmm = NULL;
 586         }
 587
 588         return 0;
 589 }
 590
 591 static int omap_dmm_probe(struct platform_device *dev)
 592 {
 593         int ret = -EFAULT, i;
 594         struct tcm_area area = {0};
 595         u32 hwinfo, pat_geom;
 596         struct resource *mem;
 597
 598         omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
 599         if (!omap_dmm)
 600                 goto fail;
 601
 602         /* initialize lists */
 603         INIT_LIST_HEAD(&omap_dmm->alloc_head);
 604         INIT_LIST_HEAD(&omap_dmm->idle_head);
 605
 606         init_waitqueue_head(&omap_dmm->engine_queue);
 607
 608         if (dev->dev.of_node) {
 609                 const struct of_device_id *match;
 610
 611                 match = of_match_node(dmm_of_match, dev->dev.of_node);
 612                 if (!match) {
 613                         dev_err(&dev->dev, "failed to find matching device node\n");
 614                         return -ENODEV;
 615                 }
 616
 617                 omap_dmm->plat_data = match->data;
 618         }
 619
 620         /* lookup hwmod data - base address and irq */
 621         mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
 622         if (!mem) {
 623                 dev_err(&dev->dev, "failed to get base address resource\n");
 624                 goto fail;
 625         }
 626
 627         omap_dmm->base = ioremap(mem->start, SZ_2K);
 628
 629         if (!omap_dmm->base) {
 630                 dev_err(&dev->dev, "failed to get dmm base address\n");
 631                 goto fail;
 632         }
 633
 634         omap_dmm->irq = platform_get_irq(dev, 0);
 635         if (omap_dmm->irq < 0) {
 636                 dev_err(&dev->dev, "failed to get IRQ resource\n");
 637                 goto fail;
 638         }
 639
 640         omap_dmm->dev = &dev->dev;
 641
 642         hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO);
 643         omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
 644         omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
 645         omap_dmm->container_width = 256;
 646         omap_dmm->container_height = 128;
 647
 648         atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
 649
 650         /* read out actual LUT width and height */
 651         pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY);
 652         omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
 653         omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
 654
 655         /* increment LUT by one if on OMAP5 */
 656         /* LUT has twice the height, and is split into a separate container */
 657         if (omap_dmm->lut_height != omap_dmm->container_height)
 658                 omap_dmm->num_lut++;
 659
 660         /* initialize DMM registers */
 661         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0);
 662         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1);
 663         writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0);
 664         writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE);
 665         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0);
 666         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1);
 667
 668         ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
 669                                 "omap_dmm_irq_handler", omap_dmm);
 670
 671         if (ret) {
 672                 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
 673                         omap_dmm->irq, ret);
 674                 omap_dmm->irq = -1;
 675                 goto fail;
 676         }
 677
 678         /* Enable all interrupts for each refill engine except
 679          * ERR_LUT_MISS<n> (which is just advisory, and we don't care
 680          * about because we want to be able to refill live scanout
 681          * buffers for accelerated pan/scroll) and FILL_DSC<n> which
 682          * we just generally don't care about.
 683          */
 684         writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET);
 685
 686         omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
 687         if (!omap_dmm->dummy_page) {
 688                 dev_err(&dev->dev, "could not allocate dummy page\n");
 689                 ret = -ENOMEM;
 690                 goto fail;
 691         }
 692
 693         /* set dma mask for device */
 694         ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 695         if (ret)
 696                 goto fail;
 697
 698         omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
 699
 700         /* alloc refill memory */
 701         omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev,
 702                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 703                                 &omap_dmm->refill_pa, GFP_KERNEL);
 704         if (!omap_dmm->refill_va) {
 705                 dev_err(&dev->dev, "could not allocate refill memory\n");
 706                 goto fail;
 707         }
 708
 709         /* alloc engines */
 710         omap_dmm->engines = kcalloc(omap_dmm->num_engines,
 711                                     sizeof(struct refill_engine), GFP_KERNEL);
 712         if (!omap_dmm->engines) {
 713                 ret = -ENOMEM;
 714                 goto fail;
 715         }
 716
 717         for (i = 0; i < omap_dmm->num_engines; i++) {
 718                 omap_dmm->engines[i].id = i;
 719                 omap_dmm->engines[i].dmm = omap_dmm;
 720                 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
 721                                                 (REFILL_BUFFER_SIZE * i);
 722                 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
 723                                                 (REFILL_BUFFER_SIZE * i);
 724                 init_completion(&omap_dmm->engines[i].compl);
 725
 726                 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
 727         }
 728
 729         omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm),
 730                                 GFP_KERNEL);
 731         if (!omap_dmm->tcm) {
 732                 ret = -ENOMEM;
 733                 goto fail;
 734         }
 735
 736         /* init containers */
 737         /* Each LUT is associated with a TCM (container manager).  We use the
 738            lut_id to denote the lut_id used to identify the correct LUT for
 739            programming during reill operations */
 740         for (i = 0; i < omap_dmm->num_lut; i++) {
 741                 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
 742                                                 omap_dmm->container_height,
 743                                                 NULL);
 744
 745                 if (!omap_dmm->tcm[i]) {
 746                         dev_err(&dev->dev, "failed to allocate container\n");
 747                         ret = -ENOMEM;
 748                         goto fail;
 749                 }
 750
 751                 omap_dmm->tcm[i]->lut_id = i;
 752         }
 753
 754         /* assign access mode containers to applicable tcm container */
 755         /* OMAP 4 has 1 container for all 4 views */
 756         /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */
 757         containers[TILFMT_8BIT] = omap_dmm->tcm[0];
 758         containers[TILFMT_16BIT] = omap_dmm->tcm[0];
 759         containers[TILFMT_32BIT] = omap_dmm->tcm[0];
 760
 761         if (omap_dmm->container_height != omap_dmm->lut_height) {
 762                 /* second LUT is used for PAGE mode.  Programming must use
 763                    y offset that is added to all y coordinates.  LUT id is still
 764                    0, because it is the same LUT, just the upper 128 lines */
 765                 containers[TILFMT_PAGE] = omap_dmm->tcm[1];
 766                 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET;
 767                 omap_dmm->tcm[1]->lut_id = 0;
 768         } else {
 769                 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
 770         }
 771
 772         area = (struct tcm_area) {
 773                 .tcm = NULL,
 774                 .p1.x = omap_dmm->container_width - 1,
 775                 .p1.y = omap_dmm->container_height - 1,
 776         };
 777
 778         /* initialize all LUTs to dummy page entries */
 779         for (i = 0; i < omap_dmm->num_lut; i++) {
 780                 area.tcm = omap_dmm->tcm[i];
 781                 if (fill(&area, NULL, 0, 0, true))
 782                         dev_err(omap_dmm->dev, "refill failed");
 783         }
 784
 785         dev_info(omap_dmm->dev, "initialized all PAT entries\n");
 786
 787         return 0;
 788
 789 fail:
 790         if (omap_dmm_remove(dev))
 791                 dev_err(&dev->dev, "cleanup failed\n");
 792         return ret;
 793 }
 794
 795 /*
 796  * debugfs support
 797  */
 798
 799 #ifdef CONFIG_DEBUG_FS
 800
 801 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
 802                                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
 803 static const char *special = ".,:;'\"`~!^-+";
 804
 805 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
 806                                                         char c, bool ovw)
 807 {
 808         int x, y;
 809         for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
 810                 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
 811                         if (map[y][x] == ' ' || ovw)
 812                                 map[y][x] = c;
 813 }
 814
 815 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
 816                                                                         char c)
 817 {
 818         map[p->y / ydiv][p->x / xdiv] = c;
 819 }
 820
 821 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
 822 {
 823         return map[p->y / ydiv][p->x / xdiv];
 824 }
 825
 826 static int map_width(int xdiv, int x0, int x1)
 827 {
 828         return (x1 / xdiv) - (x0 / xdiv) + 1;
 829 }
 830
 831 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
 832 {
 833         char *p = map[yd] + (x0 / xdiv);
 834         int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
 835         if (w >= 0) {
 836                 p += w;
 837                 while (*nice)
 838                         *p++ = *nice++;
 839         }
 840 }
 841
 842 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
 843                                                         struct tcm_area *a)
 844 {
 845         sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
 846         if (a->p0.y + 1 < a->p1.y) {
 847                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
 848                                                         256 - 1);
 849         } else if (a->p0.y < a->p1.y) {
 850                 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
 851                         text_map(map, xdiv, nice, a->p0.y / ydiv,
 852                                         a->p0.x + xdiv, 256 - 1);
 853                 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
 854                         text_map(map, xdiv, nice, a->p1.y / ydiv,
 855                                         0, a->p1.y - xdiv);
 856         } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
 857                 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
 858         }
 859 }
 860
 861 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
 862                                                         struct tcm_area *a)
 863 {
 864         sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
 865         if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
 866                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
 867                                                         a->p0.x, a->p1.x);
 868 }
 869
 870 int tiler_map_show(struct seq_file *s, void *arg)
 871 {
 872         int xdiv = 2, ydiv = 1;
 873         char **map = NULL, *global_map;
 874         struct tiler_block *block;
 875         struct tcm_area a, p;
 876         int i;
 877         const char *m2d = alphabet;
 878         const char *a2d = special;
 879         const char *m2dp = m2d, *a2dp = a2d;
 880         char nice[128];
 881         int h_adj;
 882         int w_adj;
 883         unsigned long flags;
 884         int lut_idx;
 885
 886
 887         if (!omap_dmm) {
 888                 /* early return if dmm/tiler device is not initialized */
 889                 return 0;
 890         }
 891
 892         h_adj = omap_dmm->container_height / ydiv;
 893         w_adj = omap_dmm->container_width / xdiv;
 894
 895         map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL);
 896         global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL);
 897
 898         if (!map || !global_map)
 899                 goto error;
 900
 901         for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) {
 902                 memset(map, 0, h_adj * sizeof(*map));
 903                 memset(global_map, ' ', (w_adj + 1) * h_adj);
 904
 905                 for (i = 0; i < omap_dmm->container_height; i++) {
 906                         map[i] = global_map + i * (w_adj + 1);
 907                         map[i][w_adj] = 0;
 908                 }
 909
 910                 spin_lock_irqsave(&list_lock, flags);
 911
 912                 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
 913                         if (block->area.tcm == omap_dmm->tcm[lut_idx]) {
 914                                 if (block->fmt != TILFMT_PAGE) {
 915                                         fill_map(map, xdiv, ydiv, &block->area,
 916                                                 *m2dp, true);
 917                                         if (!*++a2dp)
 918                                                 a2dp = a2d;
 919                                         if (!*++m2dp)
 920                                                 m2dp = m2d;
 921                                         map_2d_info(map, xdiv, ydiv, nice,
 922                                                         &block->area);
 923                                 } else {
 924                                         bool start = read_map_pt(map, xdiv,
 925                                                 ydiv, &block->area.p0) == ' ';
 926                                         bool end = read_map_pt(map, xdiv, ydiv,
 927                                                         &block->area.p1) == ' ';
 928
 929                                         tcm_for_each_slice(a, block->area, p)
 930                                                 fill_map(map, xdiv, ydiv, &a,
 931                                                         '=', true);
 932                                         fill_map_pt(map, xdiv, ydiv,
 933                                                         &block->area.p0,
 934                                                         start ? '<' : 'X');
 935                                         fill_map_pt(map, xdiv, ydiv,
 936                                                         &block->area.p1,
 937                                                         end ? '>' : 'X');
 938                                         map_1d_info(map, xdiv, ydiv, nice,
 939                                                         &block->area);
 940                                 }
 941                         }
 942                 }
 943
 944                 spin_unlock_irqrestore(&list_lock, flags);
 945
 946                 if (s) {
 947                         seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx);
 948                         for (i = 0; i < 128; i++)
 949                                 seq_printf(s, "%03d:%s\n", i, map[i]);
 950                         seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx);
 951                 } else {
 952                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n",
 953                                 lut_idx);
 954                         for (i = 0; i < 128; i++)
 955                                 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
 956                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n",
 957                                 lut_idx);
 958                 }
 959         }
 960
 961 error:
 962         kfree(map);
 963         kfree(global_map);
 964
 965         return 0;
 966 }
 967 #endif
 968
 969 #ifdef CONFIG_PM_SLEEP
 970 static int omap_dmm_resume(struct device *dev)
 971 {
 972         struct tcm_area area;
 973         int i;
 974
 975         if (!omap_dmm)
 976                 return -ENODEV;
 977
 978         area = (struct tcm_area) {
 979                 .tcm = NULL,
 980                 .p1.x = omap_dmm->container_width - 1,
 981                 .p1.y = omap_dmm->container_height - 1,
 982         };
 983
 984         /* initialize all LUTs to dummy page entries */
 985         for (i = 0; i < omap_dmm->num_lut; i++) {
 986                 area.tcm = omap_dmm->tcm[i];
 987                 if (fill(&area, NULL, 0, 0, true))
 988                         dev_err(dev, "refill failed");
 989         }
 990
 991         return 0;
 992 }
 993 #endif
 994
 995 static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
 996
 997 #if defined(CONFIG_OF)
 998 static const struct dmm_platform_data dmm_omap4_platform_data = {
 999         .cpu_cache_flags = OMAP_BO_WC,
1000 };
1001
1002 static const struct dmm_platform_data dmm_omap5_platform_data = {
1003         .cpu_cache_flags = OMAP_BO_UNCACHED,
1004 };
1005
1006 static const struct of_device_id dmm_of_match[] = {
1007         {
1008                 .compatible = "ti,omap4-dmm",
1009                 .data = &dmm_omap4_platform_data,
1010         },
1011         {
1012                 .compatible = "ti,omap5-dmm",
1013                 .data = &dmm_omap5_platform_data,
1014         },
1015         {},
1016 };
1017 #endif
1018
1019 struct platform_driver omap_dmm_driver = {
1020         .probe = omap_dmm_probe,
1021         .remove = omap_dmm_remove,
1022         .driver = {
1023                 .owner = THIS_MODULE,
1024                 .name = DMM_DRIVER_NAME,
1025                 .of_match_table = of_match_ptr(dmm_of_match),
1026                 .pm = &omap_dmm_pm_ops,
1027         },
1028 };
1029
1030 MODULE_LICENSE("GPL v2");
1031 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
1032 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");
1033 MODULE_ALIAS("platform:" DMM_DRIVER_NAME);