drivers/gpu/drm/radeon/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "cikd.h"
  27 #include "r600_dpm.h"
  28 #include "ci_dpm.h"
  29 #include "atom.h"
  30 #include <linux/seq_file.h>
  31
  32 #define MC_CG_ARB_FREQ_F0           0x0a
  33 #define MC_CG_ARB_FREQ_F1           0x0b
  34 #define MC_CG_ARB_FREQ_F2           0x0c
  35 #define MC_CG_ARB_FREQ_F3           0x0d
  36
  37 #define SMC_RAM_END 0x40000
  38
  39 #define VOLTAGE_SCALE               4
  40 #define VOLTAGE_VID_OFFSET_SCALE1    625
  41 #define VOLTAGE_VID_OFFSET_SCALE2    100
  42
  43 static const struct ci_pt_defaults defaults_hawaii_xt =
  44 {
  45         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  46         { 0x84,  0x0,   0x0,   0x7F,  0x0,   0x0,   0x5A,  0x60,  0x51,  0x8E,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  47         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  48 };
  49
  50 static const struct ci_pt_defaults defaults_hawaii_pro =
  51 {
  52         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  53         { 0x93,  0x0,   0x0,   0x97,  0x0,   0x0,   0x6B,  0x60,  0x51,  0x95,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  54         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  55 };
  56
  57 static const struct ci_pt_defaults defaults_bonaire_xt =
  58 {
  59         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  60         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  61         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  62 };
  63
  64 static const struct ci_pt_defaults defaults_bonaire_pro =
  65 {
  66         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  67         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  68         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  69 };
  70
  71 static const struct ci_pt_defaults defaults_saturn_xt =
  72 {
  73         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  74         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  75         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  76 };
  77
  78 static const struct ci_pt_defaults defaults_saturn_pro =
  79 {
  80         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  81         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
  82         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  83 };
  84
  85 static const struct ci_pt_config_reg didt_config_ci[] =
  86 {
  87         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  88         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  89         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  90         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  91         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  92         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  93         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  94         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  95         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  96         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  97         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  98         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  99         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 100         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 101         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 102         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 103         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 104         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 105         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 106         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 107         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 108         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 109         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0xFFFFFFFF }
 160 };
 161
 162 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 163 extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
 164                                                             u32 *max_clock);
 165 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 166                                        u32 arb_freq_src, u32 arb_freq_dest);
 167 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 168 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
 169 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
 170                                                      u32 max_voltage_steps,
 171                                                      struct atom_voltage_table *voltage_table);
 172 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 173 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
 174 extern void cik_update_cg(struct radeon_device *rdev,
 175                           u32 block, bool enable);
 176
 177 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 178                                          struct atom_voltage_table_entry *voltage_table,
 179                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 180 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
 181 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
 182                                        u32 target_tdp);
 183 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 184
 185 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
 186 {
 187         struct ci_power_info *pi = rdev->pm.dpm.priv;
 188
 189         return pi;
 190 }
 191
 192 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
 193 {
 194         struct ci_ps *ps = rps->ps_priv;
 195
 196         return ps;
 197 }
 198
 199 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
 200 {
 201         struct ci_power_info *pi = ci_get_pi(rdev);
 202
 203         switch (rdev->pdev->device) {
 204         case 0x6650:
 205         case 0x6658:
 206         case 0x665C:
 207         default:
 208                 pi->powertune_defaults = &defaults_bonaire_xt;
 209                 break;
 210         case 0x6651:
 211         case 0x665D:
 212                 pi->powertune_defaults = &defaults_bonaire_pro;
 213                 break;
 214         case 0x6640:
 215                 pi->powertune_defaults = &defaults_saturn_xt;
 216                 break;
 217         case 0x6641:
 218                 pi->powertune_defaults = &defaults_saturn_pro;
 219                 break;
 220         case 0x67B8:
 221         case 0x67B0:
 222         case 0x67A0:
 223         case 0x67A1:
 224         case 0x67A2:
 225         case 0x67A8:
 226         case 0x67A9:
 227         case 0x67AA:
 228         case 0x67B9:
 229         case 0x67BE:
 230                 pi->powertune_defaults = &defaults_hawaii_xt;
 231                 break;
 232         case 0x67BA:
 233         case 0x67B1:
 234                 pi->powertune_defaults = &defaults_hawaii_pro;
 235                 break;
 236         }
 237
 238         pi->dte_tj_offset = 0;
 239
 240         pi->caps_power_containment = true;
 241         pi->caps_cac = false;
 242         pi->caps_sq_ramping = false;
 243         pi->caps_db_ramping = false;
 244         pi->caps_td_ramping = false;
 245         pi->caps_tcp_ramping = false;
 246
 247         if (pi->caps_power_containment) {
 248                 pi->caps_cac = true;
 249                 pi->enable_bapm_feature = true;
 250                 pi->enable_tdc_limit_feature = true;
 251                 pi->enable_pkg_pwr_tracking_feature = true;
 252         }
 253 }
 254
 255 static u8 ci_convert_to_vid(u16 vddc)
 256 {
 257         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 258 }
 259
 260 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
 261 {
 262         struct ci_power_info *pi = ci_get_pi(rdev);
 263         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 264         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 265         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 266         u32 i;
 267
 268         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 269                 return -EINVAL;
 270         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 271                 return -EINVAL;
 272         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
 273             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 274                 return -EINVAL;
 275
 276         for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 277                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 278                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 279                         hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 280                         hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 281                 } else {
 282                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 283                         hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 284                 }
 285         }
 286         return 0;
 287 }
 288
 289 static int ci_populate_vddc_vid(struct radeon_device *rdev)
 290 {
 291         struct ci_power_info *pi = ci_get_pi(rdev);
 292         u8 *vid = pi->smc_powertune_table.VddCVid;
 293         u32 i;
 294
 295         if (pi->vddc_voltage_table.count > 8)
 296                 return -EINVAL;
 297
 298         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 299                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 300
 301         return 0;
 302 }
 303
 304 static int ci_populate_svi_load_line(struct radeon_device *rdev)
 305 {
 306         struct ci_power_info *pi = ci_get_pi(rdev);
 307         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 308
 309         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 310         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 311         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 312         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 313
 314         return 0;
 315 }
 316
 317 static int ci_populate_tdc_limit(struct radeon_device *rdev)
 318 {
 319         struct ci_power_info *pi = ci_get_pi(rdev);
 320         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 321         u16 tdc_limit;
 322
 323         tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 324         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 325         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 326                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 327         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 328
 329         return 0;
 330 }
 331
 332 static int ci_populate_dw8(struct radeon_device *rdev)
 333 {
 334         struct ci_power_info *pi = ci_get_pi(rdev);
 335         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 336         int ret;
 337
 338         ret = ci_read_smc_sram_dword(rdev,
 339                                      SMU7_FIRMWARE_HEADER_LOCATION +
 340                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 341                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 342                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 343                                      pi->sram_end);
 344         if (ret)
 345                 return -EINVAL;
 346         else
 347                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 348
 349         return 0;
 350 }
 351
 352 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
 353 {
 354         struct ci_power_info *pi = ci_get_pi(rdev);
 355         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 356         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 357         int i, min, max;
 358
 359         min = max = hi_vid[0];
 360         for (i = 0; i < 8; i++) {
 361                 if (0 != hi_vid[i]) {
 362                         if (min > hi_vid[i])
 363                                 min = hi_vid[i];
 364                         if (max < hi_vid[i])
 365                                 max = hi_vid[i];
 366                 }
 367
 368                 if (0 != lo_vid[i]) {
 369                         if (min > lo_vid[i])
 370                                 min = lo_vid[i];
 371                         if (max < lo_vid[i])
 372                                 max = lo_vid[i];
 373                 }
 374         }
 375
 376         if ((min == 0) || (max == 0))
 377                 return -EINVAL;
 378         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 379         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 380
 381         return 0;
 382 }
 383
 384 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
 385 {
 386         struct ci_power_info *pi = ci_get_pi(rdev);
 387         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 388         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 389         struct radeon_cac_tdp_table *cac_tdp_table =
 390                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 391
 392         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 393         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 394
 395         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 396         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 397
 398         return 0;
 399 }
 400
 401 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
 402 {
 403         struct ci_power_info *pi = ci_get_pi(rdev);
 404         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 405         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 406         struct radeon_cac_tdp_table *cac_tdp_table =
 407                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 408         struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
 409         int i, j, k;
 410         const u16 *def1;
 411         const u16 *def2;
 412
 413         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 414         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 415
 416         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 417         dpm_table->GpuTjMax =
 418                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 419         dpm_table->GpuTjHyst = 8;
 420
 421         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 422
 423         if (ppm) {
 424                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 425                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 426         } else {
 427                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 428                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 429         }
 430
 431         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 432         def1 = pt_defaults->bapmti_r;
 433         def2 = pt_defaults->bapmti_rc;
 434
 435         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 436                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 437                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 438                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 439                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 440                                 def1++;
 441                                 def2++;
 442                         }
 443                 }
 444         }
 445
 446         return 0;
 447 }
 448
 449 static int ci_populate_pm_base(struct radeon_device *rdev)
 450 {
 451         struct ci_power_info *pi = ci_get_pi(rdev);
 452         u32 pm_fuse_table_offset;
 453         int ret;
 454
 455         if (pi->caps_power_containment) {
 456                 ret = ci_read_smc_sram_dword(rdev,
 457                                              SMU7_FIRMWARE_HEADER_LOCATION +
 458                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 459                                              &pm_fuse_table_offset, pi->sram_end);
 460                 if (ret)
 461                         return ret;
 462                 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
 463                 if (ret)
 464                         return ret;
 465                 ret = ci_populate_vddc_vid(rdev);
 466                 if (ret)
 467                         return ret;
 468                 ret = ci_populate_svi_load_line(rdev);
 469                 if (ret)
 470                         return ret;
 471                 ret = ci_populate_tdc_limit(rdev);
 472                 if (ret)
 473                         return ret;
 474                 ret = ci_populate_dw8(rdev);
 475                 if (ret)
 476                         return ret;
 477                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
 478                 if (ret)
 479                         return ret;
 480                 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
 481                 if (ret)
 482                         return ret;
 483                 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
 484                                            (u8 *)&pi->smc_powertune_table,
 485                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 486                 if (ret)
 487                         return ret;
 488         }
 489
 490         return 0;
 491 }
 492
 493 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
 494 {
 495         struct ci_power_info *pi = ci_get_pi(rdev);
 496         u32 data;
 497
 498         if (pi->caps_sq_ramping) {
 499                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 500                 if (enable)
 501                         data |= DIDT_CTRL_EN;
 502                 else
 503                         data &= ~DIDT_CTRL_EN;
 504                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 505         }
 506
 507         if (pi->caps_db_ramping) {
 508                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 509                 if (enable)
 510                         data |= DIDT_CTRL_EN;
 511                 else
 512                         data &= ~DIDT_CTRL_EN;
 513                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 514         }
 515
 516         if (pi->caps_td_ramping) {
 517                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 518                 if (enable)
 519                         data |= DIDT_CTRL_EN;
 520                 else
 521                         data &= ~DIDT_CTRL_EN;
 522                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 523         }
 524
 525         if (pi->caps_tcp_ramping) {
 526                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 527                 if (enable)
 528                         data |= DIDT_CTRL_EN;
 529                 else
 530                         data &= ~DIDT_CTRL_EN;
 531                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 532         }
 533 }
 534
 535 static int ci_program_pt_config_registers(struct radeon_device *rdev,
 536                                           const struct ci_pt_config_reg *cac_config_regs)
 537 {
 538         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 539         u32 data;
 540         u32 cache = 0;
 541
 542         if (config_regs == NULL)
 543                 return -EINVAL;
 544
 545         while (config_regs->offset != 0xFFFFFFFF) {
 546                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 547                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 548                 } else {
 549                         switch (config_regs->type) {
 550                         case CISLANDS_CONFIGREG_SMC_IND:
 551                                 data = RREG32_SMC(config_regs->offset);
 552                                 break;
 553                         case CISLANDS_CONFIGREG_DIDT_IND:
 554                                 data = RREG32_DIDT(config_regs->offset);
 555                                 break;
 556                         default:
 557                                 data = RREG32(config_regs->offset << 2);
 558                                 break;
 559                         }
 560
 561                         data &= ~config_regs->mask;
 562                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 563                         data |= cache;
 564
 565                         switch (config_regs->type) {
 566                         case CISLANDS_CONFIGREG_SMC_IND:
 567                                 WREG32_SMC(config_regs->offset, data);
 568                                 break;
 569                         case CISLANDS_CONFIGREG_DIDT_IND:
 570                                 WREG32_DIDT(config_regs->offset, data);
 571                                 break;
 572                         default:
 573                                 WREG32(config_regs->offset << 2, data);
 574                                 break;
 575                         }
 576                         cache = 0;
 577                 }
 578                 config_regs++;
 579         }
 580         return 0;
 581 }
 582
 583 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
 584 {
 585         struct ci_power_info *pi = ci_get_pi(rdev);
 586         int ret;
 587
 588         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 589             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 590                 cik_enter_rlc_safe_mode(rdev);
 591
 592                 if (enable) {
 593                         ret = ci_program_pt_config_registers(rdev, didt_config_ci);
 594                         if (ret) {
 595                                 cik_exit_rlc_safe_mode(rdev);
 596                                 return ret;
 597                         }
 598                 }
 599
 600                 ci_do_enable_didt(rdev, enable);
 601
 602                 cik_exit_rlc_safe_mode(rdev);
 603         }
 604
 605         return 0;
 606 }
 607
 608 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
 609 {
 610         struct ci_power_info *pi = ci_get_pi(rdev);
 611         PPSMC_Result smc_result;
 612         int ret = 0;
 613
 614         if (enable) {
 615                 pi->power_containment_features = 0;
 616                 if (pi->caps_power_containment) {
 617                         if (pi->enable_bapm_feature) {
 618                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
 619                                 if (smc_result != PPSMC_Result_OK)
 620                                         ret = -EINVAL;
 621                                 else
 622                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 623                         }
 624
 625                         if (pi->enable_tdc_limit_feature) {
 626                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
 627                                 if (smc_result != PPSMC_Result_OK)
 628                                         ret = -EINVAL;
 629                                 else
 630                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 631                         }
 632
 633                         if (pi->enable_pkg_pwr_tracking_feature) {
 634                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
 635                                 if (smc_result != PPSMC_Result_OK) {
 636                                         ret = -EINVAL;
 637                                 } else {
 638                                         struct radeon_cac_tdp_table *cac_tdp_table =
 639                                                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 640                                         u32 default_pwr_limit =
 641                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 642
 643                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 644
 645                                         ci_set_power_limit(rdev, default_pwr_limit);
 646                                 }
 647                         }
 648                 }
 649         } else {
 650                 if (pi->caps_power_containment && pi->power_containment_features) {
 651                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 652                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
 653
 654                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 655                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 656
 657                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 658                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
 659                         pi->power_containment_features = 0;
 660                 }
 661         }
 662
 663         return ret;
 664 }
 665
 666 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
 667 {
 668         struct ci_power_info *pi = ci_get_pi(rdev);
 669         PPSMC_Result smc_result;
 670         int ret = 0;
 671
 672         if (pi->caps_cac) {
 673                 if (enable) {
 674                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
 675                         if (smc_result != PPSMC_Result_OK) {
 676                                 ret = -EINVAL;
 677                                 pi->cac_enabled = false;
 678                         } else {
 679                                 pi->cac_enabled = true;
 680                         }
 681                 } else if (pi->cac_enabled) {
 682                         ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
 683                         pi->cac_enabled = false;
 684                 }
 685         }
 686
 687         return ret;
 688 }
 689
 690 static int ci_power_control_set_level(struct radeon_device *rdev)
 691 {
 692         struct ci_power_info *pi = ci_get_pi(rdev);
 693         struct radeon_cac_tdp_table *cac_tdp_table =
 694                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 695         s32 adjust_percent;
 696         s32 target_tdp;
 697         int ret = 0;
 698         bool adjust_polarity = false; /* ??? */
 699
 700         if (pi->caps_power_containment &&
 701             (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
 702                 adjust_percent = adjust_polarity ?
 703                         rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
 704                 target_tdp = ((100 + adjust_percent) *
 705                               (s32)cac_tdp_table->configurable_tdp) / 100;
 706                 target_tdp *= 256;
 707
 708                 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
 709         }
 710
 711         return ret;
 712 }
 713
 714 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
 715 {
 716         struct ci_power_info *pi = ci_get_pi(rdev);
 717
 718         if (pi->uvd_power_gated == gate)
 719                 return;
 720
 721         pi->uvd_power_gated = gate;
 722
 723         ci_update_uvd_dpm(rdev, gate);
 724 }
 725
 726 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
 727 {
 728         struct ci_power_info *pi = ci_get_pi(rdev);
 729         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 730         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 731
 732         if (vblank_time < switch_limit)
 733                 return true;
 734         else
 735                 return false;
 736
 737 }
 738
 739 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
 740                                         struct radeon_ps *rps)
 741 {
 742         struct ci_ps *ps = ci_get_ps(rps);
 743         struct ci_power_info *pi = ci_get_pi(rdev);
 744         struct radeon_clock_and_voltage_limits *max_limits;
 745         bool disable_mclk_switching;
 746         u32 sclk, mclk;
 747         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 748         int i;
 749
 750         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 751             ci_dpm_vblank_too_short(rdev))
 752                 disable_mclk_switching = true;
 753         else
 754                 disable_mclk_switching = false;
 755
 756         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 757                 pi->battery_state = true;
 758         else
 759                 pi->battery_state = false;
 760
 761         if (rdev->pm.dpm.ac_power)
 762                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 763         else
 764                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 765
 766         if (rdev->pm.dpm.ac_power == false) {
 767                 for (i = 0; i < ps->performance_level_count; i++) {
 768                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 769                                 ps->performance_levels[i].mclk = max_limits->mclk;
 770                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 771                                 ps->performance_levels[i].sclk = max_limits->sclk;
 772                 }
 773         }
 774
 775         /* limit clocks to max supported clocks based on voltage dependency tables */
 776         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
 777                                                         &max_sclk_vddc);
 778         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
 779                                                         &max_mclk_vddci);
 780         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
 781                                                         &max_mclk_vddc);
 782
 783         for (i = 0; i < ps->performance_level_count; i++) {
 784                 if (max_sclk_vddc) {
 785                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
 786                                 ps->performance_levels[i].sclk = max_sclk_vddc;
 787                 }
 788                 if (max_mclk_vddci) {
 789                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
 790                                 ps->performance_levels[i].mclk = max_mclk_vddci;
 791                 }
 792                 if (max_mclk_vddc) {
 793                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
 794                                 ps->performance_levels[i].mclk = max_mclk_vddc;
 795                 }
 796         }
 797
 798         /* XXX validate the min clocks required for display */
 799
 800         if (disable_mclk_switching) {
 801                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 802                 sclk = ps->performance_levels[0].sclk;
 803         } else {
 804                 mclk = ps->performance_levels[0].mclk;
 805                 sclk = ps->performance_levels[0].sclk;
 806         }
 807
 808         ps->performance_levels[0].sclk = sclk;
 809         ps->performance_levels[0].mclk = mclk;
 810
 811         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 812                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 813
 814         if (disable_mclk_switching) {
 815                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 816                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 817         } else {
 818                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 819                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 820         }
 821 }
 822
 823 static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
 824                                             int min_temp, int max_temp)
 825 {
 826         int low_temp = 0 * 1000;
 827         int high_temp = 255 * 1000;
 828         u32 tmp;
 829
 830         if (low_temp < min_temp)
 831                 low_temp = min_temp;
 832         if (high_temp > max_temp)
 833                 high_temp = max_temp;
 834         if (high_temp < low_temp) {
 835                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 836                 return -EINVAL;
 837         }
 838
 839         tmp = RREG32_SMC(CG_THERMAL_INT);
 840         tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
 841         tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
 842                 CI_DIG_THERM_INTL(low_temp / 1000);
 843         WREG32_SMC(CG_THERMAL_INT, tmp);
 844
 845 #if 0
 846         /* XXX: need to figure out how to handle this properly */
 847         tmp = RREG32_SMC(CG_THERMAL_CTRL);
 848         tmp &= DIG_THERM_DPM_MASK;
 849         tmp |= DIG_THERM_DPM(high_temp / 1000);
 850         WREG32_SMC(CG_THERMAL_CTRL, tmp);
 851 #endif
 852
 853         return 0;
 854 }
 855
 856 #if 0
 857 static int ci_read_smc_soft_register(struct radeon_device *rdev,
 858                                      u16 reg_offset, u32 *value)
 859 {
 860         struct ci_power_info *pi = ci_get_pi(rdev);
 861
 862         return ci_read_smc_sram_dword(rdev,
 863                                       pi->soft_regs_start + reg_offset,
 864                                       value, pi->sram_end);
 865 }
 866 #endif
 867
 868 static int ci_write_smc_soft_register(struct radeon_device *rdev,
 869                                       u16 reg_offset, u32 value)
 870 {
 871         struct ci_power_info *pi = ci_get_pi(rdev);
 872
 873         return ci_write_smc_sram_dword(rdev,
 874                                        pi->soft_regs_start + reg_offset,
 875                                        value, pi->sram_end);
 876 }
 877
 878 static void ci_init_fps_limits(struct radeon_device *rdev)
 879 {
 880         struct ci_power_info *pi = ci_get_pi(rdev);
 881         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
 882
 883         if (pi->caps_fps) {
 884                 u16 tmp;
 885
 886                 tmp = 45;
 887                 table->FpsHighT = cpu_to_be16(tmp);
 888
 889                 tmp = 30;
 890                 table->FpsLowT = cpu_to_be16(tmp);
 891         }
 892 }
 893
 894 static int ci_update_sclk_t(struct radeon_device *rdev)
 895 {
 896         struct ci_power_info *pi = ci_get_pi(rdev);
 897         int ret = 0;
 898         u32 low_sclk_interrupt_t = 0;
 899
 900         if (pi->caps_sclk_throttle_low_notification) {
 901                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 902
 903                 ret = ci_copy_bytes_to_smc(rdev,
 904                                            pi->dpm_table_start +
 905                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
 906                                            (u8 *)&low_sclk_interrupt_t,
 907                                            sizeof(u32), pi->sram_end);
 908
 909         }
 910
 911         return ret;
 912 }
 913
 914 static void ci_get_leakage_voltages(struct radeon_device *rdev)
 915 {
 916         struct ci_power_info *pi = ci_get_pi(rdev);
 917         u16 leakage_id, virtual_voltage_id;
 918         u16 vddc, vddci;
 919         int i;
 920
 921         pi->vddc_leakage.count = 0;
 922         pi->vddci_leakage.count = 0;
 923
 924         if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
 925                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 926                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 927                         if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
 928                                                                                  virtual_voltage_id,
 929                                                                                  leakage_id) == 0) {
 930                                 if (vddc != 0 && vddc != virtual_voltage_id) {
 931                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 932                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 933                                         pi->vddc_leakage.count++;
 934                                 }
 935                                 if (vddci != 0 && vddci != virtual_voltage_id) {
 936                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
 937                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
 938                                         pi->vddci_leakage.count++;
 939                                 }
 940                         }
 941                 }
 942         }
 943 }
 944
 945 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
 946 {
 947         struct ci_power_info *pi = ci_get_pi(rdev);
 948         bool want_thermal_protection;
 949         enum radeon_dpm_event_src dpm_event_src;
 950         u32 tmp;
 951
 952         switch (sources) {
 953         case 0:
 954         default:
 955                 want_thermal_protection = false;
 956                 break;
 957         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
 958                 want_thermal_protection = true;
 959                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
 960                 break;
 961         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
 962                 want_thermal_protection = true;
 963                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
 964                 break;
 965         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
 966               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
 967                 want_thermal_protection = true;
 968                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
 969                 break;
 970         }
 971
 972         if (want_thermal_protection) {
 973 #if 0
 974                 /* XXX: need to figure out how to handle this properly */
 975                 tmp = RREG32_SMC(CG_THERMAL_CTRL);
 976                 tmp &= DPM_EVENT_SRC_MASK;
 977                 tmp |= DPM_EVENT_SRC(dpm_event_src);
 978                 WREG32_SMC(CG_THERMAL_CTRL, tmp);
 979 #endif
 980
 981                 tmp = RREG32_SMC(GENERAL_PWRMGT);
 982                 if (pi->thermal_protection)
 983                         tmp &= ~THERMAL_PROTECTION_DIS;
 984                 else
 985                         tmp |= THERMAL_PROTECTION_DIS;
 986                 WREG32_SMC(GENERAL_PWRMGT, tmp);
 987         } else {
 988                 tmp = RREG32_SMC(GENERAL_PWRMGT);
 989                 tmp |= THERMAL_PROTECTION_DIS;
 990                 WREG32_SMC(GENERAL_PWRMGT, tmp);
 991         }
 992 }
 993
 994 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
 995                                            enum radeon_dpm_auto_throttle_src source,
 996                                            bool enable)
 997 {
 998         struct ci_power_info *pi = ci_get_pi(rdev);
 999
1000         if (enable) {
1001                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1002                         pi->active_auto_throttle_sources |= 1 << source;
1003                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1004                 }
1005         } else {
1006                 if (pi->active_auto_throttle_sources & (1 << source)) {
1007                         pi->active_auto_throttle_sources &= ~(1 << source);
1008                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1009                 }
1010         }
1011 }
1012
1013 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1014 {
1015         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1016                 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1017 }
1018
1019 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1020 {
1021         struct ci_power_info *pi = ci_get_pi(rdev);
1022         PPSMC_Result smc_result;
1023
1024         if (!pi->need_update_smu7_dpm_table)
1025                 return 0;
1026
1027         if ((!pi->sclk_dpm_key_disabled) &&
1028             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1029                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1030                 if (smc_result != PPSMC_Result_OK)
1031                         return -EINVAL;
1032         }
1033
1034         if ((!pi->mclk_dpm_key_disabled) &&
1035             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1036                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1037                 if (smc_result != PPSMC_Result_OK)
1038                         return -EINVAL;
1039         }
1040
1041         pi->need_update_smu7_dpm_table = 0;
1042         return 0;
1043 }
1044
1045 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1046 {
1047         struct ci_power_info *pi = ci_get_pi(rdev);
1048         PPSMC_Result smc_result;
1049
1050         if (enable) {
1051                 if (!pi->sclk_dpm_key_disabled) {
1052                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1053                         if (smc_result != PPSMC_Result_OK)
1054                                 return -EINVAL;
1055                 }
1056
1057                 if (!pi->mclk_dpm_key_disabled) {
1058                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1059                         if (smc_result != PPSMC_Result_OK)
1060                                 return -EINVAL;
1061
1062                         WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1063
1064                         WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1065                         WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1066                         WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1067
1068                         udelay(10);
1069
1070                         WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1071                         WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1072                         WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1073                 }
1074         } else {
1075                 if (!pi->sclk_dpm_key_disabled) {
1076                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1077                         if (smc_result != PPSMC_Result_OK)
1078                                 return -EINVAL;
1079                 }
1080
1081                 if (!pi->mclk_dpm_key_disabled) {
1082                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1083                         if (smc_result != PPSMC_Result_OK)
1084                                 return -EINVAL;
1085                 }
1086         }
1087
1088         return 0;
1089 }
1090
1091 static int ci_start_dpm(struct radeon_device *rdev)
1092 {
1093         struct ci_power_info *pi = ci_get_pi(rdev);
1094         PPSMC_Result smc_result;
1095         int ret;
1096         u32 tmp;
1097
1098         tmp = RREG32_SMC(GENERAL_PWRMGT);
1099         tmp |= GLOBAL_PWRMGT_EN;
1100         WREG32_SMC(GENERAL_PWRMGT, tmp);
1101
1102         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1103         tmp |= DYNAMIC_PM_EN;
1104         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1105
1106         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1107
1108         WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1109
1110         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1111         if (smc_result != PPSMC_Result_OK)
1112                 return -EINVAL;
1113
1114         ret = ci_enable_sclk_mclk_dpm(rdev, true);
1115         if (ret)
1116                 return ret;
1117
1118         if (!pi->pcie_dpm_key_disabled) {
1119                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1120                 if (smc_result != PPSMC_Result_OK)
1121                         return -EINVAL;
1122         }
1123
1124         return 0;
1125 }
1126
1127 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1128 {
1129         struct ci_power_info *pi = ci_get_pi(rdev);
1130         PPSMC_Result smc_result;
1131
1132         if (!pi->need_update_smu7_dpm_table)
1133                 return 0;
1134
1135         if ((!pi->sclk_dpm_key_disabled) &&
1136             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1137                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1138                 if (smc_result != PPSMC_Result_OK)
1139                         return -EINVAL;
1140         }
1141
1142         if ((!pi->mclk_dpm_key_disabled) &&
1143             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1144                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1145                 if (smc_result != PPSMC_Result_OK)
1146                         return -EINVAL;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int ci_stop_dpm(struct radeon_device *rdev)
1153 {
1154         struct ci_power_info *pi = ci_get_pi(rdev);
1155         PPSMC_Result smc_result;
1156         int ret;
1157         u32 tmp;
1158
1159         tmp = RREG32_SMC(GENERAL_PWRMGT);
1160         tmp &= ~GLOBAL_PWRMGT_EN;
1161         WREG32_SMC(GENERAL_PWRMGT, tmp);
1162
1163         tmp = RREG32(SCLK_PWRMGT_CNTL);
1164         tmp &= ~DYNAMIC_PM_EN;
1165         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1166
1167         if (!pi->pcie_dpm_key_disabled) {
1168                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1169                 if (smc_result != PPSMC_Result_OK)
1170                         return -EINVAL;
1171         }
1172
1173         ret = ci_enable_sclk_mclk_dpm(rdev, false);
1174         if (ret)
1175                 return ret;
1176
1177         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1178         if (smc_result != PPSMC_Result_OK)
1179                 return -EINVAL;
1180
1181         return 0;
1182 }
1183
1184 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1185 {
1186         u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1187
1188         if (enable)
1189                 tmp &= ~SCLK_PWRMGT_OFF;
1190         else
1191                 tmp |= SCLK_PWRMGT_OFF;
1192         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1193 }
1194
1195 #if 0
1196 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1197                                         bool ac_power)
1198 {
1199         struct ci_power_info *pi = ci_get_pi(rdev);
1200         struct radeon_cac_tdp_table *cac_tdp_table =
1201                 rdev->pm.dpm.dyn_state.cac_tdp_table;
1202         u32 power_limit;
1203
1204         if (ac_power)
1205                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1206         else
1207                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1208
1209         ci_set_power_limit(rdev, power_limit);
1210
1211         if (pi->caps_automatic_dc_transition) {
1212                 if (ac_power)
1213                         ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1214                 else
1215                         ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1216         }
1217
1218         return 0;
1219 }
1220 #endif
1221
1222 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1223                                                       PPSMC_Msg msg, u32 parameter)
1224 {
1225         WREG32(SMC_MSG_ARG_0, parameter);
1226         return ci_send_msg_to_smc(rdev, msg);
1227 }
1228
1229 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1230                                                         PPSMC_Msg msg, u32 *parameter)
1231 {
1232         PPSMC_Result smc_result;
1233
1234         smc_result = ci_send_msg_to_smc(rdev, msg);
1235
1236         if ((smc_result == PPSMC_Result_OK) && parameter)
1237                 *parameter = RREG32(SMC_MSG_ARG_0);
1238
1239         return smc_result;
1240 }
1241
1242 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1243 {
1244         struct ci_power_info *pi = ci_get_pi(rdev);
1245
1246         if (!pi->sclk_dpm_key_disabled) {
1247                 PPSMC_Result smc_result =
1248                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1249                 if (smc_result != PPSMC_Result_OK)
1250                         return -EINVAL;
1251         }
1252
1253         return 0;
1254 }
1255
1256 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1257 {
1258         struct ci_power_info *pi = ci_get_pi(rdev);
1259
1260         if (!pi->mclk_dpm_key_disabled) {
1261                 PPSMC_Result smc_result =
1262                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1263                 if (smc_result != PPSMC_Result_OK)
1264                         return -EINVAL;
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1271 {
1272         struct ci_power_info *pi = ci_get_pi(rdev);
1273
1274         if (!pi->pcie_dpm_key_disabled) {
1275                 PPSMC_Result smc_result =
1276                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1277                 if (smc_result != PPSMC_Result_OK)
1278                         return -EINVAL;
1279         }
1280
1281         return 0;
1282 }
1283
1284 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1285 {
1286         struct ci_power_info *pi = ci_get_pi(rdev);
1287
1288         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1289                 PPSMC_Result smc_result =
1290                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1291                 if (smc_result != PPSMC_Result_OK)
1292                         return -EINVAL;
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1299                                        u32 target_tdp)
1300 {
1301         PPSMC_Result smc_result =
1302                 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1303         if (smc_result != PPSMC_Result_OK)
1304                 return -EINVAL;
1305         return 0;
1306 }
1307
1308 static int ci_set_boot_state(struct radeon_device *rdev)
1309 {
1310         return ci_enable_sclk_mclk_dpm(rdev, false);
1311 }
1312
1313 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1314 {
1315         u32 sclk_freq;
1316         PPSMC_Result smc_result =
1317                 ci_send_msg_to_smc_return_parameter(rdev,
1318                                                     PPSMC_MSG_API_GetSclkFrequency,
1319                                                     &sclk_freq);
1320         if (smc_result != PPSMC_Result_OK)
1321                 sclk_freq = 0;
1322
1323         return sclk_freq;
1324 }
1325
1326 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1327 {
1328         u32 mclk_freq;
1329         PPSMC_Result smc_result =
1330                 ci_send_msg_to_smc_return_parameter(rdev,
1331                                                     PPSMC_MSG_API_GetMclkFrequency,
1332                                                     &mclk_freq);
1333         if (smc_result != PPSMC_Result_OK)
1334                 mclk_freq = 0;
1335
1336         return mclk_freq;
1337 }
1338
1339 static void ci_dpm_start_smc(struct radeon_device *rdev)
1340 {
1341         int i;
1342
1343         ci_program_jump_on_start(rdev);
1344         ci_start_smc_clock(rdev);
1345         ci_start_smc(rdev);
1346         for (i = 0; i < rdev->usec_timeout; i++) {
1347                 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1348                         break;
1349         }
1350 }
1351
1352 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1353 {
1354         ci_reset_smc(rdev);
1355         ci_stop_smc_clock(rdev);
1356 }
1357
1358 static int ci_process_firmware_header(struct radeon_device *rdev)
1359 {
1360         struct ci_power_info *pi = ci_get_pi(rdev);
1361         u32 tmp;
1362         int ret;
1363
1364         ret = ci_read_smc_sram_dword(rdev,
1365                                      SMU7_FIRMWARE_HEADER_LOCATION +
1366                                      offsetof(SMU7_Firmware_Header, DpmTable),
1367                                      &tmp, pi->sram_end);
1368         if (ret)
1369                 return ret;
1370
1371         pi->dpm_table_start = tmp;
1372
1373         ret = ci_read_smc_sram_dword(rdev,
1374                                      SMU7_FIRMWARE_HEADER_LOCATION +
1375                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1376                                      &tmp, pi->sram_end);
1377         if (ret)
1378                 return ret;
1379
1380         pi->soft_regs_start = tmp;
1381
1382         ret = ci_read_smc_sram_dword(rdev,
1383                                      SMU7_FIRMWARE_HEADER_LOCATION +
1384                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1385                                      &tmp, pi->sram_end);
1386         if (ret)
1387                 return ret;
1388
1389         pi->mc_reg_table_start = tmp;
1390
1391         ret = ci_read_smc_sram_dword(rdev,
1392                                      SMU7_FIRMWARE_HEADER_LOCATION +
1393                                      offsetof(SMU7_Firmware_Header, FanTable),
1394                                      &tmp, pi->sram_end);
1395         if (ret)
1396                 return ret;
1397
1398         pi->fan_table_start = tmp;
1399
1400         ret = ci_read_smc_sram_dword(rdev,
1401                                      SMU7_FIRMWARE_HEADER_LOCATION +
1402                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1403                                      &tmp, pi->sram_end);
1404         if (ret)
1405                 return ret;
1406
1407         pi->arb_table_start = tmp;
1408
1409         return 0;
1410 }
1411
1412 static void ci_read_clock_registers(struct radeon_device *rdev)
1413 {
1414         struct ci_power_info *pi = ci_get_pi(rdev);
1415
1416         pi->clock_registers.cg_spll_func_cntl =
1417                 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1418         pi->clock_registers.cg_spll_func_cntl_2 =
1419                 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1420         pi->clock_registers.cg_spll_func_cntl_3 =
1421                 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1422         pi->clock_registers.cg_spll_func_cntl_4 =
1423                 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1424         pi->clock_registers.cg_spll_spread_spectrum =
1425                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1426         pi->clock_registers.cg_spll_spread_spectrum_2 =
1427                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1428         pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1429         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1430         pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1431         pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1432         pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1433         pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1434         pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1435         pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1436         pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1437 }
1438
1439 static void ci_init_sclk_t(struct radeon_device *rdev)
1440 {
1441         struct ci_power_info *pi = ci_get_pi(rdev);
1442
1443         pi->low_sclk_interrupt_t = 0;
1444 }
1445
1446 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1447                                          bool enable)
1448 {
1449         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1450
1451         if (enable)
1452                 tmp &= ~THERMAL_PROTECTION_DIS;
1453         else
1454                 tmp |= THERMAL_PROTECTION_DIS;
1455         WREG32_SMC(GENERAL_PWRMGT, tmp);
1456 }
1457
1458 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1459 {
1460         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1461
1462         tmp |= STATIC_PM_EN;
1463
1464         WREG32_SMC(GENERAL_PWRMGT, tmp);
1465 }
1466
1467 #if 0
1468 static int ci_enter_ulp_state(struct radeon_device *rdev)
1469 {
1470
1471         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1472
1473         udelay(25000);
1474
1475         return 0;
1476 }
1477
1478 static int ci_exit_ulp_state(struct radeon_device *rdev)
1479 {
1480         int i;
1481
1482         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1483
1484         udelay(7000);
1485
1486         for (i = 0; i < rdev->usec_timeout; i++) {
1487                 if (RREG32(SMC_RESP_0) == 1)
1488                         break;
1489                 udelay(1000);
1490         }
1491
1492         return 0;
1493 }
1494 #endif
1495
1496 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1497                                         bool has_display)
1498 {
1499         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1500
1501         return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
1502 }
1503
1504 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1505                                       bool enable)
1506 {
1507         struct ci_power_info *pi = ci_get_pi(rdev);
1508
1509         if (enable) {
1510                 if (pi->caps_sclk_ds) {
1511                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1512                                 return -EINVAL;
1513                 } else {
1514                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1515                                 return -EINVAL;
1516                 }
1517         } else {
1518                 if (pi->caps_sclk_ds) {
1519                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1520                                 return -EINVAL;
1521                 }
1522         }
1523
1524         return 0;
1525 }
1526
1527 static void ci_program_display_gap(struct radeon_device *rdev)
1528 {
1529         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1530         u32 pre_vbi_time_in_us;
1531         u32 frame_time_in_us;
1532         u32 ref_clock = rdev->clock.spll.reference_freq;
1533         u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1534         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1535
1536         tmp &= ~DISP_GAP_MASK;
1537         if (rdev->pm.dpm.new_active_crtc_count > 0)
1538                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1539         else
1540                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1541         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1542
1543         if (refresh_rate == 0)
1544                 refresh_rate = 60;
1545         if (vblank_time == 0xffffffff)
1546                 vblank_time = 500;
1547         frame_time_in_us = 1000000 / refresh_rate;
1548         pre_vbi_time_in_us =
1549                 frame_time_in_us - 200 - vblank_time;
1550         tmp = pre_vbi_time_in_us * (ref_clock / 100);
1551
1552         WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1553         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1554         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1555
1556
1557         ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1558
1559 }
1560
1561 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1562 {
1563         struct ci_power_info *pi = ci_get_pi(rdev);
1564         u32 tmp;
1565
1566         if (enable) {
1567                 if (pi->caps_sclk_ss_support) {
1568                         tmp = RREG32_SMC(GENERAL_PWRMGT);
1569                         tmp |= DYN_SPREAD_SPECTRUM_EN;
1570                         WREG32_SMC(GENERAL_PWRMGT, tmp);
1571                 }
1572         } else {
1573                 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1574                 tmp &= ~SSEN;
1575                 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1576
1577                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1578                 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1579                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1580         }
1581 }
1582
1583 static void ci_program_sstp(struct radeon_device *rdev)
1584 {
1585         WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1586 }
1587
1588 static void ci_enable_display_gap(struct radeon_device *rdev)
1589 {
1590         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1591
1592         tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1593         tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1594                 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1595
1596         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1597 }
1598
1599 static void ci_program_vc(struct radeon_device *rdev)
1600 {
1601         u32 tmp;
1602
1603         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1604         tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1605         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1606
1607         WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1608         WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1609         WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1610         WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1611         WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1612         WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1613         WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1614         WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1615 }
1616
1617 static void ci_clear_vc(struct radeon_device *rdev)
1618 {
1619         u32 tmp;
1620
1621         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1622         tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1623         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1624
1625         WREG32_SMC(CG_FTV_0, 0);
1626         WREG32_SMC(CG_FTV_1, 0);
1627         WREG32_SMC(CG_FTV_2, 0);
1628         WREG32_SMC(CG_FTV_3, 0);
1629         WREG32_SMC(CG_FTV_4, 0);
1630         WREG32_SMC(CG_FTV_5, 0);
1631         WREG32_SMC(CG_FTV_6, 0);
1632         WREG32_SMC(CG_FTV_7, 0);
1633 }
1634
1635 static int ci_upload_firmware(struct radeon_device *rdev)
1636 {
1637         struct ci_power_info *pi = ci_get_pi(rdev);
1638         int i, ret;
1639
1640         for (i = 0; i < rdev->usec_timeout; i++) {
1641                 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1642                         break;
1643         }
1644         WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1645
1646         ci_stop_smc_clock(rdev);
1647         ci_reset_smc(rdev);
1648
1649         ret = ci_load_smc_ucode(rdev, pi->sram_end);
1650
1651         return ret;
1652
1653 }
1654
1655 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1656                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1657                                      struct atom_voltage_table *voltage_table)
1658 {
1659         u32 i;
1660
1661         if (voltage_dependency_table == NULL)
1662                 return -EINVAL;
1663
1664         voltage_table->mask_low = 0;
1665         voltage_table->phase_delay = 0;
1666
1667         voltage_table->count = voltage_dependency_table->count;
1668         for (i = 0; i < voltage_table->count; i++) {
1669                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1670                 voltage_table->entries[i].smio_low = 0;
1671         }
1672
1673         return 0;
1674 }
1675
1676 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1677 {
1678         struct ci_power_info *pi = ci_get_pi(rdev);
1679         int ret;
1680
1681         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1682                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1683                                                     VOLTAGE_OBJ_GPIO_LUT,
1684                                                     &pi->vddc_voltage_table);
1685                 if (ret)
1686                         return ret;
1687         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1688                 ret = ci_get_svi2_voltage_table(rdev,
1689                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1690                                                 &pi->vddc_voltage_table);
1691                 if (ret)
1692                         return ret;
1693         }
1694
1695         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1696                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1697                                                          &pi->vddc_voltage_table);
1698
1699         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1700                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1701                                                     VOLTAGE_OBJ_GPIO_LUT,
1702                                                     &pi->vddci_voltage_table);
1703                 if (ret)
1704                         return ret;
1705         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1706                 ret = ci_get_svi2_voltage_table(rdev,
1707                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1708                                                 &pi->vddci_voltage_table);
1709                 if (ret)
1710                         return ret;
1711         }
1712
1713         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1714                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1715                                                          &pi->vddci_voltage_table);
1716
1717         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1718                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1719                                                     VOLTAGE_OBJ_GPIO_LUT,
1720                                                     &pi->mvdd_voltage_table);
1721                 if (ret)
1722                         return ret;
1723         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1724                 ret = ci_get_svi2_voltage_table(rdev,
1725                                                 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1726                                                 &pi->mvdd_voltage_table);
1727                 if (ret)
1728                         return ret;
1729         }
1730
1731         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1732                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1733                                                          &pi->mvdd_voltage_table);
1734
1735         return 0;
1736 }
1737
1738 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1739                                           struct atom_voltage_table_entry *voltage_table,
1740                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
1741 {
1742         int ret;
1743
1744         ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1745                                             &smc_voltage_table->StdVoltageHiSidd,
1746                                             &smc_voltage_table->StdVoltageLoSidd);
1747
1748         if (ret) {
1749                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1750                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1751         }
1752
1753         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1754         smc_voltage_table->StdVoltageHiSidd =
1755                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1756         smc_voltage_table->StdVoltageLoSidd =
1757                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1758 }
1759
1760 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1761                                       SMU7_Discrete_DpmTable *table)
1762 {
1763         struct ci_power_info *pi = ci_get_pi(rdev);
1764         unsigned int count;
1765
1766         table->VddcLevelCount = pi->vddc_voltage_table.count;
1767         for (count = 0; count < table->VddcLevelCount; count++) {
1768                 ci_populate_smc_voltage_table(rdev,
1769                                               &pi->vddc_voltage_table.entries[count],
1770                                               &table->VddcLevel[count]);
1771
1772                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1773                         table->VddcLevel[count].Smio |=
1774                                 pi->vddc_voltage_table.entries[count].smio_low;
1775                 else
1776                         table->VddcLevel[count].Smio = 0;
1777         }
1778         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1779
1780         return 0;
1781 }
1782
1783 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1784                                        SMU7_Discrete_DpmTable *table)
1785 {
1786         unsigned int count;
1787         struct ci_power_info *pi = ci_get_pi(rdev);
1788
1789         table->VddciLevelCount = pi->vddci_voltage_table.count;
1790         for (count = 0; count < table->VddciLevelCount; count++) {
1791                 ci_populate_smc_voltage_table(rdev,
1792                                               &pi->vddci_voltage_table.entries[count],
1793                                               &table->VddciLevel[count]);
1794
1795                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1796                         table->VddciLevel[count].Smio |=
1797                                 pi->vddci_voltage_table.entries[count].smio_low;
1798                 else
1799                         table->VddciLevel[count].Smio = 0;
1800         }
1801         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1802
1803         return 0;
1804 }
1805
1806 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1807                                       SMU7_Discrete_DpmTable *table)
1808 {
1809         struct ci_power_info *pi = ci_get_pi(rdev);
1810         unsigned int count;
1811
1812         table->MvddLevelCount = pi->mvdd_voltage_table.count;
1813         for (count = 0; count < table->MvddLevelCount; count++) {
1814                 ci_populate_smc_voltage_table(rdev,
1815                                               &pi->mvdd_voltage_table.entries[count],
1816                                               &table->MvddLevel[count]);
1817
1818                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1819                         table->MvddLevel[count].Smio |=
1820                                 pi->mvdd_voltage_table.entries[count].smio_low;
1821                 else
1822                         table->MvddLevel[count].Smio = 0;
1823         }
1824         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1825
1826         return 0;
1827 }
1828
1829 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1830                                           SMU7_Discrete_DpmTable *table)
1831 {
1832         int ret;
1833
1834         ret = ci_populate_smc_vddc_table(rdev, table);
1835         if (ret)
1836                 return ret;
1837
1838         ret = ci_populate_smc_vddci_table(rdev, table);
1839         if (ret)
1840                 return ret;
1841
1842         ret = ci_populate_smc_mvdd_table(rdev, table);
1843         if (ret)
1844                 return ret;
1845
1846         return 0;
1847 }
1848
1849 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1850                                   SMU7_Discrete_VoltageLevel *voltage)
1851 {
1852         struct ci_power_info *pi = ci_get_pi(rdev);
1853         u32 i = 0;
1854
1855         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1856                 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1857                         if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1858                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1859                                 break;
1860                         }
1861                 }
1862
1863                 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1864                         return -EINVAL;
1865         }
1866
1867         return -EINVAL;
1868 }
1869
1870 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1871                                          struct atom_voltage_table_entry *voltage_table,
1872                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1873 {
1874         u16 v_index, idx;
1875         bool voltage_found = false;
1876         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1877         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1878
1879         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1880                 return -EINVAL;
1881
1882         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1883                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1884                         if (voltage_table->value ==
1885                             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1886                                 voltage_found = true;
1887                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1888                                         idx = v_index;
1889                                 else
1890                                         idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1891                                 *std_voltage_lo_sidd =
1892                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1893                                 *std_voltage_hi_sidd =
1894                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1895                                 break;
1896                         }
1897                 }
1898
1899                 if (!voltage_found) {
1900                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1901                                 if (voltage_table->value <=
1902                                     rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1903                                         voltage_found = true;
1904                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1905                                                 idx = v_index;
1906                                         else
1907                                                 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1908                                         *std_voltage_lo_sidd =
1909                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1910                                         *std_voltage_hi_sidd =
1911                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1912                                         break;
1913                                 }
1914                         }
1915                 }
1916         }
1917
1918         return 0;
1919 }
1920
1921 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1922                                                   const struct radeon_phase_shedding_limits_table *limits,
1923                                                   u32 sclk,
1924                                                   u32 *phase_shedding)
1925 {
1926         unsigned int i;
1927
1928         *phase_shedding = 1;
1929
1930         for (i = 0; i < limits->count; i++) {
1931                 if (sclk < limits->entries[i].sclk) {
1932                         *phase_shedding = i;
1933                         break;
1934                 }
1935         }
1936 }
1937
1938 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1939                                                   const struct radeon_phase_shedding_limits_table *limits,
1940                                                   u32 mclk,
1941                                                   u32 *phase_shedding)
1942 {
1943         unsigned int i;
1944
1945         *phase_shedding = 1;
1946
1947         for (i = 0; i < limits->count; i++) {
1948                 if (mclk < limits->entries[i].mclk) {
1949                         *phase_shedding = i;
1950                         break;
1951                 }
1952         }
1953 }
1954
1955 static int ci_init_arb_table_index(struct radeon_device *rdev)
1956 {
1957         struct ci_power_info *pi = ci_get_pi(rdev);
1958         u32 tmp;
1959         int ret;
1960
1961         ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1962                                      &tmp, pi->sram_end);
1963         if (ret)
1964                 return ret;
1965
1966         tmp &= 0x00FFFFFF;
1967         tmp |= MC_CG_ARB_FREQ_F1 << 24;
1968
1969         return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
1970                                        tmp, pi->sram_end);
1971 }
1972
1973 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
1974                                          struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
1975                                          u32 clock, u32 *voltage)
1976 {
1977         u32 i = 0;
1978
1979         if (allowed_clock_voltage_table->count == 0)
1980                 return -EINVAL;
1981
1982         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1983                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1984                         *voltage = allowed_clock_voltage_table->entries[i].v;
1985                         return 0;
1986                 }
1987         }
1988
1989         *voltage = allowed_clock_voltage_table->entries[i-1].v;
1990
1991         return 0;
1992 }
1993
1994 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1995                                              u32 sclk, u32 min_sclk_in_sr)
1996 {
1997         u32 i;
1998         u32 tmp;
1999         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2000                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2001
2002         if (sclk < min)
2003                 return 0;
2004
2005         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2006                 tmp = sclk / (1 << i);
2007                 if (tmp >= min || i == 0)
2008                         break;
2009         }
2010
2011         return (u8)i;
2012 }
2013
2014 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2015 {
2016         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2017 }
2018
2019 static int ci_reset_to_default(struct radeon_device *rdev)
2020 {
2021         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2022                 0 : -EINVAL;
2023 }
2024
2025 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2026 {
2027         u32 tmp;
2028
2029         tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2030
2031         if (tmp == MC_CG_ARB_FREQ_F0)
2032                 return 0;
2033
2034         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2035 }
2036
2037 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2038                                                 u32 sclk,
2039                                                 u32 mclk,
2040                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2041 {
2042         u32 dram_timing;
2043         u32 dram_timing2;
2044         u32 burst_time;
2045
2046         radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2047
2048         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
2049         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2050         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2051
2052         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2053         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2054         arb_regs->McArbBurstTime = (u8)burst_time;
2055
2056         return 0;
2057 }
2058
2059 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2060 {
2061         struct ci_power_info *pi = ci_get_pi(rdev);
2062         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2063         u32 i, j;
2064         int ret =  0;
2065
2066         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2067
2068         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2069                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2070                         ret = ci_populate_memory_timing_parameters(rdev,
2071                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2072                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2073                                                                    &arb_regs.entries[i][j]);
2074                         if (ret)
2075                                 break;
2076                 }
2077         }
2078
2079         if (ret == 0)
2080                 ret = ci_copy_bytes_to_smc(rdev,
2081                                            pi->arb_table_start,
2082                                            (u8 *)&arb_regs,
2083                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2084                                            pi->sram_end);
2085
2086         return ret;
2087 }
2088
2089 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2090 {
2091         struct ci_power_info *pi = ci_get_pi(rdev);
2092
2093         if (pi->need_update_smu7_dpm_table == 0)
2094                 return 0;
2095
2096         return ci_do_program_memory_timing_parameters(rdev);
2097 }
2098
2099 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2100                                           struct radeon_ps *radeon_boot_state)
2101 {
2102         struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2103         struct ci_power_info *pi = ci_get_pi(rdev);
2104         u32 level = 0;
2105
2106         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2107                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2108                     boot_state->performance_levels[0].sclk) {
2109                         pi->smc_state_table.GraphicsBootLevel = level;
2110                         break;
2111                 }
2112         }
2113
2114         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2115                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2116                     boot_state->performance_levels[0].mclk) {
2117                         pi->smc_state_table.MemoryBootLevel = level;
2118                         break;
2119                 }
2120         }
2121 }
2122
2123 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2124 {
2125         u32 i;
2126         u32 mask_value = 0;
2127
2128         for (i = dpm_table->count; i > 0; i--) {
2129                 mask_value = mask_value << 1;
2130                 if (dpm_table->dpm_levels[i-1].enabled)
2131                         mask_value |= 0x1;
2132                 else
2133                         mask_value &= 0xFFFFFFFE;
2134         }
2135
2136         return mask_value;
2137 }
2138
2139 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2140                                        SMU7_Discrete_DpmTable *table)
2141 {
2142         struct ci_power_info *pi = ci_get_pi(rdev);
2143         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2144         u32 i;
2145
2146         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2147                 table->LinkLevel[i].PcieGenSpeed =
2148                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2149                 table->LinkLevel[i].PcieLaneCount =
2150                         r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2151                 table->LinkLevel[i].EnabledForActivity = 1;
2152                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2153                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2154         }
2155
2156         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2157         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2158                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2159 }
2160
2161 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2162                                      SMU7_Discrete_DpmTable *table)
2163 {
2164         u32 count;
2165         struct atom_clock_dividers dividers;
2166         int ret = -EINVAL;
2167
2168         table->UvdLevelCount =
2169                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2170
2171         for (count = 0; count < table->UvdLevelCount; count++) {
2172                 table->UvdLevel[count].VclkFrequency =
2173                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2174                 table->UvdLevel[count].DclkFrequency =
2175                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2176                 table->UvdLevel[count].MinVddc =
2177                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2178                 table->UvdLevel[count].MinVddcPhases = 1;
2179
2180                 ret = radeon_atom_get_clock_dividers(rdev,
2181                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2182                                                      table->UvdLevel[count].VclkFrequency, false, &dividers);
2183                 if (ret)
2184                         return ret;
2185
2186                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2187
2188                 ret = radeon_atom_get_clock_dividers(rdev,
2189                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2190                                                      table->UvdLevel[count].DclkFrequency, false, &dividers);
2191                 if (ret)
2192                         return ret;
2193
2194                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2195
2196                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2197                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2198                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2199         }
2200
2201         return ret;
2202 }
2203
2204 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2205                                      SMU7_Discrete_DpmTable *table)
2206 {
2207         u32 count;
2208         struct atom_clock_dividers dividers;
2209         int ret = -EINVAL;
2210
2211         table->VceLevelCount =
2212                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2213
2214         for (count = 0; count < table->VceLevelCount; count++) {
2215                 table->VceLevel[count].Frequency =
2216                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2217                 table->VceLevel[count].MinVoltage =
2218                         (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2219                 table->VceLevel[count].MinPhases = 1;
2220
2221                 ret = radeon_atom_get_clock_dividers(rdev,
2222                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2223                                                      table->VceLevel[count].Frequency, false, &dividers);
2224                 if (ret)
2225                         return ret;
2226
2227                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2228
2229                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2230                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2231         }
2232
2233         return ret;
2234
2235 }
2236
2237 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2238                                      SMU7_Discrete_DpmTable *table)
2239 {
2240         u32 count;
2241         struct atom_clock_dividers dividers;
2242         int ret = -EINVAL;
2243
2244         table->AcpLevelCount = (u8)
2245                 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2246
2247         for (count = 0; count < table->AcpLevelCount; count++) {
2248                 table->AcpLevel[count].Frequency =
2249                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2250                 table->AcpLevel[count].MinVoltage =
2251                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2252                 table->AcpLevel[count].MinPhases = 1;
2253
2254                 ret = radeon_atom_get_clock_dividers(rdev,
2255                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2256                                                      table->AcpLevel[count].Frequency, false, &dividers);
2257                 if (ret)
2258                         return ret;
2259
2260                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2261
2262                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2263                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2264         }
2265
2266         return ret;
2267 }
2268
2269 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2270                                       SMU7_Discrete_DpmTable *table)
2271 {
2272         u32 count;
2273         struct atom_clock_dividers dividers;
2274         int ret = -EINVAL;
2275
2276         table->SamuLevelCount =
2277                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2278
2279         for (count = 0; count < table->SamuLevelCount; count++) {
2280                 table->SamuLevel[count].Frequency =
2281                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2282                 table->SamuLevel[count].MinVoltage =
2283                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2284                 table->SamuLevel[count].MinPhases = 1;
2285
2286                 ret = radeon_atom_get_clock_dividers(rdev,
2287                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2288                                                      table->SamuLevel[count].Frequency, false, &dividers);
2289                 if (ret)
2290                         return ret;
2291
2292                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2293
2294                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2295                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2296         }
2297
2298         return ret;
2299 }
2300
2301 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2302                                     u32 memory_clock,
2303                                     SMU7_Discrete_MemoryLevel *mclk,
2304                                     bool strobe_mode,
2305                                     bool dll_state_on)
2306 {
2307         struct ci_power_info *pi = ci_get_pi(rdev);
2308         u32  dll_cntl = pi->clock_registers.dll_cntl;
2309         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2310         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2311         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2312         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2313         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2314         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2315         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2316         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2317         struct atom_mpll_param mpll_param;
2318         int ret;
2319
2320         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2321         if (ret)
2322                 return ret;
2323
2324         mpll_func_cntl &= ~BWCTRL_MASK;
2325         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2326
2327         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2328         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2329                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2330
2331         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2332         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2333
2334         if (pi->mem_gddr5) {
2335                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2336                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2337                         YCLK_POST_DIV(mpll_param.post_div);
2338         }
2339
2340         if (pi->caps_mclk_ss_support) {
2341                 struct radeon_atom_ss ss;
2342                 u32 freq_nom;
2343                 u32 tmp;
2344                 u32 reference_clock = rdev->clock.mpll.reference_freq;
2345
2346                 if (pi->mem_gddr5)
2347                         freq_nom = memory_clock * 4;
2348                 else
2349                         freq_nom = memory_clock * 2;
2350
2351                 tmp = (freq_nom / reference_clock);
2352                 tmp = tmp * tmp;
2353                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2354                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2355                         u32 clks = reference_clock * 5 / ss.rate;
2356                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2357
2358                         mpll_ss1 &= ~CLKV_MASK;
2359                         mpll_ss1 |= CLKV(clkv);
2360
2361                         mpll_ss2 &= ~CLKS_MASK;
2362                         mpll_ss2 |= CLKS(clks);
2363                 }
2364         }
2365
2366         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2367         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2368
2369         if (dll_state_on)
2370                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2371         else
2372                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2373
2374         mclk->MclkFrequency = memory_clock;
2375         mclk->MpllFuncCntl = mpll_func_cntl;
2376         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2377         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2378         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2379         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2380         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2381         mclk->DllCntl = dll_cntl;
2382         mclk->MpllSs1 = mpll_ss1;
2383         mclk->MpllSs2 = mpll_ss2;
2384
2385         return 0;
2386 }
2387
2388 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2389                                            u32 memory_clock,
2390                                            SMU7_Discrete_MemoryLevel *memory_level)
2391 {
2392         struct ci_power_info *pi = ci_get_pi(rdev);
2393         int ret;
2394         bool dll_state_on;
2395
2396         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2397                 ret = ci_get_dependency_volt_by_clk(rdev,
2398                                                     &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2399                                                     memory_clock, &memory_level->MinVddc);
2400                 if (ret)
2401                         return ret;
2402         }
2403
2404         if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2405                 ret = ci_get_dependency_volt_by_clk(rdev,
2406                                                     &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2407                                                     memory_clock, &memory_level->MinVddci);
2408                 if (ret)
2409                         return ret;
2410         }
2411
2412         if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2413                 ret = ci_get_dependency_volt_by_clk(rdev,
2414                                                     &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2415                                                     memory_clock, &memory_level->MinMvdd);
2416                 if (ret)
2417                         return ret;
2418         }
2419
2420         memory_level->MinVddcPhases = 1;
2421
2422         if (pi->vddc_phase_shed_control)
2423                 ci_populate_phase_value_based_on_mclk(rdev,
2424                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2425                                                       memory_clock,
2426                                                       &memory_level->MinVddcPhases);
2427
2428         memory_level->EnabledForThrottle = 1;
2429         memory_level->EnabledForActivity = 1;
2430         memory_level->UpH = 0;
2431         memory_level->DownH = 100;
2432         memory_level->VoltageDownH = 0;
2433         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2434
2435         memory_level->StutterEnable = false;
2436         memory_level->StrobeEnable = false;
2437         memory_level->EdcReadEnable = false;
2438         memory_level->EdcWriteEnable = false;
2439         memory_level->RttEnable = false;
2440
2441         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2442
2443         if (pi->mclk_stutter_mode_threshold &&
2444             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2445             (pi->uvd_enabled == false) &&
2446             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2447             (rdev->pm.dpm.new_active_crtc_count <= 2))
2448                 memory_level->StutterEnable = true;
2449
2450         if (pi->mclk_strobe_mode_threshold &&
2451             (memory_clock <= pi->mclk_strobe_mode_threshold))
2452                 memory_level->StrobeEnable = 1;
2453
2454         if (pi->mem_gddr5) {
2455                 memory_level->StrobeRatio =
2456                         si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2457                 if (pi->mclk_edc_enable_threshold &&
2458                     (memory_clock > pi->mclk_edc_enable_threshold))
2459                         memory_level->EdcReadEnable = true;
2460
2461                 if (pi->mclk_edc_wr_enable_threshold &&
2462                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
2463                         memory_level->EdcWriteEnable = true;
2464
2465                 if (memory_level->StrobeEnable) {
2466                         if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2467                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2468                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2469                         else
2470                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2471                 } else {
2472                         dll_state_on = pi->dll_default_on;
2473                 }
2474         } else {
2475                 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2476                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2477         }
2478
2479         ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2480         if (ret)
2481                 return ret;
2482
2483         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2484         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2485         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2486         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2487
2488         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2489         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2490         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2491         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2492         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2493         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2494         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2495         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2496         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2497         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2498         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2499
2500         return 0;
2501 }
2502
2503 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2504                                       SMU7_Discrete_DpmTable *table)
2505 {
2506         struct ci_power_info *pi = ci_get_pi(rdev);
2507         struct atom_clock_dividers dividers;
2508         SMU7_Discrete_VoltageLevel voltage_level;
2509         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2510         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2511         u32 dll_cntl = pi->clock_registers.dll_cntl;
2512         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2513         int ret;
2514
2515         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2516
2517         if (pi->acpi_vddc)
2518                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2519         else
2520                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2521
2522         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2523
2524         table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2525
2526         ret = radeon_atom_get_clock_dividers(rdev,
2527                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2528                                              table->ACPILevel.SclkFrequency, false, &dividers);
2529         if (ret)
2530                 return ret;
2531
2532         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2533         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2534         table->ACPILevel.DeepSleepDivId = 0;
2535
2536         spll_func_cntl &= ~SPLL_PWRON;
2537         spll_func_cntl |= SPLL_RESET;
2538
2539         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2540         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2541
2542         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2543         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2544         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2545         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2546         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2547         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2548         table->ACPILevel.CcPwrDynRm = 0;
2549         table->ACPILevel.CcPwrDynRm1 = 0;
2550
2551         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2552         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2553         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2554         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2555         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2556         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2557         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2558         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2559         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2560         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2561         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2562
2563         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2564         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2565
2566         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2567                 if (pi->acpi_vddci)
2568                         table->MemoryACPILevel.MinVddci =
2569                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2570                 else
2571                         table->MemoryACPILevel.MinVddci =
2572                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2573         }
2574
2575         if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2576                 table->MemoryACPILevel.MinMvdd = 0;
2577         else
2578                 table->MemoryACPILevel.MinMvdd =
2579                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2580
2581         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2582         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2583
2584         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2585
2586         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2587         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2588         table->MemoryACPILevel.MpllAdFuncCntl =
2589                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2590         table->MemoryACPILevel.MpllDqFuncCntl =
2591                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2592         table->MemoryACPILevel.MpllFuncCntl =
2593                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2594         table->MemoryACPILevel.MpllFuncCntl_1 =
2595                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2596         table->MemoryACPILevel.MpllFuncCntl_2 =
2597                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2598         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2599         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2600
2601         table->MemoryACPILevel.EnabledForThrottle = 0;
2602         table->MemoryACPILevel.EnabledForActivity = 0;
2603         table->MemoryACPILevel.UpH = 0;
2604         table->MemoryACPILevel.DownH = 100;
2605         table->MemoryACPILevel.VoltageDownH = 0;
2606         table->MemoryACPILevel.ActivityLevel =
2607                 cpu_to_be16((u16)pi->mclk_activity_target);
2608
2609         table->MemoryACPILevel.StutterEnable = false;
2610         table->MemoryACPILevel.StrobeEnable = false;
2611         table->MemoryACPILevel.EdcReadEnable = false;
2612         table->MemoryACPILevel.EdcWriteEnable = false;
2613         table->MemoryACPILevel.RttEnable = false;
2614
2615         return 0;
2616 }
2617
2618
2619 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2620 {
2621         struct ci_power_info *pi = ci_get_pi(rdev);
2622         struct ci_ulv_parm *ulv = &pi->ulv;
2623
2624         if (ulv->supported) {
2625                 if (enable)
2626                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2627                                 0 : -EINVAL;
2628                 else
2629                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2630                                 0 : -EINVAL;
2631         }
2632
2633         return 0;
2634 }
2635
2636 static int ci_populate_ulv_level(struct radeon_device *rdev,
2637                                  SMU7_Discrete_Ulv *state)
2638 {
2639         struct ci_power_info *pi = ci_get_pi(rdev);
2640         u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2641
2642         state->CcPwrDynRm = 0;
2643         state->CcPwrDynRm1 = 0;
2644
2645         if (ulv_voltage == 0) {
2646                 pi->ulv.supported = false;
2647                 return 0;
2648         }
2649
2650         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2651                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2652                         state->VddcOffset = 0;
2653                 else
2654                         state->VddcOffset =
2655                                 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2656         } else {
2657                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2658                         state->VddcOffsetVid = 0;
2659                 else
2660                         state->VddcOffsetVid = (u8)
2661                                 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2662                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2663         }
2664         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2665
2666         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2667         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2668         state->VddcOffset = cpu_to_be16(state->VddcOffset);
2669
2670         return 0;
2671 }
2672
2673 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2674                                     u32 engine_clock,
2675                                     SMU7_Discrete_GraphicsLevel *sclk)
2676 {
2677         struct ci_power_info *pi = ci_get_pi(rdev);
2678         struct atom_clock_dividers dividers;
2679         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2680         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2681         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2682         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2683         u32 reference_clock = rdev->clock.spll.reference_freq;
2684         u32 reference_divider;
2685         u32 fbdiv;
2686         int ret;
2687
2688         ret = radeon_atom_get_clock_dividers(rdev,
2689                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2690                                              engine_clock, false, &dividers);
2691         if (ret)
2692                 return ret;
2693
2694         reference_divider = 1 + dividers.ref_div;
2695         fbdiv = dividers.fb_div & 0x3FFFFFF;
2696
2697         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2698         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2699         spll_func_cntl_3 |= SPLL_DITHEN;
2700
2701         if (pi->caps_sclk_ss_support) {
2702                 struct radeon_atom_ss ss;
2703                 u32 vco_freq = engine_clock * dividers.post_div;
2704
2705                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2706                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2707                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2708                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2709
2710                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
2711                         cg_spll_spread_spectrum |= CLK_S(clk_s);
2712                         cg_spll_spread_spectrum |= SSEN;
2713
2714                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2715                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2716                 }
2717         }
2718
2719         sclk->SclkFrequency = engine_clock;
2720         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2721         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2722         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2723         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2724         sclk->SclkDid = (u8)dividers.post_divider;
2725
2726         return 0;
2727 }
2728
2729 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2730                                             u32 engine_clock,
2731                                             u16 sclk_activity_level_t,
2732                                             SMU7_Discrete_GraphicsLevel *graphic_level)
2733 {
2734         struct ci_power_info *pi = ci_get_pi(rdev);
2735         int ret;
2736
2737         ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2738         if (ret)
2739                 return ret;
2740
2741         ret = ci_get_dependency_volt_by_clk(rdev,
2742                                             &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2743                                             engine_clock, &graphic_level->MinVddc);
2744         if (ret)
2745                 return ret;
2746
2747         graphic_level->SclkFrequency = engine_clock;
2748
2749         graphic_level->Flags =  0;
2750         graphic_level->MinVddcPhases = 1;
2751
2752         if (pi->vddc_phase_shed_control)
2753                 ci_populate_phase_value_based_on_sclk(rdev,
2754                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2755                                                       engine_clock,
2756                                                       &graphic_level->MinVddcPhases);
2757
2758         graphic_level->ActivityLevel = sclk_activity_level_t;
2759
2760         graphic_level->CcPwrDynRm = 0;
2761         graphic_level->CcPwrDynRm1 = 0;
2762         graphic_level->EnabledForActivity = 1;
2763         graphic_level->EnabledForThrottle = 1;
2764         graphic_level->UpH = 0;
2765         graphic_level->DownH = 0;
2766         graphic_level->VoltageDownH = 0;
2767         graphic_level->PowerThrottle = 0;
2768
2769         if (pi->caps_sclk_ds)
2770                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2771                                                                                    engine_clock,
2772                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
2773
2774         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2775
2776         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2777         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2778         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2779         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2780         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2781         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2782         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2783         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2784         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2785         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2786         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2787
2788         return 0;
2789 }
2790
2791 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2792 {
2793         struct ci_power_info *pi = ci_get_pi(rdev);
2794         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2795         u32 level_array_address = pi->dpm_table_start +
2796                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2797         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2798                 SMU7_MAX_LEVELS_GRAPHICS;
2799         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2800         u32 i, ret;
2801
2802         memset(levels, 0, level_array_size);
2803
2804         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2805                 ret = ci_populate_single_graphic_level(rdev,
2806                                                        dpm_table->sclk_table.dpm_levels[i].value,
2807                                                        (u16)pi->activity_target[i],
2808                                                        &pi->smc_state_table.GraphicsLevel[i]);
2809                 if (ret)
2810                         return ret;
2811                 if (i == (dpm_table->sclk_table.count - 1))
2812                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2813                                 PPSMC_DISPLAY_WATERMARK_HIGH;
2814         }
2815
2816         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2817         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2818                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2819
2820         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2821                                    (u8 *)levels, level_array_size,
2822                                    pi->sram_end);
2823         if (ret)
2824                 return ret;
2825
2826         return 0;
2827 }
2828
2829 static int ci_populate_ulv_state(struct radeon_device *rdev,
2830                                  SMU7_Discrete_Ulv *ulv_level)
2831 {
2832         return ci_populate_ulv_level(rdev, ulv_level);
2833 }
2834
2835 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2836 {
2837         struct ci_power_info *pi = ci_get_pi(rdev);
2838         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2839         u32 level_array_address = pi->dpm_table_start +
2840                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2841         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2842                 SMU7_MAX_LEVELS_MEMORY;
2843         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2844         u32 i, ret;
2845
2846         memset(levels, 0, level_array_size);
2847
2848         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2849                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2850                         return -EINVAL;
2851                 ret = ci_populate_single_memory_level(rdev,
2852                                                       dpm_table->mclk_table.dpm_levels[i].value,
2853                                                       &pi->smc_state_table.MemoryLevel[i]);
2854                 if (ret)
2855                         return ret;
2856         }
2857
2858         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2859
2860         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2861         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2862                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2863
2864         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2865                 PPSMC_DISPLAY_WATERMARK_HIGH;
2866
2867         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2868                                    (u8 *)levels, level_array_size,
2869                                    pi->sram_end);
2870         if (ret)
2871                 return ret;
2872
2873         return 0;
2874 }
2875
2876 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2877                                       struct ci_single_dpm_table* dpm_table,
2878                                       u32 count)
2879 {
2880         u32 i;
2881
2882         dpm_table->count = count;
2883         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2884                 dpm_table->dpm_levels[i].enabled = false;
2885 }
2886
2887 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2888                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
2889 {
2890         dpm_table->dpm_levels[index].value = pcie_gen;
2891         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2892         dpm_table->dpm_levels[index].enabled = true;
2893 }
2894
2895 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2896 {
2897         struct ci_power_info *pi = ci_get_pi(rdev);
2898
2899         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2900                 return -EINVAL;
2901
2902         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2903                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2904                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2905         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2906                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2907                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2908         }
2909
2910         ci_reset_single_dpm_table(rdev,
2911                                   &pi->dpm_table.pcie_speed_table,
2912                                   SMU7_MAX_LEVELS_LINK);
2913
2914         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2915                                   pi->pcie_gen_powersaving.min,
2916                                   pi->pcie_lane_powersaving.min);
2917         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2918                                   pi->pcie_gen_performance.min,
2919                                   pi->pcie_lane_performance.min);
2920         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2921                                   pi->pcie_gen_powersaving.min,
2922                                   pi->pcie_lane_powersaving.max);
2923         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2924                                   pi->pcie_gen_performance.min,
2925                                   pi->pcie_lane_performance.max);
2926         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2927                                   pi->pcie_gen_powersaving.max,
2928                                   pi->pcie_lane_powersaving.max);
2929         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2930                                   pi->pcie_gen_performance.max,
2931                                   pi->pcie_lane_performance.max);
2932
2933         pi->dpm_table.pcie_speed_table.count = 6;
2934
2935         return 0;
2936 }
2937
2938 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2939 {
2940         struct ci_power_info *pi = ci_get_pi(rdev);
2941         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2942                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2943         struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2944                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2945         struct radeon_cac_leakage_table *std_voltage_table =
2946                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2947         u32 i;
2948
2949         if (allowed_sclk_vddc_table == NULL)
2950                 return -EINVAL;
2951         if (allowed_sclk_vddc_table->count < 1)
2952                 return -EINVAL;
2953         if (allowed_mclk_table == NULL)
2954                 return -EINVAL;
2955         if (allowed_mclk_table->count < 1)
2956                 return -EINVAL;
2957
2958         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2959
2960         ci_reset_single_dpm_table(rdev,
2961                                   &pi->dpm_table.sclk_table,
2962                                   SMU7_MAX_LEVELS_GRAPHICS);
2963         ci_reset_single_dpm_table(rdev,
2964                                   &pi->dpm_table.mclk_table,
2965                                   SMU7_MAX_LEVELS_MEMORY);
2966         ci_reset_single_dpm_table(rdev,
2967                                   &pi->dpm_table.vddc_table,
2968                                   SMU7_MAX_LEVELS_VDDC);
2969         ci_reset_single_dpm_table(rdev,
2970                                   &pi->dpm_table.vddci_table,
2971                                   SMU7_MAX_LEVELS_VDDCI);
2972         ci_reset_single_dpm_table(rdev,
2973                                   &pi->dpm_table.mvdd_table,
2974                                   SMU7_MAX_LEVELS_MVDD);
2975
2976         pi->dpm_table.sclk_table.count = 0;
2977         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
2978                 if ((i == 0) ||
2979                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
2980                      allowed_sclk_vddc_table->entries[i].clk)) {
2981                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
2982                                 allowed_sclk_vddc_table->entries[i].clk;
2983                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
2984                         pi->dpm_table.sclk_table.count++;
2985                 }
2986         }
2987
2988         pi->dpm_table.mclk_table.count = 0;
2989         for (i = 0; i < allowed_mclk_table->count; i++) {
2990                 if ((i==0) ||
2991                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
2992                      allowed_mclk_table->entries[i].clk)) {
2993                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
2994                                 allowed_mclk_table->entries[i].clk;
2995                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
2996                         pi->dpm_table.mclk_table.count++;
2997                 }
2998         }
2999
3000         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3001                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3002                         allowed_sclk_vddc_table->entries[i].v;
3003                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3004                         std_voltage_table->entries[i].leakage;
3005                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3006         }
3007         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3008
3009         allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3010         if (allowed_mclk_table) {
3011                 for (i = 0; i < allowed_mclk_table->count; i++) {
3012                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3013                                 allowed_mclk_table->entries[i].v;
3014                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3015                 }
3016                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3017         }
3018
3019         allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3020         if (allowed_mclk_table) {
3021                 for (i = 0; i < allowed_mclk_table->count; i++) {
3022                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3023                                 allowed_mclk_table->entries[i].v;
3024                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3025                 }
3026                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3027         }
3028
3029         ci_setup_default_pcie_tables(rdev);
3030
3031         return 0;
3032 }
3033
3034 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3035                               u32 value, u32 *boot_level)
3036 {
3037         u32 i;
3038         int ret = -EINVAL;
3039
3040         for(i = 0; i < table->count; i++) {
3041                 if (value == table->dpm_levels[i].value) {
3042                         *boot_level = i;
3043                         ret = 0;
3044                 }
3045         }
3046
3047         return ret;
3048 }
3049
3050 static int ci_init_smc_table(struct radeon_device *rdev)
3051 {
3052         struct ci_power_info *pi = ci_get_pi(rdev);
3053         struct ci_ulv_parm *ulv = &pi->ulv;
3054         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3055         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3056         int ret;
3057
3058         ret = ci_setup_default_dpm_tables(rdev);
3059         if (ret)
3060                 return ret;
3061
3062         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3063                 ci_populate_smc_voltage_tables(rdev, table);
3064
3065         ci_init_fps_limits(rdev);
3066
3067         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3068                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3069
3070         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3071                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3072
3073         if (pi->mem_gddr5)
3074                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3075
3076         if (ulv->supported) {
3077                 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3078                 if (ret)
3079                         return ret;
3080                 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3081         }
3082
3083         ret = ci_populate_all_graphic_levels(rdev);
3084         if (ret)
3085                 return ret;
3086
3087         ret = ci_populate_all_memory_levels(rdev);
3088         if (ret)
3089                 return ret;
3090
3091         ci_populate_smc_link_level(rdev, table);
3092
3093         ret = ci_populate_smc_acpi_level(rdev, table);
3094         if (ret)
3095                 return ret;
3096
3097         ret = ci_populate_smc_vce_level(rdev, table);
3098         if (ret)
3099                 return ret;
3100
3101         ret = ci_populate_smc_acp_level(rdev, table);
3102         if (ret)
3103                 return ret;
3104
3105         ret = ci_populate_smc_samu_level(rdev, table);
3106         if (ret)
3107                 return ret;
3108
3109         ret = ci_do_program_memory_timing_parameters(rdev);
3110         if (ret)
3111                 return ret;
3112
3113         ret = ci_populate_smc_uvd_level(rdev, table);
3114         if (ret)
3115                 return ret;
3116
3117         table->UvdBootLevel  = 0;
3118         table->VceBootLevel  = 0;
3119         table->AcpBootLevel  = 0;
3120         table->SamuBootLevel  = 0;
3121         table->GraphicsBootLevel  = 0;
3122         table->MemoryBootLevel  = 0;
3123
3124         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3125                                  pi->vbios_boot_state.sclk_bootup_value,
3126                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3127
3128         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3129                                  pi->vbios_boot_state.mclk_bootup_value,
3130                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3131
3132         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3133         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3134         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3135
3136         ci_populate_smc_initial_state(rdev, radeon_boot_state);
3137
3138         ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3139         if (ret)
3140                 return ret;
3141
3142         table->UVDInterval = 1;
3143         table->VCEInterval = 1;
3144         table->ACPInterval = 1;
3145         table->SAMUInterval = 1;
3146         table->GraphicsVoltageChangeEnable = 1;
3147         table->GraphicsThermThrottleEnable = 1;
3148         table->GraphicsInterval = 1;
3149         table->VoltageInterval = 1;
3150         table->ThermalInterval = 1;
3151         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3152                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3153         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3154                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3155         table->MemoryVoltageChangeEnable = 1;
3156         table->MemoryInterval = 1;
3157         table->VoltageResponseTime = 0;
3158         table->VddcVddciDelta = 4000;
3159         table->PhaseResponseTime = 0;
3160         table->MemoryThermThrottleEnable = 1;
3161         table->PCIeBootLinkLevel = 0;
3162         table->PCIeGenInterval = 1;
3163         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3164                 table->SVI2Enable  = 1;
3165         else
3166                 table->SVI2Enable  = 0;
3167
3168         table->ThermGpio = 17;
3169         table->SclkStepSize = 0x4000;
3170
3171         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3172         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3173         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3174         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3175         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3176         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3177         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3178         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3179         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3180         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3181         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3182         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3183         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3184         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3185
3186         ret = ci_copy_bytes_to_smc(rdev,
3187                                    pi->dpm_table_start +
3188                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3189                                    (u8 *)&table->SystemFlags,
3190                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3191                                    pi->sram_end);
3192         if (ret)
3193                 return ret;
3194
3195         return 0;
3196 }
3197
3198 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3199                                       struct ci_single_dpm_table *dpm_table,
3200                                       u32 low_limit, u32 high_limit)
3201 {
3202         u32 i;
3203
3204         for (i = 0; i < dpm_table->count; i++) {
3205                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3206                     (dpm_table->dpm_levels[i].value > high_limit))
3207                         dpm_table->dpm_levels[i].enabled = false;
3208                 else
3209                         dpm_table->dpm_levels[i].enabled = true;
3210         }
3211 }
3212
3213 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3214                                     u32 speed_low, u32 lanes_low,
3215                                     u32 speed_high, u32 lanes_high)
3216 {
3217         struct ci_power_info *pi = ci_get_pi(rdev);
3218         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3219         u32 i, j;
3220
3221         for (i = 0; i < pcie_table->count; i++) {
3222                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3223                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3224                     (pcie_table->dpm_levels[i].value > speed_high) ||
3225                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3226                         pcie_table->dpm_levels[i].enabled = false;
3227                 else
3228                         pcie_table->dpm_levels[i].enabled = true;
3229         }
3230
3231         for (i = 0; i < pcie_table->count; i++) {
3232                 if (pcie_table->dpm_levels[i].enabled) {
3233                         for (j = i + 1; j < pcie_table->count; j++) {
3234                                 if (pcie_table->dpm_levels[j].enabled) {
3235                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3236                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3237                                                 pcie_table->dpm_levels[j].enabled = false;
3238                                 }
3239                         }
3240                 }
3241         }
3242 }
3243
3244 static int ci_trim_dpm_states(struct radeon_device *rdev,
3245                               struct radeon_ps *radeon_state)
3246 {
3247         struct ci_ps *state = ci_get_ps(radeon_state);
3248         struct ci_power_info *pi = ci_get_pi(rdev);
3249         u32 high_limit_count;
3250
3251         if (state->performance_level_count < 1)
3252                 return -EINVAL;
3253
3254         if (state->performance_level_count == 1)
3255                 high_limit_count = 0;
3256         else
3257                 high_limit_count = 1;
3258
3259         ci_trim_single_dpm_states(rdev,
3260                                   &pi->dpm_table.sclk_table,
3261                                   state->performance_levels[0].sclk,
3262                                   state->performance_levels[high_limit_count].sclk);
3263
3264         ci_trim_single_dpm_states(rdev,
3265                                   &pi->dpm_table.mclk_table,
3266                                   state->performance_levels[0].mclk,
3267                                   state->performance_levels[high_limit_count].mclk);
3268
3269         ci_trim_pcie_dpm_states(rdev,
3270                                 state->performance_levels[0].pcie_gen,
3271                                 state->performance_levels[0].pcie_lane,
3272                                 state->performance_levels[high_limit_count].pcie_gen,
3273                                 state->performance_levels[high_limit_count].pcie_lane);
3274
3275         return 0;
3276 }
3277
3278 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3279 {
3280         struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3281                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3282         struct radeon_clock_voltage_dependency_table *vddc_table =
3283                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3284         u32 requested_voltage = 0;
3285         u32 i;
3286
3287         if (disp_voltage_table == NULL)
3288                 return -EINVAL;
3289         if (!disp_voltage_table->count)
3290                 return -EINVAL;
3291
3292         for (i = 0; i < disp_voltage_table->count; i++) {
3293                 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3294                         requested_voltage = disp_voltage_table->entries[i].v;
3295         }
3296
3297         for (i = 0; i < vddc_table->count; i++) {
3298                 if (requested_voltage <= vddc_table->entries[i].v) {
3299                         requested_voltage = vddc_table->entries[i].v;
3300                         return (ci_send_msg_to_smc_with_parameter(rdev,
3301                                                                   PPSMC_MSG_VddC_Request,
3302                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3303                                 0 : -EINVAL;
3304                 }
3305         }
3306
3307         return -EINVAL;
3308 }
3309
3310 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3311 {
3312         struct ci_power_info *pi = ci_get_pi(rdev);
3313         PPSMC_Result result;
3314
3315         if (!pi->sclk_dpm_key_disabled) {
3316                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3317                         result = ci_send_msg_to_smc_with_parameter(rdev,
3318                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3319                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3320                         if (result != PPSMC_Result_OK)
3321                                 return -EINVAL;
3322                 }
3323         }
3324
3325         if (!pi->mclk_dpm_key_disabled) {
3326                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3327                         result = ci_send_msg_to_smc_with_parameter(rdev,
3328                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3329                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3330                         if (result != PPSMC_Result_OK)
3331                                 return -EINVAL;
3332                 }
3333         }
3334
3335         if (!pi->pcie_dpm_key_disabled) {
3336                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3337                         result = ci_send_msg_to_smc_with_parameter(rdev,
3338                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3339                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3340                         if (result != PPSMC_Result_OK)
3341                                 return -EINVAL;
3342                 }
3343         }
3344
3345         ci_apply_disp_minimum_voltage_request(rdev);
3346
3347         return 0;
3348 }
3349
3350 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3351                                                    struct radeon_ps *radeon_state)
3352 {
3353         struct ci_power_info *pi = ci_get_pi(rdev);
3354         struct ci_ps *state = ci_get_ps(radeon_state);
3355         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3356         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3357         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3358         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3359         u32 i;
3360
3361         pi->need_update_smu7_dpm_table = 0;
3362
3363         for (i = 0; i < sclk_table->count; i++) {
3364                 if (sclk == sclk_table->dpm_levels[i].value)
3365                         break;
3366         }
3367
3368         if (i >= sclk_table->count) {
3369                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3370         } else {
3371                 /* XXX check display min clock requirements */
3372                 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3373                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3374         }
3375
3376         for (i = 0; i < mclk_table->count; i++) {
3377                 if (mclk == mclk_table->dpm_levels[i].value)
3378                         break;
3379         }
3380
3381         if (i >= mclk_table->count)
3382                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3383
3384         if (rdev->pm.dpm.current_active_crtc_count !=
3385             rdev->pm.dpm.new_active_crtc_count)
3386                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3387 }
3388
3389 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3390                                                        struct radeon_ps *radeon_state)
3391 {
3392         struct ci_power_info *pi = ci_get_pi(rdev);
3393         struct ci_ps *state = ci_get_ps(radeon_state);
3394         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3395         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3396         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3397         int ret;
3398
3399         if (!pi->need_update_smu7_dpm_table)
3400                 return 0;
3401
3402         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3403                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3404
3405         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3406                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3407
3408         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3409                 ret = ci_populate_all_graphic_levels(rdev);
3410                 if (ret)
3411                         return ret;
3412         }
3413
3414         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3415                 ret = ci_populate_all_memory_levels(rdev);
3416                 if (ret)
3417                         return ret;
3418         }
3419
3420         return 0;
3421 }
3422
3423 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3424 {
3425         struct ci_power_info *pi = ci_get_pi(rdev);
3426         const struct radeon_clock_and_voltage_limits *max_limits;
3427         int i;
3428
3429         if (rdev->pm.dpm.ac_power)
3430                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3431         else
3432                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3433
3434         if (enable) {
3435                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3436
3437                 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3438                         if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3439                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3440
3441                                 if (!pi->caps_uvd_dpm)
3442                                         break;
3443                         }
3444                 }
3445
3446                 ci_send_msg_to_smc_with_parameter(rdev,
3447                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
3448                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3449
3450                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3451                         pi->uvd_enabled = true;
3452                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3453                         ci_send_msg_to_smc_with_parameter(rdev,
3454                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3455                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3456                 }
3457         } else {
3458                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3459                         pi->uvd_enabled = false;
3460                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3461                         ci_send_msg_to_smc_with_parameter(rdev,
3462                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3463                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3464                 }
3465         }
3466
3467         return (ci_send_msg_to_smc(rdev, enable ?
3468                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3469                 0 : -EINVAL;
3470 }
3471
3472 #if 0
3473 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3474 {
3475         struct ci_power_info *pi = ci_get_pi(rdev);
3476         const struct radeon_clock_and_voltage_limits *max_limits;
3477         int i;
3478
3479         if (rdev->pm.dpm.ac_power)
3480                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3481         else
3482                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3483
3484         if (enable) {
3485                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3486                 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3487                         if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3488                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3489
3490                                 if (!pi->caps_vce_dpm)
3491                                         break;
3492                         }
3493                 }
3494
3495                 ci_send_msg_to_smc_with_parameter(rdev,
3496                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
3497                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3498         }
3499
3500         return (ci_send_msg_to_smc(rdev, enable ?
3501                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3502                 0 : -EINVAL;
3503 }
3504
3505 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3506 {
3507         struct ci_power_info *pi = ci_get_pi(rdev);
3508         const struct radeon_clock_and_voltage_limits *max_limits;
3509         int i;
3510
3511         if (rdev->pm.dpm.ac_power)
3512                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3513         else
3514                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3515
3516         if (enable) {
3517                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3518                 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3519                         if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3520                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3521
3522                                 if (!pi->caps_samu_dpm)
3523                                         break;
3524                         }
3525                 }
3526
3527                 ci_send_msg_to_smc_with_parameter(rdev,
3528                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
3529                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3530         }
3531         return (ci_send_msg_to_smc(rdev, enable ?
3532                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3533                 0 : -EINVAL;
3534 }
3535
3536 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3537 {
3538         struct ci_power_info *pi = ci_get_pi(rdev);
3539         const struct radeon_clock_and_voltage_limits *max_limits;
3540         int i;
3541
3542         if (rdev->pm.dpm.ac_power)
3543                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3544         else
3545                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3546
3547         if (enable) {
3548                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3549                 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3550                         if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3551                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3552
3553                                 if (!pi->caps_acp_dpm)
3554                                         break;
3555                         }
3556                 }
3557
3558                 ci_send_msg_to_smc_with_parameter(rdev,
3559                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
3560                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3561         }
3562
3563         return (ci_send_msg_to_smc(rdev, enable ?
3564                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3565                 0 : -EINVAL;
3566 }
3567 #endif
3568
3569 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3570 {
3571         struct ci_power_info *pi = ci_get_pi(rdev);
3572         u32 tmp;
3573
3574         if (!gate) {
3575                 if (pi->caps_uvd_dpm ||
3576                     (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3577                         pi->smc_state_table.UvdBootLevel = 0;
3578                 else
3579                         pi->smc_state_table.UvdBootLevel =
3580                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3581
3582                 tmp = RREG32_SMC(DPM_TABLE_475);
3583                 tmp &= ~UvdBootLevel_MASK;
3584                 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3585                 WREG32_SMC(DPM_TABLE_475, tmp);
3586         }
3587
3588         return ci_enable_uvd_dpm(rdev, !gate);
3589 }
3590
3591 #if 0
3592 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3593 {
3594         u8 i;
3595         u32 min_evclk = 30000; /* ??? */
3596         struct radeon_vce_clock_voltage_dependency_table *table =
3597                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3598
3599         for (i = 0; i < table->count; i++) {
3600                 if (table->entries[i].evclk >= min_evclk)
3601                         return i;
3602         }
3603
3604         return table->count - 1;
3605 }
3606
3607 static int ci_update_vce_dpm(struct radeon_device *rdev,
3608                              struct radeon_ps *radeon_new_state,
3609                              struct radeon_ps *radeon_current_state)
3610 {
3611         struct ci_power_info *pi = ci_get_pi(rdev);
3612         bool new_vce_clock_non_zero = (radeon_new_state->evclk != 0);
3613         bool old_vce_clock_non_zero = (radeon_current_state->evclk != 0);
3614         int ret = 0;
3615         u32 tmp;
3616
3617         if (new_vce_clock_non_zero != old_vce_clock_non_zero) {
3618                 if (new_vce_clock_non_zero) {
3619                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3620
3621                         tmp = RREG32_SMC(DPM_TABLE_475);
3622                         tmp &= ~VceBootLevel_MASK;
3623                         tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3624                         WREG32_SMC(DPM_TABLE_475, tmp);
3625
3626                         ret = ci_enable_vce_dpm(rdev, true);
3627                 } else {
3628                         ret = ci_enable_vce_dpm(rdev, false);
3629                 }
3630         }
3631         return ret;
3632 }
3633
3634 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3635 {
3636         return ci_enable_samu_dpm(rdev, gate);
3637 }
3638
3639 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3640 {
3641         struct ci_power_info *pi = ci_get_pi(rdev);
3642         u32 tmp;
3643
3644         if (!gate) {
3645                 pi->smc_state_table.AcpBootLevel = 0;
3646
3647                 tmp = RREG32_SMC(DPM_TABLE_475);
3648                 tmp &= ~AcpBootLevel_MASK;
3649                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3650                 WREG32_SMC(DPM_TABLE_475, tmp);
3651         }
3652
3653         return ci_enable_acp_dpm(rdev, !gate);
3654 }
3655 #endif
3656
3657 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3658                                              struct radeon_ps *radeon_state)
3659 {
3660         struct ci_power_info *pi = ci_get_pi(rdev);
3661         int ret;
3662
3663         ret = ci_trim_dpm_states(rdev, radeon_state);
3664         if (ret)
3665                 return ret;
3666
3667         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3668                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3669         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3670                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3671         pi->last_mclk_dpm_enable_mask =
3672                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3673         if (pi->uvd_enabled) {
3674                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3675                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3676         }
3677         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3678                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3679
3680         return 0;
3681 }
3682
3683 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3684                                        u32 level_mask)
3685 {
3686         u32 level = 0;
3687
3688         while ((level_mask & (1 << level)) == 0)
3689                 level++;
3690
3691         return level;
3692 }
3693
3694
3695 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3696                                    enum radeon_dpm_forced_level level)
3697 {
3698         struct ci_power_info *pi = ci_get_pi(rdev);
3699         PPSMC_Result smc_result;
3700         u32 tmp, levels, i;
3701         int ret;
3702
3703         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3704                 if ((!pi->sclk_dpm_key_disabled) &&
3705                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3706                         levels = 0;
3707                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3708                         while (tmp >>= 1)
3709                                 levels++;
3710                         if (levels) {
3711                                 ret = ci_dpm_force_state_sclk(rdev, levels);
3712                                 if (ret)
3713                                         return ret;
3714                                 for (i = 0; i < rdev->usec_timeout; i++) {
3715                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3716                                                CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3717                                         if (tmp == levels)
3718                                                 break;
3719                                         udelay(1);
3720                                 }
3721                         }
3722                 }
3723                 if ((!pi->mclk_dpm_key_disabled) &&
3724                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3725                         levels = 0;
3726                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3727                         while (tmp >>= 1)
3728                                 levels++;
3729                         if (levels) {
3730                                 ret = ci_dpm_force_state_mclk(rdev, levels);
3731                                 if (ret)
3732                                         return ret;
3733                                 for (i = 0; i < rdev->usec_timeout; i++) {
3734                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3735                                                CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3736                                         if (tmp == levels)
3737                                                 break;
3738                                         udelay(1);
3739                                 }
3740                         }
3741                 }
3742                 if ((!pi->pcie_dpm_key_disabled) &&
3743                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3744                         levels = 0;
3745                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3746                         while (tmp >>= 1)
3747                                 levels++;
3748                         if (levels) {
3749                                 ret = ci_dpm_force_state_pcie(rdev, level);
3750                                 if (ret)
3751                                         return ret;
3752                                 for (i = 0; i < rdev->usec_timeout; i++) {
3753                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3754                                                CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3755                                         if (tmp == levels)
3756                                                 break;
3757                                         udelay(1);
3758                                 }
3759                         }
3760                 }
3761         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3762                 if ((!pi->sclk_dpm_key_disabled) &&
3763                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3764                         levels = ci_get_lowest_enabled_level(rdev,
3765                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3766                         ret = ci_dpm_force_state_sclk(rdev, levels);
3767                         if (ret)
3768                                 return ret;
3769                         for (i = 0; i < rdev->usec_timeout; i++) {
3770                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3771                                        CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3772                                 if (tmp == levels)
3773                                         break;
3774                                 udelay(1);
3775                         }
3776                 }
3777                 if ((!pi->mclk_dpm_key_disabled) &&
3778                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3779                         levels = ci_get_lowest_enabled_level(rdev,
3780                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3781                         ret = ci_dpm_force_state_mclk(rdev, levels);
3782                         if (ret)
3783                                 return ret;
3784                         for (i = 0; i < rdev->usec_timeout; i++) {
3785                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3786                                        CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3787                                 if (tmp == levels)
3788                                         break;
3789                                 udelay(1);
3790                         }
3791                 }
3792                 if ((!pi->pcie_dpm_key_disabled) &&
3793                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3794                         levels = ci_get_lowest_enabled_level(rdev,
3795                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3796                         ret = ci_dpm_force_state_pcie(rdev, levels);
3797                         if (ret)
3798                                 return ret;
3799                         for (i = 0; i < rdev->usec_timeout; i++) {
3800                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3801                                        CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3802                                 if (tmp == levels)
3803                                         break;
3804                                 udelay(1);
3805                         }
3806                 }
3807         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3808                 if (!pi->sclk_dpm_key_disabled) {
3809                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3810                         if (smc_result != PPSMC_Result_OK)
3811                                 return -EINVAL;
3812                 }
3813                 if (!pi->mclk_dpm_key_disabled) {
3814                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3815                         if (smc_result != PPSMC_Result_OK)
3816                                 return -EINVAL;
3817                 }
3818                 if (!pi->pcie_dpm_key_disabled) {
3819                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3820                         if (smc_result != PPSMC_Result_OK)
3821                                 return -EINVAL;
3822                 }
3823         }
3824
3825         rdev->pm.dpm.forced_level = level;
3826
3827         return 0;
3828 }
3829
3830 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3831                                        struct ci_mc_reg_table *table)
3832 {
3833         struct ci_power_info *pi = ci_get_pi(rdev);
3834         u8 i, j, k;
3835         u32 temp_reg;
3836
3837         for (i = 0, j = table->last; i < table->last; i++) {
3838                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3839                         return -EINVAL;
3840                 switch(table->mc_reg_address[i].s1 << 2) {
3841                 case MC_SEQ_MISC1:
3842                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
3843                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3844                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3845                         for (k = 0; k < table->num_entries; k++) {
3846                                 table->mc_reg_table_entry[k].mc_data[j] =
3847                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3848                         }
3849                         j++;
3850                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3851                                 return -EINVAL;
3852
3853                         temp_reg = RREG32(MC_PMG_CMD_MRS);
3854                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3855                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3856                         for (k = 0; k < table->num_entries; k++) {
3857                                 table->mc_reg_table_entry[k].mc_data[j] =
3858                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3859                                 if (!pi->mem_gddr5)
3860                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3861                         }
3862                         j++;
3863                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3864                                 return -EINVAL;
3865
3866                         if (!pi->mem_gddr5) {
3867                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3868                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3869                                 for (k = 0; k < table->num_entries; k++) {
3870                                         table->mc_reg_table_entry[k].mc_data[j] =
3871                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3872                                 }
3873                                 j++;
3874                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3875                                         return -EINVAL;
3876                         }
3877                         break;
3878                 case MC_SEQ_RESERVE_M:
3879                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
3880                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3881                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3882                         for (k = 0; k < table->num_entries; k++) {
3883                                 table->mc_reg_table_entry[k].mc_data[j] =
3884                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3885                         }
3886                         j++;
3887                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3888                                 return -EINVAL;
3889                         break;
3890                 default:
3891                         break;
3892                 }
3893
3894         }
3895
3896         table->last = j;
3897
3898         return 0;
3899 }
3900
3901 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3902 {
3903         bool result = true;
3904
3905         switch(in_reg) {
3906         case MC_SEQ_RAS_TIMING >> 2:
3907                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3908                 break;
3909         case MC_SEQ_DLL_STBY >> 2:
3910                 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3911                 break;
3912         case MC_SEQ_G5PDX_CMD0 >> 2:
3913                 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3914                 break;
3915         case MC_SEQ_G5PDX_CMD1 >> 2:
3916                 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3917                 break;
3918         case MC_SEQ_G5PDX_CTRL >> 2:
3919                 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3920                 break;
3921         case MC_SEQ_CAS_TIMING >> 2:
3922                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3923             break;
3924         case MC_SEQ_MISC_TIMING >> 2:
3925                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3926                 break;
3927         case MC_SEQ_MISC_TIMING2 >> 2:
3928                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3929                 break;
3930         case MC_SEQ_PMG_DVS_CMD >> 2:
3931                 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3932                 break;
3933         case MC_SEQ_PMG_DVS_CTL >> 2:
3934                 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3935                 break;
3936         case MC_SEQ_RD_CTL_D0 >> 2:
3937                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3938                 break;
3939         case MC_SEQ_RD_CTL_D1 >> 2:
3940                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3941                 break;
3942         case MC_SEQ_WR_CTL_D0 >> 2:
3943                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3944                 break;
3945         case MC_SEQ_WR_CTL_D1 >> 2:
3946                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3947                 break;
3948         case MC_PMG_CMD_EMRS >> 2:
3949                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3950                 break;
3951         case MC_PMG_CMD_MRS >> 2:
3952                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3953                 break;
3954         case MC_PMG_CMD_MRS1 >> 2:
3955                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3956                 break;
3957         case MC_SEQ_PMG_TIMING >> 2:
3958                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3959                 break;
3960         case MC_PMG_CMD_MRS2 >> 2:
3961                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
3962                 break;
3963         case MC_SEQ_WR_CTL_2 >> 2:
3964                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
3965                 break;
3966         default:
3967                 result = false;
3968                 break;
3969         }
3970
3971         return result;
3972 }
3973
3974 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
3975 {
3976         u8 i, j;
3977
3978         for (i = 0; i < table->last; i++) {
3979                 for (j = 1; j < table->num_entries; j++) {
3980                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3981                             table->mc_reg_table_entry[j].mc_data[i]) {
3982                                 table->valid_flag |= 1 << i;
3983                                 break;
3984                         }
3985                 }
3986         }
3987 }
3988
3989 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
3990 {
3991         u32 i;
3992         u16 address;
3993
3994         for (i = 0; i < table->last; i++) {
3995                 table->mc_reg_address[i].s0 =
3996                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
3997                         address : table->mc_reg_address[i].s1;
3998         }
3999 }
4000
4001 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4002                                       struct ci_mc_reg_table *ci_table)
4003 {
4004         u8 i, j;
4005
4006         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4007                 return -EINVAL;
4008         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4009                 return -EINVAL;
4010
4011         for (i = 0; i < table->last; i++)
4012                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4013
4014         ci_table->last = table->last;
4015
4016         for (i = 0; i < table->num_entries; i++) {
4017                 ci_table->mc_reg_table_entry[i].mclk_max =
4018                         table->mc_reg_table_entry[i].mclk_max;
4019                 for (j = 0; j < table->last; j++)
4020                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4021                                 table->mc_reg_table_entry[i].mc_data[j];
4022         }
4023         ci_table->num_entries = table->num_entries;
4024
4025         return 0;
4026 }
4027
4028 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4029 {
4030         struct ci_power_info *pi = ci_get_pi(rdev);
4031         struct atom_mc_reg_table *table;
4032         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4033         u8 module_index = rv770_get_memory_module_index(rdev);
4034         int ret;
4035
4036         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4037         if (!table)
4038                 return -ENOMEM;
4039
4040         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4041         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4042         WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4043         WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4044         WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4045         WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4046         WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4047         WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4048         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4049         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4050         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4051         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4052         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4053         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4054         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4055         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4056         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4057         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4058         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4059         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4060
4061         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4062         if (ret)
4063                 goto init_mc_done;
4064
4065         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4066         if (ret)
4067                 goto init_mc_done;
4068
4069         ci_set_s0_mc_reg_index(ci_table);
4070
4071         ret = ci_set_mc_special_registers(rdev, ci_table);
4072         if (ret)
4073                 goto init_mc_done;
4074
4075         ci_set_valid_flag(ci_table);
4076
4077 init_mc_done:
4078         kfree(table);
4079
4080         return ret;
4081 }
4082
4083 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4084                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4085 {
4086         struct ci_power_info *pi = ci_get_pi(rdev);
4087         u32 i, j;
4088
4089         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4090                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4091                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4092                                 return -EINVAL;
4093                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4094                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4095                         i++;
4096                 }
4097         }
4098
4099         mc_reg_table->last = (u8)i;
4100
4101         return 0;
4102 }
4103
4104 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4105                                     SMU7_Discrete_MCRegisterSet *data,
4106                                     u32 num_entries, u32 valid_flag)
4107 {
4108         u32 i, j;
4109
4110         for (i = 0, j = 0; j < num_entries; j++) {
4111                 if (valid_flag & (1 << j)) {
4112                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4113                         i++;
4114                 }
4115         }
4116 }
4117
4118 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4119                                                  const u32 memory_clock,
4120                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4121 {
4122         struct ci_power_info *pi = ci_get_pi(rdev);
4123         u32 i = 0;
4124
4125         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4126                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4127                         break;
4128         }
4129
4130         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4131                 --i;
4132
4133         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4134                                 mc_reg_table_data, pi->mc_reg_table.last,
4135                                 pi->mc_reg_table.valid_flag);
4136 }
4137
4138 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4139                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4140 {
4141         struct ci_power_info *pi = ci_get_pi(rdev);
4142         u32 i;
4143
4144         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4145                 ci_convert_mc_reg_table_entry_to_smc(rdev,
4146                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4147                                                      &mc_reg_table->data[i]);
4148 }
4149
4150 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4151 {
4152         struct ci_power_info *pi = ci_get_pi(rdev);
4153         int ret;
4154
4155         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4156
4157         ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4158         if (ret)
4159                 return ret;
4160         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4161
4162         return ci_copy_bytes_to_smc(rdev,
4163                                     pi->mc_reg_table_start,
4164                                     (u8 *)&pi->smc_mc_reg_table,
4165                                     sizeof(SMU7_Discrete_MCRegisters),
4166                                     pi->sram_end);
4167 }
4168
4169 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4170 {
4171         struct ci_power_info *pi = ci_get_pi(rdev);
4172
4173         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4174                 return 0;
4175
4176         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4177
4178         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4179
4180         return ci_copy_bytes_to_smc(rdev,
4181                                     pi->mc_reg_table_start +
4182                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4183                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4184                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4185                                     pi->dpm_table.mclk_table.count,
4186                                     pi->sram_end);
4187 }
4188
4189 static void ci_enable_voltage_control(struct radeon_device *rdev)
4190 {
4191         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4192
4193         tmp |= VOLT_PWRMGT_EN;
4194         WREG32_SMC(GENERAL_PWRMGT, tmp);
4195 }
4196
4197 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4198                                                       struct radeon_ps *radeon_state)
4199 {
4200         struct ci_ps *state = ci_get_ps(radeon_state);
4201         int i;
4202         u16 pcie_speed, max_speed = 0;
4203
4204         for (i = 0; i < state->performance_level_count; i++) {
4205                 pcie_speed = state->performance_levels[i].pcie_gen;
4206                 if (max_speed < pcie_speed)
4207                         max_speed = pcie_speed;
4208         }
4209
4210         return max_speed;
4211 }
4212
4213 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4214 {
4215         u32 speed_cntl = 0;
4216
4217         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4218         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4219
4220         return (u16)speed_cntl;
4221 }
4222
4223 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4224 {
4225         u32 link_width = 0;
4226
4227         link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4228         link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4229
4230         switch (link_width) {
4231         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4232                 return 1;
4233         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4234                 return 2;
4235         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4236                 return 4;
4237         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4238                 return 8;
4239         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4240                 /* not actually supported */
4241                 return 12;
4242         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4243         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4244         default:
4245                 return 16;
4246         }
4247 }
4248
4249 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4250                                                              struct radeon_ps *radeon_new_state,
4251                                                              struct radeon_ps *radeon_current_state)
4252 {
4253         struct ci_power_info *pi = ci_get_pi(rdev);
4254         enum radeon_pcie_gen target_link_speed =
4255                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4256         enum radeon_pcie_gen current_link_speed;
4257
4258         if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4259                 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4260         else
4261                 current_link_speed = pi->force_pcie_gen;
4262
4263         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4264         pi->pspp_notify_required = false;
4265         if (target_link_speed > current_link_speed) {
4266                 switch (target_link_speed) {
4267 #ifdef CONFIG_ACPI
4268                 case RADEON_PCIE_GEN3:
4269                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4270                                 break;
4271                         pi->force_pcie_gen = RADEON_PCIE_GEN2;
4272                         if (current_link_speed == RADEON_PCIE_GEN2)
4273                                 break;
4274                 case RADEON_PCIE_GEN2:
4275                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4276                                 break;
4277 #endif
4278                 default:
4279                         pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4280                         break;
4281                 }
4282         } else {
4283                 if (target_link_speed < current_link_speed)
4284                         pi->pspp_notify_required = true;
4285         }
4286 }
4287
4288 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4289                                                            struct radeon_ps *radeon_new_state,
4290                                                            struct radeon_ps *radeon_current_state)
4291 {
4292         struct ci_power_info *pi = ci_get_pi(rdev);
4293         enum radeon_pcie_gen target_link_speed =
4294                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4295         u8 request;
4296
4297         if (pi->pspp_notify_required) {
4298                 if (target_link_speed == RADEON_PCIE_GEN3)
4299                         request = PCIE_PERF_REQ_PECI_GEN3;
4300                 else if (target_link_speed == RADEON_PCIE_GEN2)
4301                         request = PCIE_PERF_REQ_PECI_GEN2;
4302                 else
4303                         request = PCIE_PERF_REQ_PECI_GEN1;
4304
4305                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4306                     (ci_get_current_pcie_speed(rdev) > 0))
4307                         return;
4308
4309 #ifdef CONFIG_ACPI
4310                 radeon_acpi_pcie_performance_request(rdev, request, false);
4311 #endif
4312         }
4313 }
4314
4315 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4316 {
4317         struct ci_power_info *pi = ci_get_pi(rdev);
4318         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4319                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4320         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4321                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4322         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4323                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4324
4325         if (allowed_sclk_vddc_table == NULL)
4326                 return -EINVAL;
4327         if (allowed_sclk_vddc_table->count < 1)
4328                 return -EINVAL;
4329         if (allowed_mclk_vddc_table == NULL)
4330                 return -EINVAL;
4331         if (allowed_mclk_vddc_table->count < 1)
4332                 return -EINVAL;
4333         if (allowed_mclk_vddci_table == NULL)
4334                 return -EINVAL;
4335         if (allowed_mclk_vddci_table->count < 1)
4336                 return -EINVAL;
4337
4338         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4339         pi->max_vddc_in_pp_table =
4340                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4341
4342         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4343         pi->max_vddci_in_pp_table =
4344                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4345
4346         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4347                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4348         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4349                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4350         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4351                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4352         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4353                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4354
4355         return 0;
4356 }
4357
4358 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4359 {
4360         struct ci_power_info *pi = ci_get_pi(rdev);
4361         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4362         u32 leakage_index;
4363
4364         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4365                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4366                         *vddc = leakage_table->actual_voltage[leakage_index];
4367                         break;
4368                 }
4369         }
4370 }
4371
4372 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4373 {
4374         struct ci_power_info *pi = ci_get_pi(rdev);
4375         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4376         u32 leakage_index;
4377
4378         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4379                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4380                         *vddci = leakage_table->actual_voltage[leakage_index];
4381                         break;
4382                 }
4383         }
4384 }
4385
4386 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4387                                                                       struct radeon_clock_voltage_dependency_table *table)
4388 {
4389         u32 i;
4390
4391         if (table) {
4392                 for (i = 0; i < table->count; i++)
4393                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4394         }
4395 }
4396
4397 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4398                                                                        struct radeon_clock_voltage_dependency_table *table)
4399 {
4400         u32 i;
4401
4402         if (table) {
4403                 for (i = 0; i < table->count; i++)
4404                         ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4405         }
4406 }
4407
4408 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4409                                                                           struct radeon_vce_clock_voltage_dependency_table *table)
4410 {
4411         u32 i;
4412
4413         if (table) {
4414                 for (i = 0; i < table->count; i++)
4415                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4416         }
4417 }
4418
4419 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4420                                                                           struct radeon_uvd_clock_voltage_dependency_table *table)
4421 {
4422         u32 i;
4423
4424         if (table) {
4425                 for (i = 0; i < table->count; i++)
4426                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4427         }
4428 }
4429
4430 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4431                                                                    struct radeon_phase_shedding_limits_table *table)
4432 {
4433         u32 i;
4434
4435         if (table) {
4436                 for (i = 0; i < table->count; i++)
4437                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4438         }
4439 }
4440
4441 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4442                                                             struct radeon_clock_and_voltage_limits *table)
4443 {
4444         if (table) {
4445                 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4446                 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4447         }
4448 }
4449
4450 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4451                                                          struct radeon_cac_leakage_table *table)
4452 {
4453         u32 i;
4454
4455         if (table) {
4456                 for (i = 0; i < table->count; i++)
4457                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4458         }
4459 }
4460
4461 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4462 {
4463
4464         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4465                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4466         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4467                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4468         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4469                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4470         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4471                                                                    &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4472         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4473                                                                       &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4474         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4475                                                                       &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4476         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4477                                                                   &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4478         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4479                                                                   &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4480         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4481                                                                &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4482         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4483                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4484         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4485                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4486         ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4487                                                      &rdev->pm.dpm.dyn_state.cac_leakage_table);
4488
4489 }
4490
4491 static void ci_get_memory_type(struct radeon_device *rdev)
4492 {
4493         struct ci_power_info *pi = ci_get_pi(rdev);
4494         u32 tmp;
4495
4496         tmp = RREG32(MC_SEQ_MISC0);
4497
4498         if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4499             MC_SEQ_MISC0_GDDR5_VALUE)
4500                 pi->mem_gddr5 = true;
4501         else
4502                 pi->mem_gddr5 = false;
4503
4504 }
4505
4506 void ci_update_current_ps(struct radeon_device *rdev,
4507                           struct radeon_ps *rps)
4508 {
4509         struct ci_ps *new_ps = ci_get_ps(rps);
4510         struct ci_power_info *pi = ci_get_pi(rdev);
4511
4512         pi->current_rps = *rps;
4513         pi->current_ps = *new_ps;
4514         pi->current_rps.ps_priv = &pi->current_ps;
4515 }
4516
4517 void ci_update_requested_ps(struct radeon_device *rdev,
4518                             struct radeon_ps *rps)
4519 {
4520         struct ci_ps *new_ps = ci_get_ps(rps);
4521         struct ci_power_info *pi = ci_get_pi(rdev);
4522
4523         pi->requested_rps = *rps;
4524         pi->requested_ps = *new_ps;
4525         pi->requested_rps.ps_priv = &pi->requested_ps;
4526 }
4527
4528 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4529 {
4530         struct ci_power_info *pi = ci_get_pi(rdev);
4531         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4532         struct radeon_ps *new_ps = &requested_ps;
4533
4534         ci_update_requested_ps(rdev, new_ps);
4535
4536         ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4537
4538         return 0;
4539 }
4540
4541 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4542 {
4543         struct ci_power_info *pi = ci_get_pi(rdev);
4544         struct radeon_ps *new_ps = &pi->requested_rps;
4545
4546         ci_update_current_ps(rdev, new_ps);
4547 }
4548
4549
4550 void ci_dpm_setup_asic(struct radeon_device *rdev)
4551 {
4552         ci_read_clock_registers(rdev);
4553         ci_get_memory_type(rdev);
4554         ci_enable_acpi_power_management(rdev);
4555         ci_init_sclk_t(rdev);
4556 }
4557
4558 int ci_dpm_enable(struct radeon_device *rdev)
4559 {
4560         struct ci_power_info *pi = ci_get_pi(rdev);
4561         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4562         int ret;
4563
4564         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4565                              RADEON_CG_BLOCK_MC |
4566                              RADEON_CG_BLOCK_SDMA |
4567                              RADEON_CG_BLOCK_BIF |
4568                              RADEON_CG_BLOCK_UVD |
4569                              RADEON_CG_BLOCK_HDP), false);
4570
4571         if (ci_is_smc_running(rdev))
4572                 return -EINVAL;
4573         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4574                 ci_enable_voltage_control(rdev);
4575                 ret = ci_construct_voltage_tables(rdev);
4576                 if (ret) {
4577                         DRM_ERROR("ci_construct_voltage_tables failed\n");
4578                         return ret;
4579                 }
4580         }
4581         if (pi->caps_dynamic_ac_timing) {
4582                 ret = ci_initialize_mc_reg_table(rdev);
4583                 if (ret)
4584                         pi->caps_dynamic_ac_timing = false;
4585         }
4586         if (pi->dynamic_ss)
4587                 ci_enable_spread_spectrum(rdev, true);
4588         if (pi->thermal_protection)
4589                 ci_enable_thermal_protection(rdev, true);
4590         ci_program_sstp(rdev);
4591         ci_enable_display_gap(rdev);
4592         ci_program_vc(rdev);
4593         ret = ci_upload_firmware(rdev);
4594         if (ret) {
4595                 DRM_ERROR("ci_upload_firmware failed\n");
4596                 return ret;
4597         }
4598         ret = ci_process_firmware_header(rdev);
4599         if (ret) {
4600                 DRM_ERROR("ci_process_firmware_header failed\n");
4601                 return ret;
4602         }
4603         ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4604         if (ret) {
4605                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4606                 return ret;
4607         }
4608         ret = ci_init_smc_table(rdev);
4609         if (ret) {
4610                 DRM_ERROR("ci_init_smc_table failed\n");
4611                 return ret;
4612         }
4613         ret = ci_init_arb_table_index(rdev);
4614         if (ret) {
4615                 DRM_ERROR("ci_init_arb_table_index failed\n");
4616                 return ret;
4617         }
4618         if (pi->caps_dynamic_ac_timing) {
4619                 ret = ci_populate_initial_mc_reg_table(rdev);
4620                 if (ret) {
4621                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4622                         return ret;
4623                 }
4624         }
4625         ret = ci_populate_pm_base(rdev);
4626         if (ret) {
4627                 DRM_ERROR("ci_populate_pm_base failed\n");
4628                 return ret;
4629         }
4630         ci_dpm_start_smc(rdev);
4631         ci_enable_vr_hot_gpio_interrupt(rdev);
4632         ret = ci_notify_smc_display_change(rdev, false);
4633         if (ret) {
4634                 DRM_ERROR("ci_notify_smc_display_change failed\n");
4635                 return ret;
4636         }
4637         ci_enable_sclk_control(rdev, true);
4638         ret = ci_enable_ulv(rdev, true);
4639         if (ret) {
4640                 DRM_ERROR("ci_enable_ulv failed\n");
4641                 return ret;
4642         }
4643         ret = ci_enable_ds_master_switch(rdev, true);
4644         if (ret) {
4645                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4646                 return ret;
4647         }
4648         ret = ci_start_dpm(rdev);
4649         if (ret) {
4650                 DRM_ERROR("ci_start_dpm failed\n");
4651                 return ret;
4652         }
4653         ret = ci_enable_didt(rdev, true);
4654         if (ret) {
4655                 DRM_ERROR("ci_enable_didt failed\n");
4656                 return ret;
4657         }
4658         ret = ci_enable_smc_cac(rdev, true);
4659         if (ret) {
4660                 DRM_ERROR("ci_enable_smc_cac failed\n");
4661                 return ret;
4662         }
4663         ret = ci_enable_power_containment(rdev, true);
4664         if (ret) {
4665                 DRM_ERROR("ci_enable_power_containment failed\n");
4666                 return ret;
4667         }
4668         if (rdev->irq.installed &&
4669             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4670 #if 0
4671                 PPSMC_Result result;
4672 #endif
4673                 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4674                 if (ret) {
4675                         DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4676                         return ret;
4677                 }
4678                 rdev->irq.dpm_thermal = true;
4679                 radeon_irq_set(rdev);
4680 #if 0
4681                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4682
4683                 if (result != PPSMC_Result_OK)
4684                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4685 #endif
4686         }
4687
4688         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4689
4690         ci_dpm_powergate_uvd(rdev, true);
4691
4692         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4693                              RADEON_CG_BLOCK_MC |
4694                              RADEON_CG_BLOCK_SDMA |
4695                              RADEON_CG_BLOCK_BIF |
4696                              RADEON_CG_BLOCK_UVD |
4697                              RADEON_CG_BLOCK_HDP), true);
4698
4699         ci_update_current_ps(rdev, boot_ps);
4700
4701         return 0;
4702 }
4703
4704 void ci_dpm_disable(struct radeon_device *rdev)
4705 {
4706         struct ci_power_info *pi = ci_get_pi(rdev);
4707         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4708
4709         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4710                              RADEON_CG_BLOCK_MC |
4711                              RADEON_CG_BLOCK_SDMA |
4712                              RADEON_CG_BLOCK_UVD |
4713                              RADEON_CG_BLOCK_HDP), false);
4714
4715         ci_dpm_powergate_uvd(rdev, false);
4716
4717         if (!ci_is_smc_running(rdev))
4718                 return;
4719
4720         if (pi->thermal_protection)
4721                 ci_enable_thermal_protection(rdev, false);
4722         ci_enable_power_containment(rdev, false);
4723         ci_enable_smc_cac(rdev, false);
4724         ci_enable_didt(rdev, false);
4725         ci_enable_spread_spectrum(rdev, false);
4726         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4727         ci_stop_dpm(rdev);
4728         ci_enable_ds_master_switch(rdev, true);
4729         ci_enable_ulv(rdev, false);
4730         ci_clear_vc(rdev);
4731         ci_reset_to_default(rdev);
4732         ci_dpm_stop_smc(rdev);
4733         ci_force_switch_to_arb_f0(rdev);
4734
4735         ci_update_current_ps(rdev, boot_ps);
4736 }
4737
4738 int ci_dpm_set_power_state(struct radeon_device *rdev)
4739 {
4740         struct ci_power_info *pi = ci_get_pi(rdev);
4741         struct radeon_ps *new_ps = &pi->requested_rps;
4742         struct radeon_ps *old_ps = &pi->current_rps;
4743         int ret;
4744
4745         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4746                              RADEON_CG_BLOCK_MC |
4747                              RADEON_CG_BLOCK_SDMA |
4748                              RADEON_CG_BLOCK_BIF |
4749                              RADEON_CG_BLOCK_UVD |
4750                              RADEON_CG_BLOCK_HDP), false);
4751
4752         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4753         if (pi->pcie_performance_request)
4754                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4755         ret = ci_freeze_sclk_mclk_dpm(rdev);
4756         if (ret) {
4757                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4758                 return ret;
4759         }
4760         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4761         if (ret) {
4762                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4763                 return ret;
4764         }
4765         ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4766         if (ret) {
4767                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4768                 return ret;
4769         }
4770 #if 0
4771         ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4772         if (ret) {
4773                 DRM_ERROR("ci_update_vce_dpm failed\n");
4774                 return ret;
4775         }
4776 #endif
4777         ret = ci_update_sclk_t(rdev);
4778         if (ret) {
4779                 DRM_ERROR("ci_update_sclk_t failed\n");
4780                 return ret;
4781         }
4782         if (pi->caps_dynamic_ac_timing) {
4783                 ret = ci_update_and_upload_mc_reg_table(rdev);
4784                 if (ret) {
4785                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4786                         return ret;
4787                 }
4788         }
4789         ret = ci_program_memory_timing_parameters(rdev);
4790         if (ret) {
4791                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4792                 return ret;
4793         }
4794         ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4795         if (ret) {
4796                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4797                 return ret;
4798         }
4799         ret = ci_upload_dpm_level_enable_mask(rdev);
4800         if (ret) {
4801                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4802                 return ret;
4803         }
4804         if (pi->pcie_performance_request)
4805                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4806
4807         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4808                              RADEON_CG_BLOCK_MC |
4809                              RADEON_CG_BLOCK_SDMA |
4810                              RADEON_CG_BLOCK_BIF |
4811                              RADEON_CG_BLOCK_UVD |
4812                              RADEON_CG_BLOCK_HDP), true);
4813
4814         return 0;
4815 }
4816
4817 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4818 {
4819         return ci_power_control_set_level(rdev);
4820 }
4821
4822 void ci_dpm_reset_asic(struct radeon_device *rdev)
4823 {
4824         ci_set_boot_state(rdev);
4825 }
4826
4827 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4828 {
4829         ci_program_display_gap(rdev);
4830 }
4831
4832 union power_info {
4833         struct _ATOM_POWERPLAY_INFO info;
4834         struct _ATOM_POWERPLAY_INFO_V2 info_2;
4835         struct _ATOM_POWERPLAY_INFO_V3 info_3;
4836         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4837         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4838         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4839 };
4840
4841 union pplib_clock_info {
4842         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4843         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4844         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4845         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4846         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4847         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4848 };
4849
4850 union pplib_power_state {
4851         struct _ATOM_PPLIB_STATE v1;
4852         struct _ATOM_PPLIB_STATE_V2 v2;
4853 };
4854
4855 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4856                                           struct radeon_ps *rps,
4857                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4858                                           u8 table_rev)
4859 {
4860         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4861         rps->class = le16_to_cpu(non_clock_info->usClassification);
4862         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4863
4864         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4865                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4866                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4867         } else {
4868                 rps->vclk = 0;
4869                 rps->dclk = 0;
4870         }
4871
4872         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4873                 rdev->pm.dpm.boot_ps = rps;
4874         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4875                 rdev->pm.dpm.uvd_ps = rps;
4876 }
4877
4878 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4879                                       struct radeon_ps *rps, int index,
4880                                       union pplib_clock_info *clock_info)
4881 {
4882         struct ci_power_info *pi = ci_get_pi(rdev);
4883         struct ci_ps *ps = ci_get_ps(rps);
4884         struct ci_pl *pl = &ps->performance_levels[index];
4885
4886         ps->performance_level_count = index + 1;
4887
4888         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4889         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4890         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4891         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4892
4893         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4894                                                  pi->sys_pcie_mask,
4895                                                  pi->vbios_boot_state.pcie_gen_bootup_value,
4896                                                  clock_info->ci.ucPCIEGen);
4897         pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4898                                                    pi->vbios_boot_state.pcie_lane_bootup_value,
4899                                                    le16_to_cpu(clock_info->ci.usPCIELane));
4900
4901         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4902                 pi->acpi_pcie_gen = pl->pcie_gen;
4903         }
4904
4905         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4906                 pi->ulv.supported = true;
4907                 pi->ulv.pl = *pl;
4908                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4909         }
4910
4911         /* patch up boot state */
4912         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4913                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4914                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4915                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4916                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4917         }
4918
4919         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4920         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4921                 pi->use_pcie_powersaving_levels = true;
4922                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4923                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
4924                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4925                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
4926                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4927                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
4928                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4929                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
4930                 break;
4931         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4932                 pi->use_pcie_performance_levels = true;
4933                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4934                         pi->pcie_gen_performance.max = pl->pcie_gen;
4935                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4936                         pi->pcie_gen_performance.min = pl->pcie_gen;
4937                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4938                         pi->pcie_lane_performance.max = pl->pcie_lane;
4939                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4940                         pi->pcie_lane_performance.min = pl->pcie_lane;
4941                 break;
4942         default:
4943                 break;
4944         }
4945 }
4946
4947 static int ci_parse_power_table(struct radeon_device *rdev)
4948 {
4949         struct radeon_mode_info *mode_info = &rdev->mode_info;
4950         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4951         union pplib_power_state *power_state;
4952         int i, j, k, non_clock_array_index, clock_array_index;
4953         union pplib_clock_info *clock_info;
4954         struct _StateArray *state_array;
4955         struct _ClockInfoArray *clock_info_array;
4956         struct _NonClockInfoArray *non_clock_info_array;
4957         union power_info *power_info;
4958         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4959         u16 data_offset;
4960         u8 frev, crev;
4961         u8 *power_state_offset;
4962         struct ci_ps *ps;
4963
4964         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4965                                    &frev, &crev, &data_offset))
4966                 return -EINVAL;
4967         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4968
4969         state_array = (struct _StateArray *)
4970                 (mode_info->atom_context->bios + data_offset +
4971                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
4972         clock_info_array = (struct _ClockInfoArray *)
4973                 (mode_info->atom_context->bios + data_offset +
4974                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4975         non_clock_info_array = (struct _NonClockInfoArray *)
4976                 (mode_info->atom_context->bios + data_offset +
4977                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4978
4979         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4980                                   state_array->ucNumEntries, GFP_KERNEL);
4981         if (!rdev->pm.dpm.ps)
4982                 return -ENOMEM;
4983         power_state_offset = (u8 *)state_array->states;
4984         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
4985         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
4986         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
4987         for (i = 0; i < state_array->ucNumEntries; i++) {
4988                 u8 *idx;
4989                 power_state = (union pplib_power_state *)power_state_offset;
4990                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
4991                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
4992                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
4993                 if (!rdev->pm.power_state[i].clock_info)
4994                         return -EINVAL;
4995                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
4996                 if (ps == NULL) {
4997                         kfree(rdev->pm.dpm.ps);
4998                         return -ENOMEM;
4999                 }
5000                 rdev->pm.dpm.ps[i].ps_priv = ps;
5001                 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5002                                               non_clock_info,
5003                                               non_clock_info_array->ucEntrySize);
5004                 k = 0;
5005                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5006                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5007                         clock_array_index = idx[j];
5008                         if (clock_array_index >= clock_info_array->ucNumEntries)
5009                                 continue;
5010                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5011                                 break;
5012                         clock_info = (union pplib_clock_info *)
5013                                 ((u8 *)&clock_info_array->clockInfo[0] +
5014                                  (clock_array_index * clock_info_array->ucEntrySize));
5015                         ci_parse_pplib_clock_info(rdev,
5016                                                   &rdev->pm.dpm.ps[i], k,
5017                                                   clock_info);
5018                         k++;
5019                 }
5020                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5021         }
5022         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5023         return 0;
5024 }
5025
5026 int ci_get_vbios_boot_values(struct radeon_device *rdev,
5027                              struct ci_vbios_boot_state *boot_state)
5028 {
5029         struct radeon_mode_info *mode_info = &rdev->mode_info;
5030         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5031         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5032         u8 frev, crev;
5033         u16 data_offset;
5034
5035         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5036                                    &frev, &crev, &data_offset)) {
5037                 firmware_info =
5038                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5039                                                     data_offset);
5040                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5041                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5042                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5043                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5044                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5045                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5046                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5047
5048                 return 0;
5049         }
5050         return -EINVAL;
5051 }
5052
5053 void ci_dpm_fini(struct radeon_device *rdev)
5054 {
5055         int i;
5056
5057         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5058                 kfree(rdev->pm.dpm.ps[i].ps_priv);
5059         }
5060         kfree(rdev->pm.dpm.ps);
5061         kfree(rdev->pm.dpm.priv);
5062         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5063         r600_free_extended_power_table(rdev);
5064 }
5065
5066 int ci_dpm_init(struct radeon_device *rdev)
5067 {
5068         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5069         u16 data_offset, size;
5070         u8 frev, crev;
5071         struct ci_power_info *pi;
5072         int ret;
5073         u32 mask;
5074
5075         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5076         if (pi == NULL)
5077                 return -ENOMEM;
5078         rdev->pm.dpm.priv = pi;
5079
5080         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5081         if (ret)
5082                 pi->sys_pcie_mask = 0;
5083         else
5084                 pi->sys_pcie_mask = mask;
5085         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5086
5087         pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5088         pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5089         pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5090         pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5091
5092         pi->pcie_lane_performance.max = 0;
5093         pi->pcie_lane_performance.min = 16;
5094         pi->pcie_lane_powersaving.max = 0;
5095         pi->pcie_lane_powersaving.min = 16;
5096
5097         ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5098         if (ret) {
5099                 ci_dpm_fini(rdev);
5100                 return ret;
5101         }
5102         ret = ci_parse_power_table(rdev);
5103         if (ret) {
5104                 ci_dpm_fini(rdev);
5105                 return ret;
5106         }
5107         ret = r600_parse_extended_power_table(rdev);
5108         if (ret) {
5109                 ci_dpm_fini(rdev);
5110                 return ret;
5111         }
5112
5113         pi->dll_default_on = false;
5114         pi->sram_end = SMC_RAM_END;
5115
5116         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5117         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5118         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5119         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5120         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5121         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5122         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5123         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5124
5125         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5126
5127         pi->sclk_dpm_key_disabled = 0;
5128         pi->mclk_dpm_key_disabled = 0;
5129         pi->pcie_dpm_key_disabled = 0;
5130
5131         pi->caps_sclk_ds = true;
5132
5133         pi->mclk_strobe_mode_threshold = 40000;
5134         pi->mclk_stutter_mode_threshold = 40000;
5135         pi->mclk_edc_enable_threshold = 40000;
5136         pi->mclk_edc_wr_enable_threshold = 40000;
5137
5138         ci_initialize_powertune_defaults(rdev);
5139
5140         pi->caps_fps = false;
5141
5142         pi->caps_sclk_throttle_low_notification = false;
5143
5144         pi->caps_uvd_dpm = true;
5145
5146         ci_get_leakage_voltages(rdev);
5147         ci_patch_dependency_tables_with_leakage(rdev);
5148         ci_set_private_data_variables_based_on_pptable(rdev);
5149
5150         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5151                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5152         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5153                 ci_dpm_fini(rdev);
5154                 return -ENOMEM;
5155         }
5156         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5157         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5158         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5159         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5160         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5161         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5162         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5163         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5164         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5165
5166         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5167         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5168         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5169
5170         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5171         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5172         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5173         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5174
5175         if (rdev->family == CHIP_HAWAII) {
5176                 pi->thermal_temp_setting.temperature_low = 94500;
5177                 pi->thermal_temp_setting.temperature_high = 95000;
5178                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5179         } else {
5180                 pi->thermal_temp_setting.temperature_low = 99500;
5181                 pi->thermal_temp_setting.temperature_high = 100000;
5182                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5183         }
5184
5185         pi->uvd_enabled = false;
5186
5187         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5188         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5189         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5190         if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5191                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5192         else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5193                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5194
5195         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5196                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5197                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5198                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5199                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5200                 else
5201                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5202         }
5203
5204         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5205                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5206                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5207                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5208                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5209                 else
5210                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5211         }
5212
5213         pi->vddc_phase_shed_control = true;
5214
5215 #if defined(CONFIG_ACPI)
5216         pi->pcie_performance_request =
5217                 radeon_acpi_is_pcie_performance_request_supported(rdev);
5218 #else
5219         pi->pcie_performance_request = false;
5220 #endif
5221
5222         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5223                                    &frev, &crev, &data_offset)) {
5224                 pi->caps_sclk_ss_support = true;
5225                 pi->caps_mclk_ss_support = true;
5226                 pi->dynamic_ss = true;
5227         } else {
5228                 pi->caps_sclk_ss_support = false;
5229                 pi->caps_mclk_ss_support = false;
5230                 pi->dynamic_ss = true;
5231         }
5232
5233         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5234                 pi->thermal_protection = true;
5235         else
5236                 pi->thermal_protection = false;
5237
5238         pi->caps_dynamic_ac_timing = true;
5239
5240         pi->uvd_power_gated = false;
5241
5242         /* make sure dc limits are valid */
5243         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5244             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5245                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5246                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5247
5248         return 0;
5249 }
5250
5251 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5252                                                     struct seq_file *m)
5253 {
5254         u32 sclk = ci_get_average_sclk_freq(rdev);
5255         u32 mclk = ci_get_average_mclk_freq(rdev);
5256
5257         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
5258                    sclk, mclk);
5259 }
5260
5261 void ci_dpm_print_power_state(struct radeon_device *rdev,
5262                               struct radeon_ps *rps)
5263 {
5264         struct ci_ps *ps = ci_get_ps(rps);
5265         struct ci_pl *pl;
5266         int i;
5267
5268         r600_dpm_print_class_info(rps->class, rps->class2);
5269         r600_dpm_print_cap_info(rps->caps);
5270         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5271         for (i = 0; i < ps->performance_level_count; i++) {
5272                 pl = &ps->performance_levels[i];
5273                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5274                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5275         }
5276         r600_dpm_print_ps_status(rdev, rps);
5277 }
5278
5279 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5280 {
5281         struct ci_power_info *pi = ci_get_pi(rdev);
5282         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5283
5284         if (low)
5285                 return requested_state->performance_levels[0].sclk;
5286         else
5287                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5288 }
5289
5290 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5291 {
5292         struct ci_power_info *pi = ci_get_pi(rdev);
5293         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5294
5295         if (low)
5296                 return requested_state->performance_levels[0].mclk;
5297         else
5298                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5299 }