2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include "radeon_reg.h"
33 #include "radeon_asic.h"
37 #include "r420_reg_safe.h"
39 void r420_pm_init_profile(struct radeon_device *rdev)
42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
52 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
54 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
57 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
60 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
62 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
65 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
68 static void r420_set_reg_safe(struct radeon_device *rdev)
70 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
71 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
74 void r420_pipes_init(struct radeon_device *rdev)
77 unsigned gb_pipe_select;
80 /* GA_ENHANCE workaround TCL deadlock issue */
81 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
83 /* add idle wait as per freedesktop.org bug 24041 */
84 if (r100_gui_wait_for_idle(rdev)) {
85 printk(KERN_WARNING "Failed to wait GUI idle while "
86 "programming pipes. Bad things might happen.\n");
88 /* get max number of pipes */
89 gb_pipe_select = RREG32(0x402C);
90 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
92 /* SE chips have 1 pipe */
93 if ((rdev->pdev->device == 0x5e4c) ||
94 (rdev->pdev->device == 0x5e4f))
97 rdev->num_gb_pipes = num_pipes;
101 /* force to 1 pipe */
116 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
117 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
118 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
119 WREG32(R300_GB_TILE_CONFIG, tmp);
120 if (r100_gui_wait_for_idle(rdev)) {
121 printk(KERN_WARNING "Failed to wait GUI idle while "
122 "programming pipes. Bad things might happen.\n");
125 tmp = RREG32(R300_DST_PIPE_CONFIG);
126 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
128 WREG32(R300_RB2D_DSTCACHE_MODE,
129 RREG32(R300_RB2D_DSTCACHE_MODE) |
130 R300_DC_AUTOFLUSH_ENABLE |
131 R300_DC_DC_DISABLE_IGNORE_PE);
133 if (r100_gui_wait_for_idle(rdev)) {
134 printk(KERN_WARNING "Failed to wait GUI idle while "
135 "programming pipes. Bad things might happen.\n");
138 if (rdev->family == CHIP_RV530) {
139 tmp = RREG32(RV530_GB_PIPE_SELECT2);
141 rdev->num_z_pipes = 2;
143 rdev->num_z_pipes = 1;
145 rdev->num_z_pipes = 1;
147 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
148 rdev->num_gb_pipes, rdev->num_z_pipes);
151 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
155 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
156 r = RREG32(R_0001FC_MC_IND_DATA);
160 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
162 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
163 S_0001F8_MC_IND_WR_EN(1));
164 WREG32(R_0001FC_MC_IND_DATA, v);
167 static void r420_debugfs(struct radeon_device *rdev)
169 if (r100_debugfs_rbbm_init(rdev)) {
170 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
172 if (r420_debugfs_pipes_info_init(rdev)) {
173 DRM_ERROR("Failed to register debugfs file for pipes !\n");
177 static void r420_clock_resume(struct radeon_device *rdev)
181 if (radeon_dynclks != -1 && radeon_dynclks)
182 radeon_atom_set_clock_gating(rdev, 1);
183 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
184 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
185 if (rdev->family == CHIP_R420)
186 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
187 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
190 static void r420_cp_errata_init(struct radeon_device *rdev)
192 /* RV410 and R420 can lock up if CP DMA to host memory happens
193 * while the 2D engine is busy.
195 * The proper workaround is to queue a RESYNC at the beginning
196 * of the CP init, apparently.
198 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
199 radeon_ring_lock(rdev, 8);
200 radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
201 radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
202 radeon_ring_write(rdev, 0xDEADBEEF);
203 radeon_ring_unlock_commit(rdev);
206 static void r420_cp_errata_fini(struct radeon_device *rdev)
208 /* Catch the RESYNC we dispatched all the way back,
209 * at the very beginning of the CP init.
211 radeon_ring_lock(rdev, 8);
212 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
213 radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
214 radeon_ring_unlock_commit(rdev);
215 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
218 static int r420_startup(struct radeon_device *rdev)
222 /* set common regs */
223 r100_set_common_regs(rdev);
225 r300_mc_program(rdev);
227 r420_clock_resume(rdev);
228 /* Initialize GART (initialize after TTM so we can allocate
229 * memory through TTM but finalize after TTM) */
230 if (rdev->flags & RADEON_IS_PCIE) {
231 r = rv370_pcie_gart_enable(rdev);
235 if (rdev->flags & RADEON_IS_PCI) {
236 r = r100_pci_gart_enable(rdev);
240 r420_pipes_init(rdev);
243 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
245 r = r100_cp_init(rdev, 1024 * 1024);
247 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
250 r420_cp_errata_init(rdev);
251 r = r100_wb_init(rdev);
253 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
255 r = r100_ib_init(rdev);
257 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
263 int r420_resume(struct radeon_device *rdev)
265 /* Make sur GART are not working */
266 if (rdev->flags & RADEON_IS_PCIE)
267 rv370_pcie_gart_disable(rdev);
268 if (rdev->flags & RADEON_IS_PCI)
269 r100_pci_gart_disable(rdev);
270 /* Resume clock before doing reset */
271 r420_clock_resume(rdev);
272 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
273 if (radeon_asic_reset(rdev)) {
274 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
275 RREG32(R_000E40_RBBM_STATUS),
276 RREG32(R_0007C0_CP_STAT));
278 /* check if cards are posted or not */
279 if (rdev->is_atom_bios) {
280 atom_asic_init(rdev->mode_info.atom_context);
282 radeon_combios_asic_init(rdev->ddev);
284 /* Resume clock after posting */
285 r420_clock_resume(rdev);
286 /* Initialize surface registers */
287 radeon_surface_init(rdev);
288 return r420_startup(rdev);
291 int r420_suspend(struct radeon_device *rdev)
293 r420_cp_errata_fini(rdev);
294 r100_cp_disable(rdev);
295 r100_wb_disable(rdev);
296 r100_irq_disable(rdev);
297 if (rdev->flags & RADEON_IS_PCIE)
298 rv370_pcie_gart_disable(rdev);
299 if (rdev->flags & RADEON_IS_PCI)
300 r100_pci_gart_disable(rdev);
304 void r420_fini(struct radeon_device *rdev)
309 radeon_gem_fini(rdev);
310 if (rdev->flags & RADEON_IS_PCIE)
311 rv370_pcie_gart_fini(rdev);
312 if (rdev->flags & RADEON_IS_PCI)
313 r100_pci_gart_fini(rdev);
314 radeon_agp_fini(rdev);
315 radeon_irq_kms_fini(rdev);
316 radeon_fence_driver_fini(rdev);
317 radeon_bo_fini(rdev);
318 if (rdev->is_atom_bios) {
319 radeon_atombios_fini(rdev);
321 radeon_combios_fini(rdev);
327 int r420_init(struct radeon_device *rdev)
331 /* Initialize scratch registers */
332 radeon_scratch_init(rdev);
333 /* Initialize surface registers */
334 radeon_surface_init(rdev);
335 /* TODO: disable VGA need to use VGA request */
337 if (!radeon_get_bios(rdev)) {
338 if (ASIC_IS_AVIVO(rdev))
341 if (rdev->is_atom_bios) {
342 r = radeon_atombios_init(rdev);
347 r = radeon_combios_init(rdev);
352 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
353 if (radeon_asic_reset(rdev)) {
355 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
356 RREG32(R_000E40_RBBM_STATUS),
357 RREG32(R_0007C0_CP_STAT));
359 /* check if cards are posted or not */
360 if (radeon_boot_test_post_card(rdev) == false)
363 /* Initialize clocks */
364 radeon_get_clock_info(rdev->ddev);
366 if (rdev->flags & RADEON_IS_AGP) {
367 r = radeon_agp_init(rdev);
369 radeon_agp_disable(rdev);
372 /* initialize memory controller */
376 r = radeon_fence_driver_init(rdev);
380 r = radeon_irq_kms_init(rdev);
385 r = radeon_bo_init(rdev);
389 if (rdev->family == CHIP_R420)
390 r100_enable_bm(rdev);
392 if (rdev->flags & RADEON_IS_PCIE) {
393 r = rv370_pcie_gart_init(rdev);
397 if (rdev->flags & RADEON_IS_PCI) {
398 r = r100_pci_gart_init(rdev);
402 r420_set_reg_safe(rdev);
403 rdev->accel_working = true;
404 r = r420_startup(rdev);
406 /* Somethings want wront with the accel init stop accel */
407 dev_err(rdev->dev, "Disabling GPU acceleration\n");
411 radeon_irq_kms_fini(rdev);
412 if (rdev->flags & RADEON_IS_PCIE)
413 rv370_pcie_gart_fini(rdev);
414 if (rdev->flags & RADEON_IS_PCI)
415 r100_pci_gart_fini(rdev);
416 radeon_agp_fini(rdev);
417 rdev->accel_working = false;
425 #if defined(CONFIG_DEBUG_FS)
426 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
428 struct drm_info_node *node = (struct drm_info_node *) m->private;
429 struct drm_device *dev = node->minor->dev;
430 struct radeon_device *rdev = dev->dev_private;
433 tmp = RREG32(R400_GB_PIPE_SELECT);
434 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
435 tmp = RREG32(R300_GB_TILE_CONFIG);
436 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
437 tmp = RREG32(R300_DST_PIPE_CONFIG);
438 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
442 static struct drm_info_list r420_pipes_info_list[] = {
443 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
447 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
449 #if defined(CONFIG_DEBUG_FS)
450 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);