2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
91 extern int radeon_new_pll;
92 extern int radeon_dynpm;
93 extern int radeon_audio;
94 extern int radeon_disp_priority;
95 extern int radeon_hw_i2c;
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
102 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103 /* RADEON_IB_POOL_SIZE must be a power of 2 */
104 #define RADEON_IB_POOL_SIZE 16
105 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
106 #define RADEONFB_CONN_LIMIT 4
107 #define RADEON_BIOS_NUM_SCRATCH 8
110 * Errata workarounds.
112 enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
119 struct radeon_device;
125 #define ATRM_BIOS_PAGE 4096
127 #if defined(CONFIG_VGA_SWITCHEROO)
128 bool radeon_atrm_supported(struct pci_dev *pdev);
129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
131 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
140 bool radeon_get_bios(struct radeon_device *rdev);
146 struct radeon_dummy_page {
150 int radeon_dummy_page_init(struct radeon_device *rdev);
151 void radeon_dummy_page_fini(struct radeon_device *rdev);
157 struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll dcpll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166 uint32_t default_dispclk;
173 int radeon_pm_init(struct radeon_device *rdev);
174 void radeon_pm_fini(struct radeon_device *rdev);
175 void radeon_pm_compute_clocks(struct radeon_device *rdev);
176 void radeon_combios_get_power_modes(struct radeon_device *rdev);
177 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
178 bool radeon_pm_in_vbl(struct radeon_device *rdev);
179 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
180 void radeon_sync_with_vblank(struct radeon_device *rdev);
185 struct radeon_fence_driver {
186 uint32_t scratch_reg;
189 unsigned long last_jiffies;
190 unsigned long last_timeout;
191 wait_queue_head_t queue;
193 struct list_head created;
194 struct list_head emited;
195 struct list_head signaled;
199 struct radeon_fence {
200 struct radeon_device *rdev;
202 struct list_head list;
203 /* protected by radeon_fence.lock */
209 int radeon_fence_driver_init(struct radeon_device *rdev);
210 void radeon_fence_driver_fini(struct radeon_device *rdev);
211 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
212 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
213 void radeon_fence_process(struct radeon_device *rdev);
214 bool radeon_fence_signaled(struct radeon_fence *fence);
215 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
216 int radeon_fence_wait_next(struct radeon_device *rdev);
217 int radeon_fence_wait_last(struct radeon_device *rdev);
218 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
219 void radeon_fence_unref(struct radeon_fence **fence);
224 struct radeon_surface_reg {
225 struct radeon_bo *bo;
228 #define RADEON_GEM_MAX_SURFACES 8
234 struct ttm_bo_global_ref bo_global_ref;
235 struct ttm_global_reference mem_global_ref;
236 struct ttm_bo_device bdev;
237 bool mem_global_referenced;
242 /* Protected by gem.mutex */
243 struct list_head list;
244 /* Protected by tbo.reserved */
246 struct ttm_placement placement;
247 struct ttm_buffer_object tbo;
248 struct ttm_bo_kmap_obj kmap;
254 /* Constant after initialization */
255 struct radeon_device *rdev;
256 struct drm_gem_object *gobj;
259 struct radeon_bo_list {
260 struct list_head list;
261 struct radeon_bo *bo;
273 struct list_head objects;
276 int radeon_gem_init(struct radeon_device *rdev);
277 void radeon_gem_fini(struct radeon_device *rdev);
278 int radeon_gem_object_create(struct radeon_device *rdev, int size,
279 int alignment, int initial_domain,
280 bool discardable, bool kernel,
281 struct drm_gem_object **obj);
282 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
284 void radeon_gem_object_unpin(struct drm_gem_object *obj);
288 * GART structures, functions & helpers
292 struct radeon_gart_table_ram {
293 volatile uint32_t *ptr;
296 struct radeon_gart_table_vram {
297 struct radeon_bo *robj;
298 volatile uint32_t *ptr;
301 union radeon_gart_table {
302 struct radeon_gart_table_ram ram;
303 struct radeon_gart_table_vram vram;
306 #define RADEON_GPU_PAGE_SIZE 4096
307 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
310 dma_addr_t table_addr;
311 unsigned num_gpu_pages;
312 unsigned num_cpu_pages;
314 union radeon_gart_table table;
316 dma_addr_t *pages_addr;
320 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
321 void radeon_gart_table_ram_free(struct radeon_device *rdev);
322 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
323 void radeon_gart_table_vram_free(struct radeon_device *rdev);
324 int radeon_gart_init(struct radeon_device *rdev);
325 void radeon_gart_fini(struct radeon_device *rdev);
326 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
328 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
329 int pages, struct page **pagelist);
333 * GPU MC structures, functions & helpers
336 resource_size_t aper_size;
337 resource_size_t aper_base;
338 resource_size_t agp_base;
339 /* for some chips with <= 32MB we need to lie
340 * about vram size near mc fb location */
342 u64 visible_vram_size;
352 bool igp_sideport_enabled;
355 bool radeon_combios_sideport_present(struct radeon_device *rdev);
356 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
359 * GPU scratch registers structures, functions & helpers
361 struct radeon_scratch {
367 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
368 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
377 /* FIXME: use a define max crtc rather than hardcode it */
378 bool crtc_vblank_int[6];
379 wait_queue_head_t vblank_queue;
380 /* FIXME: use defines for max hpd/dacs */
384 wait_queue_head_t idle_queue;
385 /* FIXME: use defines for max HDMI blocks */
391 int radeon_irq_kms_init(struct radeon_device *rdev);
392 void radeon_irq_kms_fini(struct radeon_device *rdev);
393 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
394 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
400 struct list_head list;
403 struct radeon_fence *fence;
411 * mutex protects scheduled_ibs, ready, alloc_bm
413 struct radeon_ib_pool {
415 struct radeon_bo *robj;
416 struct list_head bogus_ib;
417 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
423 struct radeon_bo *ring_obj;
424 volatile uint32_t *ring;
429 unsigned ring_free_dw;
442 struct radeon_bo *ring_obj;
443 volatile uint32_t *ring;
456 struct radeon_bo *shader_obj;
458 u32 vs_offset, ps_offset;
461 u32 vb_used, vb_total;
462 struct radeon_ib *vb_ib;
465 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
466 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
467 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
468 int radeon_ib_pool_init(struct radeon_device *rdev);
469 void radeon_ib_pool_fini(struct radeon_device *rdev);
470 int radeon_ib_test(struct radeon_device *rdev);
471 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
472 /* Ring access between begin & end cannot sleep */
473 void radeon_ring_free_size(struct radeon_device *rdev);
474 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
475 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
476 void radeon_ring_commit(struct radeon_device *rdev);
477 void radeon_ring_unlock_commit(struct radeon_device *rdev);
478 void radeon_ring_unlock_undo(struct radeon_device *rdev);
479 int radeon_ring_test(struct radeon_device *rdev);
480 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
481 void radeon_ring_fini(struct radeon_device *rdev);
487 struct radeon_cs_reloc {
488 struct drm_gem_object *gobj;
489 struct radeon_bo *robj;
490 struct radeon_bo_list lobj;
495 struct radeon_cs_chunk {
501 void __user *user_ptr;
502 int last_copied_page;
506 struct radeon_cs_parser {
508 struct radeon_device *rdev;
509 struct drm_file *filp;
512 struct radeon_cs_chunk *chunks;
513 uint64_t *chunks_array;
518 struct radeon_cs_reloc *relocs;
519 struct radeon_cs_reloc **relocs_ptr;
520 struct list_head validated;
521 /* indices of various chunks */
523 int chunk_relocs_idx;
524 struct radeon_ib *ib;
530 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
531 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
534 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
536 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
537 u32 pg_idx, pg_offset;
541 pg_idx = (idx * 4) / PAGE_SIZE;
542 pg_offset = (idx * 4) % PAGE_SIZE;
544 if (ibc->kpage_idx[0] == pg_idx)
545 return ibc->kpage[0][pg_offset/4];
546 if (ibc->kpage_idx[1] == pg_idx)
547 return ibc->kpage[1][pg_offset/4];
549 new_page = radeon_cs_update_pages(p, pg_idx);
551 p->parser_error = new_page;
555 idx_value = ibc->kpage[new_page][pg_offset/4];
559 struct radeon_cs_packet {
568 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
569 struct radeon_cs_packet *pkt,
570 unsigned idx, unsigned reg);
571 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
572 struct radeon_cs_packet *pkt);
578 int radeon_agp_init(struct radeon_device *rdev);
579 void radeon_agp_resume(struct radeon_device *rdev);
580 void radeon_agp_fini(struct radeon_device *rdev);
587 struct radeon_bo *wb_obj;
588 volatile uint32_t *wb;
593 * struct radeon_pm - power management datas
594 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
595 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
596 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
597 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
598 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
599 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
600 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
601 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
602 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
603 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
604 * @needed_bandwidth: current bandwidth needs
606 * It keeps track of various data needed to take powermanagement decision.
607 * Bandwith need is used to determine minimun clock of the GPU and memory.
608 * Equation between gpu/memory clock and available bandwidth is hw dependent
609 * (type of memory, bus size, efficiency, ...)
611 enum radeon_pm_state {
617 enum radeon_pm_action {
625 enum radeon_voltage_type {
632 enum radeon_pm_state_type {
633 POWER_STATE_TYPE_DEFAULT,
634 POWER_STATE_TYPE_POWERSAVE,
635 POWER_STATE_TYPE_BATTERY,
636 POWER_STATE_TYPE_BALANCED,
637 POWER_STATE_TYPE_PERFORMANCE,
640 enum radeon_pm_clock_mode_type {
641 POWER_MODE_TYPE_DEFAULT,
644 POWER_MODE_TYPE_HIGH,
647 struct radeon_voltage {
648 enum radeon_voltage_type type;
650 struct radeon_gpio_rec gpio;
651 u32 delay; /* delay in usec from voltage drop to sclk change */
652 bool active_high; /* voltage drop is active when bit is high */
654 u8 vddc_id; /* index into vddc voltage table */
655 u8 vddci_id; /* index into vddci voltage table */
661 struct radeon_pm_clock_info {
667 struct radeon_voltage voltage;
668 /* standardized clock flags - not sure we'll need these */
673 #define RADEON_PM_SINGLE_DISPLAY_ONLY (1 << 0)
675 struct radeon_power_state {
676 enum radeon_pm_state_type type;
677 /* XXX: use a define for num clock modes */
678 struct radeon_pm_clock_info clock_info[8];
679 /* number of valid clock modes in this power state */
681 struct radeon_pm_clock_info *default_clock_mode;
682 /* standardized state flags */
684 u32 misc; /* vbios specific flags */
685 u32 misc2; /* vbios specific flags */
686 int pcie_lanes; /* pcie lanes */
690 * Some modes are overclocked by very low value, accept them
692 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
696 struct delayed_work idle_work;
697 enum radeon_pm_state state;
698 enum radeon_pm_action planned_action;
699 unsigned long action_timeout;
703 int active_crtc_count;
707 fixed20_12 max_bandwidth;
708 fixed20_12 igp_sideport_mclk;
709 fixed20_12 igp_system_mclk;
710 fixed20_12 igp_ht_link_clk;
711 fixed20_12 igp_ht_link_width;
712 fixed20_12 k8_bandwidth;
713 fixed20_12 sideport_bandwidth;
714 fixed20_12 ht_bandwidth;
715 fixed20_12 core_bandwidth;
718 fixed20_12 needed_bandwidth;
719 /* XXX: use a define for num power modes */
720 struct radeon_power_state power_state[8];
721 /* number of valid power states */
722 int num_power_states;
723 int current_power_state_index;
724 int current_clock_mode_index;
725 int requested_power_state_index;
726 int requested_clock_mode_index;
727 int default_power_state_index;
730 struct radeon_i2c_chan *i2c_bus;
737 void radeon_benchmark(struct radeon_device *rdev);
743 void radeon_test_moves(struct radeon_device *rdev);
749 int radeon_debugfs_add_files(struct radeon_device *rdev,
750 struct drm_info_list *files,
752 int radeon_debugfs_fence_init(struct radeon_device *rdev);
756 * ASIC specific functions.
759 int (*init)(struct radeon_device *rdev);
760 void (*fini)(struct radeon_device *rdev);
761 int (*resume)(struct radeon_device *rdev);
762 int (*suspend)(struct radeon_device *rdev);
763 void (*vga_set_state)(struct radeon_device *rdev, bool state);
764 bool (*gpu_is_lockup)(struct radeon_device *rdev);
765 int (*asic_reset)(struct radeon_device *rdev);
766 void (*gart_tlb_flush)(struct radeon_device *rdev);
767 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
768 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
769 void (*cp_fini)(struct radeon_device *rdev);
770 void (*cp_disable)(struct radeon_device *rdev);
771 void (*cp_commit)(struct radeon_device *rdev);
772 void (*ring_start)(struct radeon_device *rdev);
773 int (*ring_test)(struct radeon_device *rdev);
774 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
775 int (*irq_set)(struct radeon_device *rdev);
776 int (*irq_process)(struct radeon_device *rdev);
777 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
778 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
779 int (*cs_parse)(struct radeon_cs_parser *p);
780 int (*copy_blit)(struct radeon_device *rdev,
784 struct radeon_fence *fence);
785 int (*copy_dma)(struct radeon_device *rdev,
789 struct radeon_fence *fence);
790 int (*copy)(struct radeon_device *rdev,
794 struct radeon_fence *fence);
795 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
796 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
797 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
798 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
799 int (*get_pcie_lanes)(struct radeon_device *rdev);
800 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
801 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
802 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
803 uint32_t tiling_flags, uint32_t pitch,
804 uint32_t offset, uint32_t obj_size);
805 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
806 void (*bandwidth_update)(struct radeon_device *rdev);
807 void (*hpd_init)(struct radeon_device *rdev);
808 void (*hpd_fini)(struct radeon_device *rdev);
809 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
810 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
811 /* ioctl hw specific callback. Some hw might want to perform special
812 * operation on specific ioctl. For instance on wait idle some hw
813 * might want to perform and HDP flush through MMIO as it seems that
814 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
817 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
818 bool (*gui_idle)(struct radeon_device *rdev);
819 void (*get_power_state)(struct radeon_device *rdev, enum radeon_pm_action action);
820 void (*set_power_state)(struct radeon_device *rdev, bool static_switch);
821 void (*pm_misc)(struct radeon_device *rdev);
822 void (*pm_prepare)(struct radeon_device *rdev);
823 void (*pm_finish)(struct radeon_device *rdev);
829 struct r100_gpu_lockup {
830 unsigned long last_jiffies;
835 const unsigned *reg_safe_bm;
836 unsigned reg_safe_bm_size;
838 struct r100_gpu_lockup lockup;
842 const unsigned *reg_safe_bm;
843 unsigned reg_safe_bm_size;
846 struct r100_gpu_lockup lockup;
851 unsigned max_tile_pipes;
853 unsigned max_backends;
855 unsigned max_threads;
856 unsigned max_stack_entries;
857 unsigned max_hw_contexts;
858 unsigned max_gs_threads;
859 unsigned sx_max_export_size;
860 unsigned sx_max_export_pos_size;
861 unsigned sx_max_export_smx_size;
862 unsigned sq_num_cf_insts;
863 unsigned tiling_nbanks;
864 unsigned tiling_npipes;
865 unsigned tiling_group_size;
866 struct r100_gpu_lockup lockup;
871 unsigned max_tile_pipes;
873 unsigned max_backends;
875 unsigned max_threads;
876 unsigned max_stack_entries;
877 unsigned max_hw_contexts;
878 unsigned max_gs_threads;
879 unsigned sx_max_export_size;
880 unsigned sx_max_export_pos_size;
881 unsigned sx_max_export_smx_size;
882 unsigned sq_num_cf_insts;
883 unsigned sx_num_of_sets;
884 unsigned sc_prim_fifo_size;
885 unsigned sc_hiz_tile_fifo_size;
886 unsigned sc_earlyz_tile_fifo_fize;
887 unsigned tiling_nbanks;
888 unsigned tiling_npipes;
889 unsigned tiling_group_size;
890 struct r100_gpu_lockup lockup;
893 struct evergreen_asic {
896 unsigned max_tile_pipes;
898 unsigned max_backends;
900 unsigned max_threads;
901 unsigned max_stack_entries;
902 unsigned max_hw_contexts;
903 unsigned max_gs_threads;
904 unsigned sx_max_export_size;
905 unsigned sx_max_export_pos_size;
906 unsigned sx_max_export_smx_size;
907 unsigned sq_num_cf_insts;
908 unsigned sx_num_of_sets;
909 unsigned sc_prim_fifo_size;
910 unsigned sc_hiz_tile_fifo_size;
911 unsigned sc_earlyz_tile_fifo_size;
912 unsigned tiling_nbanks;
913 unsigned tiling_npipes;
914 unsigned tiling_group_size;
917 union radeon_asic_config {
918 struct r300_asic r300;
919 struct r100_asic r100;
920 struct r600_asic r600;
921 struct rv770_asic rv770;
922 struct evergreen_asic evergreen;
926 * asic initizalization from radeon_asic.c
928 void radeon_agp_disable(struct radeon_device *rdev);
929 int radeon_asic_init(struct radeon_device *rdev);
935 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
936 struct drm_file *filp);
937 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
938 struct drm_file *filp);
939 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
940 struct drm_file *file_priv);
941 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
942 struct drm_file *file_priv);
943 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
944 struct drm_file *file_priv);
945 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
946 struct drm_file *file_priv);
947 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
948 struct drm_file *filp);
949 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
950 struct drm_file *filp);
951 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
952 struct drm_file *filp);
953 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
954 struct drm_file *filp);
955 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
956 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
957 struct drm_file *filp);
958 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
959 struct drm_file *filp);
963 * Core structure, functions and helpers.
965 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
966 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
968 struct radeon_device {
970 struct drm_device *ddev;
971 struct pci_dev *pdev;
973 union radeon_asic_config config;
974 enum radeon_family family;
977 enum radeon_pll_errata pll_errata;
984 uint16_t bios_header_start;
985 struct radeon_bo *stollen_vga_memory;
987 resource_size_t rmmio_base;
988 resource_size_t rmmio_size;
990 radeon_rreg_t mc_rreg;
991 radeon_wreg_t mc_wreg;
992 radeon_rreg_t pll_rreg;
993 radeon_wreg_t pll_wreg;
994 uint32_t pcie_reg_mask;
995 radeon_rreg_t pciep_rreg;
996 radeon_wreg_t pciep_wreg;
997 struct radeon_clock clock;
999 struct radeon_gart gart;
1000 struct radeon_mode_info mode_info;
1001 struct radeon_scratch scratch;
1002 struct radeon_mman mman;
1003 struct radeon_fence_driver fence_drv;
1004 struct radeon_cp cp;
1005 struct radeon_ib_pool ib_pool;
1006 struct radeon_irq irq;
1007 struct radeon_asic *asic;
1008 struct radeon_gem gem;
1009 struct radeon_pm pm;
1010 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1011 struct mutex cs_mutex;
1012 struct radeon_wb wb;
1013 struct radeon_dummy_page dummy_page;
1019 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1020 const struct firmware *me_fw; /* all family ME firmware */
1021 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1022 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1023 struct r600_blit r600_blit;
1024 int msi_enabled; /* msi enabled */
1025 struct r600_ih ih; /* r6/700 interrupt ring */
1026 struct workqueue_struct *wq;
1027 struct work_struct hotplug_work;
1028 int num_crtc; /* number of crtcs */
1029 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1030 struct mutex vram_mutex;
1033 struct timer_list audio_timer;
1036 int audio_bits_per_sample;
1037 uint8_t audio_status_bits;
1038 uint8_t audio_category_code;
1043 int radeon_device_init(struct radeon_device *rdev,
1044 struct drm_device *ddev,
1045 struct pci_dev *pdev,
1047 void radeon_device_fini(struct radeon_device *rdev);
1048 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1051 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1052 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1053 void r600_kms_blit_copy(struct radeon_device *rdev,
1054 u64 src_gpu_addr, u64 dst_gpu_addr,
1057 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1059 if (reg < rdev->rmmio_size)
1060 return readl(((void __iomem *)rdev->rmmio) + reg);
1062 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1063 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1067 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1069 if (reg < rdev->rmmio_size)
1070 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1072 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1073 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1080 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1083 * Registers read & write functions.
1085 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1086 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1087 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1088 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1089 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1090 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1091 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1092 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1093 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1094 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1095 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1096 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1097 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1098 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1099 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1100 #define WREG32_P(reg, val, mask) \
1102 uint32_t tmp_ = RREG32(reg); \
1104 tmp_ |= ((val) & ~(mask)); \
1105 WREG32(reg, tmp_); \
1107 #define WREG32_PLL_P(reg, val, mask) \
1109 uint32_t tmp_ = RREG32_PLL(reg); \
1111 tmp_ |= ((val) & ~(mask)); \
1112 WREG32_PLL(reg, tmp_); \
1114 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1117 * Indirect registers accessor
1119 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1123 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1124 r = RREG32(RADEON_PCIE_DATA);
1128 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1130 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1131 WREG32(RADEON_PCIE_DATA, (v));
1134 void r100_pll_errata_after_index(struct radeon_device *rdev);
1140 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1141 (rdev->pdev->device == 0x5969))
1142 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1143 (rdev->family == CHIP_RV200) || \
1144 (rdev->family == CHIP_RS100) || \
1145 (rdev->family == CHIP_RS200) || \
1146 (rdev->family == CHIP_RV250) || \
1147 (rdev->family == CHIP_RV280) || \
1148 (rdev->family == CHIP_RS300))
1149 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1150 (rdev->family == CHIP_RV350) || \
1151 (rdev->family == CHIP_R350) || \
1152 (rdev->family == CHIP_RV380) || \
1153 (rdev->family == CHIP_R420) || \
1154 (rdev->family == CHIP_R423) || \
1155 (rdev->family == CHIP_RV410) || \
1156 (rdev->family == CHIP_RS400) || \
1157 (rdev->family == CHIP_RS480))
1158 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1159 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1160 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1161 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1166 #define RBIOS8(i) (rdev->bios[i])
1167 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1168 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1170 int radeon_combios_init(struct radeon_device *rdev);
1171 void radeon_combios_fini(struct radeon_device *rdev);
1172 int radeon_atombios_init(struct radeon_device *rdev);
1173 void radeon_atombios_fini(struct radeon_device *rdev);
1179 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1182 if (rdev->cp.count_dw <= 0) {
1183 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1186 rdev->cp.ring[rdev->cp.wptr++] = v;
1187 rdev->cp.wptr &= rdev->cp.ptr_mask;
1188 rdev->cp.count_dw--;
1189 rdev->cp.ring_free_dw--;
1196 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1197 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1198 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1199 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1200 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1201 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1202 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1203 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1204 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1205 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1206 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1207 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1208 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1209 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1210 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1211 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1212 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1213 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1214 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1215 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1216 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1217 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1218 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1219 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1220 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1221 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1222 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1223 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1224 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1225 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1226 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1227 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1228 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1229 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1230 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1231 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1232 #define radeon_get_power_state(rdev, a) (rdev)->asic->get_power_state((rdev), (a))
1233 #define radeon_set_power_state(rdev, s) (rdev)->asic->set_power_state((rdev), (s))
1234 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1235 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1236 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1238 /* Common functions */
1240 extern int radeon_gpu_reset(struct radeon_device *rdev);
1241 extern void radeon_agp_disable(struct radeon_device *rdev);
1242 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1243 extern void radeon_gart_restore(struct radeon_device *rdev);
1244 extern int radeon_modeset_init(struct radeon_device *rdev);
1245 extern void radeon_modeset_fini(struct radeon_device *rdev);
1246 extern bool radeon_card_posted(struct radeon_device *rdev);
1247 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1248 extern void radeon_update_display_priority(struct radeon_device *rdev);
1249 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1250 extern int radeon_clocks_init(struct radeon_device *rdev);
1251 extern void radeon_clocks_fini(struct radeon_device *rdev);
1252 extern void radeon_scratch_init(struct radeon_device *rdev);
1253 extern void radeon_surface_init(struct radeon_device *rdev);
1254 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1255 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1256 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1257 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1258 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1259 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1260 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1261 extern int radeon_resume_kms(struct drm_device *dev);
1262 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1264 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1265 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1266 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1268 /* rv200,rv250,rv280 */
1269 extern void r200_set_safe_registers(struct radeon_device *rdev);
1271 /* r300,r350,rv350,rv370,rv380 */
1272 extern void r300_set_reg_safe(struct radeon_device *rdev);
1273 extern void r300_mc_program(struct radeon_device *rdev);
1274 extern void r300_mc_init(struct radeon_device *rdev);
1275 extern void r300_clock_startup(struct radeon_device *rdev);
1276 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1277 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1278 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1279 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1280 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1282 /* r420,r423,rv410 */
1283 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1284 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1285 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1286 extern void r420_pipes_init(struct radeon_device *rdev);
1289 struct rv515_mc_save {
1292 u32 vga_render_control;
1293 u32 vga_hdp_control;
1297 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1298 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1299 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1300 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1301 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1302 extern void rv515_clock_startup(struct radeon_device *rdev);
1303 extern void rv515_debugfs(struct radeon_device *rdev);
1304 extern int rv515_suspend(struct radeon_device *rdev);
1307 extern int rs400_gart_init(struct radeon_device *rdev);
1308 extern int rs400_gart_enable(struct radeon_device *rdev);
1309 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1310 extern void rs400_gart_disable(struct radeon_device *rdev);
1311 extern void rs400_gart_fini(struct radeon_device *rdev);
1314 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1315 extern int rs600_irq_set(struct radeon_device *rdev);
1316 extern void rs600_irq_disable(struct radeon_device *rdev);
1319 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1320 struct drm_display_mode *mode1,
1321 struct drm_display_mode *mode2);
1323 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1324 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1325 extern bool r600_card_posted(struct radeon_device *rdev);
1326 extern void r600_cp_stop(struct radeon_device *rdev);
1327 extern int r600_cp_start(struct radeon_device *rdev);
1328 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1329 extern int r600_cp_resume(struct radeon_device *rdev);
1330 extern void r600_cp_fini(struct radeon_device *rdev);
1331 extern int r600_count_pipe_bits(uint32_t val);
1332 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1333 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1334 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1335 extern int r600_ib_test(struct radeon_device *rdev);
1336 extern int r600_ring_test(struct radeon_device *rdev);
1337 extern void r600_wb_fini(struct radeon_device *rdev);
1338 extern int r600_wb_enable(struct radeon_device *rdev);
1339 extern void r600_wb_disable(struct radeon_device *rdev);
1340 extern void r600_scratch_init(struct radeon_device *rdev);
1341 extern int r600_blit_init(struct radeon_device *rdev);
1342 extern void r600_blit_fini(struct radeon_device *rdev);
1343 extern int r600_init_microcode(struct radeon_device *rdev);
1344 extern int r600_asic_reset(struct radeon_device *rdev);
1346 extern int r600_irq_init(struct radeon_device *rdev);
1347 extern void r600_irq_fini(struct radeon_device *rdev);
1348 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1349 extern int r600_irq_set(struct radeon_device *rdev);
1350 extern void r600_irq_suspend(struct radeon_device *rdev);
1351 extern void r600_disable_interrupts(struct radeon_device *rdev);
1352 extern void r600_rlc_stop(struct radeon_device *rdev);
1354 extern int r600_audio_init(struct radeon_device *rdev);
1355 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1356 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1357 extern int r600_audio_channels(struct radeon_device *rdev);
1358 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1359 extern int r600_audio_rate(struct radeon_device *rdev);
1360 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1361 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1362 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1363 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1364 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1365 extern void r600_audio_fini(struct radeon_device *rdev);
1366 extern void r600_hdmi_init(struct drm_encoder *encoder);
1367 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1368 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1369 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1370 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1371 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1373 extern void r700_cp_stop(struct radeon_device *rdev);
1374 extern void r700_cp_fini(struct radeon_device *rdev);
1375 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1376 extern int evergreen_irq_set(struct radeon_device *rdev);
1379 struct evergreen_mc_save {
1381 u32 vga_render_control;
1382 u32 vga_hdp_control;
1383 u32 crtc_control[6];
1386 #include "radeon_object.h"