drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* some evergreen boards have bad data for this entry */
  89                         if (ASIC_IS_DCE4(rdev)) {
  90                                 if ((i == 7) &&
  91                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
  92                                     (gpio->sucI2cId.ucAccess == 0)) {
  93                                         gpio->sucI2cId.ucAccess = 0x97;
  94                                         gpio->ucDataMaskShift = 8;
  95                                         gpio->ucDataEnShift = 8;
  96                                         gpio->ucDataY_Shift = 8;
  97                                         gpio->ucDataA_Shift = 8;
  98                                 }
  99                         }
 100
 101                         /* some DCE3 boards have bad data for this entry */
 102                         if (ASIC_IS_DCE3(rdev)) {
 103                                 if ((i == 4) &&
 104                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 105                                     (gpio->sucI2cId.ucAccess == 0x94))
 106                                         gpio->sucI2cId.ucAccess = 0x14;
 107                         }
 108
 109                         if (gpio->sucI2cId.ucAccess == id) {
 110                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 111                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 112                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 113                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 114                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 115                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 116                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 117                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 118                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 119                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 120                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 121                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 122                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 123                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 124                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 125                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 126
 127                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 128                                         i2c.hw_capable = true;
 129                                 else
 130                                         i2c.hw_capable = false;
 131
 132                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 133                                         i2c.mm_i2c = true;
 134                                 else
 135                                         i2c.mm_i2c = false;
 136
 137                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 138
 139                                 if (i2c.mask_clk_reg)
 140                                         i2c.valid = true;
 141                                 break;
 142                         }
 143                 }
 144         }
 145
 146         return i2c;
 147 }
 148
 149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 150 {
 151         struct atom_context *ctx = rdev->mode_info.atom_context;
 152         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 153         struct radeon_i2c_bus_rec i2c;
 154         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 155         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 156         uint16_t data_offset, size;
 157         int i, num_indices;
 158         char stmp[32];
 159
 160         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 161
 162         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 163                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 164
 165                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 166                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 167
 168                 for (i = 0; i < num_indices; i++) {
 169                         gpio = &i2c_info->asGPIO_Info[i];
 170                         i2c.valid = false;
 171
 172                         /* some evergreen boards have bad data for this entry */
 173                         if (ASIC_IS_DCE4(rdev)) {
 174                                 if ((i == 7) &&
 175                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
 176                                     (gpio->sucI2cId.ucAccess == 0)) {
 177                                         gpio->sucI2cId.ucAccess = 0x97;
 178                                         gpio->ucDataMaskShift = 8;
 179                                         gpio->ucDataEnShift = 8;
 180                                         gpio->ucDataY_Shift = 8;
 181                                         gpio->ucDataA_Shift = 8;
 182                                 }
 183                         }
 184
 185                         /* some DCE3 boards have bad data for this entry */
 186                         if (ASIC_IS_DCE3(rdev)) {
 187                                 if ((i == 4) &&
 188                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 189                                     (gpio->sucI2cId.ucAccess == 0x94))
 190                                         gpio->sucI2cId.ucAccess = 0x14;
 191                         }
 192
 193                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 194                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 195                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 196                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 197                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 198                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 199                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 200                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 201                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 202                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 203                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 204                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 205                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 206                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 207                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 208                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 209
 210                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 211                                 i2c.hw_capable = true;
 212                         else
 213                                 i2c.hw_capable = false;
 214
 215                         if (gpio->sucI2cId.ucAccess == 0xa0)
 216                                 i2c.mm_i2c = true;
 217                         else
 218                                 i2c.mm_i2c = false;
 219
 220                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 221
 222                         if (i2c.mask_clk_reg) {
 223                                 i2c.valid = true;
 224                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 225                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 226                         }
 227                 }
 228         }
 229 }
 230
 231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 232                                                         u8 id)
 233 {
 234         struct atom_context *ctx = rdev->mode_info.atom_context;
 235         struct radeon_gpio_rec gpio;
 236         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 237         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 238         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 239         u16 data_offset, size;
 240         int i, num_indices;
 241
 242         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 243         gpio.valid = false;
 244
 245         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 246                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 247
 248                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 249                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 250
 251                 for (i = 0; i < num_indices; i++) {
 252                         pin = &gpio_info->asGPIO_Pin[i];
 253                         if (id == pin->ucGPIO_ID) {
 254                                 gpio.id = pin->ucGPIO_ID;
 255                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 256                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 257                                 gpio.valid = true;
 258                                 break;
 259                         }
 260                 }
 261         }
 262
 263         return gpio;
 264 }
 265
 266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 267                                                             struct radeon_gpio_rec *gpio)
 268 {
 269         struct radeon_hpd hpd;
 270         u32 reg;
 271
 272         memset(&hpd, 0, sizeof(struct radeon_hpd));
 273
 274         if (ASIC_IS_DCE4(rdev))
 275                 reg = EVERGREEN_DC_GPIO_HPD_A;
 276         else
 277                 reg = AVIVO_DC_GPIO_HPD_A;
 278
 279         hpd.gpio = *gpio;
 280         if (gpio->reg == reg) {
 281                 switch(gpio->mask) {
 282                 case (1 << 0):
 283                         hpd.hpd = RADEON_HPD_1;
 284                         break;
 285                 case (1 << 8):
 286                         hpd.hpd = RADEON_HPD_2;
 287                         break;
 288                 case (1 << 16):
 289                         hpd.hpd = RADEON_HPD_3;
 290                         break;
 291                 case (1 << 24):
 292                         hpd.hpd = RADEON_HPD_4;
 293                         break;
 294                 case (1 << 26):
 295                         hpd.hpd = RADEON_HPD_5;
 296                         break;
 297                 case (1 << 28):
 298                         hpd.hpd = RADEON_HPD_6;
 299                         break;
 300                 default:
 301                         hpd.hpd = RADEON_HPD_NONE;
 302                         break;
 303                 }
 304         } else
 305                 hpd.hpd = RADEON_HPD_NONE;
 306         return hpd;
 307 }
 308
 309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 310                                      uint32_t supported_device,
 311                                      int *connector_type,
 312                                      struct radeon_i2c_bus_rec *i2c_bus,
 313                                      uint16_t *line_mux,
 314                                      struct radeon_hpd *hpd)
 315 {
 316
 317         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 318         if ((dev->pdev->device == 0x791e) &&
 319             (dev->pdev->subsystem_vendor == 0x1043) &&
 320             (dev->pdev->subsystem_device == 0x826d)) {
 321                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 322                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 323                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 324         }
 325
 326         /* Asrock RS600 board lists the DVI port as HDMI */
 327         if ((dev->pdev->device == 0x7941) &&
 328             (dev->pdev->subsystem_vendor == 0x1849) &&
 329             (dev->pdev->subsystem_device == 0x7941)) {
 330                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 331                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 332                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 333         }
 334
 335         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 336         if ((dev->pdev->device == 0x796e) &&
 337             (dev->pdev->subsystem_vendor == 0x1462) &&
 338             (dev->pdev->subsystem_device == 0x7302)) {
 339                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 340                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 341                         return false;
 342         }
 343
 344         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 345         if ((dev->pdev->device == 0x7941) &&
 346             (dev->pdev->subsystem_vendor == 0x147b) &&
 347             (dev->pdev->subsystem_device == 0x2412)) {
 348                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 349                         return false;
 350         }
 351
 352         /* Falcon NW laptop lists vga ddc line for LVDS */
 353         if ((dev->pdev->device == 0x5653) &&
 354             (dev->pdev->subsystem_vendor == 0x1462) &&
 355             (dev->pdev->subsystem_device == 0x0291)) {
 356                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 357                         i2c_bus->valid = false;
 358                         *line_mux = 53;
 359                 }
 360         }
 361
 362         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 363         if ((dev->pdev->device == 0x7146) &&
 364             (dev->pdev->subsystem_vendor == 0x17af) &&
 365             (dev->pdev->subsystem_device == 0x2058)) {
 366                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 367                         return false;
 368         }
 369
 370         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 371         if ((dev->pdev->device == 0x7142) &&
 372             (dev->pdev->subsystem_vendor == 0x1458) &&
 373             (dev->pdev->subsystem_device == 0x2134)) {
 374                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 375                         return false;
 376         }
 377
 378
 379         /* Funky macbooks */
 380         if ((dev->pdev->device == 0x71C5) &&
 381             (dev->pdev->subsystem_vendor == 0x106b) &&
 382             (dev->pdev->subsystem_device == 0x0080)) {
 383                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 384                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 385                         return false;
 386                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 387                         *line_mux = 0x90;
 388         }
 389
 390         /* mac rv630 */
 391         if ((dev->pdev->device == 0x9588) &&
 392             (dev->pdev->subsystem_vendor == 0x106b) &&
 393             (dev->pdev->subsystem_device == 0x00a6)) {
 394                 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 395                     (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 396                         *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 397                         *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 398                 }
 399         }
 400
 401         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 402         if ((dev->pdev->device == 0x9598) &&
 403             (dev->pdev->subsystem_vendor == 0x1043) &&
 404             (dev->pdev->subsystem_device == 0x01da)) {
 405                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 406                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 407                 }
 408         }
 409
 410         /* ASUS HD 3600 board lists the DVI port as HDMI */
 411         if ((dev->pdev->device == 0x9598) &&
 412             (dev->pdev->subsystem_vendor == 0x1043) &&
 413             (dev->pdev->subsystem_device == 0x01e4)) {
 414                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 415                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 416                 }
 417         }
 418
 419         /* ASUS HD 3450 board lists the DVI port as HDMI */
 420         if ((dev->pdev->device == 0x95C5) &&
 421             (dev->pdev->subsystem_vendor == 0x1043) &&
 422             (dev->pdev->subsystem_device == 0x01e2)) {
 423                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 424                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 425                 }
 426         }
 427
 428         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 429          * HDMI + VGA reporting as HDMI
 430          */
 431         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 432                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 433                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 434                         *line_mux = 0;
 435                 }
 436         }
 437
 438         /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
 439          * on the laptop and a DVI port on the docking station and
 440          * both share the same encoder, hpd pin, and ddc line.
 441          * So while the bios table is technically correct,
 442          * we drop the DVI port here since xrandr has no concept of
 443          * encoders and will try and drive both connectors
 444          * with different crtcs which isn't possible on the hardware
 445          * side and leaves no crtcs for LVDS or VGA.
 446          */
 447         if ((dev->pdev->device == 0x95c4) &&
 448             (dev->pdev->subsystem_vendor == 0x1025) &&
 449             (dev->pdev->subsystem_device == 0x013c)) {
 450                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 451                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 452                         /* actually it's a DVI-D port not DVI-I */
 453                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 454                         return false;
 455                 }
 456         }
 457
 458         /* XFX Pine Group device rv730 reports no VGA DDC lines
 459          * even though they are wired up to record 0x93
 460          */
 461         if ((dev->pdev->device == 0x9498) &&
 462             (dev->pdev->subsystem_vendor == 0x1682) &&
 463             (dev->pdev->subsystem_device == 0x2452)) {
 464                 struct radeon_device *rdev = dev->dev_private;
 465                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 466         }
 467         return true;
 468 }
 469
 470 const int supported_devices_connector_convert[] = {
 471         DRM_MODE_CONNECTOR_Unknown,
 472         DRM_MODE_CONNECTOR_VGA,
 473         DRM_MODE_CONNECTOR_DVII,
 474         DRM_MODE_CONNECTOR_DVID,
 475         DRM_MODE_CONNECTOR_DVIA,
 476         DRM_MODE_CONNECTOR_SVIDEO,
 477         DRM_MODE_CONNECTOR_Composite,
 478         DRM_MODE_CONNECTOR_LVDS,
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_Unknown,
 481         DRM_MODE_CONNECTOR_HDMIA,
 482         DRM_MODE_CONNECTOR_HDMIB,
 483         DRM_MODE_CONNECTOR_Unknown,
 484         DRM_MODE_CONNECTOR_Unknown,
 485         DRM_MODE_CONNECTOR_9PinDIN,
 486         DRM_MODE_CONNECTOR_DisplayPort
 487 };
 488
 489 const uint16_t supported_devices_connector_object_id_convert[] = {
 490         CONNECTOR_OBJECT_ID_NONE,
 491         CONNECTOR_OBJECT_ID_VGA,
 492         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 493         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 494         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 495         CONNECTOR_OBJECT_ID_COMPOSITE,
 496         CONNECTOR_OBJECT_ID_SVIDEO,
 497         CONNECTOR_OBJECT_ID_LVDS,
 498         CONNECTOR_OBJECT_ID_9PIN_DIN,
 499         CONNECTOR_OBJECT_ID_9PIN_DIN,
 500         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 501         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 502         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 503         CONNECTOR_OBJECT_ID_SVIDEO
 504 };
 505
 506 const int object_connector_convert[] = {
 507         DRM_MODE_CONNECTOR_Unknown,
 508         DRM_MODE_CONNECTOR_DVII,
 509         DRM_MODE_CONNECTOR_DVII,
 510         DRM_MODE_CONNECTOR_DVID,
 511         DRM_MODE_CONNECTOR_DVID,
 512         DRM_MODE_CONNECTOR_VGA,
 513         DRM_MODE_CONNECTOR_Composite,
 514         DRM_MODE_CONNECTOR_SVIDEO,
 515         DRM_MODE_CONNECTOR_Unknown,
 516         DRM_MODE_CONNECTOR_Unknown,
 517         DRM_MODE_CONNECTOR_9PinDIN,
 518         DRM_MODE_CONNECTOR_Unknown,
 519         DRM_MODE_CONNECTOR_HDMIA,
 520         DRM_MODE_CONNECTOR_HDMIB,
 521         DRM_MODE_CONNECTOR_LVDS,
 522         DRM_MODE_CONNECTOR_9PinDIN,
 523         DRM_MODE_CONNECTOR_Unknown,
 524         DRM_MODE_CONNECTOR_Unknown,
 525         DRM_MODE_CONNECTOR_Unknown,
 526         DRM_MODE_CONNECTOR_DisplayPort,
 527         DRM_MODE_CONNECTOR_eDP,
 528         DRM_MODE_CONNECTOR_Unknown
 529 };
 530
 531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 532 {
 533         struct radeon_device *rdev = dev->dev_private;
 534         struct radeon_mode_info *mode_info = &rdev->mode_info;
 535         struct atom_context *ctx = mode_info->atom_context;
 536         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 537         u16 size, data_offset;
 538         u8 frev, crev;
 539         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 540         ATOM_OBJECT_TABLE *router_obj;
 541         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 542         ATOM_OBJECT_HEADER *obj_header;
 543         int i, j, k, path_size, device_support;
 544         int connector_type;
 545         u16 igp_lane_info, conn_id, connector_object_id;
 546         struct radeon_i2c_bus_rec ddc_bus;
 547         struct radeon_router router;
 548         struct radeon_gpio_rec gpio;
 549         struct radeon_hpd hpd;
 550
 551         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 552                 return false;
 553
 554         if (crev < 2)
 555                 return false;
 556
 557         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 558         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 559             (ctx->bios + data_offset +
 560              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 561         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 562             (ctx->bios + data_offset +
 563              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 564         router_obj = (ATOM_OBJECT_TABLE *)
 565                 (ctx->bios + data_offset +
 566                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 567         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 568
 569         path_size = 0;
 570         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 571                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 572                 ATOM_DISPLAY_OBJECT_PATH *path;
 573                 addr += path_size;
 574                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 575                 path_size += le16_to_cpu(path->usSize);
 576
 577                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 578                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 579
 580                         con_obj_id =
 581                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 582                             >> OBJECT_ID_SHIFT;
 583                         con_obj_num =
 584                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 585                             >> ENUM_ID_SHIFT;
 586                         con_obj_type =
 587                             (le16_to_cpu(path->usConnObjectId) &
 588                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 589
 590                         /* TODO CV support */
 591                         if (le16_to_cpu(path->usDeviceTag) ==
 592                                 ATOM_DEVICE_CV_SUPPORT)
 593                                 continue;
 594
 595                         /* IGP chips */
 596                         if ((rdev->flags & RADEON_IS_IGP) &&
 597                             (con_obj_id ==
 598                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 599                                 uint16_t igp_offset = 0;
 600                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 601
 602                                 index =
 603                                     GetIndexIntoMasterTable(DATA,
 604                                                             IntegratedSystemInfo);
 605
 606                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 607                                                            &crev, &igp_offset)) {
 608
 609                                         if (crev >= 2) {
 610                                                 igp_obj =
 611                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 612                                                          *) (ctx->bios + igp_offset);
 613
 614                                                 if (igp_obj) {
 615                                                         uint32_t slot_config, ct;
 616
 617                                                         if (con_obj_num == 1)
 618                                                                 slot_config =
 619                                                                         igp_obj->
 620                                                                         ulDDISlot1Config;
 621                                                         else
 622                                                                 slot_config =
 623                                                                         igp_obj->
 624                                                                         ulDDISlot2Config;
 625
 626                                                         ct = (slot_config >> 16) & 0xff;
 627                                                         connector_type =
 628                                                                 object_connector_convert
 629                                                                 [ct];
 630                                                         connector_object_id = ct;
 631                                                         igp_lane_info =
 632                                                                 slot_config & 0xffff;
 633                                                 } else
 634                                                         continue;
 635                                         } else
 636                                                 continue;
 637                                 } else {
 638                                         igp_lane_info = 0;
 639                                         connector_type =
 640                                                 object_connector_convert[con_obj_id];
 641                                         connector_object_id = con_obj_id;
 642                                 }
 643                         } else {
 644                                 igp_lane_info = 0;
 645                                 connector_type =
 646                                     object_connector_convert[con_obj_id];
 647                                 connector_object_id = con_obj_id;
 648                         }
 649
 650                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 651                                 continue;
 652
 653                         router.ddc_valid = false;
 654                         router.cd_valid = false;
 655                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 656                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 657
 658                                 grph_obj_id =
 659                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 660                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 661                                 grph_obj_num =
 662                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 663                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 664                                 grph_obj_type =
 665                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 666                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 667
 668                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 669                                         u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
 670
 671                                         radeon_add_atom_encoder(dev,
 672                                                                 encoder_obj,
 673                                                                 le16_to_cpu
 674                                                                 (path->
 675                                                                  usDeviceTag));
 676
 677                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 678                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 679                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 680                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 681                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 682                                                                 (ctx->bios + data_offset +
 683                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 684                                                         ATOM_I2C_RECORD *i2c_record;
 685                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 686                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 687                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 688                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 689                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 690                                                                 (ctx->bios + data_offset +
 691                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 692                                                         int enum_id;
 693
 694                                                         router.router_id = router_obj_id;
 695                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 696                                                              enum_id++) {
 697                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 698                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 699                                                                         break;
 700                                                         }
 701
 702                                                         while (record->ucRecordType > 0 &&
 703                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 704                                                                 switch (record->ucRecordType) {
 705                                                                 case ATOM_I2C_RECORD_TYPE:
 706                                                                         i2c_record =
 707                                                                                 (ATOM_I2C_RECORD *)
 708                                                                                 record;
 709                                                                         i2c_config =
 710                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 711                                                                                 &i2c_record->sucI2cId;
 712                                                                         router.i2c_info =
 713                                                                                 radeon_lookup_i2c_gpio(rdev,
 714                                                                                                        i2c_config->
 715                                                                                                        ucAccess);
 716                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 717                                                                         break;
 718                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 719                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 720                                                                                 record;
 721                                                                         router.ddc_valid = true;
 722                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 723                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 724                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 725                                                                         break;
 726                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 727                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 728                                                                                 record;
 729                                                                         router.cd_valid = true;
 730                                                                         router.cd_mux_type = cd_path->ucMuxType;
 731                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 732                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 733                                                                         break;
 734                                                                 }
 735                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 736                                                                         ((char *)record + record->ucRecordSize);
 737                                                         }
 738                                                 }
 739                                         }
 740                                 }
 741                         }
 742
 743                         /* look up gpio for ddc, hpd */
 744                         ddc_bus.valid = false;
 745                         hpd.hpd = RADEON_HPD_NONE;
 746                         if ((le16_to_cpu(path->usDeviceTag) &
 747                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 748                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 749                                         if (le16_to_cpu(path->usConnObjectId) ==
 750                                             le16_to_cpu(con_obj->asObjects[j].
 751                                                         usObjectID)) {
 752                                                 ATOM_COMMON_RECORD_HEADER
 753                                                     *record =
 754                                                     (ATOM_COMMON_RECORD_HEADER
 755                                                      *)
 756                                                     (ctx->bios + data_offset +
 757                                                      le16_to_cpu(con_obj->
 758                                                                  asObjects[j].
 759                                                                  usRecordOffset));
 760                                                 ATOM_I2C_RECORD *i2c_record;
 761                                                 ATOM_HPD_INT_RECORD *hpd_record;
 762                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 763
 764                                                 while (record->ucRecordType > 0
 765                                                        && record->
 766                                                        ucRecordType <=
 767                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 768                                                         switch (record->ucRecordType) {
 769                                                         case ATOM_I2C_RECORD_TYPE:
 770                                                                 i2c_record =
 771                                                                     (ATOM_I2C_RECORD *)
 772                                                                         record;
 773                                                                 i2c_config =
 774                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 775                                                                         &i2c_record->sucI2cId;
 776                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 777                                                                                                  i2c_config->
 778                                                                                                  ucAccess);
 779                                                                 break;
 780                                                         case ATOM_HPD_INT_RECORD_TYPE:
 781                                                                 hpd_record =
 782                                                                         (ATOM_HPD_INT_RECORD *)
 783                                                                         record;
 784                                                                 gpio = radeon_lookup_gpio(rdev,
 785                                                                                           hpd_record->ucHPDIntGPIOID);
 786                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 787                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 788                                                                 break;
 789                                                         }
 790                                                         record =
 791                                                             (ATOM_COMMON_RECORD_HEADER
 792                                                              *) ((char *)record
 793                                                                  +
 794                                                                  record->
 795                                                                  ucRecordSize);
 796                                                 }
 797                                                 break;
 798                                         }
 799                                 }
 800                         }
 801
 802                         /* needed for aux chan transactions */
 803                         ddc_bus.hpd = hpd.hpd;
 804
 805                         conn_id = le16_to_cpu(path->usConnObjectId);
 806
 807                         if (!radeon_atom_apply_quirks
 808                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 809                              &ddc_bus, &conn_id, &hpd))
 810                                 continue;
 811
 812                         radeon_add_atom_connector(dev,
 813                                                   conn_id,
 814                                                   le16_to_cpu(path->
 815                                                               usDeviceTag),
 816                                                   connector_type, &ddc_bus,
 817                                                   igp_lane_info,
 818                                                   connector_object_id,
 819                                                   &hpd,
 820                                                   &router);
 821
 822                 }
 823         }
 824
 825         radeon_link_encoder_connector(dev);
 826
 827         return true;
 828 }
 829
 830 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 831                                                  int connector_type,
 832                                                  uint16_t devices)
 833 {
 834         struct radeon_device *rdev = dev->dev_private;
 835
 836         if (rdev->flags & RADEON_IS_IGP) {
 837                 return supported_devices_connector_object_id_convert
 838                         [connector_type];
 839         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 840                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 841                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 842                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 843                 struct atom_context *ctx = mode_info->atom_context;
 844                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 845                 uint16_t size, data_offset;
 846                 uint8_t frev, crev;
 847                 ATOM_XTMDS_INFO *xtmds;
 848
 849                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 850                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 851
 852                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 853                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 854                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 855                                 else
 856                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 857                         } else {
 858                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 859                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 860                                 else
 861                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 862                         }
 863                 } else
 864                         return supported_devices_connector_object_id_convert
 865                                 [connector_type];
 866         } else {
 867                 return supported_devices_connector_object_id_convert
 868                         [connector_type];
 869         }
 870 }
 871
 872 struct bios_connector {
 873         bool valid;
 874         uint16_t line_mux;
 875         uint16_t devices;
 876         int connector_type;
 877         struct radeon_i2c_bus_rec ddc_bus;
 878         struct radeon_hpd hpd;
 879 };
 880
 881 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 882                                                                  drm_device
 883                                                                  *dev)
 884 {
 885         struct radeon_device *rdev = dev->dev_private;
 886         struct radeon_mode_info *mode_info = &rdev->mode_info;
 887         struct atom_context *ctx = mode_info->atom_context;
 888         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 889         uint16_t size, data_offset;
 890         uint8_t frev, crev;
 891         uint16_t device_support;
 892         uint8_t dac;
 893         union atom_supported_devices *supported_devices;
 894         int i, j, max_device;
 895         struct bios_connector *bios_connectors;
 896         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 897         struct radeon_router router;
 898
 899         router.ddc_valid = false;
 900         router.cd_valid = false;
 901
 902         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 903         if (!bios_connectors)
 904                 return false;
 905
 906         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 907                                     &data_offset)) {
 908                 kfree(bios_connectors);
 909                 return false;
 910         }
 911
 912         supported_devices =
 913             (union atom_supported_devices *)(ctx->bios + data_offset);
 914
 915         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 916
 917         if (frev > 1)
 918                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 919         else
 920                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 921
 922         for (i = 0; i < max_device; i++) {
 923                 ATOM_CONNECTOR_INFO_I2C ci =
 924                     supported_devices->info.asConnInfo[i];
 925
 926                 bios_connectors[i].valid = false;
 927
 928                 if (!(device_support & (1 << i))) {
 929                         continue;
 930                 }
 931
 932                 if (i == ATOM_DEVICE_CV_INDEX) {
 933                         DRM_DEBUG_KMS("Skipping Component Video\n");
 934                         continue;
 935                 }
 936
 937                 bios_connectors[i].connector_type =
 938                     supported_devices_connector_convert[ci.sucConnectorInfo.
 939                                                         sbfAccess.
 940                                                         bfConnectorType];
 941
 942                 if (bios_connectors[i].connector_type ==
 943                     DRM_MODE_CONNECTOR_Unknown)
 944                         continue;
 945
 946                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 947
 948                 bios_connectors[i].line_mux =
 949                         ci.sucI2cId.ucAccess;
 950
 951                 /* give tv unique connector ids */
 952                 if (i == ATOM_DEVICE_TV1_INDEX) {
 953                         bios_connectors[i].ddc_bus.valid = false;
 954                         bios_connectors[i].line_mux = 50;
 955                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 956                         bios_connectors[i].ddc_bus.valid = false;
 957                         bios_connectors[i].line_mux = 51;
 958                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 959                         bios_connectors[i].ddc_bus.valid = false;
 960                         bios_connectors[i].line_mux = 52;
 961                 } else
 962                         bios_connectors[i].ddc_bus =
 963                             radeon_lookup_i2c_gpio(rdev,
 964                                                    bios_connectors[i].line_mux);
 965
 966                 if ((crev > 1) && (frev > 1)) {
 967                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 968                         switch (isb) {
 969                         case 0x4:
 970                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 971                                 break;
 972                         case 0xa:
 973                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 974                                 break;
 975                         default:
 976                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 977                                 break;
 978                         }
 979                 } else {
 980                         if (i == ATOM_DEVICE_DFP1_INDEX)
 981                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 982                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 983                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 984                         else
 985                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 986                 }
 987
 988                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 989                  * shared with a DVI port, we'll pick up the DVI connector when we
 990                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 991                  */
 992                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 993                         bios_connectors[i].connector_type =
 994                             DRM_MODE_CONNECTOR_VGA;
 995
 996                 if (!radeon_atom_apply_quirks
 997                     (dev, (1 << i), &bios_connectors[i].connector_type,
 998                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 999                      &bios_connectors[i].hpd))
1000                         continue;
1001
1002                 bios_connectors[i].valid = true;
1003                 bios_connectors[i].devices = (1 << i);
1004
1005                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1006                         radeon_add_atom_encoder(dev,
1007                                                 radeon_get_encoder_enum(dev,
1008                                                                       (1 << i),
1009                                                                       dac),
1010                                                 (1 << i));
1011                 else
1012                         radeon_add_legacy_encoder(dev,
1013                                                   radeon_get_encoder_enum(dev,
1014                                                                         (1 << i),
1015                                                                         dac),
1016                                                   (1 << i));
1017         }
1018
1019         /* combine shared connectors */
1020         for (i = 0; i < max_device; i++) {
1021                 if (bios_connectors[i].valid) {
1022                         for (j = 0; j < max_device; j++) {
1023                                 if (bios_connectors[j].valid && (i != j)) {
1024                                         if (bios_connectors[i].line_mux ==
1025                                             bios_connectors[j].line_mux) {
1026                                                 /* make sure not to combine LVDS */
1027                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1028                                                         bios_connectors[i].line_mux = 53;
1029                                                         bios_connectors[i].ddc_bus.valid = false;
1030                                                         continue;
1031                                                 }
1032                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1033                                                         bios_connectors[j].line_mux = 53;
1034                                                         bios_connectors[j].ddc_bus.valid = false;
1035                                                         continue;
1036                                                 }
1037                                                 /* combine analog and digital for DVI-I */
1038                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1039                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1040                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1041                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1042                                                         bios_connectors[i].devices |=
1043                                                                 bios_connectors[j].devices;
1044                                                         bios_connectors[i].connector_type =
1045                                                                 DRM_MODE_CONNECTOR_DVII;
1046                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1047                                                                 bios_connectors[i].hpd =
1048                                                                         bios_connectors[j].hpd;
1049                                                         bios_connectors[j].valid = false;
1050                                                 }
1051                                         }
1052                                 }
1053                         }
1054                 }
1055         }
1056
1057         /* add the connectors */
1058         for (i = 0; i < max_device; i++) {
1059                 if (bios_connectors[i].valid) {
1060                         uint16_t connector_object_id =
1061                                 atombios_get_connector_object_id(dev,
1062                                                       bios_connectors[i].connector_type,
1063                                                       bios_connectors[i].devices);
1064                         radeon_add_atom_connector(dev,
1065                                                   bios_connectors[i].line_mux,
1066                                                   bios_connectors[i].devices,
1067                                                   bios_connectors[i].
1068                                                   connector_type,
1069                                                   &bios_connectors[i].ddc_bus,
1070                                                   0,
1071                                                   connector_object_id,
1072                                                   &bios_connectors[i].hpd,
1073                                                   &router);
1074                 }
1075         }
1076
1077         radeon_link_encoder_connector(dev);
1078
1079         kfree(bios_connectors);
1080         return true;
1081 }
1082
1083 union firmware_info {
1084         ATOM_FIRMWARE_INFO info;
1085         ATOM_FIRMWARE_INFO_V1_2 info_12;
1086         ATOM_FIRMWARE_INFO_V1_3 info_13;
1087         ATOM_FIRMWARE_INFO_V1_4 info_14;
1088         ATOM_FIRMWARE_INFO_V2_1 info_21;
1089         ATOM_FIRMWARE_INFO_V2_2 info_22;
1090 };
1091
1092 bool radeon_atom_get_clock_info(struct drm_device *dev)
1093 {
1094         struct radeon_device *rdev = dev->dev_private;
1095         struct radeon_mode_info *mode_info = &rdev->mode_info;
1096         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1097         union firmware_info *firmware_info;
1098         uint8_t frev, crev;
1099         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1100         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1101         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1102         struct radeon_pll *spll = &rdev->clock.spll;
1103         struct radeon_pll *mpll = &rdev->clock.mpll;
1104         uint16_t data_offset;
1105
1106         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1107                                    &frev, &crev, &data_offset)) {
1108                 firmware_info =
1109                         (union firmware_info *)(mode_info->atom_context->bios +
1110                                                 data_offset);
1111                 /* pixel clocks */
1112                 p1pll->reference_freq =
1113                     le16_to_cpu(firmware_info->info.usReferenceClock);
1114                 p1pll->reference_div = 0;
1115
1116                 if (crev < 2)
1117                         p1pll->pll_out_min =
1118                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1119                 else
1120                         p1pll->pll_out_min =
1121                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1122                 p1pll->pll_out_max =
1123                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1124
1125                 if (crev >= 4) {
1126                         p1pll->lcd_pll_out_min =
1127                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1128                         if (p1pll->lcd_pll_out_min == 0)
1129                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1130                         p1pll->lcd_pll_out_max =
1131                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1132                         if (p1pll->lcd_pll_out_max == 0)
1133                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1134                 } else {
1135                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1136                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1137                 }
1138
1139                 if (p1pll->pll_out_min == 0) {
1140                         if (ASIC_IS_AVIVO(rdev))
1141                                 p1pll->pll_out_min = 64800;
1142                         else
1143                                 p1pll->pll_out_min = 20000;
1144                 } else if (p1pll->pll_out_min > 64800) {
1145                         /* Limiting the pll output range is a good thing generally as
1146                          * it limits the number of possible pll combinations for a given
1147                          * frequency presumably to the ones that work best on each card.
1148                          * However, certain duallink DVI monitors seem to like
1149                          * pll combinations that would be limited by this at least on
1150                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
1151                          * family.
1152                          */
1153                         p1pll->pll_out_min = 64800;
1154                 }
1155
1156                 p1pll->pll_in_min =
1157                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1158                 p1pll->pll_in_max =
1159                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1160
1161                 *p2pll = *p1pll;
1162
1163                 /* system clock */
1164                 if (ASIC_IS_DCE4(rdev))
1165                         spll->reference_freq =
1166                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1167                 else
1168                         spll->reference_freq =
1169                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1170                 spll->reference_div = 0;
1171
1172                 spll->pll_out_min =
1173                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1174                 spll->pll_out_max =
1175                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1176
1177                 /* ??? */
1178                 if (spll->pll_out_min == 0) {
1179                         if (ASIC_IS_AVIVO(rdev))
1180                                 spll->pll_out_min = 64800;
1181                         else
1182                                 spll->pll_out_min = 20000;
1183                 }
1184
1185                 spll->pll_in_min =
1186                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1187                 spll->pll_in_max =
1188                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1189
1190                 /* memory clock */
1191                 if (ASIC_IS_DCE4(rdev))
1192                         mpll->reference_freq =
1193                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1194                 else
1195                         mpll->reference_freq =
1196                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1197                 mpll->reference_div = 0;
1198
1199                 mpll->pll_out_min =
1200                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1201                 mpll->pll_out_max =
1202                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1203
1204                 /* ??? */
1205                 if (mpll->pll_out_min == 0) {
1206                         if (ASIC_IS_AVIVO(rdev))
1207                                 mpll->pll_out_min = 64800;
1208                         else
1209                                 mpll->pll_out_min = 20000;
1210                 }
1211
1212                 mpll->pll_in_min =
1213                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1214                 mpll->pll_in_max =
1215                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1216
1217                 rdev->clock.default_sclk =
1218                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1219                 rdev->clock.default_mclk =
1220                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1221
1222                 if (ASIC_IS_DCE4(rdev)) {
1223                         rdev->clock.default_dispclk =
1224                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1225                         if (rdev->clock.default_dispclk == 0) {
1226                                 if (ASIC_IS_DCE5(rdev))
1227                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1228                                 else
1229                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1230                         }
1231                         rdev->clock.dp_extclk =
1232                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1233                 }
1234                 *dcpll = *p1pll;
1235
1236                 return true;
1237         }
1238
1239         return false;
1240 }
1241
1242 union igp_info {
1243         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1244         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1245 };
1246
1247 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1248 {
1249         struct radeon_mode_info *mode_info = &rdev->mode_info;
1250         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1251         union igp_info *igp_info;
1252         u8 frev, crev;
1253         u16 data_offset;
1254
1255         /* sideport is AMD only */
1256         if (rdev->family == CHIP_RS600)
1257                 return false;
1258
1259         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1260                                    &frev, &crev, &data_offset)) {
1261                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1262                                       data_offset);
1263                 switch (crev) {
1264                 case 1:
1265                         if (igp_info->info.ulBootUpMemoryClock)
1266                                 return true;
1267                         break;
1268                 case 2:
1269                         if (igp_info->info_2.ulBootUpSidePortClock)
1270                                 return true;
1271                         break;
1272                 default:
1273                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1274                         break;
1275                 }
1276         }
1277         return false;
1278 }
1279
1280 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1281                                    struct radeon_encoder_int_tmds *tmds)
1282 {
1283         struct drm_device *dev = encoder->base.dev;
1284         struct radeon_device *rdev = dev->dev_private;
1285         struct radeon_mode_info *mode_info = &rdev->mode_info;
1286         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1287         uint16_t data_offset;
1288         struct _ATOM_TMDS_INFO *tmds_info;
1289         uint8_t frev, crev;
1290         uint16_t maxfreq;
1291         int i;
1292
1293         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1294                                    &frev, &crev, &data_offset)) {
1295                 tmds_info =
1296                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1297                                                    data_offset);
1298
1299                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1300                 for (i = 0; i < 4; i++) {
1301                         tmds->tmds_pll[i].freq =
1302                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1303                         tmds->tmds_pll[i].value =
1304                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1305                         tmds->tmds_pll[i].value |=
1306                             (tmds_info->asMiscInfo[i].
1307                              ucPLL_VCO_Gain & 0x3f) << 6;
1308                         tmds->tmds_pll[i].value |=
1309                             (tmds_info->asMiscInfo[i].
1310                              ucPLL_DutyCycle & 0xf) << 12;
1311                         tmds->tmds_pll[i].value |=
1312                             (tmds_info->asMiscInfo[i].
1313                              ucPLL_VoltageSwing & 0xf) << 16;
1314
1315                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1316                                   tmds->tmds_pll[i].freq,
1317                                   tmds->tmds_pll[i].value);
1318
1319                         if (maxfreq == tmds->tmds_pll[i].freq) {
1320                                 tmds->tmds_pll[i].freq = 0xffffffff;
1321                                 break;
1322                         }
1323                 }
1324                 return true;
1325         }
1326         return false;
1327 }
1328
1329 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1330                                       struct radeon_atom_ss *ss,
1331                                       int id)
1332 {
1333         struct radeon_mode_info *mode_info = &rdev->mode_info;
1334         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1335         uint16_t data_offset, size;
1336         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1337         uint8_t frev, crev;
1338         int i, num_indices;
1339
1340         memset(ss, 0, sizeof(struct radeon_atom_ss));
1341         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1342                                    &frev, &crev, &data_offset)) {
1343                 ss_info =
1344                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1345
1346                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1347                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1348
1349                 for (i = 0; i < num_indices; i++) {
1350                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1351                                 ss->percentage =
1352                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1353                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1354                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1355                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1356                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1357                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1358                                 return true;
1359                         }
1360                 }
1361         }
1362         return false;
1363 }
1364
1365 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1366                                                  struct radeon_atom_ss *ss,
1367                                                  int id)
1368 {
1369         struct radeon_mode_info *mode_info = &rdev->mode_info;
1370         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1371         u16 data_offset, size;
1372         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1373         u8 frev, crev;
1374         u16 percentage = 0, rate = 0;
1375
1376         /* get any igp specific overrides */
1377         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1378                                    &frev, &crev, &data_offset)) {
1379                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1380                         (mode_info->atom_context->bios + data_offset);
1381                 switch (id) {
1382                 case ASIC_INTERNAL_SS_ON_TMDS:
1383                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1384                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1385                         break;
1386                 case ASIC_INTERNAL_SS_ON_HDMI:
1387                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1388                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1389                         break;
1390                 case ASIC_INTERNAL_SS_ON_LVDS:
1391                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1392                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1393                         break;
1394                 }
1395                 if (percentage)
1396                         ss->percentage = percentage;
1397                 if (rate)
1398                         ss->rate = rate;
1399         }
1400 }
1401
1402 union asic_ss_info {
1403         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1404         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1405         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1406 };
1407
1408 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1409                                       struct radeon_atom_ss *ss,
1410                                       int id, u32 clock)
1411 {
1412         struct radeon_mode_info *mode_info = &rdev->mode_info;
1413         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1414         uint16_t data_offset, size;
1415         union asic_ss_info *ss_info;
1416         uint8_t frev, crev;
1417         int i, num_indices;
1418
1419         memset(ss, 0, sizeof(struct radeon_atom_ss));
1420         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1421                                    &frev, &crev, &data_offset)) {
1422
1423                 ss_info =
1424                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1425
1426                 switch (frev) {
1427                 case 1:
1428                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1429                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1430
1431                         for (i = 0; i < num_indices; i++) {
1432                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1433                                     (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1434                                         ss->percentage =
1435                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1436                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1437                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1438                                         return true;
1439                                 }
1440                         }
1441                         break;
1442                 case 2:
1443                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1444                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1445                         for (i = 0; i < num_indices; i++) {
1446                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1447                                     (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1448                                         ss->percentage =
1449                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1450                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1451                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1452                                         return true;
1453                                 }
1454                         }
1455                         break;
1456                 case 3:
1457                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1458                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1459                         for (i = 0; i < num_indices; i++) {
1460                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1461                                     (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1462                                         ss->percentage =
1463                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1464                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1465                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1466                                         if (rdev->flags & RADEON_IS_IGP)
1467                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1468                                         return true;
1469                                 }
1470                         }
1471                         break;
1472                 default:
1473                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1474                         break;
1475                 }
1476
1477         }
1478         return false;
1479 }
1480
1481 union lvds_info {
1482         struct _ATOM_LVDS_INFO info;
1483         struct _ATOM_LVDS_INFO_V12 info_12;
1484 };
1485
1486 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1487                                                               radeon_encoder
1488                                                               *encoder)
1489 {
1490         struct drm_device *dev = encoder->base.dev;
1491         struct radeon_device *rdev = dev->dev_private;
1492         struct radeon_mode_info *mode_info = &rdev->mode_info;
1493         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1494         uint16_t data_offset, misc;
1495         union lvds_info *lvds_info;
1496         uint8_t frev, crev;
1497         struct radeon_encoder_atom_dig *lvds = NULL;
1498         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1499
1500         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1501                                    &frev, &crev, &data_offset)) {
1502                 lvds_info =
1503                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1504                 lvds =
1505                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1506
1507                 if (!lvds)
1508                         return NULL;
1509
1510                 lvds->native_mode.clock =
1511                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1512                 lvds->native_mode.hdisplay =
1513                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1514                 lvds->native_mode.vdisplay =
1515                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1516                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1517                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1518                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1519                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1520                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1521                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1522                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1523                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1524                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1525                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1526                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1527                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1528                 lvds->panel_pwr_delay =
1529                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1530                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1531
1532                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1533                 if (misc & ATOM_VSYNC_POLARITY)
1534                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1535                 if (misc & ATOM_HSYNC_POLARITY)
1536                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1537                 if (misc & ATOM_COMPOSITESYNC)
1538                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1539                 if (misc & ATOM_INTERLACE)
1540                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1541                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1542                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1543
1544                 lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize;
1545                 lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize;
1546
1547                 /* set crtc values */
1548                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1549
1550                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1551
1552                 encoder->native_mode = lvds->native_mode;
1553
1554                 if (encoder_enum == 2)
1555                         lvds->linkb = true;
1556                 else
1557                         lvds->linkb = false;
1558
1559                 /* parse the lcd record table */
1560                 if (lvds_info->info.usModePatchTableOffset) {
1561                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1562                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1563                         bool bad_record = false;
1564                         u8 *record = (u8 *)(mode_info->atom_context->bios +
1565                                             data_offset +
1566                                             lvds_info->info.usModePatchTableOffset);
1567                         while (*record != ATOM_RECORD_END_TYPE) {
1568                                 switch (*record) {
1569                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1570                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1571                                         break;
1572                                 case LCD_RTS_RECORD_TYPE:
1573                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1574                                         break;
1575                                 case LCD_CAP_RECORD_TYPE:
1576                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1577                                         break;
1578                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1579                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1580                                         if (fake_edid_record->ucFakeEDIDLength) {
1581                                                 struct edid *edid;
1582                                                 int edid_size =
1583                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1584                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1585                                                 if (edid) {
1586                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1587                                                                fake_edid_record->ucFakeEDIDLength);
1588
1589                                                         if (drm_edid_is_valid(edid))
1590                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1591                                                         else
1592                                                                 kfree(edid);
1593                                                 }
1594                                         }
1595                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1596                                         break;
1597                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1598                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1599                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1600                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1601                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1602                                         break;
1603                                 default:
1604                                         DRM_ERROR("Bad LCD record %d\n", *record);
1605                                         bad_record = true;
1606                                         break;
1607                                 }
1608                                 if (bad_record)
1609                                         break;
1610                         }
1611                 }
1612         }
1613         return lvds;
1614 }
1615
1616 struct radeon_encoder_primary_dac *
1617 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1618 {
1619         struct drm_device *dev = encoder->base.dev;
1620         struct radeon_device *rdev = dev->dev_private;
1621         struct radeon_mode_info *mode_info = &rdev->mode_info;
1622         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1623         uint16_t data_offset;
1624         struct _COMPASSIONATE_DATA *dac_info;
1625         uint8_t frev, crev;
1626         uint8_t bg, dac;
1627         struct radeon_encoder_primary_dac *p_dac = NULL;
1628
1629         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1630                                    &frev, &crev, &data_offset)) {
1631                 dac_info = (struct _COMPASSIONATE_DATA *)
1632                         (mode_info->atom_context->bios + data_offset);
1633
1634                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1635
1636                 if (!p_dac)
1637                         return NULL;
1638
1639                 bg = dac_info->ucDAC1_BG_Adjustment;
1640                 dac = dac_info->ucDAC1_DAC_Adjustment;
1641                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1642
1643         }
1644         return p_dac;
1645 }
1646
1647 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1648                                 struct drm_display_mode *mode)
1649 {
1650         struct radeon_mode_info *mode_info = &rdev->mode_info;
1651         ATOM_ANALOG_TV_INFO *tv_info;
1652         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1653         ATOM_DTD_FORMAT *dtd_timings;
1654         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1655         u8 frev, crev;
1656         u16 data_offset, misc;
1657
1658         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1659                                     &frev, &crev, &data_offset))
1660                 return false;
1661
1662         switch (crev) {
1663         case 1:
1664                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1665                 if (index >= MAX_SUPPORTED_TV_TIMING)
1666                         return false;
1667
1668                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1669                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1670                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1671                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1672                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1673
1674                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1675                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1676                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1677                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1678                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1679
1680                 mode->flags = 0;
1681                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1682                 if (misc & ATOM_VSYNC_POLARITY)
1683                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1684                 if (misc & ATOM_HSYNC_POLARITY)
1685                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1686                 if (misc & ATOM_COMPOSITESYNC)
1687                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1688                 if (misc & ATOM_INTERLACE)
1689                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1690                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1691                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1692
1693                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1694
1695                 if (index == 1) {
1696                         /* PAL timings appear to have wrong values for totals */
1697                         mode->crtc_htotal -= 1;
1698                         mode->crtc_vtotal -= 1;
1699                 }
1700                 break;
1701         case 2:
1702                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1703                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1704                         return false;
1705
1706                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1707                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1708                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1709                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1710                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1711                         le16_to_cpu(dtd_timings->usHSyncOffset);
1712                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1713                         le16_to_cpu(dtd_timings->usHSyncWidth);
1714
1715                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1716                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1717                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1718                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1719                         le16_to_cpu(dtd_timings->usVSyncOffset);
1720                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1721                         le16_to_cpu(dtd_timings->usVSyncWidth);
1722
1723                 mode->flags = 0;
1724                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1725                 if (misc & ATOM_VSYNC_POLARITY)
1726                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1727                 if (misc & ATOM_HSYNC_POLARITY)
1728                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1729                 if (misc & ATOM_COMPOSITESYNC)
1730                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1731                 if (misc & ATOM_INTERLACE)
1732                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1733                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1734                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1735
1736                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1737                 break;
1738         }
1739         return true;
1740 }
1741
1742 enum radeon_tv_std
1743 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1744 {
1745         struct radeon_mode_info *mode_info = &rdev->mode_info;
1746         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1747         uint16_t data_offset;
1748         uint8_t frev, crev;
1749         struct _ATOM_ANALOG_TV_INFO *tv_info;
1750         enum radeon_tv_std tv_std = TV_STD_NTSC;
1751
1752         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1753                                    &frev, &crev, &data_offset)) {
1754
1755                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1756                         (mode_info->atom_context->bios + data_offset);
1757
1758                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1759                 case ATOM_TV_NTSC:
1760                         tv_std = TV_STD_NTSC;
1761                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1762                         break;
1763                 case ATOM_TV_NTSCJ:
1764                         tv_std = TV_STD_NTSC_J;
1765                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1766                         break;
1767                 case ATOM_TV_PAL:
1768                         tv_std = TV_STD_PAL;
1769                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1770                         break;
1771                 case ATOM_TV_PALM:
1772                         tv_std = TV_STD_PAL_M;
1773                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1774                         break;
1775                 case ATOM_TV_PALN:
1776                         tv_std = TV_STD_PAL_N;
1777                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1778                         break;
1779                 case ATOM_TV_PALCN:
1780                         tv_std = TV_STD_PAL_CN;
1781                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1782                         break;
1783                 case ATOM_TV_PAL60:
1784                         tv_std = TV_STD_PAL_60;
1785                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1786                         break;
1787                 case ATOM_TV_SECAM:
1788                         tv_std = TV_STD_SECAM;
1789                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1790                         break;
1791                 default:
1792                         tv_std = TV_STD_NTSC;
1793                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1794                         break;
1795                 }
1796         }
1797         return tv_std;
1798 }
1799
1800 struct radeon_encoder_tv_dac *
1801 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1802 {
1803         struct drm_device *dev = encoder->base.dev;
1804         struct radeon_device *rdev = dev->dev_private;
1805         struct radeon_mode_info *mode_info = &rdev->mode_info;
1806         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1807         uint16_t data_offset;
1808         struct _COMPASSIONATE_DATA *dac_info;
1809         uint8_t frev, crev;
1810         uint8_t bg, dac;
1811         struct radeon_encoder_tv_dac *tv_dac = NULL;
1812
1813         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1814                                    &frev, &crev, &data_offset)) {
1815
1816                 dac_info = (struct _COMPASSIONATE_DATA *)
1817                         (mode_info->atom_context->bios + data_offset);
1818
1819                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1820
1821                 if (!tv_dac)
1822                         return NULL;
1823
1824                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1825                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1826                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1827
1828                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1829                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1830                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1831
1832                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1833                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1834                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1835
1836                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1837         }
1838         return tv_dac;
1839 }
1840
1841 static const char *thermal_controller_names[] = {
1842         "NONE",
1843         "lm63",
1844         "adm1032",
1845         "adm1030",
1846         "max6649",
1847         "lm64",
1848         "f75375",
1849         "asc7xxx",
1850 };
1851
1852 static const char *pp_lib_thermal_controller_names[] = {
1853         "NONE",
1854         "lm63",
1855         "adm1032",
1856         "adm1030",
1857         "max6649",
1858         "lm64",
1859         "f75375",
1860         "RV6xx",
1861         "RV770",
1862         "adt7473",
1863         "NONE",
1864         "External GPIO",
1865         "Evergreen",
1866         "emc2103",
1867         "Sumo",
1868 };
1869
1870 union power_info {
1871         struct _ATOM_POWERPLAY_INFO info;
1872         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1873         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1874         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1875         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1876         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1877 };
1878
1879 union pplib_clock_info {
1880         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1881         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1882         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1883         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1884 };
1885
1886 union pplib_power_state {
1887         struct _ATOM_PPLIB_STATE v1;
1888         struct _ATOM_PPLIB_STATE_V2 v2;
1889 };
1890
1891 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1892                                                  int state_index,
1893                                                  u32 misc, u32 misc2)
1894 {
1895         rdev->pm.power_state[state_index].misc = misc;
1896         rdev->pm.power_state[state_index].misc2 = misc2;
1897         /* order matters! */
1898         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1899                 rdev->pm.power_state[state_index].type =
1900                         POWER_STATE_TYPE_POWERSAVE;
1901         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1902                 rdev->pm.power_state[state_index].type =
1903                         POWER_STATE_TYPE_BATTERY;
1904         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1905                 rdev->pm.power_state[state_index].type =
1906                         POWER_STATE_TYPE_BATTERY;
1907         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1908                 rdev->pm.power_state[state_index].type =
1909                         POWER_STATE_TYPE_BALANCED;
1910         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1911                 rdev->pm.power_state[state_index].type =
1912                         POWER_STATE_TYPE_PERFORMANCE;
1913                 rdev->pm.power_state[state_index].flags &=
1914                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1915         }
1916         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1917                 rdev->pm.power_state[state_index].type =
1918                         POWER_STATE_TYPE_BALANCED;
1919         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1920                 rdev->pm.power_state[state_index].type =
1921                         POWER_STATE_TYPE_DEFAULT;
1922                 rdev->pm.default_power_state_index = state_index;
1923                 rdev->pm.power_state[state_index].default_clock_mode =
1924                         &rdev->pm.power_state[state_index].clock_info[0];
1925         } else if (state_index == 0) {
1926                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1927                         RADEON_PM_MODE_NO_DISPLAY;
1928         }
1929 }
1930
1931 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1932 {
1933         struct radeon_mode_info *mode_info = &rdev->mode_info;
1934         u32 misc, misc2 = 0;
1935         int num_modes = 0, i;
1936         int state_index = 0;
1937         struct radeon_i2c_bus_rec i2c_bus;
1938         union power_info *power_info;
1939         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1940         u16 data_offset;
1941         u8 frev, crev;
1942
1943         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1944                                    &frev, &crev, &data_offset))
1945                 return state_index;
1946         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1947
1948         /* add the i2c bus for thermal/fan chip */
1949         if (power_info->info.ucOverdriveThermalController > 0) {
1950                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1951                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1952                          power_info->info.ucOverdriveControllerAddress >> 1);
1953                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1954                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1955                 if (rdev->pm.i2c_bus) {
1956                         struct i2c_board_info info = { };
1957                         const char *name = thermal_controller_names[power_info->info.
1958                                                                     ucOverdriveThermalController];
1959                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1960                         strlcpy(info.type, name, sizeof(info.type));
1961                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1962                 }
1963         }
1964         num_modes = power_info->info.ucNumOfPowerModeEntries;
1965         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1966                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1967         /* last mode is usually default, array is low to high */
1968         for (i = 0; i < num_modes; i++) {
1969                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1970                 switch (frev) {
1971                 case 1:
1972                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1973                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1974                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1975                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1976                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1977                         /* skip invalid modes */
1978                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1979                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1980                                 continue;
1981                         rdev->pm.power_state[state_index].pcie_lanes =
1982                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1983                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1984                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1985                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1986                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1987                                         VOLTAGE_GPIO;
1988                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1989                                         radeon_lookup_gpio(rdev,
1990                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1991                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1992                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1993                                                 true;
1994                                 else
1995                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1996                                                 false;
1997                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1998                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1999                                         VOLTAGE_VDDC;
2000                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2001                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2002                         }
2003                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2004                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2005                         state_index++;
2006                         break;
2007                 case 2:
2008                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2009                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2010                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2011                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2012                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2013                         /* skip invalid modes */
2014                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2015                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2016                                 continue;
2017                         rdev->pm.power_state[state_index].pcie_lanes =
2018                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2019                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2020                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2021                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2022                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2023                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2024                                         VOLTAGE_GPIO;
2025                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2026                                         radeon_lookup_gpio(rdev,
2027                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2028                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2029                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2030                                                 true;
2031                                 else
2032                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2033                                                 false;
2034                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2035                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2036                                         VOLTAGE_VDDC;
2037                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2038                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2039                         }
2040                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2041                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2042                         state_index++;
2043                         break;
2044                 case 3:
2045                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2046                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2047                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2048                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2049                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2050                         /* skip invalid modes */
2051                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2052                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2053                                 continue;
2054                         rdev->pm.power_state[state_index].pcie_lanes =
2055                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2056                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2057                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2058                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2059                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2060                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2061                                         VOLTAGE_GPIO;
2062                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2063                                         radeon_lookup_gpio(rdev,
2064                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2065                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2066                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2067                                                 true;
2068                                 else
2069                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2070                                                 false;
2071                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2072                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2073                                         VOLTAGE_VDDC;
2074                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2075                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2076                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2077                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2078                                                 true;
2079                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2080                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2081                                 }
2082                         }
2083                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2084                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2085                         state_index++;
2086                         break;
2087                 }
2088         }
2089         /* last mode is usually default */
2090         if (rdev->pm.default_power_state_index == -1) {
2091                 rdev->pm.power_state[state_index - 1].type =
2092                         POWER_STATE_TYPE_DEFAULT;
2093                 rdev->pm.default_power_state_index = state_index - 1;
2094                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2095                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2096                 rdev->pm.power_state[state_index].flags &=
2097                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2098                 rdev->pm.power_state[state_index].misc = 0;
2099                 rdev->pm.power_state[state_index].misc2 = 0;
2100         }
2101         return state_index;
2102 }
2103
2104 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2105                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2106 {
2107         struct radeon_i2c_bus_rec i2c_bus;
2108
2109         /* add the i2c bus for thermal/fan chip */
2110         if (controller->ucType > 0) {
2111                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2112                         DRM_INFO("Internal thermal controller %s fan control\n",
2113                                  (controller->ucFanParameters &
2114                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2115                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2116                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2117                         DRM_INFO("Internal thermal controller %s fan control\n",
2118                                  (controller->ucFanParameters &
2119                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2120                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2121                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2122                         DRM_INFO("Internal thermal controller %s fan control\n",
2123                                  (controller->ucFanParameters &
2124                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2125                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2126                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2127                         DRM_INFO("Internal thermal controller %s fan control\n",
2128                                  (controller->ucFanParameters &
2129                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2130                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2131                 } else if ((controller->ucType ==
2132                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2133                            (controller->ucType ==
2134                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2135                            (controller->ucType ==
2136                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2137                         DRM_INFO("Special thermal controller config\n");
2138                 } else {
2139                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2140                                  pp_lib_thermal_controller_names[controller->ucType],
2141                                  controller->ucI2cAddress >> 1,
2142                                  (controller->ucFanParameters &
2143                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2144                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2145                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2146                         if (rdev->pm.i2c_bus) {
2147                                 struct i2c_board_info info = { };
2148                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2149                                 info.addr = controller->ucI2cAddress >> 1;
2150                                 strlcpy(info.type, name, sizeof(info.type));
2151                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2152                         }
2153                 }
2154         }
2155 }
2156
2157 static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2158 {
2159         struct radeon_mode_info *mode_info = &rdev->mode_info;
2160         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2161         u8 frev, crev;
2162         u16 data_offset;
2163         union firmware_info *firmware_info;
2164         u16 vddc = 0;
2165
2166         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2167                                    &frev, &crev, &data_offset)) {
2168                 firmware_info =
2169                         (union firmware_info *)(mode_info->atom_context->bios +
2170                                                 data_offset);
2171                 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2172         }
2173
2174         return vddc;
2175 }
2176
2177 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2178                                                        int state_index, int mode_index,
2179                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2180 {
2181         int j;
2182         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2183         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2184         u16 vddc = radeon_atombios_get_default_vddc(rdev);
2185
2186         rdev->pm.power_state[state_index].misc = misc;
2187         rdev->pm.power_state[state_index].misc2 = misc2;
2188         rdev->pm.power_state[state_index].pcie_lanes =
2189                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2190                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2191         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2192         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2193                 rdev->pm.power_state[state_index].type =
2194                         POWER_STATE_TYPE_BATTERY;
2195                 break;
2196         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2197                 rdev->pm.power_state[state_index].type =
2198                         POWER_STATE_TYPE_BALANCED;
2199                 break;
2200         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2201                 rdev->pm.power_state[state_index].type =
2202                         POWER_STATE_TYPE_PERFORMANCE;
2203                 break;
2204         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2205                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2206                         rdev->pm.power_state[state_index].type =
2207                                 POWER_STATE_TYPE_PERFORMANCE;
2208                 break;
2209         }
2210         rdev->pm.power_state[state_index].flags = 0;
2211         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2212                 rdev->pm.power_state[state_index].flags |=
2213                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2214         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2215                 rdev->pm.power_state[state_index].type =
2216                         POWER_STATE_TYPE_DEFAULT;
2217                 rdev->pm.default_power_state_index = state_index;
2218                 rdev->pm.power_state[state_index].default_clock_mode =
2219                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2220                 /* patch the table values with the default slck/mclk from firmware info */
2221                 for (j = 0; j < mode_index; j++) {
2222                         rdev->pm.power_state[state_index].clock_info[j].mclk =
2223                                 rdev->clock.default_mclk;
2224                         rdev->pm.power_state[state_index].clock_info[j].sclk =
2225                                 rdev->clock.default_sclk;
2226                         if (vddc)
2227                                 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2228                                         vddc;
2229                 }
2230         }
2231 }
2232
2233 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2234                                                    int state_index, int mode_index,
2235                                                    union pplib_clock_info *clock_info)
2236 {
2237         u32 sclk, mclk;
2238
2239         if (rdev->flags & RADEON_IS_IGP) {
2240                 if (rdev->family >= CHIP_PALM) {
2241                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2242                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2243                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2244                 } else {
2245                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2246                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2247                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2248                 }
2249         } else if (ASIC_IS_DCE4(rdev)) {
2250                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2251                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2252                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2253                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2254                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2255                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2256                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2257                         VOLTAGE_SW;
2258                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2259                         clock_info->evergreen.usVDDC;
2260         } else {
2261                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2262                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2263                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2264                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2265                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2266                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2267                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2268                         VOLTAGE_SW;
2269                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2270                         clock_info->r600.usVDDC;
2271         }
2272
2273         if (rdev->flags & RADEON_IS_IGP) {
2274                 /* skip invalid modes */
2275                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2276                         return false;
2277         } else {
2278                 /* skip invalid modes */
2279                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2280                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2281                         return false;
2282         }
2283         return true;
2284 }
2285
2286 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2287 {
2288         struct radeon_mode_info *mode_info = &rdev->mode_info;
2289         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2290         union pplib_power_state *power_state;
2291         int i, j;
2292         int state_index = 0, mode_index = 0;
2293         union pplib_clock_info *clock_info;
2294         bool valid;
2295         union power_info *power_info;
2296         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2297         u16 data_offset;
2298         u8 frev, crev;
2299
2300         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2301                                    &frev, &crev, &data_offset))
2302                 return state_index;
2303         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2304
2305         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2306         /* first mode is usually default, followed by low to high */
2307         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2308                 mode_index = 0;
2309                 power_state = (union pplib_power_state *)
2310                         (mode_info->atom_context->bios + data_offset +
2311                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2312                          i * power_info->pplib.ucStateEntrySize);
2313                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2314                         (mode_info->atom_context->bios + data_offset +
2315                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2316                          (power_state->v1.ucNonClockStateIndex *
2317                           power_info->pplib.ucNonClockSize));
2318                 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2319                         clock_info = (union pplib_clock_info *)
2320                                 (mode_info->atom_context->bios + data_offset +
2321                                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2322                                  (power_state->v1.ucClockStateIndices[j] *
2323                                   power_info->pplib.ucClockInfoSize));
2324                         valid = radeon_atombios_parse_pplib_clock_info(rdev,
2325                                                                        state_index, mode_index,
2326                                                                        clock_info);
2327                         if (valid)
2328                                 mode_index++;
2329                 }
2330                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2331                 if (mode_index) {
2332                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2333                                                                    non_clock_info);
2334                         state_index++;
2335                 }
2336         }
2337         /* if multiple clock modes, mark the lowest as no display */
2338         for (i = 0; i < state_index; i++) {
2339                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2340                         rdev->pm.power_state[i].clock_info[0].flags |=
2341                                 RADEON_PM_MODE_NO_DISPLAY;
2342         }
2343         /* first mode is usually default */
2344         if (rdev->pm.default_power_state_index == -1) {
2345                 rdev->pm.power_state[0].type =
2346                         POWER_STATE_TYPE_DEFAULT;
2347                 rdev->pm.default_power_state_index = 0;
2348                 rdev->pm.power_state[0].default_clock_mode =
2349                         &rdev->pm.power_state[0].clock_info[0];
2350         }
2351         return state_index;
2352 }
2353
2354 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2355 {
2356         struct radeon_mode_info *mode_info = &rdev->mode_info;
2357         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2358         union pplib_power_state *power_state;
2359         int i, j, non_clock_array_index, clock_array_index;
2360         int state_index = 0, mode_index = 0;
2361         union pplib_clock_info *clock_info;
2362         struct StateArray *state_array;
2363         struct ClockInfoArray *clock_info_array;
2364         struct NonClockInfoArray *non_clock_info_array;
2365         bool valid;
2366         union power_info *power_info;
2367         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2368         u16 data_offset;
2369         u8 frev, crev;
2370
2371         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2372                                    &frev, &crev, &data_offset))
2373                 return state_index;
2374         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2375
2376         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2377         state_array = (struct StateArray *)
2378                 (mode_info->atom_context->bios + data_offset +
2379                  power_info->pplib.usStateArrayOffset);
2380         clock_info_array = (struct ClockInfoArray *)
2381                 (mode_info->atom_context->bios + data_offset +
2382                  power_info->pplib.usClockInfoArrayOffset);
2383         non_clock_info_array = (struct NonClockInfoArray *)
2384                 (mode_info->atom_context->bios + data_offset +
2385                  power_info->pplib.usNonClockInfoArrayOffset);
2386         for (i = 0; i < state_array->ucNumEntries; i++) {
2387                 mode_index = 0;
2388                 power_state = (union pplib_power_state *)&state_array->states[i];
2389                 /* XXX this might be an inagua bug... */
2390                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2391                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2392                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2393                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2394                         clock_array_index = power_state->v2.clockInfoIndex[j];
2395                         /* XXX this might be an inagua bug... */
2396                         if (clock_array_index >= clock_info_array->ucNumEntries)
2397                                 continue;
2398                         clock_info = (union pplib_clock_info *)
2399                                 &clock_info_array->clockInfo[clock_array_index];
2400                         valid = radeon_atombios_parse_pplib_clock_info(rdev,
2401                                                                        state_index, mode_index,
2402                                                                        clock_info);
2403                         if (valid)
2404                                 mode_index++;
2405                 }
2406                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2407                 if (mode_index) {
2408                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2409                                                                    non_clock_info);
2410                         state_index++;
2411                 }
2412         }
2413         /* if multiple clock modes, mark the lowest as no display */
2414         for (i = 0; i < state_index; i++) {
2415                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2416                         rdev->pm.power_state[i].clock_info[0].flags |=
2417                                 RADEON_PM_MODE_NO_DISPLAY;
2418         }
2419         /* first mode is usually default */
2420         if (rdev->pm.default_power_state_index == -1) {
2421                 rdev->pm.power_state[0].type =
2422                         POWER_STATE_TYPE_DEFAULT;
2423                 rdev->pm.default_power_state_index = 0;
2424                 rdev->pm.power_state[0].default_clock_mode =
2425                         &rdev->pm.power_state[0].clock_info[0];
2426         }
2427         return state_index;
2428 }
2429
2430 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2431 {
2432         struct radeon_mode_info *mode_info = &rdev->mode_info;
2433         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2434         u16 data_offset;
2435         u8 frev, crev;
2436         int state_index = 0;
2437
2438         rdev->pm.default_power_state_index = -1;
2439
2440         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2441                                    &frev, &crev, &data_offset)) {
2442                 switch (frev) {
2443                 case 1:
2444                 case 2:
2445                 case 3:
2446                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2447                         break;
2448                 case 4:
2449                 case 5:
2450                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2451                         break;
2452                 case 6:
2453                         state_index = radeon_atombios_parse_power_table_6(rdev);
2454                         break;
2455                 default:
2456                         break;
2457                 }
2458         } else {
2459                 /* add the default mode */
2460                 rdev->pm.power_state[state_index].type =
2461                         POWER_STATE_TYPE_DEFAULT;
2462                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2463                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2464                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2465                 rdev->pm.power_state[state_index].default_clock_mode =
2466                         &rdev->pm.power_state[state_index].clock_info[0];
2467                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2468                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2469                 rdev->pm.default_power_state_index = state_index;
2470                 rdev->pm.power_state[state_index].flags = 0;
2471                 state_index++;
2472         }
2473
2474         rdev->pm.num_power_states = state_index;
2475
2476         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2477         rdev->pm.current_clock_mode_index = 0;
2478         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2479 }
2480
2481 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2482 {
2483         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2484         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2485
2486         args.ucEnable = enable;
2487
2488         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2489 }
2490
2491 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2492 {
2493         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2494         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2495
2496         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2497         return args.ulReturnEngineClock;
2498 }
2499
2500 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2501 {
2502         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2503         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2504
2505         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2506         return args.ulReturnMemoryClock;
2507 }
2508
2509 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2510                                   uint32_t eng_clock)
2511 {
2512         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2513         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2514
2515         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
2516
2517         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2518 }
2519
2520 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2521                                   uint32_t mem_clock)
2522 {
2523         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2524         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2525
2526         if (rdev->flags & RADEON_IS_IGP)
2527                 return;
2528
2529         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
2530
2531         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2532 }
2533
2534 union set_voltage {
2535         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2536         struct _SET_VOLTAGE_PARAMETERS v1;
2537         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2538 };
2539
2540 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2541 {
2542         union set_voltage args;
2543         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2544         u8 frev, crev, volt_index = level;
2545
2546         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2547                 return;
2548
2549         switch (crev) {
2550         case 1:
2551                 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2552                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2553                 args.v1.ucVoltageIndex = volt_index;
2554                 break;
2555         case 2:
2556                 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2557                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2558                 args.v2.usVoltageLevel = cpu_to_le16(level);
2559                 break;
2560         default:
2561                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2562                 return;
2563         }
2564
2565         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2566 }
2567
2568
2569
2570 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2571 {
2572         struct radeon_device *rdev = dev->dev_private;
2573         uint32_t bios_2_scratch, bios_6_scratch;
2574
2575         if (rdev->family >= CHIP_R600) {
2576                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2577                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2578         } else {
2579                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2580                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2581         }
2582
2583         /* let the bios control the backlight */
2584         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2585
2586         /* tell the bios not to handle mode switching */
2587         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2588
2589         if (rdev->family >= CHIP_R600) {
2590                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2591                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2592         } else {
2593                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2594                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2595         }
2596
2597 }
2598
2599 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2600 {
2601         uint32_t scratch_reg;
2602         int i;
2603
2604         if (rdev->family >= CHIP_R600)
2605                 scratch_reg = R600_BIOS_0_SCRATCH;
2606         else
2607                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2608
2609         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2610                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2611 }
2612
2613 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2614 {
2615         uint32_t scratch_reg;
2616         int i;
2617
2618         if (rdev->family >= CHIP_R600)
2619                 scratch_reg = R600_BIOS_0_SCRATCH;
2620         else
2621                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2622
2623         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2624                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2625 }
2626
2627 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2628 {
2629         struct drm_device *dev = encoder->dev;
2630         struct radeon_device *rdev = dev->dev_private;
2631         uint32_t bios_6_scratch;
2632
2633         if (rdev->family >= CHIP_R600)
2634                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2635         else
2636                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2637
2638         if (lock)
2639                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2640         else
2641                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2642
2643         if (rdev->family >= CHIP_R600)
2644                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2645         else
2646                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2647 }
2648
2649 /* at some point we may want to break this out into individual functions */
2650 void
2651 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2652                                        struct drm_encoder *encoder,
2653                                        bool connected)
2654 {
2655         struct drm_device *dev = connector->dev;
2656         struct radeon_device *rdev = dev->dev_private;
2657         struct radeon_connector *radeon_connector =
2658             to_radeon_connector(connector);
2659         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2660         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2661
2662         if (rdev->family >= CHIP_R600) {
2663                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2664                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2665                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2666         } else {
2667                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2668                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2669                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2670         }
2671
2672         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2673             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2674                 if (connected) {
2675                         DRM_DEBUG_KMS("TV1 connected\n");
2676                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2677                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2678                 } else {
2679                         DRM_DEBUG_KMS("TV1 disconnected\n");
2680                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2681                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2682                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2683                 }
2684         }
2685         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2686             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2687                 if (connected) {
2688                         DRM_DEBUG_KMS("CV connected\n");
2689                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2690                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2691                 } else {
2692                         DRM_DEBUG_KMS("CV disconnected\n");
2693                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2694                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2695                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2696                 }
2697         }
2698         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2699             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2700                 if (connected) {
2701                         DRM_DEBUG_KMS("LCD1 connected\n");
2702                         bios_0_scratch |= ATOM_S0_LCD1;
2703                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2704                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2705                 } else {
2706                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2707                         bios_0_scratch &= ~ATOM_S0_LCD1;
2708                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2709                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2710                 }
2711         }
2712         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2713             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2714                 if (connected) {
2715                         DRM_DEBUG_KMS("CRT1 connected\n");
2716                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2717                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2718                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2719                 } else {
2720                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2721                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2722                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2723                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2724                 }
2725         }
2726         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2727             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2728                 if (connected) {
2729                         DRM_DEBUG_KMS("CRT2 connected\n");
2730                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2731                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2732                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2733                 } else {
2734                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2735                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2736                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2737                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2738                 }
2739         }
2740         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2741             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2742                 if (connected) {
2743                         DRM_DEBUG_KMS("DFP1 connected\n");
2744                         bios_0_scratch |= ATOM_S0_DFP1;
2745                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2746                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2747                 } else {
2748                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2749                         bios_0_scratch &= ~ATOM_S0_DFP1;
2750                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2751                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2752                 }
2753         }
2754         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2755             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2756                 if (connected) {
2757                         DRM_DEBUG_KMS("DFP2 connected\n");
2758                         bios_0_scratch |= ATOM_S0_DFP2;
2759                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2760                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2761                 } else {
2762                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2763                         bios_0_scratch &= ~ATOM_S0_DFP2;
2764                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2765                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2766                 }
2767         }
2768         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2769             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2770                 if (connected) {
2771                         DRM_DEBUG_KMS("DFP3 connected\n");
2772                         bios_0_scratch |= ATOM_S0_DFP3;
2773                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2774                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2775                 } else {
2776                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2777                         bios_0_scratch &= ~ATOM_S0_DFP3;
2778                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2779                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2780                 }
2781         }
2782         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2783             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2784                 if (connected) {
2785                         DRM_DEBUG_KMS("DFP4 connected\n");
2786                         bios_0_scratch |= ATOM_S0_DFP4;
2787                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2788                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2789                 } else {
2790                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2791                         bios_0_scratch &= ~ATOM_S0_DFP4;
2792                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2793                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2794                 }
2795         }
2796         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2797             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2798                 if (connected) {
2799                         DRM_DEBUG_KMS("DFP5 connected\n");
2800                         bios_0_scratch |= ATOM_S0_DFP5;
2801                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2802                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2803                 } else {
2804                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2805                         bios_0_scratch &= ~ATOM_S0_DFP5;
2806                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2807                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2808                 }
2809         }
2810
2811         if (rdev->family >= CHIP_R600) {
2812                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2813                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2814                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2815         } else {
2816                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2817                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2818                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2819         }
2820 }
2821
2822 void
2823 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2824 {
2825         struct drm_device *dev = encoder->dev;
2826         struct radeon_device *rdev = dev->dev_private;
2827         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2828         uint32_t bios_3_scratch;
2829
2830         if (rdev->family >= CHIP_R600)
2831                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2832         else
2833                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2834
2835         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2836                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2837                 bios_3_scratch |= (crtc << 18);
2838         }
2839         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2840                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2841                 bios_3_scratch |= (crtc << 24);
2842         }
2843         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2844                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2845                 bios_3_scratch |= (crtc << 16);
2846         }
2847         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2848                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2849                 bios_3_scratch |= (crtc << 20);
2850         }
2851         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2852                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2853                 bios_3_scratch |= (crtc << 17);
2854         }
2855         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2856                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2857                 bios_3_scratch |= (crtc << 19);
2858         }
2859         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2860                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2861                 bios_3_scratch |= (crtc << 23);
2862         }
2863         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2864                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2865                 bios_3_scratch |= (crtc << 25);
2866         }
2867
2868         if (rdev->family >= CHIP_R600)
2869                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2870         else
2871                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2872 }
2873
2874 void
2875 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2876 {
2877         struct drm_device *dev = encoder->dev;
2878         struct radeon_device *rdev = dev->dev_private;
2879         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2880         uint32_t bios_2_scratch;
2881
2882         if (rdev->family >= CHIP_R600)
2883                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2884         else
2885                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2886
2887         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2888                 if (on)
2889                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2890                 else
2891                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2892         }
2893         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2894                 if (on)
2895                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2896                 else
2897                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2898         }
2899         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2900                 if (on)
2901                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2902                 else
2903                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2904         }
2905         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2906                 if (on)
2907                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2908                 else
2909                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2910         }
2911         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2912                 if (on)
2913                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2914                 else
2915                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2916         }
2917         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2918                 if (on)
2919                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2920                 else
2921                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2922         }
2923         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2924                 if (on)
2925                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2926                 else
2927                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2928         }
2929         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2930                 if (on)
2931                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2932                 else
2933                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2934         }
2935         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2936                 if (on)
2937                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2938                 else
2939                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2940         }
2941         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2942                 if (on)
2943                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2944                 else
2945                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2946         }
2947
2948         if (rdev->family >= CHIP_R600)
2949                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2950         else
2951                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2952 }